IDTCV115-2 [IDT]
PROGRAMMABLE FLEXPC? CLOCK FOR P4 PROCESSOR; 可编程FLEXPC ™时钟为P4处理器
| 型号： | IDTCV115-2 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | PROGRAMMABLE FLEXPC? CLOCK FOR P4 PROCESSOR |
| 文件： | 总19页 (文件大小：102K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IDTCV115-2
PROGRAMMABLE FLEXPC™
CLOCK FOR P4 PROCESSOR
DESCRIPTION:
FEATURES:
IDTCV115-2 is a 56 pin clock device, complying the latest Intel CK410
requirements, for Intel advance P4 processors. The CPU output buffer is
designedtosupportupto400MHzprocessor. OnededicatedPLLforSerial
ATAclockprovides highaccuracyfrequency. This device alsoimplements
Band-gapreferencedIREF toreducetheimpactofVDD variationondifferential
outputs,whichcanprovidemorerobustsystemperformance.
• One high precision N Programming PLL for CPU
• One high precision N Programming PLL for SRC/PCI
• One high precision PLL for SATA
• One high precision PLL for 96MHz/48MHz
• Band-gap circuit for differential outputs
• Support multiple spread spectrum modulation, down and
center
• Support SMBus block read/write, index read/write
• Selectable output strength for REF, PCI, and 48MHz
• Available in SSOP package
EachCPU/SRC/PCI,SATAclockhasitsownSpreadSpectrumselection,
whichallowsforisolatedchangesinsteadofaffecting otherclockgroups.
KEYSPECIFICATION:
• CPU/SRC CLK cycle to cycle jitter < 85ps
• SATA CLK cycle to cycle jitter < 85ps
• Static PLL frequency divide error < 114 ppm
• Static PLL frequency divide error for 48MHz < 5 ppm
FUNCTIONALBLOCKDIAGRAM
SATA PLL
SCC
SRC4 - SATA
SATA/
PCI[4:0], PCIF[2:0]
PCI/
PCIEX PLL
SCC
N Programming
14.318MHz
Osc
PCIE/
Host/
SRC[6:5] [3:1]
CPU_ITP/
SRC7
MUX
CPU PLL
SCC
N Programming
CPU[1:0]
USB48
48MHz/
96MHz/
DOT96
RESET
Fixed PLL
No SCC
OUTPUTTABLE
CPU
CPU_ITP/SRC
SRC
SATA
PCI/PCIF
REF/PCI
REF
DOT96
24_48MHz
RESET
TURBO
2
1
5
1
8
1
1
1
1
1
2
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.
COMMERCIAL TEMPERATURE RANGE
APRIL 2004
1
© 2004 Integrated Device Technology, Inc.
DSC 6544/9
IDTCV115-2
PROGRAMMABLEFLEXPC™CLOCKFORP4PROCESSOR
COMMERCIALTEMPERATURERANGE
PINCONFIGURATION
TESTMODESELECT(1)
If TEST_SEL sampled above 2V at VTT_PWRGD active LOW
VDD_PCI
VSS_PCI
1
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
PCI1
Pin38
(test_mode)
2
PCI0
CPU
REF/N
Hi-Z
SRC
REF/N REF/N REF REF/N REF/N
Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z
PCI/F REF DOT96 USB
PCI2
3
FS_A(REF1/PCI5)(3)
1
0
VDD_suspend
PCI3
(1)PCI4/Turbo1
4
5
FS_C/REF0
VSS_REF
XTAL_IN
XTAL_OUT
VDD_REF
SCL(2)
NOTE:
1. Once test clock operation has been invoked, TEST_MODE pin will select between
the Hi-Z and REF/N,
VSS_PCI
6
VDD_PCI
7
PCIF0/ITP_EN
PCIF1
8
9
PCIF2
VDD_48
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
SDA(2)
ITP_EN
FS_B/USB48MHz
VSS_48
CPUT0
ITP_EN
pin 35
CPUC2_ITP
SRCC7
pin 36
CPUT_ITP
SRCT7
CPUC0
1
0
DOT_96
VDD_CPU
DOT_96#
(2) VTT_PWRGD/PWRDWN#
CPUT1
CPUC1
VSS_CPU
SRCT1
SRCC1
IREF
VDD_SRC
Reset#
Turbo2(4)
VSS
SRCT2
CPU2_ITP/SRCT7
CPU2_ITP/SRCC7
VDD_SRC
SRCC2
SRCT3
SRCC3
SRCT6
SRCC6
SRCT5
SRCC5
VSS_SRC
VSS_GND
SRCT4_SATA
SRCC4_SATA
VDD_SRC
NOTES:
1. After power on, pin 5 is tristate (see Byte 30 and Byte 2).
2. ~ 130KΩ internal pull-up.
3. After power on, REF1/PCI5 is tristate (see Byte 1).
4. Disabled at power on.
SSOP
TOP VIEW
HWFREQUENCYSELECTIONTABLE
FSC, B, A
101
CPU
100
SRC4_SATA
SRC[3:1],SCR[7:5]
PCI
USB
DOT
96
REF
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
33.3
33.3
33.3
33.3
33.3
33.3
33.3
33.3
48
48
48
48
48
48
48
48
14.318
14.318
14.318
14.318
14.318
14.318
14.318
14.318
001
133
96
011
166
96
010
200
96
000
266
96
100
333
96
110
400
96
111
Reserve
96
2
IDTCV115-2
COMMERCIALTEMPERATURERANGE
PROGRAMMABLEFLEXPC™ CLOCKFORP4PROCESSOR
PINDESCRIPTION
Pin Number
Name
VDD_PCI
VSS_PCI
PCI2
Type
PWR
GND
OUT
OUT
OUT
Description
1
2
3
4
5
3.3V
GND
PCI clock
PCI clock
PCI3
PCI4/Turbo1
PCIclockoutputorTurboinput. Byte30,bit3modeselection. Byte30,bit3=1,PCIclock. 0=Turbo
mode. In Turbo mode, 1 = load TCN and TPN into CPU and SRC PLL.
6
7
VSS_PCI
VDD_PCI
GND
PWR
I/0
GND
3.3V
8
PCIF0/ITP_EN
PCIF1
PCI clock, free running. CPU_2 select (sampled at VTT_PWRGD assertion), HIGH = CPU_2.
9
OUT
OUT
PWR
I/O
PCI clock,
10
11
12
13
14
15
16
PCIF2
PCI clock,
VDD_48
3.3V
FS_B/USB48
VSS_48
CPU Frequency selection. 48MHz afterward.
GND
GND
OUT
OUT
I/O
DOT_96T
96MHz0.7Vcurrentmodedifferentialclockoutput
96MHz0.7Vcurrentmodedifferentialclockoutput
DOT_96C
VTT_PWRGD/PWRDWN#
3.3V LVTTL input is a level-sensitive strobe used to latch the FS_A, FS_B, FS_C/TEST_SEL and
PCIF_0/ITP_EN inputs. After VTT_PWRGD assertion, active HIGH, becomes a real-time input for
asserting power down (active LOW). Internal pull HIGH.
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
SRCT1
SRCC1
OUT
OUT
PWR
GND
OUT
OUT
OUT
OUT
GND
OUT
OUT
PWR
GND
OUT
OUT
OUT
OUT
PWR
OUT
OUT
I N
DifferentialSerialreferenceclock
DifferentialSerialreferenceclock
VDD_SRC
VSS
3.3V
GND
SRCT2
DifferentialSerialreferenceclock
SRCC2
DifferentialSerialreferenceclock
SRCT3
DifferentialSerialreferenceclock
SRCC3
DifferentialSerialreferenceclock
VSS
GND
SRCT4_SATA
SRCC4_SATA
VDD_SRC
VSS_SRC
SRCC5
SATA clock
SATA clock
3.3V
GND
DifferentialSerialreferenceclock
SRCT5
DifferentialSerialreferenceclock
SRCC6
DifferentialSerialreferenceclock
SRCT6
DifferentialSerialreferenceclock
VDD_SRC
CPUC2_ITP/ SRCC7
CPUT2_ITP/ SRCT7
Turbo2
3.3V
Selectable CPU or SRC differential clock output. ITP_EN=0 @ VTT_PWRGD assertion = SRC_7
Selectable CPU or SRC differential clock output. ITP_EN=0 @ VTT_PWRGD assertion = SRC_7
Load TCN2 into CPU PLL. Disabled at power on (see Byte 26).
Resetoutput
Reset#
OUT
OUT
GND
OUT
OUT
PWR
OUT
OUT
I/O
IREF
Referencecurrentfordifferentialoutputbuffer
GND
VSS
CPUC1
Host0.7Vcurrentmodedifferentialclockoutput
Host0.7Vcurrentmodedifferentialclockoutput
3.3V
CPUT1
VDD_CPU
CPUC0
Host0.7Vcurrentmodedifferentialclockoutput
Host0.7Vcurrentmodedifferentialclockoutput
SMBus data
CPUT0
SDA
3
IDTCV115-2
PROGRAMMABLEFLEXPC™CLOCKFORP4PROCESSOR
COMMERCIALTEMPERATURERANGE
PINDESCRIPTION(CONT.)
Pin Number
Name
Type
Description
47
48
49
50
51
52
53
54
SCL
VDD_REF
IN
PWR
OUT
IN
SMBus CLK
3.3V
XTAL_OUT
XTAL_IN
Xtaloutput
Xtalinput
GND
VSS_REF
GND
I/O
FS_C/REF0
VDD_Suspend
FS_A(REF1/PCI5)
CPUfrequencyselectioninputatVTT_PWRGD assertion. 14.318referenceclockoutputafterward.
Keep supply 3.3V in the power down
POWER
I/O
CPUfrequencyselectioninputatVTT_PWRGD assertion. 14.318orPCIreferenceclockoutputafterward,
SMBus selectable. Tristate atpoweron.
55
56
PCI0
PCI1
OUT
OUT
PCI clock
PCI clock
SMPROTOCOL
INDEXBLOCKWRITEPROTOCOL
INDEXBLOCKREADPROTOCOL
Mastercanstopreadinganytimebyissuingthestopbitwithoutwaiting
untilNthbyte(bytecountbit30-37).
Bit
1
# of bits
From
Master
Master
Slave
Description
1
8
1
8
1
8
1
8
1
8
1
Start
D2h
2-9
Bit
1
# of bits
From
Master
Master
Slave
Description
10
Ack (Acknowledge)
Registeroffsetbyte(startingbyte)
Ack (Acknowledge)
Byte count, N, (0 is not valid
Ack (Acknowledge)
firstdatabyte(Offsetdatabyte)
Ack (Acknowledge)
2nddatabyte
1
8
1
8
1
1
8
1
8
Start
D2H
11-18
19
Master
Slave
2-9
10
Ack (Acknowledge)
Registeroffsetbyte(startingbyte)
Ack (Acknowledge)
RepeatedStart
20-27
28
Master
Slave
11-18
19
Master
Slave
29-36
37
Master
Slave
20
Master
Master
Slave
21-28
29
D3H
38-45
46
Master
Slave
Ack (Acknowledge)
Ack (Acknowledge)
:
30-37
Slave
Byte count, N (block read back of N
bytes), Byte 8
38
39-46
47
1
8
1
8
Master
Slave
Master
Slave
Ack (Acknowledge)
firstdatabyte(Offsetdatabyte)
Ack (Acknowledge)
2nddatabyte
Master
Slave
Nthdatabyte
Acknowledge
Master
Stop
48-55
Ack (Acknowledge)
:
Master
Slave
Ack (Acknowledge)
Nthdatabyte
Notacknowledge
Stop
Master
INDEX BYTE READ
INDEX BYTE WRITE
Settingbit[11:18]=startingaddress. Afterreadingbackthe firstdata byte,
masterissuesStopbit.
Settingbit[11:18]=startingaddress,bit[20:27]=01h.
4
IDTCV115-2
COMMERCIALTEMPERATURERANGE
PROGRAMMABLEFLEXPC™ CLOCKFORP4PROCESSOR
CB1_[2:0], CB2_[2:0], CPU MODE
SELECTION
RESOLUTION
N Resolution (MHz)
0.666667
%
N =
150
150
125
150
100
125
150
150
CB[2:0]
101
CPU Mode, MHz
CPU = 100MHz mode
CPU = 133MHz mode
CPU = 166MHz mode
CPU = 200MHz mode
CPU = 266MHz mode
CPU = 333MHz mode
CPU = 400MHz mode
SRC (PCI Express)
0.67%
0.67%
0.8%
100
133
0.888889
001
1.333333
011
166
1.333333
0.67%
1.00%
0.8%
010
200
2.666667
000
266
2.666667
100
333
2.666667
0.67%
0.67%
0.666667
110
400
111
RESERVE
SSCMAGNITUDECONTROL
PCI
WhenByte5bit6=0
SMC[2:0]
000
%
OFF
PCIS[1:0]
PCI
33.33
36.36
40
001
-0.25
-0.5
00
01
10
11
010
011
±0.125
±0.25
±0.375
±0.5
100
101
110
111
±0.75
S_CBS[1:0], H_CBS[1:0] BAND
S_CNS, S_PNS, H_CNS,H_PNS N
SELECTION
SELECTION
CBS[1:0]
NS[1:0]
00
01
10
11
FS[C,B,A]
CB1_[2:0]
CB2_[2:0]
Don’tcare
00
01
10
11
Standard of Each CPU Mode (Band)
N Selection 1
N Selection 2
Don’tcare
S.E. CLOCK STRENGTH SELECTION (PCI, REF, USB48)
Str[1:0]
00
Multiple loads
Single loads
USB48
2L
1H
1L
Recommend
Recommend
01
Recommend
Recommend
10
11
2H
Recommend
Recommend
5
IDTCV115-2
PROGRAMMABLEFLEXPC™CLOCKFORP4PROCESSOR
COMMERCIALTEMPERATURERANGE
BYTE 0
Bit
Output(s)Affected
Description/Function
0
1
Type
Power On
7
CPUT2, CPUC2/
SRCT7, SRCC7
Outputenable
Tristate
Enable
RW
1
6
5
4
3
2
1
0
SRCT6, SRCC6
SRCT5, SRCC5
SRCT4, SRCC4 (SATA)
SRCT3, SRCC3
SRCT2, SRCC2
SRCT1, SRCC1
REF0 2x drive
Outputenable
Outputenable
Outputenable
Outputenable
Outputenable
Outputenable
2x drive enable
Tristate
Tristate
Tristate
Tristate
Tristate
Tristate
1x
Enable
Enable
Enable
Enable
Enable
Enable
2x
RW
RW
RW
RW
RW
RW
RW
1
1
1
1
1
1
1
BYTE 1
Bit
Output(s)Affected
Description/Function
0
1
Type
Power On
Recommended
7
6
5
4
3
2
1
0
DOT96T,DOT96C
Outputenable
Notbondedout
Outputenable
ModeSelect
Outputenable
Outputenable
Outputenable
Outputenable
Tristate
Tristate
Tristate
PCI5
Enable
Enable
Enable
REF1
RW
RW
RW
RW
RW
RW
RW
1
1
1
0
1
1
1
0
0
USB48
REF1/PCI5
REF0
Tristate
Tristate
Tristate
Tristate
Enable
Enable
Enable
Enable
CPUT1, CPUC1
CPUT0, CPUC0
REF1/PCI5
BYTE 2
Bit
Output(s)Affected
Description/Function
0
1
Type
Power On
7
6
5
4
3
2
1
0
PCI4
PCI3
Outputenable
Outputenable
Outputenable
Outputenable
Outputenable
Outputenable
Outputenable
Outputenable
Tristate
Tristate
Tristate
Tristate
Tristate
Tristate
Tristate
Tristate
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Enable
RW
RW
RW
RW
RW
RW
RW
RW
1
1
1
1
1
1
1
1
PCI2
PCI1
PCI0
PCIF2
PCIF1
PCIF0
BYTE 3
Bit
Output(s)Affected
Description / Function
0
1
Type
Power On
7
6
5
4
3
2
1
0
FSC latched value on power up
FSB latched value on power up
FSA latched value on power up
SRCT Pwrdwn drive mode
R
R
R
SRCT[7:1]
CPUT2
Driven in power down
Driven in power down
Driven in power down
Driven in power down
Driven in power down
Tristateinpowerdown
Tristateinpowerdown
Tristateinpowerdown
Tristateinpowerdown
Tristate
RW
RW
RW
RW
RW
0
0
0
0
0
CPUT2 Pwrdwn drive mode
CPUT1 Pwrdwn drive mode
CPUT0 Pwrdwn drive mode
DOT96powerdowndrive mode
CPUT1
CPUT0
DOT96T
6
IDTCV115-2
COMMERCIALTEMPERATURERANGE
PROGRAMMABLEFLEXPC™ CLOCKFORP4PROCESSOR
BYTE 4
Bit
Output(s)Affected
Description / Function
0
1
Type
Power On
7
6
5
4
3
2
1
0
PCIFStr1
PCIFStr0
PCIStrC1
PCIStrC0
REFStr1
PCIFstrengthselection
0
0
0
1
0
0
1
1
PCIstrengthselection
REFstrengthselection
REFStr0
48MHStr1
48MHzStr0
USB48MHz0strengthselection
BYTE 5
Bit
Output(s)Affected
Description / Function
0
1
Type
Power On
7
6
5
PCIPLLS
PCIS1
PCI PLL select
SATA PLL
PCI EX PLL
RW
RW
0
0
See PCIS table, only valid when
Byte5 bit 6 = 0 See PCIS Table
4
3
PCIS0
RW
RW
0
1
SMcontrolregisters
contents
During the Power Down
ResetSMtodefault
SMcontents have
no change
2
1
0
SATA_SMC2
SATA_SMC1
SATA_SMC0
SATAPLLspreadspectrum
magnitudecontrolselect
(see SMC table)
RW
RW
RW
0
1
0
BYTE 6
Bit
Output(s)Affected
Description / Function
0
1
Type
Power On
7
WDHRB
Hard Alarm read back,
reset by WD disable
R
6
WDSRB
SoftAlarmreadback,
rest by WD disable
R
5
4
3
2
1
0
SRC_SMC2
SRC_SMC1
SRC_SMC0
CPU_SMC2
CPU_SMC1
CPU_SMC0
SRC(PCIEXpress)
PLLspreadspectrummagnitude
control select (see SMC table)
CPU PLL spread spectrum
controlmagnitudeselect
RW
RW
RW
RW
RW
RW
0
1
0
1
0
0
(see SMC table)
BYTE 7
Bit
Output(s)Affected
Description / Function
0
1
Type
Power On
7
6
5
4
3
2
1
0
Revision ID
Revision ID
Revision ID
Revision ID
VendorID
VendorID
VendorID
VendorID
0
0
0
0
0
1
0
1
7
IDTCV115-2
PROGRAMMABLEFLEXPC™CLOCKFORP4PROCESSOR
COMMERCIALTEMPERATURERANGE
BYTE 8
Bit
Output(s)Affected
Description / Function
0
1
Type
Power On
7
6
5
4
3
2
1
0
RW
RW
RW
RW
RW
RW
RW
RW
0
0
0
1
1
1
1
1
BYTES 9 - 16 ARE DUMMY BITES
BYTE17
Bit
Output(s)Affected
Description / Function
0
1
Type
Power On
7
6
5
4
3
2
1
0
CB1_2
CB1_1
CB1_0
CPU PLL Band Selection 1
RW
RW
RW
RW
RW
RW
RW
RW
0
0
0
0
0
0
0
0
(see CPU Mode Selection table)
CB2_2
CB2_1
CPU PLL Band Selection 2
(see CPU Mode Selection table)
CB2_0
CN1_8 (MSB)
CPU PLL N selection 1
BYTE18
Bit
Output(s)Affected
Description / Function
0
1
Type
Power On
7
6
5
4
3
2
1
0
CN1_7
CN1_6
RW
RW
RW
RW
RW
RW
RW
RW
1
0
0
1
0
1
1
0
CN1_5
CPU PLL N selection 1
CPU Frequency = N * Resolution
(seeResolutiontable)
CN1_4
CN1_3
CN1_2
CN1_1
CN1_0 (LSB)
BYTE19
Bit
Output(s)Affected
Description / Function
0
1
Type
Power On
7
6
5
4
3
2
1
0
CN2_8 (MSB)
CN2_7
0
1
0
0
1
0
1
1
CN2_6
CPU N selection 2
CPU Frequency = N * Resolution
(seeResolutiontable)
CN2_5
CN2_4
CN2_3
CN2_2
CN2_1
8
IDTCV115-2
COMMERCIALTEMPERATURERANGE
PROGRAMMABLEFLEXPC™ CLOCKFORP4PROCESSOR
BYTE20
Bit
Output(s)Affected
Description / Function
0
1
Type
Power On
7
6
5
4
3
2
1
0
CN2_0 (LSB)
CPU N selection 2
0
0
0
0
0
0
0
1
PN1_8 (MSB)
PN1_7
RW
RW
BYTE21
Bit
Output(s)Affected
Description / Function
0
1
Type
Power On
7
6
5
4
3
2
1
0
PN1_6
PN1_5
RW
RW
RW
RW
RW
RW
RW
RW
0
0
1
0
1
1
0
0
PN1_4
SRC PLL (PCI Express)
N Selection 1
PN1_3
PN1_2
SRC Frequency = N * Resolution
Resolution=0.666667
PN1_1
PN1_0 (LSB)
PN2_8 (MSB)
BYTE22
Bit
Output(s)Affected
Description / Function
0
1
Type
Power On
7
6
5
4
3
2
1
0
PN2_7
PN2_6
RW
RW
RW
RW
RW
RW
RW
RW
1
0
0
1
0
1
1
0
PN2_5
SRC PLL (PCI Express)
N Selection 1
PN2_4
PN2_3
SRC Frequency = N * Resolution
Resolution=0.666667
PN2_2
PN2_1
PN2_0 (LSB)
BYTE23
Bit
Output(s)Affected
Description / Function
0
1
Type
Power On
7
S_CBS1
Soft Alarm CPU PLL mode
select (see S_CBS Band
RW
0
6
5
4
3
S_CBS0
S_CNS1
S_CNS0
S_PNS1
SelectionTable)
RW
RW
RW
RW
0
0
0
0
Soft Alarm CPU PLL N select
(see S_CNS N Selection Table)
Soft Alarm SRC PLL (PCI
Express) N select
2
1
0
S_PNS0
(see S_PNS N Selection Table)
RW
0
0
0
9
IDTCV115-2
PROGRAMMABLEFLEXPC™CLOCKFORP4PROCESSOR
COMMERCIALTEMPERATURERANGE
BYTE24
Bit
Output(s)Affected
Description / Function
0
1
Type
Power On
7
6
5
4
3
H_CBS1
H_CBS0
H_CNS2
H_CNS0
H_PNS1
Hard Alarm CPU PLL mode select
(see H_CBS Band Selection table)
Hard Alarm CPU PLL N select
(see H_CNS N Selection table)
Hard Alarm SRC PLL
RW
RW
RW
RW
RW
0
0
0
0
0
(PCI Express) N select
2
1
0
H_PNS0
(see H_PNS N selection table)
RW
0
0
0
BYTE25
Bit
Output(s)Affected
Description / Function
0
1
Type
Power On
7
6
5
4
3
2
1
0
WD Timer 7 (MSB)
WDTimer6
HardAlarmtimer
RW
RW
RW
RW
RW
RW
RW
RW
0
0
0
0
1
0
1
1
Defaultis11*290ms
WDTimer5
WDTimer4
WDTimer3
WDTimer2
WDTimer1
WD Timer 0 (LSB)
BYTE26
Bit
Output(s)Affected
Description / Function
0
1
Type
Power On
7
6
5
4
3
2
1
0
Turbo2
TurboEnable
Disable
Enable
RW
RW
RW
RW
RW
RW
RW
RW
0
0
0
0
0
0
0
1
Soft Timer 3 (MSB)
SoftTimer2
Softalarmtimer
SoftTimer1
Soft Timer 0 (LSB)
BYTE27
Bit
Output(s)Affected
Description / Function
0
1
Type
Power On
7
6
5
4
3
2
1
WatchDogEnable
WatchDogEnable
Disable
Enable
RW
0
0
0
0
0
0
0
SoftAlarmEnable
Soft RESET#
SoftAlarmEnable
SoftResetEnable
Hard Alarm Enable
HardResetEnable
Relatch FS[C, B, A]
at Hard Alarm
Disable
Disable
Disable
Disable
Disable
Enable
SoftResetEnable
Enable
RW
RW
RW
RW
RW
Hard Alarm Enable
Hard RESET#
Hard Alarm FS
RelatchEnable
TCN8 (MSB)
HardResetEnable
Relatch
0
RW
0
10
IDTCV115-2
COMMERCIALTEMPERATURERANGE
PROGRAMMABLEFLEXPC™ CLOCKFORP4PROCESSOR
BYTE28
Bit
Output(s)Affected
Description / Function
0
1
Type
Power On
7
6
5
4
3
2
1
0
TCN7
TCN6
RW
RW
RW
RW
RW
RW
RW
RW
1
0
0
1
0
1
1
0
TCN5
Turbo CPU PLL N setting
CPU Frequency = N * Resolution
(seeResolutiontable)
TCN4
TCN3
TCN2
TCN1
TCN0 (LSB)
BYTE29
Bit
Output(s)Affected
Description / Function
0
1
Type
Power On
7
6
5
4
3
2
1
0
TPN8 (MSB)
TPN7
0
1
0
0
1
0
1
1
TPN6
Turbo SRC PLL N setting
SRC Frequency = N * Resolution
Resolution=0.666667
TPN5
TPN4
TPN3
TPN2
TPN1
BYTE30
Bit
Output(s)Affected
Description / Function
0
1
Type
Power On
7
6
5
TPN0 (LSB)
TCN28
0
0
0
Test Modeentrycontrol
Normaloperation
Testmode,
controlled by byte 30 bit 4
REF/N mode
4
3
2
1
Only valid when Byte6 bit5 is high
PCI4/TurboModeselect
Hi-Z
0
0
0
0
PCI4/Turbo1
Turbo1
Turbo1
Disable
normal
PCI4
RW
RW
RW
Enable
Test_scl
Onchiptestmodeenable
CLKoutputsenable
SCLK=1, CLK outputs=1
SCLK=0, CLK outputs=0
CLKoutputs=Tristate
0
Test_hiz
normal
RW
0
BYTE31
Bit
Output(s)Affected
Description / Function
0
1
Type
Power On
7
6
5
4
3
2
1
0
TCN27
TCN26
TCN25
TCN24
TCN23
TCN22
TCN21
TCN20
1
0
0
1
0
1
1
0
Turbo CPU PLL N setting
11
IDTCV115-2
PROGRAMMABLEFLEXPC™CLOCKFORP4PROCESSOR
COMMERCIALTEMPERATURERANGE
PLLFREQUENCYPROGRAMMINGPROCEDURES
The user changes PLL frequency through Soft Alarm or Hard Alarm. The Watch Dog circuit has to be enabled. Based on their application, the user may
enable either one or both of the alarms.
User presets the CPU PLL Mode and N, and SRC PLL N value:
1. Set CPU PLL Mode, CB1 and CB2, byte17
2. Set CPU PLL N, CN1 and CN2, byte18 and byte19
3. Set SRC(PCI Express) PLL N, PN1 and PN2, byte21, 22
Userselects thefrequencyforSoftAlarmandHardAlarm,ifenabledrespectively:
4. SelectSoftAlarmfrequency,byte23
5. SelectHardAlarmfrequency,byte24
UsersetstheTimerandenablestheWDcircuitforfrequencyswitch:
6. SetHardAlarmTimer, byte25
7. SetSoftAlarmTimer,byte26
8. Enable Soft and Hard Alarm and RESET# bit (If user needs RESET# signal to reset the system), byte27
9. EnableWatchDog(WDE),byte27
•
•
•
Soft Reset# and Hard Reset# are valid only if Soft Alarm and Hard Alarm are enabled respectively.
WDEDisableresetsWDSRBandWDHRB.
PCI CLK is selectable from SRC PLL or SATA PLL, byte5 bit6. If from SRC PLL, PCI frequency = 1/3 of SRC frequency. If from SATA, PCI is
fixedto3selections, 33MHz, 36MHzand40MHz, byte5bit[5:4].
WD SOFT AND HARD ALARM/TIME OUT OPERATION
WD HARD ALARM TIMER [7:0]
WD SOFT ALARM TIMER [3:0]
WDE
If Hard Alarm Enabled (byte 27):
Set WDHRB (byte 6)
If Soft Alarm Enabled (byte 27):
Set WDSRB (byte 6)
Trigger Watch Dog Circuit
Load CPU N and Band selections into PCU PLL
Load SRC N selections into SRC PLL
Load CPU N and Mode
selections into PCU PLL
Load SRC N selection
into SRC PLL
If Hard Reset# Enabled (byte 27):
Issue RESET#
If Soft Reset# Enabled (byte 27):
Issue RESET#
If Hard Alarm Relatch Enabled:
Latch FSC, B, A
12
IDTCV115-2
COMMERCIALTEMPERATURERANGE
PROGRAMMABLEFLEXPC™ CLOCKFORP4PROCESSOR
ELECTRICAL CHARACTERISTICS - INPUT / SUPPLY / COMMON OUTPUT
PARAMETERS
FollowingConditionsApplyUnlessOtherwiseSpecified:
Operating Condition: TA = 0°C to +70°C, Supply Voltage: VDD = 3.3V ± 5%
Symbol
VIH
Parameter
Input HIGH Voltage
Input LOW Voltage
Test Conditions
Min.
2
Typ.
—
Max.
Unit
V
3.3V ± 5%
3.3V ± 5%
VDD + 0.3
VIL
VSS - 0.3
0.7
VSS - 0.3
–5
—
0.8
V
VIH_FS
VIL_FS
IIL
FS Input HIGH Voltage
FS Input LOW Voltage
Input LeakageCurrent
Operating Supply Current
Powerdown Current
For FSA.B.C and Test_Mode
For FSA.B.C and Test_Mode
0< VIN < VDD, no internal pull-up or pull-down
Full active, CL = full load
—
VDD + 0.3
V
—
0.35
+5
400
70
12
—
7
V
—
mA
mA
mA
IDD3.3OP
IDD3.3PD
—
—
All differential pairs driven
All differential pairs tri-stated
VDD = 3.3V
—
—
—
—
(1)
FI
Input Frequency
—
14.31818
—
MHz
nH
LPIN
Pin Inductance(2)
—
CIN
Logic inputs
—
—
5
COUT
CINX
TSTAB
Input Capacitance(2)
Clock Stabilization(2,3)
Output pin capacitance
—
—
6
pF
X1 and X2 pins
—
—
5
From VDD power-up or de-assertion of PD# to first clock
Triangular modulation
—
—
1.8
33
15
300
5
ms
KHz
ns
(2)
Modulation Frequency
30
—
(2)
TDRIVE_SRC
SRC output enable after PCI_Stop# de-assertion
CPU output enable after PD# de-assertion
Fall time of PD#
—
—
TDRIVE_PD#(2)
—
—
us
TFALL_PD#(2)
—
—
ns
TRISE_PD#(3)
Rise time of PD#
—
—
5
ns
TDRIVE_CPU_Stop#(2)
TFALL_CPU_Stop#(2)
TRISE_CPU_Stop#(3)
CPU output enable after CPU_Stop# de-assertion
Fall time of PD#
—
—
10
5
us
—
—
ns
Rise time of PD#
—
—
5
ns
NOTES:
1. Input frequency should be measured at the REF output pin and tuned to ideal 14.31818MHz to meet ppm frequency accuracy on PLL outputs.
2. This parameter is guaranteed by design, but not 100% production tested.
3. See TIMING DIAGRAMS for timing requirements.
13
IDTCV115-2
PROGRAMMABLEFLEXPC™CLOCKFORP4PROCESSOR
COMMERCIALTEMPERATURERANGE
ELECTRICAL CHARACTERISTICS - CPU, SRC, AND DOT96 0.7 CURRENT MODE
DIFFERENTIALPAIR(1)
FollowingConditionsApplyUnlessOtherwiseSpecified:
Operating Condition: TA = 0°C to +70°C, Supply Voltage: VDD = 3.3V ± 5%; CL = 2pF
Symbol
ZO
Parameter
Test Conditions
Min.
3000
2.4
Typ.
—
—
—
—
—
—
—
—
—
Max.
—
Unit
Ω
Current Source Output Impedance(2) VO = VX
VOH3
VOL3
Output HIGH Voltage
Output LOW Voltage
IOH = -1mA
IOL = 1mA
—
V
—
0.4
V
(2)
VHIGH
VLOW
VOVS
Voltage HIGH
Statistical measurement on single-ended signal using
oscilloscope math function
660
–150
—
850
150
1150
—
mV
(2)
Voltage LOW
Max Voltage(2)
Min Voltage(2)
Measurement on single-ended signal using absolute value
mV
VUDS
–300
250
—
VCROSS(ABS) Crossing Voltage (abs)(2)
550
140
mV
mV
ppm
d - VCROSS
ppm
Crossing Voltage (var)(2)
Variation of crossing over all edges
(2,3)
Long Accuracy
See TPERIOD Min. - Max. values
400MHz nominal/spread
–300
—
—
—
—
300
2.4993
2.9991
3.7489
2.5008
3.0009
3.7511
333.33MHz nominal/spread
266.66MHz nominal/spread
TPERIOD
Average Period(3)
200MHz nominal/spread
4.9985
—
5.0015
ns
166.66MHz nominal/spread
133.33MHz nominal/spread
100MHz nominal/spread
5.9982
7.4978
9.997
—
—
—
6.0018
7.5023
10.003
96MHz nominal
10.4135
2.4143
2.9141
3.6639
—
—
—
—
10.4198
—
400MHz nominal/spread
333.33MHz nominal/spread
266.66MHz nominal/spread
—
—
200MHz nominal/spread
4.9135
5.9132
—
—
—
—
TABSMIN
Absolute Min Period(2,3)
166.66MHz nominal/spread
ns
133.33MHz nominal/spread
100MHz nominal/spread
7.4128
9.912
—
—
—
—
96MHz nominal
10.1635
175
175
—
—
—
—
—
—
—
—
—
—
700
700
125
125
55
tR
tF
Rise Time(2)
VOL = 0.175V, VOH = 0.525V
VOL = 0.175V, VOH = 0.525V
ps
ps
ps
ps
%
ps
ps
Fall Time(2)
d-tR
Rise Time Variation(2)
Fall Time Variation(2)
Duty Cycle(2)
d-tF
—
dT3
Measurement from differential waveform
VT = 50%
45
(2)
tSK3
Skew
—
100
85
tJCYC-CYC
NOTES:
Jitter, Cycle to Cycle(2)
Measurement from differential waveform
—
1. SRC clock outputs run only at 100MHz or 200MHz. Specs for 133.33 and 166.66 do not apply to SRC clock pair.
2. This parameter is guaranteed by design, but not 100% production tested.
3. All long term accuracy and clock period specifications are guaranteed with the assumption that the REF output is at 14.31818MHz.
14
IDTCV115-2
COMMERCIALTEMPERATURERANGE
PROGRAMMABLEFLEXPC™ CLOCKFORP4PROCESSOR
ELECTRICAL CHARACTERISTICS - PCICLK / PCICLK_F
FollowingConditionsApplyUnlessOtherwiseSpecified:
Operating Condition: TA = 0°C to +70°C, Supply Voltage: VDD = 3.3V ± 5%; CL = 10 - 30pF
Symbol
Parameter
Test Conditions
See Tperiod Min. - Max. values
33.33MHzoutputnominal
33.33MHzoutputspread
IOH = -1mA
Min.
—
Typ.
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Max.
300
30.009
30.1598
—
Unit
ppm
ns
(1,2)
ppm
LongAccuracy
ClockPeriod(2)
TPERIOD
29.991
29.991
2.4
—
VOH
VOL
IOH
OutputHIGHVoltage
OutputLOWVoltage
Output HIGH Current
V
V
IOL = 1mA
0.55
—
VOH at Min. = 1V
VOH at Max. = 3.135V
VOL at Min. = 1.95V
VOL at Max. = 0.4V
Risingedgerate
-33
—
mA
-33
—
IOL
OutputLOWCurrent
30
mA
—
38
EdgeRate(1)
EdgeRate(1)
RiseTime(1)
FallTime(1)
1
4
V/ns
V/ns
ns
Fallingedgerate
1
4
tR1
tF1
VOL = 0.4V, VOH = 2.4V
VOL = 0.4V, VOH = 2.4V
VT = 1.5V
0.5
0.5
45
2
2
ns
dT1
Duty Cycle(1)
55
%
(1)
tSK1
Skew
VT = 1.5V
—
500
250
ps
(1)
tJCYC-CYC
Jitter
VT = 1.5V
—
ps
NOTES:
1. This parameter is guaranteed by design, but not 100% production tested.
2. All long term accuracy and clock period specifications are guaranteed with the assumption that the REF output is at 14.31818MHz.
ELECTRICALCHARACTERISTICS,48MHZ,USB
FollowingConditionsApplyUnlessOtherwiseSpecified:
Operating Condition: TA = 0°C to +70°C, Supply Voltage: VDD = 3.3V ± 5%; CL = 10 - 20pF
Symbol
Parameter
Test Conditions
Min.
—
20.8257
2.4
—
-33
—
30
Typ.
—
—
—
—
—
—
—
—
—
—
—
—
—
Max.
300
20.834
—
0.55
—
-33
—
38
Unit
ppm
ns
(1,2)
ppm
LongAccuracy
See Tperiod Min. - Max. values
48MHzoutputnominal
IOH = -1mA
TPERIOD
VOH
ClockPeriod(2)
OutputHIGHVoltage
OutputLOWVoltage
Output HIGH Current
V
VOL
IOL = 1mA
V
IOH
VOH at Min. = 1V
VOH at Max. = 3.135V
VOL at Min. = 1.95V
VOL at Max. = 0.4V
Risingedgerate
mA
IOL
OutputLOWCurrent
mA
—
1
EdgeRate(1)
EdgeRate(1)
RiseTime(1)
FallTime(1)
2
V/ns
V/ns
ns
Fallingedgerate
1
2
tR1
tF1
VOL = 0.4V, VOH = 2.4V
VOL = 0.4V, VOH = 2.4V
VT = 1.5V
1
2
1
2
ns
dT1
Duty Cycle(1)
45
55
%
NOTES:
1. This parameter is guaranteed by design, but not 100% production tested.
2. All long term accuracy and clock period specifications are guaranteed with the assumption that the REF output is at 14.31818MHz.
15
IDTCV115-2
PROGRAMMABLEFLEXPC™CLOCKFORP4PROCESSOR
COMMERCIALTEMPERATURERANGE
ELECTRICALCHARACTERISTICS-REF-14.318MHZ
FollowingConditionsApplyUnlessOtherwiseSpecified:
Operating Condition: TA = 0°C to +70°C, Supply Voltage: VDD = 3.3V ± 5%; CL = 10 - 20pF
Symbol
ppm
TPERIOD
VOH
VOL
Parameter
Test Conditions
Min.
—
Typ.
—
—
—
—
—
—
—
—
—
—
—
Max.
300
69.855
—
Unit
ppm
ns
(1)
LongAccuracy
See Tperiod Min. - Max. values
14.318MHzoutputnominal
IOH = -1mA
Clock Period
69.827
2.4
—
OutputHIGHVoltage(1)
OutputLOWVoltage(1)
Output HIGH Current(1)
OutputLOWCurrent(1)
RiseTime(1)
V
IOL = 1mA
0.4
-23
29
V
IOH
VOH at Min. = 1V, VOH at Max. = 3.135V
VOL at Min. = 1.95V, VOL at Max. = 0.4V
VOL = 0.4V, VOH = 2.4V
VOL = 0.4V, VOH = 2.4V
VT = 1.5V
-29
27
mA
mA
ns
IOL
tR1
1
2
tF1
FallTime(1)
1
2
ns
(1)
tSK1
Skew
—
500
55
ps
dT1
Duty Cycle(1)
VT = 1.5V
45
%
(1)
tJCYC-CYC
Jitter
VT = 1.5V
—
1000
ps
NOTE:
1. This parameter is guaranteed by design, but not 100% production tested.
16
IDTCV115-2
COMMERCIALTEMPERATURERANGE
PROGRAMMABLEFLEXPC™ CLOCKFORP4PROCESSOR
PD#, POWER DOWN
PD# is an asynchronous active low input used to shut off all clocks cleanly prior to clock power. When PD# is asserted low all clocks will be driven low
beforeturningofftheVCO.InPD#de-assertionallclockswillstartwithoutglitches.
PWRDWN#
CPU
Normal
CPU#
Normal
Float
SRC
Normal
SRC#
Normal
Float
PCIF/PCI
33MHz
Low
USB
48MHz
Low
DOT96
Normal
DOT96#
Normal
Float
REF
14.318MHz
Low
1
0
IREF * 2 or float
IREF * 2 or float
IREF * 2 or float
PD#ASSERTION
PD#shouldbe sampledlowbytwoconsecutive CPU#risingedges before stoppingclocks.Allsingle-endedclocks willbe heldlowontheirnexthighto
lowtransition. Alldifferentialclockswillbeheldhighonthenexthightolowtransitionofthecomplimentaryclock.Ifthecontrolregisterdeterminingtodrive
modeissetto‘tri-state’,thedifferentialpairwillbestoppedintri-statemode,undriven. WhenthedrivemodebutcorrespondingtotheCPUorSRCclockof
interestis setto‘0’thetrueclockwillbedrivenhighat2xIREF andthecomplementaryclockwillbetristated.Ifthecontrolregisteris programmedto‘1’both
clockswillbetristated.
PWRDWN#
CPU 133MHz
CPU# 133MHz
SRC 100MHz
SRC# 100MHz
USB 48MHz
PCI 33MHz
REF 14.31818
17
IDTCV115-2
PROGRAMMABLEFLEXPC™CLOCKFORP4PROCESSOR
COMMERCIALTEMPERATURERANGE
PD#DE-ASSERTION
Thetimefromthede-assertionofPD#oruntilpowersupplyrampstogetstableclockswillbelessthan1.8ms.IfthedrivemodecontrolbitforPD#tristate
isprogrammedto‘1’thestoppeddifferentialpairmustfirstbedrivenhightoaminimumof200mVinlessthan300µs ofPD#deassertion.
tSTABLE <1.8mS
PWRDWN#
CPU 133MHz
CPU# 133MHz
SRC 100MHz
SRC# 100MHz
USB 48MHz
PCI 33MHz
REF 14.31818
tDRIVE_PWRDWN#
<300μS, <200mV
18
IDTCV115-2
COMMERCIALTEMPERATURERANGE
PROGRAMMABLEFLEXPC™ CLOCKFORP4PROCESSOR
ORDERINGINFORMATION
XXX
IDTCV
Device Type
XX
Package
X
Grade
Blank
Commercial Temperature Range
(0°C to +70°C)
Small Shrink Outline Package
SSOP - Green
PV
PVG
Programmable FlexPC™ Clock for P4 Processor
115-2
CORPORATE HEADQUARTERS
6024 Silver Creek Valley Road
San Jose, CA 95138
for SALES:
800-345-7015 or 408-284-8200
fax: 408-284-2775
www.idt.com
for Tech Support:
logichelp@idt.com
19
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