IDTCV193CPVG8 [IDT]
PROGRAMMABLE FLEXPC LP/S CLOCK FOR INTEL BASED SYSTEMS; 可编程FLEXPC LP / S时钟为基于Intel的系统
| 型号： | IDTCV193CPVG8 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | PROGRAMMABLE FLEXPC LP/S CLOCK FOR INTEL BASED SYSTEMS |
| 文件： | 总21页 (文件大小：177K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PROGRAMMABLE FLEXPC
LP/S CLOCK FOR INTEL BASED
SYSTEMS
IDTCV193
ADVANCE
INFORMATION
FEATURES:
KEYFEATURES
• Compliant with Intel CK505 Gen II spec
• One high precision PLL for CPU, SSC and N programming
• One high precision PLL for SRC, SSC and N programming
• One high precision PLL for SATA/PCI, and SSC
• One high precision PLL for 96MHz/48MHz
• Push-pull IOs for differential outputs
• Direct CPU and SRC clock frequency programming—write the
Hex number into Byte [16:18], 1MHz stepping.
• Linear and smooth transition for the CPU and SRC frequency
programming.
• SATA PLL source hardware select latch pin, PLL2 or PLL4.
• Internal serial resistor hardware enable latch pin.
• Support spread spectrum modulation, –0.5 down spread and • WOL 25MHz support.
others
• Support SMBus block read/write, byte read/write
• Available in TSSOP package
OUTPUTS:
KEY SPECIFICATIONS:
• 2 - 0.7V differential CPU CLK pair
• 10 - 0.7V differential SRC CLK pair
• 1 - CPU_ITP/SRC differential clock pair
• 1 - SRC0/DOT96 differential clock pair
• 6 - PCI, 33.3MHz
• CPU/SRC CLK cycle to cycle jitter < 85ps
• PCI CLK cycle to cycle jitter < 500ps
• All SRC, SRC[0:11] phase noise < 3.10s RMS, PCIE Gen II
phase noise requirement.
• SRC3, 4, 6, 7, designated PCIE Gen II outputs, nominal
interpair skew = 0 ps
• 1 - 48MHz
• 1 - REF
• 1 - SATA
FUNCTIONALBLOCKDIAGRAM
REF
PLL1
SSC
N Programmable
XTAL_IN
XTAL
CPU[1:0]
CPU
Output Buffer
Stop Logic
Osc Amp
XTAL_OUT
CPU_ITP/SRC8
SDATA
SM Bus
PLL3
SSC
SRC1/25MHz/24.576MHz
PCI[4:0], PCIF5
Controller
PCI/SATA
SRC CLK
SCLK
Output Buffer
Stop Logic
SATA/SRC2
PLL4
SSC
N Programmable
SRC CLK
Output Buffer
Stop Logic
SRC[7:3], [11:9]
CKPWRGD/PD#
CPU_STOP#
PCI_STOP#
SRC5_EN
48MHz
Control
ITP_EN
Logic
Fixed PLL
PLL2
48MHz/96MHz
Output BUffer
CR_[H:A]#
DOT96/SRC0
FSC,B,A
SATA_SEL
SR_ENABLE
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.
COMMERCIAL TEMPERATURE RANGE
APRIL 8, 2009
IDT CONFIDENTIAL
1
© 2005 Integrated Device Technology, Inc.
DSC 7165
IDTCV193
PROGRAMMABLEFLEXPCCLOCKFORP4PROCESSOR
COMMERCIALTEMPERATURERANGE
PINCONFIGURATION
64
63
62
61
60
59
1
PCI0/ CR#_A
Vdd_PCI
SCL
SDA
2
3
REF / FS_C / TestSel
Vdd_REF
PCI1/CR#_B
*PCI2/SR_ENABLE
**PCI3/SATA_SEL
PCI4/ SRC5_EN
PCIF5/ ITP_EN
4
5
Xtal_In
6
Xtal_Out
7
58 Vss_REF
8
57
56
55
54
53
FS_B / TestMode
CKPWRGD/PD#
Vdd_CPU
VSS_PCI
Vdd_48
9
USB 48 / FS_A
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
CPUT0
Vss_48
Vdd_IO
CPUC0
52 Vss_CPU
SRCT0 / DOT96T
SRCC0 / DOT96C
VSS_IO
51
50
49
48
CPUT1
CPUC1
Vdd_PLL3
Vdd_CPU_IO
Sel_SRC1_25_24.576**
SRCT1/25MHz0
SRCC1/25MHz1/24.576MHz
47 SRCT8 /CPU_ ITPT
SRCC8 /CPU_ ITPC
45 Vdd_SRC_IO
Vss_PLL3
Vdd_PLL3_IO
SRCT2/SATA
46
44
43
42
41
40
39
38
37
36
35
34
33
SRCT7/ CR#_F
SRCC7/ CR#_E
SRCC2/SATA
Vss_SRC
Vss_SRC
SRCT6
SRCT3 / CR#_C
SRCC3 / CR#_D
SRCC6
Vdd_SRC
Vdd_SRC_IO
SRCT4
PCI_Stop#/ SRCT5
CPU_Stop#/ SRCC5
SRCC4
Vdd_SRC_IO
SRCC10
Vss_SRC
SRCT9
SRCT10
SRCC9
SRCT11/ CR#_H
SRCC11/CR#_G
* Internal 100k pull high
** Internal 100k pull low
TSSOP
TOP VIEW
IDT CONFIDENTIAL
2
IDTCV193
COMMERCIALTEMPERATURERANGE
PROGRAMMABLEFLEXPCCLOCKFORP4PROCESSOR
PINDESCRIPTION
Pin #
Name
Type
Description
1
PCI0/CR#_A
I/O
33.33MHz. SRC0,2 Differentialclockoutputenable,controlSRC0andSRC2,0=enable.Modeisselected
by SMBus control register. Default is PCI clock mode.
2
3
VDD_PCI
PWR
I/O
3.3V
PCI1/CR#_B
33.33MHz. SRC1,4 Differentialclockoutputenable,controlSRC1andSRC4,0=enable.Modeisselected
by SMBus control register. Default is PCI clock mode.
4
PCI2/SRC_ENABLE
PCI3/SATA_SEL
PCI4/SRC5_EN
PCIF5/ITP_EN
VSS_PCI
I/O
OUT
I/O
Power on latch, high, internal 33 ohm resistor enabled. Low, disabled. Afterward 33.33MH
5
Power on Latch, high, SATA from PLL2. Low, SATA from PLL4 (as SRC clock). Afterward, 33.33MHz
6
33.33MHz. Pin 37, 38 mode selection. Power on latch, HIGH = SRC5, LOW = CPU and PCI Stop#.
7
I/O
33.33MHz. Pin 46, 47 mode selection. Power on latch, HIGH = CPU_ITP, LOW = SRC8.
8
GND
PWR
I/O
GND
9
VDD_48
3.3V
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
USB 48/FS_A
VSS_48
48MHz, frequency select, power on latch
GND
PWR
OUT
OUT
GND
PWR
OUT
OUT
GND
PWR
OUT
OUT
GND
I/O
GND
VDD_IO
1.05 ~ 3.3V
SRCT0/DOT96T
SRCC0/DOT96C
VSS_IO
Differential output clock. SRC or DOT96. Mode selected by SMBus control register, default is SRC0.
Differential output clock. SRC or DOT96. Mode selected by SMBus control register, default is SRC0.
GND
VDD_PLL3
3.3V
SRCT1/25MHz
SRCC1/25MHz1/24.576MHz
VSS_PLL3
SRC or 25MHz, mode selected by pin 48, Sel_SRC1_25_24.576
SRC or 25Mhz or 24.576MHz, mode selected by pin 48, Sel_SRC1_25_24.576
GND
VDD_PLL3_IO
SATAT/SRCT2
SATAC/SRCC2
VSS_SRC
1.05 ~ 3.3V
Differentialoutputclock
Differentialoutputclock
GND
SRCT3/CR#_C
SRC clock. SRC differential clock output enable, control SRC0 and SRC2, 0 = enable. Mode selected by
SMBus control register. Default is SRC3.
25
SRCC3/CR#_D
I/O
SRC clock. SRC differential clock output enable, control SRC1 and SRC4, 0 = enable. Mode selected by
SMBus control register. Default is SRC3.
26
27
28
29
30
31
32
VDD_SRC_IO
SRCT4
PWR
OUT
OUT
GND
OUT
OUT
I/O
1.05 ~ 3.3V
Differentialoutputclock
Differentialoutputclock
GND
SRCC4
VSS_SRC
SRCT9
Differentialoutputclock
Differentialoutputclock
SRCC9
SRCC11/CR#_G
SRCclock. SRCdifferentialclockoutputenable,controlSRC9,0=enable.ModeselectedbySMBuscontrol
register.DefaultisSRC11.
33
SRCT11/CR#_H
I/O
SRCclock. SRCdifferentialclockoutputenable,controlSRC10,0=enable.ModeselectedbySMBuscontrol
register.DefaultisSRC11.
34
35
36
37
38
39
40
41
42
SRCT10
SRCC10
OUT
OUT
PWR
I/O
Differentialoutputclock
Differentialoutputclock
VDD_SRC_IO
CPU_Stop#/SRCC5
PCI_Stop#/SRCT5
VDD_SRC
1.05 ~ 3.3V
CPU stop, LOW = stop. SRC clock. Mode selected by pin6, SRC5_EN.
I/O
PCI stop, LOW = stop. SRC clock. Mode selected by pin6, SRC5_EN.
PWR
OUT
OUT
GND
3.3V
SRCC6
Differentialoutputclock
Differentialoutputclock
GND
SRCT6
VSS_SRC
IDT CONFIDENTIAL
3
IDTCV193
PROGRAMMABLEFLEXPCCLOCKFORP4PROCESSOR
COMMERCIALTEMPERATURERANGE
PINDESCRIPTION,CONTINUED
Pin #
Name
Type
Description
43
SRCC7/CR#_E
I/O
SRCclock. SRCdifferentialclockoutputenable,controlSRC6,0=enable.ModeselectedbySMBuscontrol
register. DefaultisSRC7.
44
SRCT7/CR#_F
I/O
SRCclock. SRCdifferentialclockoutputenable,controlSRC8,0=enable.ModeselectedbySMBuscontrol
register. DefaultisSRC7.
45
46
47
48
49
50
51
52
53
54
55
56
VDD_SRC_IO
SRCC8/CPU_ ITPC
SRCT8/CPU_ ITPT
Sel_SRC1_25_24.576
VDD_CPU_IO
CPUC1
PWR
OUT
OUT
OUT
PWR
OUT
OUT
GND
OUT
OUT
PWR
IN
1.05 ~ 3.3V
SRC clock. CPU clock. Mode selected by pin7.
SRC clock. CPU clock. Mode selected by pin7.
Power on latch, Select pin 17, 18 Mode, see pin 48 Function Table.
1.05 ~ 3.3V
Differentialoutputclock
Differentialoutputclock
GND
CPUT1
VSS_CPU
CPUC0
Differentialoutputclock
Differentialoutputclock
3.3V
CPUT0
VDD_CPU
CKPWRGD/PD#
CKPWRGDpowergood,activeLOW,usedtolatchFSA,B,C,ITP_EN,TME, andSRC5_EN,activeHIGH.
After, becomes power down, LOW active.
57
58
59
60
61
62
FS_B/TestMode
VSS_REF
IN
GND
OUT
IN
Frequency Select at CKPWRGD assertion. Test Mode selection, see TEST_MODE selection table.q
GND
XTAL_OUT
XTALout
XTALin
3.3V
XTAL_IN
VDD_REF
PWR
I/O
REF/FS_C/TestSel
14.318MHz.FrequencySelectatCKPWRGDassertion.Selectstestmodeifpulledabove2VatCKPWRGD
assertion.
63
64
SDA
SCL
I/O
IN
SMBus data
SMBus clock
TESTMODESELECTION(1)
IfTEST_SELsampledabove2VatCKPWRGDactiveLOW
Test_Mode
CPU
REF/N
Hi-Z
SRC
REF/N
Hi-Z
PCI/F
REF/N
Hi-Z
REF
REF
Hi-Z
DOT_96/DOT_SSC
USB
REF/N
Hi-Z
1
0
REF/N
Hi-Z
NOTE:
1. Once test clock operation has been invoked, TEST_MODE pin will select between the Hi-Z and REF/N, with VIH_FS and VIL_FS thresholds.
FREQUENCYSELECTION
FSC, B, A
101
CPU
100
SRC[7:0]
100
PCI
33.3
33.3
33.3
33.3
33.3
33.3
33.3
33.3
USB
48
DOT
96
REF
14.318
14.318
14.318
14.318
14.318
14.318
14.318
14.318
001
133
100
48
96
011
166
100
48
96
010
200
100
48
96
000
266
100
48
96
100
333
100
48
96
110
400
100
48
96
111
Reserve
100
48
96
IDT CONFIDENTIAL
4
IDTCV193
COMMERCIALTEMPERATURERANGE
PROGRAMMABLEFLEXPCCLOCKFORP4PROCESSOR
SEL_SRC1_25_24.576(PIN48)VOLTAGEDECODINGTABLE
state
Low
Mid
Min
Typ
Max
0.9V
2V
0V
0.55V
1.65V
2.75V
1.3V
2.4V
High
VDD
SR_ENABLETABLE
SR_ENABLE
0
Need external 33 ohm serial resistor, Byte19 bit7 = 0
Enable 33 ohm internal serial resistor, Byte19 bit7 = 1
1 (default)
SEL_SRC1_25_24.576FUNCTIONTABLE
Sel_SRC1_25_24.576
CPU
PCI
Pin 17
Pin 18
SRC
48/96
(pin48 )
Low
PLL1
PLL4
25MHz,
PLL3
25MHz
PLL3
PLL4 down PLL2, fixed
(SS off)
(SS off)
Mid
PLL1
PLL1
PLL4
PLL4
SRCT1
SRCC1
PLL4 down PLL2, fixed
High
25MHz
PLL2
24.576MHz PLL4 down PLL2, fixed
PLL3
(SS off)
SATA_SELTABLE
SATA_SEL
SRC2/SATA
0
PLL4 (SRC PLL, SSC)
PLL2 (48/96 PLL)
1
IO_VOUT [2:0] TABLE
DEVICE ID TABLE
ID3,ID2,ID1,ID0
Comments
000
001
010
011
100
101
110
111
0.3V
0.4V
0.5V
0.6V
0.7V
0.8V
0.9V
1V
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
CK505 56 pin TSSOP
CK505 64 pin TSSOP
CK505 YC
CK505 YC
CK505 YC
48 pin QFN
56 pin QFN
64 pin QFN
72 pin QFN
48 pin SSOP
56 pin SSOP
Reserved
CK505 YC
CK505 YC
CK505 YC
CK505 YC
CK505 YC
CK505 Derivative (non YC)
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
IDT CONFIDENTIAL
5
IDTCV193
PROGRAMMABLEFLEXPCCLOCKFORP4PROCESSOR
COMMERCIALTEMPERATURERANGE
ABSOLUTEMAXIMUMRATINGS(1)
INDEXBLOCKREADPROTOCOL
Mastercanstopreadinganytimebyissuingthestopbitwithoutwaiting
until Nth byte (byte count bit 30-37).
Symbol
VDDA
Description
Min
Max
4.6
Unit
V
3.3V Core Supply Voltage
Bit
1
# of bits
From
Master
Master
Slave
Master
Slave
Master
Master
Slave
Slave
Description
VDD
3.3V Logic Input Supply Voltage GND - 0.5
4.6
V
1
8
1
8
1
1
8
1
8
Start
D2h
TSTG
Storage Temperature
–65
0
+150
+70
+115
°C
°C
°C
V
2-9
TAMBIENT
TCASE
Ambient Operating Temperature
Case Temperature
10
Ack (Acknowledge)
Registeroffsetbyte(startingbyte)
Ack (Acknowledge)
RepeatedStart
11-18
19
ESD Prot Input ESD Protection
Human Body Model
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2000
20
21-28
29
D3h
Ack (Acknowledge)
30-37
Byte count, N (block read back of N
bytes)
38
1
8
1
8
Master
Slave
Master
Slave
Ack (Acknowledge)
firstdatabyte(Offsetdatabyte)
Ack (Acknowledge)
2nddatabyte
39-46
47
48-55
SMPROTOCOL
Ack (Acknowledge)
:
Master
Slave
Ack (Acknowledge)
Nthdatabyte
INDEXBLOCK WRITEPROTOCOL
Notacknowledge
Stop
Bit
1
# of bits
From
Master
Master
Slave
Master
Slave
Master
Slave
Master
Slave
Master
Slave
Description
Master
1
8
1
8
1
8
1
8
1
8
1
Start
D2h
2-9
10
Ack (Acknowledge)
Registeroffsetbyte(startingbyte)
Ack (Acknowledge)
Byte count, N (0 is not valid)
Ack (Acknowledge)
firstdatabyte(Offsetdatabyte)
Ack (Acknowledge)
2nddatabyte
11-18
19
20-27
28
29-36
37
38-45
46
Ack (Acknowledge)
:
Master
Slave
Nthdatabyte
Acknowledge
Master
Stop
IDT CONFIDENTIAL
6
IDTCV193
COMMERCIALTEMPERATURERANGE
PROGRAMMABLEFLEXPCCLOCKFORP4PROCESSOR
N-PROGRAMMINGPROCEDURE
.
•
User writes the desired CPU frequency in HEX form into CPUN [8:0],
•
Byte 16 bit 3 has to be "1". This bit will decode the power on latched
Byte 16, 17.
User writes the desired SRC frequency in HEX form into PN [7:0], Byte
18.
value of pins 4, 5 (see CFG table 1).
•
CONTROLREGISTERS
BYTE 0
Bit
7
Output(s) Affected
FSC
Description/Function
Latched FSC
0
1
Type
R
Power On
Latched Value
Latched Value
Latched Value
6
FSB
Latched FSB
R
5
FSA
Latched FSA
R
4
iAMT_EN
Reserved
Reserved
SRC2/SATA source
iAMT Mode
Legacy Mode
PLL4
Enabled
PLL2
RW HW M1 setting(1)
3
RW
RW
0
0
2
1
RW SATA_SEL latch
SMBUS control registers
setting
after the power down
Power on default, With
some exceptions
Save register
contents
0
PD_Restore
RW
1
NOTES:
1. Sticky 1, can only be reset by power off.
BYTE 1
Bit
7
Output(s) Affected
SRC0_sel
Description/Function
Pin13/14 mode select
SSC mode selection
SSC mode selection
0
1
Type
RW
RW
RW
RW
RW
RW
RW
RW
Power On
SRC0
DOT96
0
1
0
0
0
1
1
1
6
PLL1_SSC_DC
PLL4_SSC_DC
Reserved
Down spread
Down spread
Center spread
Center spread
5
4
3
Reserved
2
1
25MHz_0
25MHz_1
PD# free run control
PD# free run control
Disabled
Disabled
PLL2
Free run
Free run
PLL4
0
PCI
BYTE 2
Bit
Output(s) Affected
Description/Function
0
1
Type
Power On
7
6
5
4
3
2
1
0
REF
USB_48
PCIF5
PCI4
OutputEnable
OutputEnable
OutputEnable
OutputEnable
OutputEnable
OutputEnable
OutputEnable
OutputEnable
Tristate
Tristate
Tristate
Tristate
Tristate
Tristate
Tristate
Tristate
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Enable
RW
RW
RW
RW
RW
RW
RW
RW
1
1
1
1
1
1
1
1
PCI3
PCI2
PCI1
PCI0
IDT CONFIDENTIAL
7
IDTCV193
PROGRAMMABLEFLEXPCCLOCKFORP4PROCESSOR
COMMERCIALTEMPERATURERANGE
BYTE 3
Bit
Output(s) Affected
Description/Function
0
1
Type
Power On
7
6
5
4
3
2
1
0
SRC11
SRC10
SRC9
OutputEnable
OutputEnable
OutputEnable
OutputEnable
OutputEnable
OutputEnable
OutputEnable
OutputEnable
Tristate
Tristate
Tristate
Tristate
Tristate
Tristate
Tristate
Tristate
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
RW
RW
RW
RW
RW
RW
RW
RW
1
1
1
1
1
1
1
1
SRC8/ITP
SRC7
SRC6
SRC5
SRC4
BYTE 4
Bit
Output(s) Affected
Description/Function
0
1
Type
Power On
7
6
5
4
3
2
1
0
SRC3
SATA/SRC2
SRC1
Output Enable
Output Enable
Output Enable
Output Enable
Output Enable
Output Enable
SSC Enable
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
RW
RW
RW
RW
RW
RW
RW
RW
1
1
1
1
1
1
1
1
SRC0/DOT96
CPU1
CPU0
PLL1_SSC_ON
PLL4_SSC_ON
SSC Enable
BYTE 5
Bit
Output(s) Affected
Description/Function
0
1
Type
Power On
7
6
5
4
3
2
1
0
CR#_A
CR#_A control
CR#_B
Pin1modeselection
CR#_A control selection
Pin3modeselection
PCI0mode
SRC0
CR#_A mode
SRC2
RW
RW
RW
RW
RW
RW
RW
RW
0
0
0
0
0
0
0
0
PCI1mode
SRC1(1)
CR#_Bmode
SRC4
CR#_B control
CR#_C
CR#_B control selection
Pin24 mode selection
CR#_C control selection
Pin25modeselection
CR#_D control selection
SRCT3mode
SRC0
CR#_Cmode
SRC2
CR#_C control
CR#_D
SRCC3 mode
SRC1
CR#_Dmode
SRC4
CR#_D control
NOTE:
1. Only when SRC1 is SRC Clock.
IDT CONFIDENTIAL
8
IDTCV193
COMMERCIALTEMPERATURERANGE
PROGRAMMABLEFLEXPCCLOCKFORP4PROCESSOR
BYTE 6(1)
Bit
Output(s)Affected
Description/Function
0
1
Type
Power On
7
6
5
4
3
2
1
0
CR#_E
CR#_F
Pin43 mode selection, control SRC6
Pin44 mode selection, control SRC8
SRCC7 mode
SRCT7 mode
CR#_E mode, Control SRC 6
CR#_F mode, Control SRC 8
RW
RW
RW
RW
RW
RW
RW
RW
0
0
0
0
0
0
0
0
CR#_G
Pin32 mode selection, control SRC9 SRCC11 mode CR#_G mode, Control SRC 9
Pin33 mode selection, control SRC10 SRCT11 mode CR#_H mode, Control SRC 10
CR#_H
Reserved
Reserved
Reserved
SRC_STP_CRTL
If set, SRCs stop with PCI_STOP#
Free running
Stoppable
NOTE:
1. STOP - CPUT and SRCT stay high, CPUC and SRCC stay low.
BYTE 7
Bit
Output(s) Affected
Description / Function
0
1
Type
Power On
7
6
5
4
3
2
1
0
Revision ID
Revision ID
Revision ID
Revision ID
Vendor ID
Vendor ID
Vendor ID
Vendor ID
0
0
0
0
0
1
0
1
BYTE 8
Bit
7
Output(s) affected
Device_ID3
Description/ Function
See device ID table
0
1
Type
R
R
Power On
Device_ID2
Device_ID1
Device_ID0
6
5
R
4
R
3
RW
RW
0
0
2
Output enable
(Cannot be reset by PD Restore)
Output enable
1
0
Pin 17_SE_OE
Pin 18_SE_OE
Disabled
Disabled
Enabled
RW
RW
1
1
(Can not be reset by PD Restore)
Enabled
BYTE 9
Bit
Output(s) Affected
Description / Function
0
1
Type
Power On
7
6
5
4
3
PCIF5 with PCI_STOP#
Reserved
Free running
Free running
stoppable
RW
0
REF Drive Strength
Strength control
1x
2x
RW
RW
RW
1
0
0
Only valid when Byte9 bit3 is 1
Test Mode entry control
Hi-Z
REF/N mode
Normal operation Test mode, controlled
by byte9 bit 4
2
1
0
IO_VOUT2
IO_VOUT1
IO_VOUT0
RW
RW
RW
1
0
1
Programmable IO_VOUT voltage
IDT CONFIDENTIAL
9
IDTCV193
PROGRAMMABLEFLEXPCCLOCKFORP4PROCESSOR
COMMERCIALTEMPERATURERANGE
BYTE10
Bit
Output(s) affected
Description/ Function
0
1
Type
Power On
The latch of
SRC5_EN
1
7
6
5
4
3
2
1
0
SRC5_EN_Strap
PLL3 enable
R
PLL3
PLL2
PLL3 pwr dwn
PLL2 pwr dwn
disable
Pwr up
Pwr up
RW
RW
RW
RW
RW
RW
RW
1
1
1
1
1
1
PLL2 enable
SRC_DIV
PCI_DIV
SRC divider disable
PCI divider disable
CPU divider disable
Controlled by CPU_STP#
Controlled by CPU_STP#
enable
disable
enable
CPU_DIV
CPU1 Free run
CPU0 Free run
disable
enable
Free run
Controllable
Controllable
Free run
BYTE 11 - RESERVED
Bit Output(s) affected
Description/ Function
0
1
Type Power On
7
6
5
4
Reserved
Reserved
Reserved
Reserved
R
R
RW
RW
0
1
M1 mode CLK enable at M1 mode
Only if ITP_EN = 1
3
2
1
CPU_ITP_AMT EN
CPU1_AMT_EN
disable
enable
enable
GEN II
RW
RW
R
0
1
1
M1 mode CLK enable at M1 mode
GEN II compliance
disable
PCI GEN II
CPU_ITP_STOP
EN
None GEN II
0
Free run control
Free run
Controlled
RW
1
BYTE 12 - BYTE COUNT - DEFAULT 0x13H
BYTE13
Bit
Output(s) Affected
Description/Function
0
1
Type
Power On
7
6
5
4
3
2
1
0
48M
REF
Strength control
Strength control
Strength control
Strength control
Strength control
Strength control
Strength control
Strength control
1x
1x
1x
1x
1x
1x
1x
1x
2x
2x
2x
2x
2x
2x
2x
2x
RW
RW
RW
RW
RW
RW
RW
RW
1
0
1
1
1
1
1
1
PCIF5
PCI4
PCI3
PCI2
PCI1
PCI0
BYTE 14 RESERVED
IDT CONFIDENTIAL
10
IDTCV193
COMMERCIALTEMPERATURERANGE
PROGRAMMABLEFLEXPCCLOCKFORP4PROCESSOR
BYTE 15, WATCH DOG(1)
Bit
7
Output(s) Affected
Watch Dog Enable
Description / Function
Watch Dog Alarm Enable
0
1
Type
RW
RW
R
Power On
Disabled
Enabled
0
0
6
Watch Dog Select
Watch Dog Hard/Soft Alarm Select Hard Alarm Only Hard and Soft Alarm
5
Watch Dog Hard Alarm Status
Watch Dog Soft Alarm Status
Watch Dog control
Watch Dog Hard Alarm Status
Watch Dog Soft Alarm Status
Watch Dog Time Base Control
WatchDog_1_AlarmTimer
Default is 7*290ms
Normal
Normal
Alarm
Alarm
4
R
3
290msbase
1160msbase
RW
RW
RW
RW
0
1
1
1
2
WD_1_ Timer 2
1
WD_1_ Timer 1
0
WD_1_ Timer 0
NOTE:
1. Hard Alarm switch to HW FS frequency.
BYTE16
Bit Output(s) Affected
Description / Function
Set Byte15 bit7 = 1 after Power Down
0
1
Type
Power On
7
6
5
WDEAPD
Reserved
Reserved
to enable the watch dog after the power down
Disabled
Enabled
RW
RW
RW
0
0
0
SCLK=1, clk
outputs = 1
4
Test _scl
N programming
Enable
On chip test mode enable
normal
SCLK=0, clk outputs=0 RW
0
3
2
1
0
Disabled
Enabled
RW
RW
RW
RW
0
Reserved
Reserved
CPUN8
0
0
FS latch
BYTE 17 (PLL1)
Bit Output(s) Affected
Description / Function
0
1
Type
Power On
7
6
5
CPUN7
CPUN6
CPUN5
RW
RW
RW
CPU clock frequency =
CPUN [8:0]
FS latch
4
3
2
1
0
CPUN4
CPUN3
CPUN2
CPUN1
CPUN0
RW
RW
RW
RW
RW
(Hex)
IDT CONFIDENTIAL
11
IDTCV193
PROGRAMMABLEFLEXPCCLOCKFORP4PROCESSOR
COMMERCIALTEMPERATURERANGE
BYTE 18 (PLL4)
Bit
Output(s) Affected
Description / Function
0
1
Type
Power On
7
6
5
4
3
2
1
0
PN 7
PN 6
PN 5
PN 4
PN 3
PN 2
PN 1
PN 0
RW
RW
RW
RW
RW
RW
RW
RW
SRC clock frequency =
PNC [7:0]
100MHz
(Hex)
BYTE 19 CLOCK SOURCE SELECTION, WRITTEN AFTER STOP BIT
Bit
Output(s) Affected
Description / Function
0
1
Type
Power On
33 ohm
(No external resistor
needed)
SR_ENABLE
latch
0 ohm
(External resistor needed)
0.5% (p-p)
7
6
5
4
3
2
1
0
Output serial resistor
PLL1 SSC
Reserved
RW
RW
RW
RW
RW
RW
RW
RW
spread % selection
spread % selection
0
0
0
0
0
0
0
0.45%(p-p)
0.5% (p-p)
PLL4 SSC
Reserved
0.45%(p-p)
Reserved
Reserved
Reserved
IDT CONFIDENTIAL
12
IDTCV193
COMMERCIALTEMPERATURERANGE
PROGRAMMABLEFLEXPCCLOCKFORP4PROCESSOR
ABSOLUTE MAXIMUM RATINGS
PARAMETER
SYMBOL
VDDxxx
VDDxxx_IO
VIH
CONDITIONS
Supply Voltage
MIN
MAX
4.6
UNITS Notes
Maximum Supply Voltage
Maximum Supply Voltage
Maximum Input Voltage
Minimum Input Voltage
Storage Temperature
Input ESD protection
V
V
1,7
1,7
Low-Voltage Differential I/O Supply
3.3V LVCMOS Inputs
Any Input
3.8
4.6
V
1,7,8
1,7
VIL
GND - 0.5
-65
V
°C
Ts
-
150
1,7
ESD prot
Human Body Model
2000
V
1,7
ELECTRICAL CHARACTERISTICS - INPUT/SUPPLY/COMMON OUTPUT
PARAMETERS
PARAMETER
Ambient Operating Temp
Supply Voltage
SYMBOL
Tambient
VDDxxx
CONDITIONS
MIN
0
MAX
70
UNITS Notes
-
°C
V
1
1
Supply Voltage
3.135
3.465
Supply Voltage
VDDxxx_IO
Low-Voltage Differential I/O Supply
1.05
3.3
V
1
Input High Voltage
Input Low Voltage
VIHSE
VILSE
IIN
Single-ended inputs
Single-ended inputs
VIN = VDD , VIN = GND
2
VSS - 0.3
-5
VDD + 0.3
V
V
1
1
1
0.8
5
Input Leakage Current
uA
Inputs with pull or pull down
resistors
Input Leakage Current
IINRES
-200
2.4
200
uA
1
VIN = VDD , VIN = GND
Output High Voltage
Output Low Voltage
Output High Voltage
Output Low Voltage
VOHSE
VOLSE
VOHDIF
VOLDIF
Single-ended outputs, IOH = -1mA
Single-ended outputs, IOL = 1 mA
Differential Outputs, IOH = TBD mA
Differential Outputs, IOL = TBD mA
V
V
V
V
1
1
1
1
0.4
0.9
0.4
0.7
Low Threshold Input-
High Voltage (Test Mode)
Low Threshold Input-
High Voltage
Low Threshold Input-
Low Voltage
VIH_FS_TEST
VIH_FS
3.3 V +/-5%
3.3 V +/-5%
3.3 V +/-5%
2
VDD + 0.3
1.5
V
V
V
1
1
1
0.7
VIL_FS
VSS - 0.3
0.35
IDDOP3.3
IDD_IO
Full active, CL=full load, IDD3.3V
Full active, CL=full load, IDD3.3
3.3V supply, Power Down Mode
200
70
5
mA
mA
mA
1
1
1
Operating Supply Current
Power Down Current
iAMT Mode Current
IDD_PD3.3
IDD_PDIO
0.8V IO supply, Power Down Mode
0.1
mA
1
IDD_iAMT3.3
IDD_iAMT0.8
Fi
3.3V supply, iAMT Mode
0.8V IO supply, iAMTMode
VDD = 3.3 V
80
10
15
7
mA
mA
MHz
nH
1
1
2
1
1
1
1
Input Frequency
Pin Inductance
Lpin
CIN
Logic Inputs
Output pin capacitance
X1 & X2 pins
1.5
30
5
pF
Input Capacitance
COUT
CINX
6
pF
TBD
pF
Spread Spectrum Modulation
Frequency
fSSMOD
Triangular Modulation
33
kHz
1
IDT CONFIDENTIAL
13
IDTCV193
PROGRAMMABLEFLEXPCCLOCKFORP4PROCESSOR
COMMERCIALTEMPERATURERANGE
AC ELECTRICAL CHARACTERISTICS - INPUT/COMMON PARAMETERS
PARAMETER
SYMBOL
CONDITIONS
MIN
MAX
UNITS Notes
From VDD Power-Up or de-assertion
of PD# to 1st clock
Clk Stabilization
TSTAB
1.8
ms
ns
us
ns
1
1
1
1
SRC output enable after
PCI_STOP# de-assertion
Differential output enable after
PD# de-assertion
CPU output enable after
CPU_STOP# de-assertion
Tdrive_SRC
Tdrive_PD#
Tdrive_CPU
TDRSRC
TDRPD
15
300
10
TDRSRC
Tfall_PD#
Trise_PD#
TFALL
TRISE
5
5
ns
ns
1
1
Fall/rise time of PD#, PCI_STOP#
and CPU_STOP# inputs
AC ELECTRICAL CHARACTERISTICS - LOW POWER DIFFERENTIAL OUTPUTS
PARAMETER
Rising Edge Slew Rate
Falling Edge Slew Rate
Slew Rate Variation
SYMBOL
CONDITIONS
MIN
MAX
UNITS NOTES
tSLR
Differential Measurement
Differential Measurement
Single-ended Measurement
Includes overshoot
2.5
8
V/ns
V/ns
%
1,2
tFLR
2.5
8
1,2
tSLVAR
20
1
Maximum Output Voltage
Minimum Output Voltage
Differential Voltage Swing
Crossing Point Voltage
Crossing Point Variation
Duty Cycle
VHIGH
1150
mV
mV
mV
mV
mV
%
1
VLOW
Includes undershoot
-300
300
300
1
VSWING
VXABS
VXABSVAR
DCYC
Differential Measurement
Single-ended Measurement
Single-ended Measurement
Differential Measurement
Differential Measurement
Differential Measurement
Differential Measurement
Differential Measurement
Differential Measurement
Differential Measurement
1
1,3,4
1,3,5
1
550
140
55
45
CPU Jitter - Cycle to Cycle
SRC Jitter - Cycle to Cycle
DOT Jitter - Cycle to Cycle
CPU[1:0] Skew
CPUJC2C
SRCJC2C
DOTJC2C
CPUSKEW10
CPUSKEW20
SRCSKEW
85
ps
1
125
250
100
150
250
ps
1
ps
1
ps
1
CPU[2_ITP:0] Skew
SRC[10:0] Skew
ps
1
ps
1,10
ELECTRICAL CHARACTERISTICS - PCICLK/PCICLK_F
NOTES
PARAMETER
SYMBOL
CONDITIONS
see Tperiod min-max values
33.33MHz output nominal
33.33MHz output spread
33.33MHz output nominal/spread
IOH = -1 mA
MIN
MAX
300
UNITS
ppm
ns
1,6
6
Long Accuracy
ppm
-300
30.00900
30.15980
30.65980
Clock period
Tperiod
29.99100
6
ns
Absolute min/max period
Output High Voltage
Output Low Voltage
Tabs
VOH
VOL
29.49100
2.4
6
ns
1
V
1
IOL = 1 mA
0.4
-33
V
V
OH @MIN = 1.0 V
-33
30
mA
1
Output High Current
Output Low Current
IOH
VOH@MAX = 3.135 V
VOL @ MIN = 1.95 V
mA
mA
mA
V/ns
V/ns
%
1
1
IOL
VOL @ MAX = 0.4 V
38
4
1
Rising Edge Slew Rate
Falling Edge Slew Rate
Duty Cycle
tSLR
tFLR
dt1
Measured from 0.8 to 2.0 V
Measured from 2.0 to 0.8 V
1
1
1
4
1
1
VT = 1.5 V
VT = 1.5 V
VT = 1.5 V
VT = 1.5 V
45
55
Skew
tskew
tdelay
1
250
ps
ps
ps
Intentional PCI-PCI delay
Jitter, Cycle to cycle
1,9
1
200 nominal
500
tjcyc-cyc
IDT CONFIDENTIAL
14
IDTCV193
COMMERCIALTEMPERATURERANGE
PROGRAMMABLEFLEXPCCLOCKFORP4PROCESSOR
ELECTRICAL CHARACTERISTICS - USB48MHZ
NOTES
PARAMETER
Long Accuracy
Clock period
SYMBOL
ppm
CONDITIONS
MIN
-100
MAX
100
UNITS
ppm
ns
see Tperiod min-max values
48.00MHz output nominal
1,2
2
Tperiod
20.83125
20.83542
Absolute min/max period
Tabs
48.00MHz output nominal
20.48130
2.4
21.18540
ns
2
1
Output High Voltage
Output Low Voltage
VOH
VOL
IOH = -1 mA
IOL = 1 mA
V
V
1
0.4
-23
V
OH @MIN = 1.0 V
VOH@MAX = 3.135 V
OL @ MIN = 1.95 V
OL @ MAX = 0.4 V
-29
29
mA
mA
1
Output High Current
Output Low Current
IOH
1
V
mA
mA
V/ns
V/ns
%
1
IOL
V
27
2
1
Rising Edge Slew Rate
Falling Edge Slew Rate
Duty Cycle
tSLR
tFLR
Measured from 0.8 to 2.0 V
Measured from 2.0 to 0.8 V
1
1
1
2
1
dt1
1
VT = 1.5 V
VT = 1.5 V
45
55
Jitter, Cycle to cycle
1
tjcyc-cyc
350
ps
ELECTRICAL CHARACTERISTICS - SMBUS INTERFACE
PARAMETER
SMBus Voltage
SYMBOL
VDD
CONDITIONS
MIN
2.7
MAX
5.5
UNITS Notes
V
V
1
1
Low-level Output Voltage
VOLSMB
@ IPULLUP
0.4
Current sinking at
VOLSMB = 0.4 V
SCLK/SDATA
IPULLUP
TRI2C
SMB Data Pin
4
mA
ns
1
1
1
1
(Max VIL - 0.15) to
(Min VIH + 0.15)
(Min VIH + 0.15) to
(Max VIL - 0.15)
1000
300
Clock/Data Rise Time
SCLK/SDATA
Clock/Data Fall Time
Maximum SMBus Operating
Frequency
TFI2C
ns
FSMBUS
Block Mode
100
kHz
IDT CONFIDENTIAL
15
IDTCV193
PROGRAMMABLEFLEXPCCLOCKFORP4PROCESSOR
COMMERCIALTEMPERATURERANGE
ELECTRICAL CHARACTERISTICS - REF-14.318MHZ
PARAMETER
Long Accuracy
SYMBOL
ppm
CONDITIONS
see Tperiod min-max values
14.318MHz output nominal
14.318MHz output nominal
IOH = -1 mA
MIN
-300
MAX
300
UNITS Notes
ppm
ns
ns
V
1,2
2
Clock period
Tperiod
Tabs
69.8203
69.8203
2.4
69.8622
70.86224
Absolute min/max period
Output High Voltage
Output Low Voltage
2
VOH
1
VOL
IOL = 1 mA
0.4
-33
V
1
VOH @MIN = 1.0 V,
Output High Current
Output Low Current
IOH
IOL
-33
30
mA
mA
1
1
V
OH@MAX = 3.135 V
VOL @MIN = 1.95 V,
VOL @MAX = 0.4 V
38
Rising Edge Slew Rate
Falling Edge Slew Rate
Duty Cycle
tSLR
tFLR
Measured from 0.8 to 2.0 V
1
1
4
4
V/ns
V/ns
%
1
1
1
1
Measured from 2.0 to 0.8 V
VT = 1.5 V
dt1
45
55
Jitter
tjcyc-cyc
VT = 1.5 V
1000
ps
Notes on Electrical Characteristics:
1Guaranteed by design and characterization, not 100% tested in production.
2 Slew rate measured through Vswing centered around differential zero
3 Vxabs is defined as the voltage where CLK = CLK#
4 Only applies to the differential rising edge (CLK rising and CLK# falling)
5 Defined as the total variation of all crossing voltages of CLK rising and CLK# falling. Matching applies to rising edge rate of CLK and falling
edge of CLK#. It is measured using a +/-75mV window centered on the average cross point where CLK meets CLK#.
6 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818MHz
7 Operation under these conditions is neither implied, nor guaranteed.
8 Maximum input voltage is not to exceed maximum VDD
9 See PCI Clock-to-Clock Delay Figure
10 SRC 3,4,6,7, are 0 ps nominal interpair skew
IDT CONFIDENTIAL
16
IDTCV193
COMMERCIALTEMPERATURERANGE
PROGRAMMABLEFLEXPCCLOCKFORP4PROCESSOR
PCISTOPFUNCTIONALITY
PCI_STOP#
SRC
Normal
High
SRC#
Normal
Low
PCI
33MHz
Low
1
0
PCI_STOP# ASSERTION (TRANSITION FROM ‘1’ TO ‘0’)
tSU
PCI_STOP#
PCIF5 33MHz
PCI[4:0] 33MHz
SRC 100MHz
SRC# 100MHz
PCI_STOP# - DE-ASSERTION (TRANSITION FROM '0' TO '1')
tSU
tDRIVE_SRC
PCI_STOP#
PCIF5 33MHz
PCI[4:0] 33MHz
SRC 100MHz
SRC# 100MHz
IDT CONFIDENTIAL
17
IDTCV193
PROGRAMMABLEFLEXPCCLOCKFORP4PROCESSOR
COMMERCIALTEMPERATURERANGE
CPUSTOPFUNCTIONALITY
The CPU_STOP# signal is an active low input controlling the CPU outputs. This signal can be asserted asynchronously.
CPU_STOP#
CPU
Normal
High
CPU#
Normal
Low
1
0
CPU_STOP# ASSERTION (TRANSITION FROM ‘1’ TO ‘0’)
AssertingCPU_STOP#pinstopsallCPUoutputsthataresettobestoppableaftertheirnexttransition.WhentheSMBusCPU_STOPtri-statebitcorresponding
totheCPUoutputofinterestisprogrammedtoa‘0’,CPUoutputwillstopCPU_True=HighandCPU_Complement=Low.WhentheSMBusCPU_STOP#
tri-statebitcorrespondingtotheCPUoutputofinterestisprogrammedtoa‘1’,CPUoutputswillbetri-stated.
CPU_STOP#
CPU
CPU#
CPU_STOP# - DE-ASSERTION (TRANSITION FROM ‘0’ TO ‘1’)
Withthede-assertionofCPU_STOP#allstoppedCPUoutputswillresumewithoutaglitch.Themaximumlatencyfromthede-assertiontoactiveoutputs
istwotosixCPUclockperiods.Ifthecontrolregistertristatebitcorrespondingtotheoutputofinterestisprogrammedto‘1’,thenthestoppedCPUoutputswill
be driven High within 10nS of CPU_STOP# de-assertion to a voltage greater than 200mV.
CPU_STOP#
CPU
CPU#
CPU Internal
tDRIVE_CPU_Stop
10nS > 200mV
IDT CONFIDENTIAL
18
IDTCV193
COMMERCIALTEMPERATURERANGE
PROGRAMMABLEFLEXPCCLOCKFORP4PROCESSOR
PD#ASSERTION
PD#
CPU 133MHz
CPU# 133MHz
SRC 100MHz
SRC# 100MHz
USB 48MHz
PCI 33MHz
REF 14.31818
PD#DE-ASSERTION
tSTABLE <1.8mS
PD#
CPU 133MHz
CPU# 133MHz
SRC 100MHz
SRC# 100MHz
USB 48MHz
PCI 33MHz
REF 14.31818
IDT CONFIDENTIAL
19
IDTCV193
PROGRAMMABLEFLEXPCCLOCKFORP4PROCESSOR
COMMERCIALTEMPERATURERANGE
TSSOPPACKAGEDIMENSIONS
6.10 mm. Body, 0.50 mm. Pitch TSSOP
(240 mil) (20 mil)
In Millimeters
COMMON DIMENSIONS
In Inches
COMMON DIMENSIONS
c
N
SYMBOL
MIN
--
0.05
0.80
0.17
0.09
MAX
1.20
0.15
1.05
0.27
0.20
MIN
--
.002
.032
.007
.0035
MAX
.047
.006
.041
.011
.008
A
A1
A2
b
L
E1
E
INDEX
AREA
c
D
E
SEE VARIATIONS
8.10 BASIC
SEE VARIATIONS
0.319 BASIC
E1
e
L
N
α
6.00
0.50 BASIC
0.45
SEE VARIATIONS
0°
--
6.20
.236
0.020 BASIC
.018 .030
SEE VARIATIONS
.244
1
2
0.75
α
D
8°
0.10
0°
--
8°
.004
aaa
VARIATIONS
D mm.
D (inch)
A
N
A22
MIN
16.90
MAX
17.10
MIN
.665
MAX
.673
64
A11
- C -
Reference Doc.: JEDEC Publication 95, MO-153
10-0039
e
SEEAATIINNGG
PLLAANNEE
b
aaa
C
ORDERINGINFORMATION
IDTCV
XXXX
XXX
XX
X
X
Device Type
Revision Package
Grade
T/R
CommercialTemperatureRange
Blank
(0°Cto+70°C)
Designation for tape and reel packaging
8
Shrink Small Outline Package - Green
Thin Shrink Small Outline Package - Green
PVG
PAG
C
RevisionDesignator
Programmable FlexPC Clock for P4 Processor
193
IDT CONFIDENTIAL
20
IDTCV193
COMMERCIALTEMPERATURERANGE
PROGRAMMABLEFLEXPCCLOCKFORP4PROCESSOR
REVISION HISTORY
August 15, 2007
August 21, 2007
December 07, 2007
April 08, 2008
Initial Release.
Updated Pinout/Pin Description (pages 2-4). Added Sata_Sel Table (page 5). Updated SMBus (pages 7-12).
Updated Byte 18 (pg. 12).
Updated VDDxxx_IO supply voltage (pg. 13).
April 24, 2008
Fixed Ordering Information (pg. 20).
June 24, 2008
Added tape and reel ordering information (page 20)
Corrected typo on pins 55 and 56 pin description (page 4)
Updated Byte 1 (page 7).
October 20, 2008
April 8, 2009
Updated Input/Supply Common Output Parameters table.
CORPORATE HEADQUARTERS
6024 Silver Creek Valley Road
San Jose, CA 95138
for SALES:
for Tech Support:
pcclockhelp@idt.com
800-345-7015 or 408-284-8200
fax: 408-284-2775
www.idt.com
IDT CONFIDENTIAL
21
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SI9135_11
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SI9136_11
Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9130CG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9130LG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9130_11
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9137
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9137DB
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9137LG
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9122E
500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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VISHAY
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