IDTQS3ST253Q8 [IDT]
Multiplexer And Demux/Decoder, 2-Func, 4 Line Input, 1 Line Output, True Output, CMOS, PDSO20, QSOP-20;型号: | IDTQS3ST253Q8 |
厂家: | INTEGRATED DEVICE TECHNOLOGY |
描述: | Multiplexer And Demux/Decoder, 2-Func, 4 Line Input, 1 Line Output, True Output, CMOS, PDSO20, QSOP-20 光电二极管 逻辑集成电路 |
文件: | 总10页 (文件大小:74K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
QUICKSWITCH® PRODUCTS
HIGH-SPEED CMOS SYNCHRO-
IDTQS3ST253
SWITCH™ DUAL 4:1 MUX/DEMUX
WITH ACTIVE TERMINATORS
DESCRIPTION:
FEATURES:
TheQS3ST253isahigh-speedCMOS dual4:1 multiplexer/demultiplexer
withactiveterminators(bus-holdcircuits)onthedemuxside. Portselection
andconnection, controlledbySELsignals, canbeeitherasynchronousor
synchronous. In the synchronous mode, the A, B, C, or D port to Y port
connection is updated on the rising edge of the input clock CLK. Once the
port-to-portconnectionismade,dataflowcanbebi-directionalwithatypical
250ps propagation delay through the switch. Clock Enable, overriding
Asynchronous Enable, and Asynchronous Select controls provide addi-
tionaldesignflexibility.
• Enhanced N channel FET with no inherent diode to Vcc
• Bidirectional signal flow
• Flow-through pinout
• Zero propagation delay, zero ground bounce
• 2 banks of 4:1 Mux/Demux
• Port select synchronous to the clock
• Undershoot clamp diodes on all switch and control inputs
• Clock enable and Asynchronous enable
• “Bus-hold” terminators on the Demux side
• Asynchronous SEL option
The bus-hold circuits latch the last data driven on the demux side,
providinginfiniteholdtimeandglitch-freesignaltransitions. Synchronous
controlsandbus-holdeasetimingconstraintsinmanyhighspeeddatamux/
demux applications, such as bank interleaving.
• Break-before-make feature
• Bus-hold eliminates floating bus lines and reduces static power
consumption
The QS3ST253 can be used in 5V to 3.3V translation.
• Available in QSOP package
APPLICATIONS:
• Video, audio, graphics switching, muxing
FUNCTIONALBLOCKDIAGRAM
=
T
OE0
OE1
SEL0
CONTROL
LOGIC
SEL1
CLKn
CLKENn
SYNCn
A0
B0
C0
D0
A1
B1
C1
D1
T
T
T
T
T
T
T
T
Bank 0
Bank 1
Y0
Y1
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.
INDUSTRIAL TEMPERATURE RANGE
NOVEMBER 1999
1
c
1999 Integrated Device Technology, Inc.
DSC-5533/1
IDTQS3ST253
HIGH-SPEEDCMOSSYNCHROSWITCHDUAL4:1MUX/DEMUX
INDUSTRIALTEMPERATURERANGE
ABSOLUTEMAXIMUMRATINGS(1)
PINCONFIGURATION
Symbol
Description
Supply Voltage to Ground
DC Switch Voltage Vs
Max
–0.5 to +7
–0.5 to +7
–0.5 to +7
–3
Unit
V
(2)
VTERM
(3)
VTERM
V
1
2
3
20
19
18
17
(3)
NC
A0
VTERM
DC Input Voltage VIN
V
Vcc
VAC
AC Input Voltage (pulse width ≤ 20ns)
DC Output Current
V
OE0
OE1
SEL0
SEL1
Y0
IOUT
PMAX
TSTG
120
mA
W
A1
B0
Maximum Power Dissipation (TA = 85°C)
Storage Temperature
0.82
4
5
6
–65 to +150
°C
B1
C0
NOTE:
16
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
15
14
13
7
8
9
C1
Y1
2. Vcc terminals.
3. All terminals except Vcc.
D0
CLKEN
CLK
SYNC
12
11
D1
10
GND
CAPACITANCE (TA = +25°C, f = 1MHz, VIN = 0V, VOUT = 0V)
Pins
Typ.
Max.(1)
Unit
QSOP
ControlInputs
4
5
pF
TOP VIEW
QuickswitchChannels
(Switch OFF)
Demux
Mux
5
13
7
14
pF
NOTE:
1. This parameter is guaranteed but not production tested.
PINDESCRIPTION
Pin Names
A0 - D0
I/O
Description
I/O
Bank 0 Demux Ports
A1 - D1
I/O
Bank 1 Demux Ports
Mux Port
Y0, Y1
I/O
SEL0, SEL1
CLK
I
I
I
I
I
SelectInputs
Clock
CLKEN
OE0, OE1
SYNC
Clock Enable
OutputEnable
SynchronousEnable
2
IDTQS3ST253
HIGH-SPEEDCMOSSYNCHROSWITCHDUAL4:1MUX/DEMUX
INDUSTRIALTEMPERATURERANGE
FUNCTIONTABLE(1)
Control Inputs
Port Status
SYNC
OE0
L
OE 1
CLK
↑
CLKEN
SEL0
SEL1
Y0
Y1
L
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
H
L
H
L
L
L
A0
A1
L
↑
B0
B1
L
↑
H
H
X
X
C0
C1
L
↑
H
X
X
D0
D1
H
L
↑
Hold Previous Data (2) (Switch OFF)
Hold Previous Data (2) (Switch OFF)
↑
Hold Previous Mux connection (3)
(Switch ON)
Hold Previous Mux connection(3)
(Switch ON)
L
H
L
L
L
L
H
H
L
L
L
L
H
↑
X
X
X
X
X
H
X
X
X
X
X
X
L
X
L
Hold Previous Data (4) (Switch OFF)
Hold Previous Data (4) (Switch OFF)
H
A0
A1
H
H
L
L
B0
B1
H
H
H
H
X
C0
C1
H
X
D0
D1
H
Hold Previous Data (2) (Switch OFF)
Hold Previous Data (2) (Switch OFF)
NOTES:
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
Z = High-Impedence
↑ = LOW-to-HIGH Transition
2. Mux switches are turned off and the terminators (last value latches) hold the previous data state. The port connections can be changed by the SEL input.
3. The contents of the “Mux select register” are unchanged and the previous Mux connection is unchanged. The output (Mux port) data state will depend on the present data
state of the input (Demux port).
4. The contents of the “Mux select register” are unchanged and the last value latch holds the previous data state.
CONTROLLOGIC
OE0
2:1
MUX
D
Q
2:1
MUX
SEL0
To Bank 0 Switches
DECODE
LOGIC
AND
CLKEN
CLK
SWITCH
CONTROL
SYNC
2:1
MUX
To Bank 1 Switches
SEL1
2:1
MUX
D
Q
OE1
3
IDTQS3ST253
HIGH-SPEEDCMOSSYNCHROSWITCHDUAL4:1MUX/DEMUX
INDUSTRIALTEMPERATURERANGE
DCELECTRICALCHARACTERISTICSOVEROPERATINGRANGE
FollowingConditionsApplyUnlessOtherwiseSpecified:
Industrial: TA = –40°C to +85°C, VCC = 5.0V ±10%
Symbol
Parameter
Input HIGH Level
Input LOW Level
Test Conditions
Min.
Typ.(1)
Max.
Unit
VIH
Guaranteed Logic HIGH for Control Pins
2
—
—
V
VIL
IIN
Guaranteed Logic LOW for Control Pins
—
—
—
—
0.8
±1
±1
V
Input Leakage Current (Control Inputs) 0V ≤ VIN ≤ VCC
0.01
µA
µA
Ω
IOZ
RON
Off-State Current (Hi-Z)
Switch ON Resistance(2)
0V ≤ Y ≤ VCC
—0.01
VCC = Min., VIN = 0V, ION = 30mA
VCC = Min., VIN = 2.4V, ION =15mA
—
—
60
7
9
10
—
13
—
IBHL
IBHH
IBH
InputHoldCurrent(3,4)
Vcc = Min.
Switch OFF
Vcc = Max.
VIN = 0.8V
µA
µA
(A, B, C, D)
InputCurrent(5)
(A, B, C, D)
VIN = 2V
– 60
—
—
—
—
—
VIN = 0V or Vcc
0.8 < VIN < 2V
±50
±500
—
NOTES:
1. Typical values are at VCC = 5.0V, TA = 25°C.
2. Measured by voltage drop between A/B/C/D and Y pin at indicated current through the switch.
3. IBHL is the minimum sustaining “sink” current at the input for VIN = 0.8V. This parameter signifies the latching capability of the bus-hold circuit in logic LOW state.
4. IBHH is the minimum sustaining “source” current at the input for VIN = 2V. This parameter signifies the latching capability of the bus-hold circuit in logic HIGH state.
5. IBH is the magnitude of the input current specified under two conditions:
a) Input voltage at GND or Vcc. This indicates the input current under steady-state condition.
b) Input voltage between 0.8V and 2V (TTL input threshold range). This indicates the maximum input current during transient condition. The driver connected to the input
must overcome this current requirement in order to switch the logic state of the bus-hold circuit.
TYPICAL ON RESISTANCE vs VIN AT VCC = 5V
16
14
12
10
8
RON
(ohms)
6
4
2
0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
VIN
(Volts)
4
IDTQS3ST253
HIGH-SPEEDCMOSSYNCHROSWITCHDUAL4:1MUX/DEMUX
INDUSTRIALTEMPERATURERANGE
POWERSUPPLYCHARACTERISTICS
Symbol
ICCQ
Parameter
TestConditions(1)
VCC = Max., VIN = GND or Vcc, f = 0
VCC = Max., VIN = 3.4V, f = 0
Max.
3
Unit
µA
Quiescent Power Supply Current
Power Supply Current per Control Input HIGH (2)
Dynamic Power Supply Current per MHz(3)
∆ICC
1.5
mA
ICCD
VCC = Max., A/B/C/D and Y pins open
Control Inputs Toggling at 50% Duty Cycle
0.25
mA/MHz
NOTES:
1. For conditions shown as Min. or Max., use the appropriate values specified under DC Electrical Characteristics.
2. Per TLL driven input (VIN = 3.4V, control inputs only). A/B/C/D and Y pins do not contribute to ∆Icc.
3. This current applies to the control inputs only and represents the current required to switch internal capacitance at the specified frequency. The A/B/C/D and Y inputs generate
no significant AC or DC currents as they transition. This parameter is guaranteed but not production tested.
SWITCHINGCHARACTERISTICSOVEROPERATINGRANGE
TA = -40°C to +85°C, VCC = 5.0V ± 10%;
CLOAD = 50pF, RLOAD = 500Ω unless otherwise noted.
Symbol
tPLH
Parameter
DataPropagationDelays(1,2)
Min.(1)
Typ.
Max.
Unit
—
0.25
—
ns
tPHL
A/B/C/D to Y, Y to A/B/C/D
tSEC
tHEC
tCSO
tASO
tW
Clock Enable to Clock Setup Time
Clock Enable to Clock Hold Time
Clock to Switch Turn-On Delay(3)
Asynchronous Select to Switch Turn-On Delay(3)
Clock Pulse Width HIGH
3
0
—
—
—
—
—
—
—
—
—
—
7
ns
ns
ns
ns
ns
ns
ns
ns
0.5
0.5
3
7
—
—
—
5.2
tSCS
tHCS
tPZL
SEL to Clock Setup Time
3
SEL to Clock Hold Time
AsynchronousEnabletoSwitchTurn-OnDelay(3)
0
1.5
tPZH
tPLZ
AsynchronousEnabletoSwitchTurn-OffDelay(1,3)
1.5
—
4.8
ns
tPHZ
NOTES:
1. This parameter is guaranteed but not tested.
2. The bus switch contributes no propagation delay other than the RC delay of the ON resistance of the switch and the load capacitance. The time constraint for the switch
alone is of the order of 0.25ns for CL = 50pF. Since this time constant is much smaller than the rise and fall times of typical driving signals, it adds very little propagation
delay to the system. Propagation delay of the bus switch, when used in a system, is determined by the driving circuit on the driving side of the switch and its interaction
with the load on the driven side.
3. Minimums guaranteed but not tested.
5
IDTQS3ST253
HIGH-SPEEDCMOSSYNCHROSWITCHDUAL4:1MUX/DEMUX
INDUSTRIALTEMPERATURERANGE
TIMINGWAVEFORMS - SYNCHRONOUS MODE, DEMUX FUNCTION
SYNC
tSEC tHEC
CLKEN
CLK
tSCS tHCS
tSCS tHCS
SEL0, SEL1
OE0, OE1
Port Y
DATA 0
DATA 2
DATA 1
tPLH, tPHL
tCSO
DATA
1
Port A
Port D
DATA 0
HOLD PREVIOUS DATA, DATA 1
tPLH, tPHL
INVALID DATA
tCSO
HOLD PREVIOUS DATA, DATA 2
INVALID DATA
DATA 1 DATA 2
Example: Port A to Port D / Port Y
6
IDTQS3ST253
HIGH-SPEEDCMOSSYNCHROSWITCHDUAL4:1MUX/DEMUX
INDUSTRIALTEMPERATURERANGE
TIMING WAVEFORMS - SYNCHRONOUS MODE, MUX FUNCTION
SYNC
tSEC tHEC
CLKEN
CLK
tSCS tHCS
tSCS tHCS
SEL0
Port A
Port B
DATA1
DATA2
DATA3
DATA4
tCSO
tCSO
tPLH,
tPHL
tPLH,
tPHL
DATA1
INVALID DATA
DATA2
DATA3
DATA4
Port Y
Example: Port A / Port D to Port Y
7
IDTQS3ST253
HIGH-SPEEDCMOSSYNCHROSWITCHDUAL4:1MUX/DEMUX
INDUSTRIALTEMPERATURERANGE
TIMING WAVEFORMS - ASYNCHRONOUS MODE, MUX FUNCTION
SYNC
SEL0, SEL1
OE0, OE1
INVALID
DATA
Port A
DATA1
DATA2
tPLH, tPHL
tPLH, tPHL
Port D
Port Y
INVALID DATA
INVALID DATA
DATA3
tASO
tPZL, tPZH
tPLZ, tPHZ
DATA1
DATA2
DATA3
DATA3
Example: Port A / Port D to Port Y
8
IDTQS3ST253
HIGH-SPEEDCMOSSYNCHROSWITCHDUAL4:1MUX/DEMUX
INDUSTRIALTEMPERATURERANGE
ACTIVE TERMINATOR OR “BUS-HOLD” CIRCUIT
TheActiveTerminatorcircuit,alsoknownasthebus-holdcircuit,isconfiguredasa“weaklatch”withpositivefeedback. WhenconnectedtoaTTLorCMOS
inputport,thebus-holdcircuitholdsthelastlogicstateattheinputwhentheinputis“disconnected”fromthedriver. Whentheoutputofadeviceconnected
tosuchaninputattemptsalogicleveltransition,itwilloverdrivethebus-holdcircuit. Theprimarybenefitofabus-holdcircuitisthatitpreventsCMOSinputs
fromfloating,asituationwhichshouldbeavoidedtopreventspuriousswitchingofinputsandunnecessarypowerdissipation.Bus-holdisabettersolutionthan
thetraditionalapproachofusingresistiveterminationtoVccorGNDtopreventbusfloating,becausethebus-holdcircuitdoesnotconsumeanystaticpower.
V-I CHARACTERISTICS OF BUS-HOLD CIRCUIT
IBH
+500
Sinking
Current
( + )
Voltage
+20 IBH
IBHL
IBH
+60
+20
+60
IBHL
VT
– 20 IBH
– 20
– 60
Vcc
IBHH
– 60 IBHL
VIL
VIH
Sourcing
Current
( – )
IBH
– 500
0.8V
2V
VT ≡ Threshold Voltage ≈ 1.5V
VIL ≈ .8 VIH ≈ 2V
ThisfigureshowstheinputV-Icharacteristicsofatypicalbus-holdimplementation. Theinputcharacteristicsresemblearesistor. Astheinputvoltageis
increasedfrom0volts,theinput“sink”currentincreaseslinearly. WhentheTTLthresholdofthecircuitisreached(typically1.5volts),thelatchchangesthe
logicstateduetopositivefeedbackandthedirectionofthecurrentisreversed. AstheinputvoltageisfurtherincreasedtowardsVcc,theinput“source”current
begins to decrease, reaching the lowest level at VIN = Vcc.
9
IDTQS3ST253
HIGH-SPEEDCMOSSYNCHROSWITCHDUAL4:1MUX/DEMUX
INDUSTRIALTEMPERATURERANGE
ORDERINGINFORMATION
XX
IDTQS
XXXXX
X
Package
Process
Device Type
Industrial (-40°C to +85°C)
Blank
Q
Quarter Size Small Outline Package
High Speed CMOS SynchroSwitch Dual 4:1
Mux/Demux with Active Terminators
3ST253
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www.idt.com
10
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