IDTQS5930-50TQ [IDT]
PLL Based Clock Driver, 5930 Series, 6 True Output(s), 0 Inverted Output(s), CMOS, PDSO20, QSOP-20;
| 型号： | IDTQS5930-50TQ |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | PLL Based Clock Driver, 5930 Series, 6 True Output(s), 0 Inverted Output(s), CMOS, PDSO20, QSOP-20 驱动 光电二极管 逻辑集成电路 |
| 文件： | 总6页 (文件大小：67K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LOW SKEW CMOS PLL
CLOCK DRIVER WITH
QS5930T
INTEGRATED LOOP FILTER
FEATURES:
DESCRIPTION
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5V operation
Q/2 output, 5 Q outputs
The QS5930T Clock Driver uses an internal phase locked loop
(PLL) to lock low skew outputs to a reference clock input. Six outputs
are available: Q0–Q4, Q/2. Careful layout and design ensure < 250ps
skew between the Q0–Q4, and Q/2 outputs. The QS5930T includes
an internal RC filter which provides excellent jitter characteristics and
eliminates the need for external components. Various combinations of
feedback and a divide-by-2 in the VCO path allow applications to be
customized for linear VCO operation over a wide range of input SYNC
frequencies. The PLL can also be disabled by the PLL_EN signal to
allow low frequency or DC testing. The QS5930T is designed for use
in cost sensitive high-performance computing systems, workstations,
multi-board computers, networking hardware, and mainframe sys-
tems. Several can be used in parallel or scattered throughout a sys-
tem for guaranteed low skew, system-wide clock distribution networks.
In the QSOP package, the QS5930T clock driver represents the best
value in small form factor, high-performance clock management prod-
ucts.
Useful for Pentium, PowerPC, and PCI systems
Internal loop filter RC network
Low noise TTL level outputs
<250ps rising edge output skew
Balanced drive outputs ±24mA
PLL bypass feature for low frequency testing
Internal VCO/2 option for wider frequency range
Outputs tri-state and reset while OE/RST is low
ESD > 2000V
Latch up > -300mA
Available in QSOP package
For more information on PLL clock driver products, see Application
Note AN-227.
FUNCTIONALBLOCKDIAGRAM
FEEDBACK
PLL_EN
FREQ_SEL
SYNC
OE/RST
0
1
1
0
PHASE
LOOP
VCO
/2
DETECTOR
FILTER
R
D
R
D
R
D
R
D
R
D
R
Q
D
Q
Q
Q
Q
Q
Q
Q/2
Q4
Q3
Q2
Q1
Q0
INDUSTRIAL TEMPERATURE RANGE
SEPTEMBER 2000
1
c
2000 Integrated Device Technology, Inc.
DSC-5849/1
QS5930T
INDUSTRIALTEMPERATURERANGE
LOWSKEWCMOSPLLCLOCKDRIVERWITHINTEGRATEDLOOPFILTER
ABSOLUTE MAXIMUM RATINGS (1)
PINCONFIGURATION
Symbol
Rating
Max.
Unit
AVDD,VDD Supply Voltage to Ground
DC Input Voltage VIN
–0.5 to +7
V
–0.5 to +7
–3
V
V
GND
OE/RST
1
2
3
4
5
6
7
8
9
10
Q4
20
19
18
17
16
15
14
13
12
11
AC Input Voltage (for pulse width ≤ 20ns)
Q/2
GND
Q3
Maximum Power Dissipation (TA = 85°C)
Storage Temperature Range
1
W
FEEDBACK
TSTG
–65 to +150
°C
AVDD
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
VDD
VDD
Q2
AGND
SYNC
GND
PLL_EN
GND
Q1
FREQ_SEL
GND
CAPACITANCE (TA = 25° C, f = 1MHz, V = 0V)
IN
Q0
Pins
Typ.
Max.
Unit
CIN
3
4
pF
COUT
7
9
pF
QSOP
TOP VIEW
PIN DESCRIPTION
Pin Name
SYNC
I/O
I
Description
Reference clock input
FREQ_SEL
I
VCO frequency select. For choosing optimal VCO operating frequency depending on input frequency. HIGH is for higher
frequencies, LOW is for lower frequencies.
FEEDBACK
I
PLL feedback input which is connected to either a Q or a Q/2 output. External feedback provides flexibility for different output
frequency relationships. See the Frequency Selection Table for more information.
Clock outputs
Q0 -Q4
Q/2
O
O
I
Clock output. Matched in phase, but frequency is half the Q frequency.
OE/
RST
Output enable/asynchronous reset. Resets all output registers. When 0, all outputs are held in a tri-stated condition. When 1,
outputs are enabled.
PLL_EN
VDD
I
PLL enable. Enables and disables the PLL. Allows the SYNC input to be single-stepped for system debug.
—
—
—
—
Power supply for output buffers.
AVDD
GND
Power supply for phase lock loop and other internal circuitries.
Ground supply for output buffers.
AGND
Ground supply for phase lock loop and other internal circuitries.
OUTPUT FREQUENCY SPECIFICATIONS
Industrial: TA = –40°C to +85°C, AVDD/VDD = 5V ± 10%
Symbol
FMAX_Q
FMAX_Q/2
FMIN_Q
Description
– 50
50
– 66
66
Units
MHz
MHz
MHz
MHz
Max Frequency, Q0 - Q4,
Max Frequency, Q/2
Min Frequency, Q0 - Q4
Min Frequency, Q/2
25
33
28
28
FMIN_Q/2
14
14
2
QS5930T
INDUSTRIALTEMPERATURERANGE
LOWSKEWCMOSPLLCLOCKDRIVERWITHINTEGRATEDLOOPFILTER
FREQUENCY SELECTION TABLE
SYNC (MHz)
Output Used for
Feedback
(allowable range) (1)
Output Frequency Relationships
FREQ_SEL
HIGH
Min.
14
28
7
Max
Q/2
Q0 - Q4
SYNC X 2
SYNC
Q/2
Q0 -Q4
Q/2
FMAX _Q/2
FMAX _Q
SYNC
HIGH
SYNC / 2
SYNC
LOW
FMAX _Q/2 /2
FMAX _Q /2
SYNC X 2
SYNC
LOW
Q0 -Q4
14
SYNC / 2
NOTE:
1. Operation in the specified SYNC frequency range guarantees that the VCO will operate in its optimal range of 28MHz to FMAX_Q x2. Operation with
Sync inputs outside specified frequency ranges may result in out-of-lock outputs. FREQ_SEL only affects VCO frequency and does not affect output
frequencies.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Industrial: TA = –40°C to +85°C, AVDD/VDD = 5V ± 5%
Symbol
Parameter
Input HIGH Voltage
Conditions
Min.
Typ.
Max.
Unit
VIH
Guaranteed Logic HIGH Level
2
—
—
V
VIL
Input LOW Voltage
Guaranteed Logic LOW Level
IOH = −24mA
—
2.4
3
—
—
—
—
—
—
0.8
—
V
V
VOH
Output HIGH Voltage
IOH = −100μA
—
V
VOL
Output LOW Voltage
VDD = Min., IOL = 24mA
VDD = Min., IOL = 100μA
—
—
—
0.55
0.2
5
V
V
IOZ
IIN
Output Leakage Current
Input Leakage Current
VOUT = VDD or GND,
VDD = Max., Outputs Disabled
AVDD = Max., VIN = AVDD or GND
μA
—
—
5
μA
POWER SUPPLY CHARACTERISTICS
Symbol
Parameter
Test Conditions
VDD = Max., OE/RST = LOW,
SYNC = LOW, All outputs unloaded
VDD = Max., VIN = 3V
Typ.
Max.
Unit
IDDQ
Quiescent Power Supply Current
—
1
mA
ΔIDD
Power Supply Current per Input HIGH
Dynamic Power Supply Current
1
30
μA
IDDD
VDD = Max., CL = 0pF
0.2
0.3
mA/MHz
INPUT TIMING REQUIREMENTS
Symbol
Description (1)
Min.
Max.
Unit
tR, tF
Maximum input rise and fall times, 0.8V to 2V
Input Clock Frequency, SYNC (1)
Input clock pulse, HIGH or LOW (2)
Duty Cycle, SYNC (2)
—
3
ns
FI
tPWC
DH
7
2
FMAX _Q
—
MHz
ns
25
75
%
NOTES:
1. See Output Frequency and Frequency Selection tables for more detail on allowable SYNC input frequencies for different speed grades with
different FEEDBACK and FREQ_SEL combinations.
2. Where pulse witdh implied by DH is less than tWPC limit, tWPC limit applies
3
QS5930T
INDUSTRIALTEMPERATURERANGE
LOWSKEWCMOSPLLCLOCKDRIVERWITHINTEGRATEDLOOPFILTER
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
Symbol
Parameter (1)
Min.
Max.
Unit
tSKR
Output Skew Between Rising Edges, Q0-Q4 (and Q/2) (2)
—
250
ps
tSKF
tPW
tJ
Output Skew Between Falling Edges, Q0-Q4 (and Q/2) (2)
Pulse Width, Q0-Q4, Q/2 outputs, 80MHz
Cycle-to-Cycle Jitter, FI > 33MHz ( 4)
—
TCY/2 − 0.5
—
350
TCY/2 + 0.5
250
ps
ns
ns
ps
ns
tPD
SYNC Input to Feedback Delay ( 5)
− 100
0
+400
tPZH
tPZL
tPHZ
tPLZ
tR, tF
Output Enable Time, OE/RST LOW to HIGH ( 3)
7
Output Disable Time, OE/RST HIGH to LOW ( 3)
0
6
ns
ns
Output Rise/Fall Times, 0.8V to 2V
0.4
1.5
NOTES:
1. See Test Loads and Waveforms for test load and termination.
2. Skew specifications apply under identical environments (loading, temperature, VDD, device speed grade).
3. Measured in open loop mode PLL_EN = 0.
4. Jitter is characterized with Q output at 20MHz. See Frequency Selection Table for information on proper FREQ_SEL level for specified input
frequencies.
5. tPD measured at device inputs at 1.5V, Q output at 28MHz.
4
QS5930T
INDUSTRIALTEMPERATURERANGE
LOWSKEWCMOSPLLCLOCKDRIVERWITHINTEGRATEDLOOPFILTER
AC TEST LOADS AND WAVEFORMS
VDD
300Ω
160Ω
7.0V
OUTPUT
OUTPUT
300Ω
30pF
28pF
68Ω
TEST CIRCUIT 1
TEST CIRCUIT 2
PLLOPERATION
The Phase Locked Loop (PLL) circuit included in the QS5930T
provides for replication of incoming SYNC clock signals. Any manipu-
lation of that signal, such as frequency multiplying, is performed by
digital logic following the PLL (see the block diagram). The key advan-
tage of the PLL circuit is to provide an effective zero propagation delay
between the output and input signals. In fact, adding delay circuits in
the feedback path, ‘propagation delay’ can even be negative! A simpli-
fied schematic of the QS5930T PLL circuit is shown below:
SIMPLIFIEDDIAGRAMOFQS5930TFEEDBACK
Q
Q/2
INPUT
VCO/2
/2
PHASE
DETECTOR
The phase difference between the output and the input frequencies
feeds the VCO which drives the outputs. Whichever output is fed back,
it will stabilize at the same frequency as the input. Hence, this is a true
negative feedback closed loop system. In most applications, the output
will optimally have zero phase shift with respect to the input. In fact, the
internal loop filter on the QS5930T typically provides within 150ps of
phase shift between input and output.
If the user wishes to vary the phase difference (typically to compen-
sate for backplane delays), this is most easily accomplished by adding
delay circuits to the feedback path. The respective output used for
feedback will be advanced by the amount of delay in the feedback
path. All other outputs will retain their proper relationships to that output.
5
QS5930T
INDUSTRIALTEMPERATURERANGE
LOWSKEWCMOSPLLCLOCKDRIVERWITHINTEGRATEDLOOPFILTER
ORDERINGINFORMATION
QS
XXXX
X
XX
X
Device Type
Speed
Package
Process
Industrial (-40°C to +85°C)
Blank
Q
Quarter Size Outline Package
-50T
-66T
50MHz. max. frequency
66MHz. max. frequency
Low Skew CMOS PLL Clock Driver
with Integrated Loop Filter
5930
CORPORATE HEADQUARTERS
6024 Silver Creek Valley Road
San Jose, CA 95138
for SALES:
800-345-7015 or 408-284-8200
fax: 408-284-2775
for Tech Support:
logichelp@idt.com
www.idt.com
6
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