IDTQS74FCT2823ATSO8 [IDT]
Bus Driver, FCT Series, 1-Func, 9-Bit, True Output, CMOS, PDSO24, SOIC-24;
| 型号： | IDTQS74FCT2823ATSO8 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Bus Driver, FCT Series, 1-Func, 9-Bit, True Output, CMOS, PDSO24, SOIC-24 驱动 光电二极管 逻辑集成电路 |
| 文件： | 总7页 (文件大小：60K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HIGH-SPEED CMOS
IDTQS74FCT2823AT/BT
BUS INTERFACE
9-BIT REGISTER
DESCRIPTION:
FEATURES:
The IDTQS74FCT2823T is a 9-bit high-speed CMOS TTL-compatible
• CMOS power levels: <7.5mW static
• Undershoot clamp diodes on all outputs
• True TTL input and output compatibility
• Ground bounce controlled outputs
• Reduced output swing of 0 to 3.5V
• Built-in 25Ω series resistor outputs reduce reflection and other
system noise
buffered register with 3-state outputs, with a 25Ωresister that is useful for
drivingtransmissionlinesandreducingsystemnoise. The2823seriesparts
can replace the 823 series to reduce noise in an existing design. All inputs
have clamp diodes for undershoot noise suppression. All outputs have
ground bounce suppression. Outputs will not load an active bus when Vcc
is removed from the device.
• A and B speed grades
• IOL = 12mA
• Available in SOIC and QSOP packages
FUNCTIONALBLOCKDIAGRAM
14
EN
Q
D
Yx
25Ω
Dx
13
CP
CP
CLR
11
1
CLR
OE
INDUSTRIAL TEMPERATURE RANGE
MARCH 2002
1
c
2002 Integrated Device Technology, Inc.
DSC-5257/4
IDTQS74FCT2823AT/BT
HIGH-SPEEDCMOSBUSINTERFACE9-BITREGISTER
INDUSTRIALTEMPERATURERANGE
ABSOLUTEMAXIMUMRATINGS(1)
PINCONFIGURATION
Symbol
VTERM
TSTG
IOUT
Description
Max
–0.5 to +7
–65 to +150
120
Unit
V
Terminal Voltage with Respect to GND
Storage Temperature
24
23
22
21
20
19
18
17
16
15
14
13
1
2
3
4
VCC
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
EN
CP
OE
D0
D1
°C
mA
mA
mA
DC Output Current Max Sink Current/Pin
Input Diode Current, VIN < 0
IIK
–20
IOK
Output Diode Current, VOUT < 0
–50
D2
D3
NOTE:
5
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
6
D4
7
D5
8
D6
9
D7
CAPACITANCE (TA = +25°C, F = 1.0MHz)
10
11
12
D8
Symbol
Parameter(1)
Conditions
Typ.
Max. Unit
CLR
GND
(2)
CIN
Input Capacitance
Input Capacitance
Output Capacitance
Output Capacitance
VIN = 0V
4
8
6
8
—
—
—
—
pF
pF
pF
pF
(3)
CIN
VIN = 0V
(4)
COUT
VOUT = 0V
VOUT = 0V
(5)
COUT
SOIC/ QSOP
TOP VIEW
NOTES:
1. This parameter is measured at characterization but not tested.
2. Pins 1, 3-11, 13.
3. Pin 2.
4. Pins 15-22.
5. Pins 14, 23.
PINDESCRIPTION
Pin Names
Dx
I/O
Description
LOGICSYMBOL
I
I
DFlip-FlopDataInputs
CLR
When the clear input is LOW and OE is LOW, the Yx
outputsareLOW. WhenclearinputisHIGH,datacan
beenteredintotheregister.
9
9
Dx
D
Q
Yx
CP
I
ClockPulsefortheregister. Entersdataintotheregister
ontheLOW-to-HIGHtransition.
CLR
CP
EN
Y x
O
I
Register3-StateOutputs
EN
Clock Enable. When the clock enable is LOW, data
ontheDx inputistransferredtotheYxoutputonthe
LOW-to-HIGHclocktransition.Whentheclock
enable is HIGH, the Yx outputs do not change state,
regardlessofthedataorclockinputtransitions.
CP
EN
CLR
OE
OE
I
Output Control. When the OE input is HIGH, the Yx
outputsareinthehighimpedancestate. WhentheOE
inputisLOW,theTRUEregisterdataispresentatthe
Yxoutputs.
2
IDTQS74FCT2823AT/BT
HIGH-SPEEDCMOSBUSINTERFACE9-BITREGISTER
INDUSTRIALTEMPERATURERANGE
FUNCTIONTABLE(1)
Inputs
Internal
Outputs
OE
H
H
H
L
CLR
X
EN
L
Dx
L
CP
↑
↑
X
Qx
L
Yx
Z
Function
High Z
High Z
Clear
Clear
Hold
X
L
H
X
X
X
X
L
H
Z
L
X
X
H
H
L
L
Z
L
X
L
L
H
L
H
X
N C
N C
L
Z
H
X
N C
Z
Hold
H
H
L
H
↑
↑
↑
↑
Load
H
L
H
L
H
Z
Load
H
L
L
L
Load
L
H
L
H
H
H
Load
NOTE:
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don't Care
NC = No Change
↑ = LOW-to-HIGH transition
Z = High-Impedance
DCELECTRICALCHARACTERISTICSOVEROPERATINGRANGE
FollowingConditionsApplyUnlessOtherwiseSpecified:
Industrial: TA = –40°C to +85°C, VCC = 5.0V ±5%
Symbol
VIH
Parameter
Input HIGH Level
Test Conditions
Guaranteed Logic HIGH Level
Min.
2
Typ.(1)
—
Max.
Unit
V
—
0.8
—
VIL
Input LOW Level
Guaranteed Logic LOW Level
VTLH - VTHL for all inputs
VCC = Max.
—
—
V
∆VT
IIH
Input Hysteresis
—
0.2
V
Input HIGH Current
Input LOW Current
Off-State Output Current (Hi-Z)
Current Drive
0 ≤ VIN ≤ VCC
0 ≤ VIN ≤ VCC
—
—
±5
µA
IIL
IOZ
IOR
VIC
VCC = Max
—
50
—
2.4
—
18
—
—
±5
—
µA
mA
V
VCC = Max., VOUT = 2.0V(2)
VCC = Min, IIN = -18mA , TA = 25°C(2)
VCC = Min.
Input Clamp Voltage
Output HIGH Voltage
OutputLOWVoltage
OutputResistance
–0.7
—
–1.2
—
VOH
VOL
IOH = -15mA
IOL = 12mA
IOH = 12mA
V
VCC = Min.
—
0.5
40
V
(3)
ROUT
VCC = Min.
25
Ω
NOTES:
1. Typical values are at VCC = 5.0V, TA = 25°C.
2. This parameter is measured at characterization but not tested.
3. ROUT changed on March 8, 2002. See rear page for more information.
3
IDTQS74FCT2823AT/BT
HIGH-SPEEDCMOSBUSINTERFACE9-BITREGISTER
INDUSTRIALTEMPERATURERANGE
POWERSUPPLYCHARACTERISTICS
FollowingConditionsApplyUnlessOtherwiseSpecified:
Industrial: TA = -40°C to +85°C, VCC = 5.0V ± 5%
Symbol
Parameter
TestConditions(1)
VCC = Max.
Min.
Max.
Unit
ICC
Quiescent Power Supply Current
—
1.5
mA
freq = 0
0V ≤ VIN ≤ 0.2V or
VCC - 0.2V ≤ VIN ≤ Vcc
VCC = Max.
∆ICC
Supply Current per Input TTL Inputs HIGH
Supply Current per Input per MHz
—
—
2
mA
VIN = 3.4V(2)
freq = 0
ICCD
VCC = Max.
0.25
mA/MHz
OutputsOpenandEnabled
OneBitToggling
50% Duty Cycle
Other inputs at GND or Vcc(3,4)
NOTES:
1. For conditions shown as Min. or Max., use the appropriate values specified under DC Electrical Characteristics.
2. Per TLL driven input (VIN = 3.4V).
3. For flip-flops, ICCD is measured by switching one of the data input pins so that the output changes every clock cycle. This is a measurement of device power consumption
only and does not include power to drive load capacitance or tester capacitance.
4. IC = IQUIESCENT + IINPUTS + IDYNAMIC
IC = ICC + ∆ICC DHNT + ICCD (fCP/2 + fiNi)
ICC = Quiescent Current
∆ICC = Power Supply Current for a TTL High Input (VIN = 3.4V)
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICCD = Dynamic Current Caused by an Output Transition Pair (HLH or LHL)
fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fi = Input Frequency
Ni = Number of Inputs at fi
All currents are in milliamps and all frequencies are in megahertz.
4
IDTQS74FCT2823AT/BT
HIGH-SPEEDCMOSBUSINTERFACE9-BITREGISTER
INDUSTRIALTEMPERATURERANGE
SWITCHINGCHARACTERISTICSOVEROPERATINGRANGE(1)
FCT2823AT
FCT2823BT
Symbol
tPLH
tPHL
tPLH
tPHL
tSU
Parameter
Min.
Max.
Min.
Max.
Unit
Clock to Y Delay
OE = LOW
Clock to Y Delay
OE = LOW(2)
—
10
—
—
7.5
ns
—
20
15
ns
Data to CP Setup Time
Data to CP Hold Time
EN to CP Setup Time
EN to CP Hold Time
4
2
4
2
—
—
—
—
3
1.5
3
—
—
—
—
ns
ns
ns
ns
tH
tENS
tENH
0
NOTES:
1. CLOAD = 50pF, RLOAD = 500Ω unless otherwise noted.
2. CLOAD = 300pF.
TIMINGREQUIREMENTSOVEROPERATINGRANGE(1)
FCT2823AT
FCT2823BT
Symbol
tCLR
Parameter(2)
Min.
—
6
Max.
11
Min.
—
6
Max.
9
Unit
ns
CLR to Y Delay
tREC
tPLH
CLR to CP Setup Time
Clock Pulse Width
HIGH or LOW
OutputEnableTime
OE to Yx
OutputEnableTime(3)
OE to Yx
OutputDisableTime(4)
—
—
ns
7
—
6
—
ns
tPHL
tPZH
tPZL
—
—
—
—
12
23
7
—
—
—
—
8
ns
ns
ns
ns
tPZH
tPZL
—
tPHZ
tPLZ
6.5
7.5
OE to Yx
OutputDisableTime
OE to Yx
tPHZ
tPLZ
9
NOTES:
1. CLOAD = 50pF, RLOAD = 500Ω unless otherwise noted.
2. See Test Circuits and Waveforms
3. CLOAD = 300pF.
4. CLOAD = 5pF.
5
IDTQS74FCT2823AT/BT
HIGH-SPEEDCMOSBUSINTERFACE9-BITREGISTER
INDUSTRIALTEMPERATURERANGE
TESTCIRCUITSANDWAVEFORMS
SWITCHPOSITION
VCC
7.0V
Test
Switch
Closed
Open
500Ω
Open Drain
Disable Low
Enable Low
VOUT
VIN
Pulse
Generator
D.U.T.
All Other Tests
50pF
500Ω
RT
DEFINITIONS:
CL = Load capacitance: includes jig and probe capacitance.
CL
RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.
FCTL link
Test Circuits for All Outputs
3V
DATA
1.5V
0V
INPUT
LOW-HIGH-LOW
tH
tSU
1.5V
PULSE
3V
1.5V
0V
TIMING
INPUT
ASYNCHRONOUS CONTROL
tW
tREM
PRESET
CLEAR
ETC.
3V
1.5V
0V
HIGH-LOW-HIGH
PULSE
1.5V
SYNCHRONOUS CONTROL
PRESET
3V
FCTL link
1.5V
0V
CLEAR
tSU
tH
CLOCK ENABLE
ETC.
Pulse Width
FCTL link
Set-Up, Hold, and Release Times
ENABLE
DISABLE
3V
1.5V
0V
3V
SAME PHASE
CONTROL
INPUT
1.5V
0V
INPUT TRANSITION
tPLH
tPLH
tPHL
tPHL
tPZL
tPLZ
VOH
1.5V
VOL
OUTPUT
3.5V
1.5V
3.5V
VOL
OUTPUT
NORMALLY
LOW
SWITCH
CLOSED
0.3V
0.3V
3V
1.5V
0V
tPZH
tPHZ
OPPOSITE PHASE
INPUT TRANSITION
VOH
OUTPUT
NORMALLY
HIGH
SWITCH
OPEN
1.5V
0V
FCTL link
0V
FCTL link
Propagation Delay
Enable and Disable Times
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns.
6
IDTQS74FCT2823AT/BT
HIGH-SPEEDCMOSBUSINTERFACE9-BITREGISTER
INDUSTRIALTEMPERATURERANGE
ORDERINGINFORMATION
XX
FCT
XXXX
XX
IDTQS
Temp. Range
Device Type Package
Small Outline IC (gull wing)
Quarter Size Small Outline Package
SO
Q
2823AT
2823BT
High-Speed CMOS Bus Interface 9-Bit Register
–40°C to +85°C
74
As per PCN L0201-02, the Output Resistance (ROUT) specifications have changed as of March 8, 2002. The original specifications were:
Parameter
Description
Min.
Typ.
Max. Unit
40
ROUT
VCC = Min, IOL = 12mA
20
28
Ω
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7
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