M1020-11-125.0000T [IDT]
CLCC-36, Reel;
| 型号： | M1020-11-125.0000T |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | CLCC-36, Reel ATM 异步传输模式 电信 电信集成电路 |
| 文件： | 总10页 (文件大小：305K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
P r o d u c t D a t a S h e e t
Integrated
Circuit
Systems, Inc.
M1020/21
VCSO BASED CLOCK PLL
GENERAL DESCRIPTION
PIN ASSIGNMENT (9 x 9 mm SMT)
The M1020/21 is a VCSO (Voltage Controlled SAW
Oscillator) based clock jitter
attenuator PLL designed for clock
jitter attenuation and frequency
translation. The device is ideal for
generating the transmit reference
clock for optical network systems
supporting up to 2.5Gb data rates.
It can serve to jitter attenuate a
MR_SEL2
MR_SEL0
MR_SEL1
LOL
P_SEL0
P_SEL1
nFOUT0
FOUT0
GND
nFOUT1
FOUT1
VCC
28
29
30
31
18
17
16
15
14
13
12
11
10
M1020
M1021
NBW
VCC
32
33
34
35
36
stratum reference clock or a recovered clock in loop
timing mode. The M1020/21 module includes a
proprietary SAW (surface acoustic wave) delay line as
part of the VCSO. This results in a high frequency,
high-Q, low phase noise oscillator that assures low
intrinsic output jitter.
( T o p V i e w )
DNC
DNC
DNC
GND
FEATURES
◆ Integrated SAW delay line; low phase jitter of < 0.5ps
rms, typical (12kHz to 20MHz)
Figure 1: Pin Assignment
◆ Output frequencies of 62.5 to 175 MHz
Example I/O Clock Frequency Combinations
Using M1020-11-155.5200 or M1021-11-155.5200
(Specify VCSO output frequency at time of order)
◆ LVPECL clock output (CML and LVDS options available)
◆ Reference clock inputs support differential LVDS,
PLL Ratio
Output Clock
Input Reference
Clock (MHz)
LVPECL, as well as single-ended LVCMOS, LVTTL
(Pin Selectable)
(MHz)
(Pin Selectable)
◆ Loss of Lock (LOL) output pin
(M1020)
(M1021)
(M1020) (M1021)
◆ Narrow Bandwidth control input (NBW pin)
19.44 or 38.88
8 or 4
2
1
155.52
or
77.76
◆ Hitless Switching (HS) options with or without Phase
Build-out (PBO) to enable SONET (GR-253) / SDH
(G.813) MTIE and TDEV compliance during reselection
77.76
155.52
622.08
0.25
◆ Pin-selectable feedback and reference divider ratios
◆ Industrial temperature grade available
◆ Single 3.3V power supply
Table 1: Example I/O Clock Frequency Combinations
◆ Small 9 x 9 mm SMT (surface mount) package
SIMPLIFIED BLOCK DIAGRAM
Loop
Filter
M1020/21
NBW
LOL
MUX
Phase
Detector
DIF_REF0
0
nDIF_REF0
R Div
VCSO
DIF_REF1
nDIF_REF1
1
M Divider
REF_SEL
4
2
M/R Divider
LUT
MR_SEL3:0
FOUT0
nFOUT0
P Divider
TriState
(1, 2, or TriState)
FOUT1
nFOUT1
P Divider
LUT
P_SEL1:0
Figure 2: Simplified Block Diagram
M1020/21 Datasheet Rev 1.0
Revised 28Jul2004
M1020/21 VCSO Based Clock PLL
Integrated Circuit Systems, Inc. ● Networking & Communications ● www.icst.com ● tel (508) 852-5400
M1020/21
Integrated
Circuit
Systems, Inc.
VCSO BASED
CLOCK PLL
P r o d u c t D a t a S h e e t
PIN DESCRIPTIONS
Number
1, 2, 3, 10, 14, 26
Name
GND
I/O
Ground
Configuration
Description
Power supply ground connections.
4
9
OP_IN
nOP_IN
Input
External loop filter connections.
See Figure 5, External Loop Filter, on pg. 6.
5
8
nOP_OUT
OP_OUT
Output
6
7
nVC
VC
Input
11, 19, 33
VCC
Power
Power supply connection, connect to +3.3V.
FOUT1
nFOUT1
12
13
Output No internal terminator
Output No internal terminator
Internal pull-down resistor
Clock output 1. Differential LVPECL (CML, LVDS available).
FOUT0
nFOUT0
15
16
Clock output 0. Differential LVPECL (CML, LVDS available).
17
18
P_SEL1
P_SEL0
Post-PLL , P divider selection. LVCMOS/LVTTL. See Table 5,
P Divider Look-Up Table (LUT), on pg. 4.
1
2
20
21
nDIF_REF1
DIF_REF1
Biased to Vcc/2
Reference clock input pair 1. Differential LVPECL or LVDS.
Resistor bias on inverting terminal supports TTL or LVCMOS.
Input
1
1
Internal pull-down resistor
Reference clock input selection. LVCMOS/LVTTL:
Logic 1 selects DIF_REF1, nDIF_REF1.
Logic 0 selects DIF_REF0, nDIF_REF0.
22
REF_SEL
Input
Input
Internal pull-down resistor
2
23
24
nDIF_REF0
DIF_REF0
Biased to Vcc/2
Reference clock input pair 0. Differential LVPECL or LVDS.
Resistor bias on inverting terminal supports TTL or LVCMOS.
1
Internal pull-down resistor
25
27
28
29
30
NC
No internal connection.
MR_SEL3
MR_SEL2
MR_SEL0
MR_SEL1
M and R divider value selection. LVCMOS/ LVTTL.
Internal pull-down resistor See Tables 3 and 4, M and R Divider Look-Up Tables (LUT)
on pg. 3.
1
Input
Loss of Lock indicator output. Asserted when internal PLL is
3
not tracking the input reference for frequency and phase.
Logic 1 indicates loss of lock.
31
LOL
Output
Input
Logic 0 indicates locked condition.
Narrow Bandwidth enable. LVCMOS/LVTTL:
Logic 1 - Narrow loop bandwidth, RIN = 2100kΩ.
1
32
NBW
DNC
Internal pull-UP resistor
Logic 0 - Wide bandwidth, RIN = 100kΩ.
Internal nodes. Connection to these pins can cause erratic
34, 35, 36
Do Not Connect.
device operation.
Table 2: Pin Descriptions
Note 1: For typical values of internal pull-down and pull-UP resistors, see DC Characteristics on pg. 8.
Note 2: Biased toVcc/2, with 50kΩ to Vcc and 50kΩ to ground. See Differential Inputs Biased to VCC/2 on pg. 8.
Note 3: See LVCMOS Output in DC Characteristics on pg. 8.
M1020/21 Datasheet Rev 1.0
2 of 10
Revised 28Jul2004
Integrated Circuit Systems, Inc. ● Networking & Communications ● www.icst.com ● tel (508) 852-5400
M1020/21
Integrated
Circuit
Systems, Inc.
VCSO BASED
CLOCK PLL
P r o d u c t D a t a S h e e t
DETAILED BLOCK DIAGRAM
RLOOP CLOOP
RPOST
External
Loop Filter
Components
CPOST
CPOST
RLOOP CLOOP
nOP_IN OP_OUT
RPOST
M1020/21
OP_IN
nOP_OUT
nVC
VC
Hitless Switching (HS) Opt.
NBW
LOL
HS with Phase Build-out Opt.
MUX
Phase
Detector
SAW Delay Line
DIF_REF0
Phase
Locked
Loop
0
RIN
nDIF_REF0
R Div
DIF_REF1
Loop Filter
Amplifier
Phase
Shifter
1
nDIF_REF1
(PLL)
VCSO
M Divider
REF_SEL
4
2
M/R Divider
LUT
MR_SEL3:0
FOUT0
P Divider
TriState
nFOUT0
(FOUT0: 1, 2, or TriState),
(FOUT1: 1, 2, or TriState)
FOUT1
nFOUT1
P Divider
LUT
P_SEL1:0
Figure 3: Detailed Block Diagram
DIVIDER SELECTION TABLES
M and R Divider Look-Up Tables (LUT)
The MR_SEL3:0 pins select the feedback and reference
divider values M and R to enable adjustment of loop
bandwidth and jitter tolerance. The look-up tables vary
by device variant. M1020 and M1021 are defined in
Tables 3 and
4
provide example Fin and phase
detector frequencies with 155.52MHz VCSO
devices (M1020-11-155.5200 and M1021-11-155.5200).
See “Ordering Information” on pg. 10.
Tables
3
and 4 respectively
.
M1020 M/R Divider LUT
M1021 M/R Divider LUT
Phase Det.
Freq. for
Phase Det.
Freq. for
Total
Fin for
Total
Fin for
MR_SEL3:0
MR_SEL3:0
MDiv R Div PLL
155.52MHz
MDiv R Div PLL
155.52MHz
155.52MHz
155.52MHz
Ratio VCSO (MHz)
VCSO (MHz)
Ratio VCSO (MHz)
VCSO (MHz)
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1
8
32
128
512
2
1
4
8
8
19.44
19.44
19.44
19.44
77.76
77.76
77.76
77.76
155.52
155.52
155.52
155.52
N/A
19.44
4.86
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1
4
16
64
256
2
1
4
4
38.88
38.88
38.88
38.88
77.76
77.76
77.76
77.76
155.52
155.52
155.52
155.52
N/A
38.88
4
9.72
16
64
1
8
1.215
0.30375
77.76
19.44
4.86
16
64
1
4
2.43
8
4
0.6075
77.76
19.44
4.86
2
2
8
4
2
8
4
2
32
128
1
16
64
1
2
32
128
1
16
64
1
2
2
1.215
155.52
38.88
9.72
2
1.215
155.52
38.88
9.72
1
1
4
4
1
4
4
1
16
16
1
16
16
1
64
64
1
2.43
64
64
1
2.43
Test Mode1
N/A
0.25
0.25
0.25
N/A
Test Mode1
N/A
0.25
0.25
0.25
N/A
1
4
4
622.08
622.08
622.08
155.52
38.88
9.72
1
4
4
622.08
622.08
622.08
155.52
38.88
9.72
16
64
16
16
16
64
Table 3: M1020 M/R Divider LUT
Table 4: M1021 M/R Divider LUT
Note 1: Factory test mode; do not use.
Note 1: Factory test mode; do not use.
M1020/21 Datasheet Rev 1.0
3 of 10
Revised 28Jul2004
Integrated Circuit Systems, Inc. ● Networking & Communications ● www.icst.com ● tel (508) 852-5400
M1020/21
Integrated
Circuit
Systems, Inc.
VCSO BASED
CLOCK PLL
P r o d u c t D a t a S h e e t
General Guidelines for M and R Divider Selection
General guidelines for M/R divider selection (see
following pages for more detail):
Input Reference Clocks
Two clock reference inputs and a selection mux are
provided. Either reference clock input can accept a
differential clock signal (such as LVPECL or LVDS) or
a single-ended clock input (LVCMOS or LVTTL on the
non-inverting input).
• A lower phase detector frequency should be used for
loop timing applications to assure PLL tracking,
especially during GR-253 jitter tolerance testing. The
recommended maximum phase detector frequency
for loop timing mode is 19.44MHz. The LOL pin should
not be used during loop timing mode.
A single-ended reference clock on the unselected
reference input can cause an increase in output
clock jitter. For this reason, differential reference
inputs are preferred; interference from a differential
input on the non-selected input is minimal.
• When LOL is to be used for system health monitoring,
the phase detector frequency should be 5MHz or
greater. Low phase detector frequencies make LOL
overly sensitive, and higher phase detector
frequencies make LOL less sensitive.
Implementation of single-ended input has been
facilitated by biasing nDIF_REF0 and nDEF_REF1 to Vcc/2,
with 50kΩ to Vcc and 50kΩ to ground. The input clock
structure, and how it is used with either
LVCMOS/LVTTL inputs or a DC- coupled LVPECL
clock, is shown in Figure 4.
P Divider Look-Up Table (LUT)
The P_SEL1 and P_SEL0 pins select the post-PLL divider
values P1 and P0. The output frequency of the SAW
can be divided by 1 or 2, or the outputs can be TriStated.
The outputs can be placed into the valid state
combinations as listed in Table 5.
.
DIF_REF0
M1020-155.5200 or M1021-155.5200
P Values
for FOUT0 for FOUT1
LVCMOS/
LVTTL
Output Frequency (MHz)
P_SEL1:0
VCC
MUX
Ω
50k
FOUT0
FOUT1
Ω
50k
0
nDIF_REF0
0
0
1
1
0
1
0
1
2
1
2
2
1
1
77.76 77.76
155.52 155.52
77.76 155.52
X
VCC
Ω
50k
1
127Ω
DIF_REF1
TriState TriState
N/A
N/A
VCC
VCC
Ω
Ω
50k
82
Table 5: P Divider Look-Up Table (LUT)
LVPECL
Ω
Ω
Ω
127
50k
nDIF_REF1
REF_SEL
FUNCTIONAL DESCRIPTION
82
50k
Ω
The M1020/21 is a PLL (Phase Locked Loop) based
clock generator that generates output clocks synchro-
nized to one of two selectable input reference clocks.
An internal high "Q" SAW delay line provides low jitter
signal performance.
M1020/21
Figure 4: Input Reference Clocks
Differential LVPECL Inputs
Differential LVPECL inputs are connected to both
reference input pins in the usual manner. The external
load termination resistors shown in Figure 4 (the 127Ω
and 82Ω resistors) will work for both AC and DC
coupled LVPECL reference clock lines. These provide
the 50Ω load termination and the VTT bias voltage.
A pin-selected look-up table is used to select the PLL
feedback divider (M Div) and reference divider (R Div)
as shown in Tables
3 and 4 on pg. 3. These look-up
tables provide flexibility in both the overall frequency
multiplication ratio (total PLL ratio) and phase detector
frequency.
Single-ended Inputs
The M1020/21 includes a Loss of Lock (LOL) indicator,
which provides status information to system
management software. A Narrow Bandwidth (NBW)
control pin is provided as an additional mechanism for
adjusting PLL loop bandwidth without affecting the
phase detector frequency.
Single-ended inputs (LVCMOS or LVTTL) are
connected to the non-inverting reference input pin
(DIF_REF0 or DIF_REF1). The inverting reference input pin
(nDIF_REF0 or nDIF_REF1) must be left unconnected.
In single-ended operation, when the unused inverting
input pin (nDIF_REF0 or nDEF_REF1) is left floating (not
connected), the input will self-bias at VCC/2.
Options are available for Hitless Switching (HS) with or
without Phase Build-out (PBO). They provide
SONET/SDH MTIE and TDEV compliance during a
reference clock reselection.
M1020/21 Datasheet Rev 1.0
4 of 10
Revised 28Jul2004
Integrated Circuit Systems, Inc. ● Networking & Communications ● www.icst.com ● tel (508) 852-5400
M1020/21
Integrated
Circuit
Systems, Inc.
VCSO BASED
CLOCK PLL
P r o d u c t D a t a S h e e t
PLL Operation
Loss of Lock Indicator (LOL) Output Pin
The M1020/21 is a complete clock PLL. It uses a phase
detector and configurable dividers to synchronize the
output of the VCSO with the selected reference clock.
Under normal device operation, when the PLL is locked,
the LOL Phase Detector drives LOL to logic 0. Under
circumstances when the VCSO cannot lock to the input
(as measured by a greater than 4 ns discrepancy
between the feedback and reference clock rising edges
at the LOL Phase Detector) the LOL output goes to logic
1. The LOL pin will return back to logic 0 when the phase
detector error is less than 2 ns. The loss of lock
indicator is a low current LVCMOS output.
The “M” divider divides the VCSO output frequency,
feeding the result into the plus input of the phase
detector.
The output of the “R” divider is fed into the minus input
of the phase detector. The phase detector compares its
two inputs. The phase detector output, filtered
externally, causes the VCSO to increase or decrease in
speed as needed to phase- and frequency-lock the
VCSO to the reference input.
Guidelines for Using LOL
In a given application, the magnitude of peak-to-peak
jitter at the phase detector will usually increase as the R
divider is increased. If the LOL pin will be used to detect
an unusual clock condition, or a clock fault, the
MR_SEL3:0 pins should be set to provide a phase detector
frequency of 5MHz or greater. Otherwise, false LOL
indications may result. A phase detector frequency of
10MHz or greater is desirable when reference jitter is
over 500ps, or when the device is used within a noisy
The value of the M divider directly affects closed loop
bandwidth.
The relationship between the nominal VCSO center
frequency (Fvcso), the M divider, the R divider, and the
input reference frequency (Fin) is:
system environment. Refer to Tables
for phase detector frequency when using the
M1020-11-155.5200 or the M1021-11-155.5200.
3 and 4 on pg. 3
M
R
---
Fvcso = Fin ×
For the available M divider and R divider look-up table
combinations, Tables and 4 on pg. 3 list the Total PLL
TriState
3
Ratio as well as Fin when using the M1020-11-155.5200 or
the M1021-11-155.5200. (See “Ordering Information” on pg.
10.)
The TriState feature puts the LVPECL output driver into
a high impedance state, effectively disconnecting the
driver from the FOUT and nFOUT pins of the device. A
logic 0 is then present on the clock net. The impedance
of the clock net is then set to 50Ωby the external circuit
resistors. (This is in distinction to a CMOS output in
TriState, in which case the net goes to a high
impedance and the logic value floats.) The 50Ω
impedance level of the LVPECL TriState allows
manufacturing In-circuit Test to drive the clock net with
an external 50Ω generator to validate the integrity of
clock net and the clock load.
Post-PLL Divider
The M1020/21 also features a post-PLL (P) divider.
By using the P Divider, the device’s output frequency
(Fout) can be the VCSO center frequency (Fvcso) or
1/2 Fvcso, or 0.
The P_SEL0 and P_SEL1 pins select the value for the P
divider. (See Table 5 on pg. 4.)
When the P divider is included, the complete relation-
ship for the output frequency (Fout) is defined as:
Any unused output (single-ended or differential)
should be left unconnected (floating) in system
application. This minimizes output switching current
and therefore minimizes noise modulation of VCSO.
M
Fvcso
-----------------
Fout =
= Fin ×
-------------------
R × P
P
Due to the narrow tuning range of the VCSO
(+200ppm), appropriate selection of all of the following
are required for the PLL be able to lock: VCSO center
frequency, input frequency, and divider selections.
M1020/21 Datasheet Rev 1.0
5 of 10
Revised 28Jul2004
Integrated Circuit Systems, Inc. ● Networking & Communications ● www.icst.com ● tel (508) 852-5400
M1020/21
Integrated
Circuit
Systems, Inc.
VCSO BASED
CLOCK PLL
P r o d u c t D a t a S h e e t
HS/PBO Operation
Optional Hitless Switching and Phase Build-out
Once triggered, the following HS/PBO sequence
occurs:
1.The HS function disables the PLL Phase Detector
and puts the device into NBW (narrow bandwidth)
mode. The internal resistor Rin is changed to
2100kΩ. See the External Loop Filter on pg. 6.
2.If included, the PBO function adds to (builds out) the
phase in the clock feedback path (in VCSO clock
cycle increments) to align the feedback clock with
the (new) reference clock input phase.
3.The PLL Phase Detector is enabled, allowing the
PLL to re-lock.
4.Once the PLL Phase Detector feedback and input
clocks are locked to within 2 ns for eight consecutive
cycles, a timer (WBW timer) for resuming wide
bandwidth (in 175 ns) is started.
5.When the WBW timer times out, the device reverts
to wide loop bandwidth mode (i.e., Rin is returned to
100kΩ) and the HS/PBO function is re-armed.
The M1020/21 is available with a Hitless Switching
feature that is enabled during device manufacturing.
In addition, a Phase Build-out feature is also offered.
These features are offered as device options and are
specified by device order code. Refer to “Ordering
Information” on pg. 10.
The Hitless Switching feature (with or without Phase
Build-out) is designed for applications where switching
occurs between two stable system reference clocks. It
should not be used in loop timing applications, or when
reference clock jitter is greater than 1 ns pk-pk. Hitless
Switching is triggered by the LOL circuit, which is
activated by a 4 ns phase transient. This magnitude of
phase transient can generated by the CDR (Clock &
Data Recovery unit) in loop timing mode, especially
during a system jitter tolerance test. It can also be
generated by some types of Stratum clock DPLLs
(digital PLL), especially those that do not include a post
de-jitter APLL (analog PLL).
Narrow Bandwidth (NBW) Control Pin
When the M1020/21 is operating in wide bandwidth
mode (NBW=0), the optional Hitless Switching function
puts the device into narrow bandwidth mode when
activated. This allows the PLL to lock the new input
clock phase gradually. With proper configuration of the
external loop filter, the output clock complies with MTIE
and TDEV specifications for GR-253 (SONET) and ITU
G.813 (SDH) during input reference clock changes.
A Narrow Loop Bandwidth control pin (NBW pin) is
included to adjust the PLL loop bandwidth. In wide
bandwidth mode (NBW=0), the internal resistor Rin is
100kΩ. With the NBW pin asserted, the internal resistor
Rin is changed to 2100kΩ. This lowers the loop
bandwidth by a factor of about 21 (approximately 2100 /
100) and lowers the damping factor by a factor of about
4.6 (the square root of 21), assuming the same loop
filter components.
The optional proprietary Phase Build-out (PBO)
function enables the PLL to absorb most of the phase
change of the input clock. The PBO function selects a
new VCSO clock edge for the PLL Phase Detector
feedback clock, selecting the edge closest in phase to
the new input clock phase. This reduces re-lock time,
the generation of wander, and extra output clock cycles.
External Loop Filter
To provide stable PLL operation, the M1020/21 requires
the use of an external loop filter. This is provided via the
provided filter pins (see Figure 5).
Due to the differential signal path design, the
implementation requires two identical complementary
RC filters as shown here.
The Hitless Switching and Phase Build-out functions
are triggered by the LOL circuit. For proper operation,
a low phase detector frequency must be avoided. See
“Guidelines for Using LOL” on pg. 5 for information
regarding the phase detector frequency.
RLOOP CLOOP
RPOST
CPOST
CPOST
HS/PBO Triggers
The HS function (or the combined HS/PBO function)
is armed after the device locks to the input clock refer-
ence. Once armed, HS is triggered by the occurance of
a Loss of Lock condition. This would typically occur as a
consequence of a clock reference failure, a clock failure
upstream to the M1020/21, or a M1020/21 clock refer-
ence mux reselection.
RLOOP CLOOP
nOP_IN OP_OUT
RPOST
OP_IN
nOP_OUT
nVC
VC
4
9
8
5
6
7
Figure 5: External Loop Filter
M1020/21 Datasheet Rev 1.0
6 of 10
Revised 28Jul2004
Integrated Circuit Systems, Inc. ● Networking & Communications ● www.icst.com ● tel (508) 852-5400
M1020/21
Integrated
Circuit
Systems, Inc.
VCSO BASED
CLOCK PLL
P r o d u c t D a t a S h e e t
See Table 6, Example External Loop Filter Component
Values on pg. 7.
PLL Simulator Tool Available
A free PC software utility is available on the ICS website
(www.icst.com). The M2000 Timing Modules PLL
Simulator is a downloadable application that simulates
PLL jitter and wander transfer characteristics. This
enables the user to set appropriate external loop
component values in a given application.
PLL bandwidth is affected by loop filter component
values, the “M” value, and the “PLL Loop Constants”
listed in AC Characteristics on pg. 9.
The MR_SEL3:0 settings can be used to actively change
PLL loop bandwidth in a given application. See “M and
R Divider Look-Up Tables (LUT)” on pg. 3.
For guidance on device or loop filter implementa-
tion, contact CMBU (Commercial Business Unit)
Product Applications at (508) 852-5400.
1
Example External Loop Filter Component Values
for M1020-yz-155.5200 and M1021-yz-155.5200
VCSO Parameters: K
= 200kHz/V, R = 100k
Ω
(pin NBW = 0), VCSO Bandwidth = 700kHz.
VCO
IN
Device Configuration
Example External Loop Filter Comp. Values Nominal Performance Using These Values
MR_SEL3:0 MDiv NBW
FREF
FVCSO
RLOOP
CLOOP
RPOST
CPOST
PLL Loop Damping Passband
Bandwidth
315Hz
Factor Peaking(dB)
(MHz)
(MHz)
19.44 2
38.88 3
77.76 4
77.76 5
155.52 4
155.52 5
155.52
155.52
155.52
155.52
155.52
155.52
0 0 0 0
0 0 0 1 16
0 1 0 1
8
0
0
0
0
0
0
5.4
6.7
5.4
6.0
6.7
6.2
0.07
0.05
0.07
0.05
0.05
0.05
6.8kΩ
12kΩ
6.8kΩ
22kΩ 4.7µF
12kΩ 10µF
47kΩ 2.2µF
10µF
10µF
10µF
82kΩ
82kΩ
82kΩ
82kΩ
82kΩ
82kΩ
1000pF
1000pF
1000pF
1000pF
1000pF
1000pF
270Hz
8
315Hz
0 1 1 0 32
1 0 1 0 16
1 0 1 1 64
250Hz
270Hz
266Hz
Table 6: Example External Loop Filter Component Values
Note 1: KVCO , VCSO Bandwidth, M Divider Value, and External Loop Filter Component Values determine Loop Bandwidth, Damping Factor,
and Passband Peaking. For PLL Simulator software, go to www.icst.com.
Note 2: This row is for the M1020 only.
Note 3: This row is for the M1021 only.
Note 4: Optimal for system clock filtering.
Note 5: Optimal for loop timing mode (LOL or Hitless Switching should not be used).
1
ABSOLUTE MAXIMUM RATINGS
Symbol Parameter
Rating
Unit
VI
Inputs
-0.5 to VCC +0.5
V
VO
VCC
TS
Outputs
-0.5 to VCC +0.5
4.6
V
V
Power Supply Voltage
Storage Temperature
-45 to +100
oC
Table 7: Absolute Maximum Ratings
Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional operation of product at these conditions
or any conditions beyond those listed in Recommended Conditions of Operation, DC Characteristics, or
AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect product reliability
.
RECOMMENDED CONDITIONS OF OPERATION
Symbol Parameter
Min
Typ
Max Unit
3.135
3.3
3.465
VCC
Positive Supply Voltage
V
TA
Ambient Operating Temperature
oC
oC
0
Commercial
Industrial
+70
+85
-40
Table 8: Recommended Conditions of Operation
M1020/21 Datasheet Rev 1.0
7 of 10
Revised 28Jul2004
Integrated Circuit Systems, Inc. ● Networking & Communications ● www.icst.com ● tel (508) 852-5400
M1020/21
Integrated
Circuit
Systems, Inc.
VCSO BASED
CLOCK PLL
P r o d u c t D a t a S h e e t
ELECTRICAL SPECIFICATIONS
DC Characteristics
Unless stated otherwise, VCC
= 3.3V +5 = 150-175MHz,
%,TA = 0 oC to +70 oC (commercial), TA = -40 oC to +85 oC (industrial), FVCSO = FOUT
LVPECL outputs terminated with 50Ω to VCC - 2V
Symbol Parameter
Min
Typ
Max Unit Conditions
3.135
3.3
3.465
VCC
ICC
VP-P
VCMR
CIN
IIH
Positive Supply Voltage
V
Power Supply
175
225
Power Supply Current
mA
V
0.15
0.5
Peak to Peak Input Voltage
Common Mode Input
All
Differential
Inputs
DIF_REF0, nDIF_REF0,
DIF_REF1, nDIF_REF1
V
- .85
V
cc
4
Input Capacitance
pF
Input High Current (Pull-down)
Input Low Current (Pull-down)
Internal Pull-down Resistance
Input High Current (Biased)
Input Low Current (Biased)
150 µA
µA
Differential
Inputs with
Pull-down
VCC = VIN
3.456V
=
DIF_REF0, DIF_REF1
IIL
-5
50
R
kΩ
pulldown
150
Differential
Inputs
IIH
IIL
µA
µA
VIN
=
nDIF_REF0, nDIF_REF1
-150
0 to 3.456V
Biased to
VCC/2
See Figure 4
R
Biased to Vcc/2
bias
REF_SEL,
2
VIH
VIL
CIN
IIH
Input High Voltage
Input Low Voltage
V
+ 0.3 V
All LVCMOS
/ LVTTL
Inputs
cc
MR_SEL3, MR_SEL2,
MR_SEL1, MR_SEL0,
P_SEL1, P_SEL0, NBW
0.8
4
-0.3
V
Input Capacitance
Input High Current (Pull-down)
pF
REF_SEL,
LVCMOS /
LVTTL
150 µA
VCC = VIN
3.456V
=
MR_SEL3, MR_SEL2,
MR_SEL1, MR_SEL0,
P_SEL1, P_SEL0
IIL
R
Input Low Current (Pull-down)
Internal Pull-down Resistance
Input High Current (Pull-UP)
-5
µA
kΩ
Inputs with
Pull-down
LVCMOS /
LVTTL
50
50
pulldown
IIH
5
µA
VCC = 3.456V
IN = 0 V
V
NBW
IIL
R
Input Low Current (Pull-UP)
Internal Pull-UP Resistance
Output High Voltage
-150
µA
kΩ
Inputs with
Pull-UP
pullup
VOH
VOL
VP-P
VOH
VOL
V
- 1.4
- 2.0
V
V
- 1.0 V
cc
cc
FOUT0, nFOUT0,
FOUT1, nFOUT1
Differential
Outputs
Output Low Voltage
V
- 1.7 V
cc
cc
1
0.4
0.85
VCC
0.4
Peak to Peak Output Voltage
Output High Voltage
V
V
V
2.4
IOH= 1mA
IOL= 1mA
LVCMOS
Output
LOL
GND
Output Low Voltage
Table 9: DC Characteristics
Note 1: Single-ended measurement. See Figure 6, Output Rise and Fall Time, on pg. 9.
M1020/21 Datasheet Rev 1.0
8 of 10
Revised 28Jul2004
Integrated Circuit Systems, Inc. ● Networking & Communications ● www.icst.com ● tel (508) 852-5400
M1020/21
Integrated
Circuit
Systems, Inc.
VCSO BASED
CLOCK PLL
P r o d u c t D a t a S h e e t
ELECTRICAL SPECIFICATIONS (CONTINUED)
AC Characteristics
Unless stated otherwise, VCC
=
3.3V +
5
%,TA = 0 oC to +70 oC (commercial), TA = -40 oC to +85 oC (industrial), FVCSO = FOUT
Ω to VCC - 2V
= 150-175MHz,
LVPECL outputs terminated with 50
Symbol Parameter
Min
Typ
Max Unit Conditions
DIF_REF0, nDIF_REF0,
DIF_REF1, nDIF_REF1
15
700
175
FIN
Input Frequency
MHz
MHz
FOUT
APR
KVCO
Output Frequency
FOUT0, nFOUT0, FOUT1, nFOUT1
62.5
Commercial
Industrial
Absolute Pull-Range
of VCSO
±120
±50
±200
±150
200
ppm
ppm
VCO Gain
kHz/V
Wide Bandwidth
100
2100
700
kΩ
kΩ
kHz
PLL Loop
Constants
RIN
Internal Loop Resistor
1
Narrow Bandwidth
BWVCSO VCSO Bandwidth
Single Side Band
Fin=19.44 or
1kHz Offset
10kHz Offset
100kHz Offset
-83
dBc/Hz
dBc/Hz
dBc/Hz
38.88_MHz
Φn
Phase Noise
@155.52MHz
-113
-136
Tot. PLL ratio = 8
or 4. See pg. 3
PhaseNoise
and Jitter
Jitter (rms)
@155.52MHz
J(t)
12kHz to 20MHz
0.4
50
0.6
55
ps
2
45
odc
tR
Output Duty Cycle
%
2
Output Rise Time for
FOUT0, nFOUT0, FOUT1, nFOUT
350
450
550
ps
20% to 80%
20% to 80%
1
2
Output Fall Time for
FOUT0, nFOUT0, FOUT1, nFOUT
350
450
550
tF
ps
1
Table 10: AC Characteristics
Note 1: Parameters needed for PLL Simulator software; see Table 6, Example External Loop Filter Component Values, on pg. 7.
Note 2: See Parameter Measurement Information on pg. 9.
PARAMETER MEASUREMENT INFORMATION
Output Rise and Fall Time
Output Duty Cycle
nFOUT
FOUT
80%
80%
VP-P
tPW
(Output Pulse Width)
20%
t
F
20%
Clock Output
t
R
tPERIOD
t
PW
odc =
t
PERIOD
Figure 7: Output Duty Cycle
Figure 6: Output Rise and Fall Time
M1020/21 Datasheet Rev 1.0
9 of 10
Revised 28Jul2004
Integrated Circuit Systems, Inc. ● Networking & Communications ● www.icst.com ● tel (508) 852-5400
P r o d u c t D a t a S h e e t
M1020/21
Integrated
Circuit
Systems, Inc.
VCSO BASED
CLOCK PLL
DEVICE PACKAGE - 9 x 9mm CERAMIC LEADLESS CHIP CARRIER
Mechanical Dimensions:
Refer to the SAW PLL application notes web page at
www.icst.com/products/appnotes/SawPllAppNotes.htm
for application notes, including recommended PCB
footprint, solder mask, and furnace profile.
Figure 8: Device Package - 9 x 9mm Ceramic Leadless Chip Carrier
ORDERING INFORMATION
Part Numbering Scheme
Standard VCSO Output Frequencies (MHz)*
Consult ICS for the availablityofotherVCSOfrequencies
Part Number:
M102x-1z-xxx.xxxx
Frequency Input Divider Option
125.0000
155.5200
156.2500
156.8324
161.1328
166.6286
167.2820
167.3280
167.3316
167.7097
168.0400
172.6423
173.3708
0 = Fin can equal Fvcso divided by: 8, 2, or 1
1 = Fin can equal Fvcso divided by: 4, 2, or 1
Output type
1 = LVPECL
(For CML or LVDS clock output, consult factory)
Hitless Switching / Phase Build-out Options
1 = none
2 = Hitless Switching
3 = Hitless Switching with Phase Build-out
Temperature
0
to +70 o
C
(commercial)
“I-”==- 40 to +85 o
C (industrial)
VCSO Frequency (MHz)
Table 11: Standard VCSO Output Frequencies (MHz)
See Table 11, right. Consult ICS for other frequencies.
Figure 9: Part Numbering Scheme
Note *: Fout can equal Fvcso divided by: 1 or 2
Consult ICS for the availability of other VCSO frequencies.
Example Part Numbers
VCSO Frequency (MHz)
Temperature
commercial
industrial
commercial
industrial
Order Part Number (Examples)
M1020-11-155.5200 or M1021-11-155.5200
155.52
M1020-11
M1020-11-156.2500 or M1021-11-156.2500
M1020-11 156.2500 or M1021-11 156.2500
I155.5200 or M1021-11I155.5200
156.25
I
I
Table 12: Example Part Numbers
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS)
assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would
result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial
applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary
environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any
circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or
critical medical instruments.
M1020/21 Datasheet Rev 1.0
10 of 10
Revised 28Jul2004
Integrated Circuit Systems, Inc. ● Networking & Communications ● www.icst.com ● tel (508) 852-5400
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