M2006-02-627.3296LF [IDT]
PLL Based Clock Driver, 2 True Output(s), 0 Inverted Output(s), CQCC36, 9 X 9 MM, CERAMIC, LCC-36;
| 型号： | M2006-02-627.3296LF |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | PLL Based Clock Driver, 2 True Output(s), 0 Inverted Output(s), CQCC36, 9 X 9 MM, CERAMIC, LCC-36 |
| 文件： | 总8页 (文件大小：365K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
P r o d u c t D a t a S h e e t
Integrated
Circuit
Systems, Inc.
M2006-02
VCSO BASED FEC CLOCK PLL
GENERAL DESCRIPTION
PIN ASSIGNMENT (9 x 9 mm SMT)
The M2006-02 is a VCSO (Voltage Controlled SAW
Oscillator) based clock generator
PLL designed for clock frequency
translation and jitter attenuation.
The device supports both forward
and inverse FEC (Forward Error
Correction) clock multiplication
FIN_SEL0
FEC_SEL0
FEC_SEL1
FEC_SEL2
FEC_SEL3
VCC
P0_SEL
P1_SEL
nFOUT0
FOUT0
GND
nFOUT1
FOUT1
VCC
28
29
30
31
18
17
16
15
14
13
12
11
10
ratios. Multiplication ratios are
M2006-02
pin-selected from pre-programming look-up tables.
32
33
34
35
36
( T o p V i e w )
DNC
DNC
FEATURES
DNC
GND
◆ Pin-selectable PLL divider ratios support forward and
inverse FEC ratio translation, including:
• 255/238 (OTU1) Mapping and 238/255 De-mapping
• 255/237 (OTU2) Mapping and 237/255 De-mapping
• 255/236 (OTU3) Mapping and 236/255 De-mapping
◆ Supports input reference and VCSO frequencies up to
700MHz, supports loop timing modes
(Specify VCSO frequency at time of order)
Figure 1: Pin Assignment
◆ Low phase jitter < 0.5 ps rms typical
(12kHz to 20MHz or 50kHz to 80MHz)
Example I/O Clock Frequency Combinations
Using M2006-02-622.0800 and Inverse FEC Ratios
Base Input Rate 1
◆ Supports active switching between inverse-FEC and
non-FEC clock ratios (same VCSO center frequency)
◆ Ideal for complex ratio FEC ratio translation* and
for use with an unstable reference** (i.e., similar to the
M2006-12 - and pin-compatible - but without the Hitless
Switching and Phase Build-out functions)
Output Clock
FEC PLL Ratio
(either output)
MHz
Mfec / Rfec
(MHz)
1/1
622.0800
666.5143
669.3266
672.1627
622.08
or
155.52
238/255
237/255
236/255
◆ Commercial and Industrial temperature grades
◆ Single 3.3V power supply
Table 1: Example I/O Clock Frequency Combinations
Note 1: Input reference clock can be the base frequency shown
divided by “Mfin” (as shown in Table 3 on pg. 3).
◆ Small 9 x 9 mm SMT (surface mount) package
Note *: Complex ratio FEC ratio translation typically results in
low phase detector frequencies.
Note **: An unstable reference which results in phase detector
jitter beyond 2 ns under normal operating conditions
SIMPLIFIED BLOCK DIAGRAM
Loop
Filter
M2006-02
DIF_REF0
0
nDIF_REF0
Rfec Div
DIF_REF1
1
FOUT0
P0 Div
VCSO
(1 or 4)
nFOUT0
nDIF_REF1
Mfin Div
Mfec Div
(1, 4, 8, or 32)
REF_SEL
4
2
Mfec / Rfec
Divider LUT
FOUT1
FEC_SEL3:0
FIN_SEL1:0
P1 Div
(1 or 4)
nFOUT1
Mfin Divider
LUT
P0_SEL
Figure 2: Simplified Block Diagram
P1_SEL
M2006-02 Datasheet Rev 1.0
Revised 13Jul2004
M2006-02 VCSO Based FEC Clock PLL
Integrated Circuit Systems, Inc. ● Networking & Communications ● www.icst.com ● tel (508) 852-5400
M2006-02
Integrated
Circuit
Systems, Inc.
VCSO BASED FEC CLOCK PLL
P r o d u c t D a t a S h e e t
DETAILED BLOCK DIAGRAM
RLOOP CLOOP
RPOST
External
Loop Filter
Components
CPOST
CPOST
RLOOP CLOOP
nOP_IN OP_OUT
RPOST
M2006-02
OP_IN
RIN
nOP_OUT
nVC
VC
MUX
Phase
Detector
SAW Delay Line
DIF_REF0
0
Phase
Locked
Loop
Rfec
Divider
nDIF_REF0
RIN
DIF_REF1
1
Loop Filter
Amplifier
Phase
Shifter
nDIF_REF1
(PLL)
VCSO
Mfec Divider
Mfin Divider
REF_SEL
P0 Divider
FOUT0
nFOUT0
P = 1 ( P0_SEL = 0 )
or
4 ( P0_SEL = 1 )
4
2
Mfec / Rfec
Divider LUT
FEC_SEL3:0
FIN_SEL1:0
P1 Divider
FOUT1
nFOUT1
Mfin Divider
LUT
P = 1 ( P1_SEL = 0 )
or
4
( P1_SEL = 1 )
P1_SEL
P0_SEL
Figure 3: Detailed Block Diagram
PIN DESCRIPTIONS
Number
1, 2, 3, 10, 14, 26 GND
Name
Configuration
Description
Power supply ground connections.
I/O
Ground
4
9
OP_IN
nOP_IN
Input
5
8
nOP_OUT
OP_OUT
Output
External loop filter connections. See Figure 4.
6
7
nVC
VC
Input
Power
Output
11, 19, 33
VCC
Power supply connection, connect to +3.3V.
12, 13
15, 16
FOUT1, nFOUT1
FOUT0, nFOUT0
No internal terminator
Clock output pairs. Differential LVPECL.
17
18
P1_SEL
P0_SEL
P Divider controls. LVCMOS/LVTTL.
(For P0_SEL, P1_SEL, see Table 5 on pg. 3.
1
Input
Input
Internal pull-down resistor
1
nDIF_REF1
DIF_REF1
Internal pull-UP resistor
Reference clock input pair 1.
Differential LVPECL or LVDS.
20
21
1
1
Internal pull-down resistor
Reference clock input selection. LVCMOS/LVTTL:
Logic 1 selects DIF_REF1, nDIF_REF1.
Logic 0 selects DIF_REF0, nDIF_REF0.
22
REF_SEL
Input
Input
Internal pull-down resistor
1
nDIF_REF0
DIF_REF0
NC
Internal pull-UP resistor
Reference clock input pair 0.
Differential LVPECL or LVDS.
23
24
1
1
Internal pull-down resistor
25
No internal connection.
27
28
FIN_SEL1
FIN_SEL0
Input clock frequency selection. LVCMOS/LVTTL.
(For FIN_SEL1:0, see Table 3 on pg. 3.
Input
Input
Internal pull-down resistor
29
30
31
32
FEC_SEL0
FEC_SEL1
FEC_SEL2
FEC_SEL3
FEC PLL divider ratio selection. LVCMOS/ LVTTL.
(For FEC_SEL3:0, see Table 4 on pg. 3.)
1
Internal pull-UP resistor
Internal nodes. Connection to these pins can
cause erratic device operation.
34, 35, 36
DNC
Do Not Connect.
Table 2: Pin Descriptions
M2006-02 Datasheet Rev 1.0
2 of 8
Revised 13Jul2004
Integrated Circuit Systems, Inc. ● Networking & Communications ● www.icst.com ● tel (508) 852-5400
M2006-02
Integrated
Circuit
Systems, Inc.
VCSO BASED FEC CLOCK PLL
P r o d u c t D a t a S h e e t
Post-PLL Dividers
PLL DIVIDER LOOK-UP TABLES
The M2006-02 also features two post-PLL dividers,
one for each output pair. The “P1” divider is for FOUT1
and nFOUT1; the “P0” divider is for FOUT0 and nFOUT0.
Mfin (Frequency Input) Divider Look-Up Table (LUT)
The FIN_SEL1:0 pins select the feedback divider value
(“Mfin”).
Each divides the VCSO frequency to produce one of
two output frequencies (1/4 or 1/1 of the VCSO
frequency). The P1_SEL and P0_SEL pins each select the
value for their corresponding divider.
M2006-02-622.0800
FIN_SEL1:0
Mfin Value
Sample Ref. Freq. (MHz) 1
1
1
0
0
1
0
1
0
1
4
8
622.08 2
155.52
77.76
P Value
OutMp2u0t0F6-r0e2q-6u2e2.n08c0y0
(MHz)
P1_SEL, P0_SEL
32
19.44
Table 3: Mfin (Frequency Input) Divider Look-Up Table (LUT)
1
0
4
1
155.52
Note 1: Example with M2006-02-622.0800 and “Non-FEC ratio”
622.08
selection made from Table 4 (FEC_SEL2=1).
Table 5: P Divider Selector, Values, and Frequencies
Note 2: Do not use with FEC_SEL3:0=1100 or 1101.
FEC PLL Ratio Dividers Look-up Table (LUT)
FUNCTIONAL DESCRIPTION
The M2006-02 is a PLL (Phase Locked Loop) based
clock generator that generates output clocks synchro-
nized to one of two selectable input reference clocks.
The FEC_SEL3:0 pins select the FEC feedback and
reference divider values Mfec and Rfec.
Mfec Rfec1
Description
FEC_SEL3:0
An internal high "Q" SAW filter provides low jitter signal
performance and controls the output frequency of the
VCSO (Voltage Controlled SAW Oscillator).
0 0 0 0 236 255 Inverse FEC ratio
0 0 0 1 79
0 0 1 0 14
85
15 Inverse FEC ratio, equivalent to 238/255
Inverse FEC ratio, equivalent to 237/255
Configurable FEC feedback and reference dividers (the
“Mfec Divider” and “Rfec Divider”) provide the
multiplication ratios necessary to accomodate clock
translation for both forward and inverse Forward Error
Correction.
0 0 1 1 239 255 Inverse FEC ratio
Non-FEC ratio, complements 0000 or 1000
2
2
2
2
0 1 0 0 236 236
Non-FEC ratio, complements 0001 or 1001
Non-FEC ratio, complements 0010 or 1010
Non-FEC ratio, complements 0011 or 1011
0 1 0 1 79
0 1 1 0 14
79
14
0 1 1 1 239 239
In addition, a configurable feedback divider (labeled
“Mfin Divider”) provides the broader division options
needed to accomodate various reference clock
frequencies.
1 0 0 0 255 236 FEC ratio (OTU3)
1 0 0 1 85
1 0 1 0 15
79 FEC ratio, equivalent to 255/237 (OTU2)
14 FEC ratio, equivalent to 255/238 (OTU1)
1 0 1 1 255 239 FEC ratio
For example, the M2006-02-622.0800 (see “Ordering
Information” on pg. 8) has a 622.08MHz VCSO
frequency:
3
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1
1
2
4
8
1
2
4
8
Non-FEC ratio Do not use these two settings
with FIN_SEL1:0=11
• The inverse FEC PLL ratios (at top of Table 4) enable
the M2006-02-622.0800 to accept “base” input reference
frequencies of: 663.7255, 666.5143, 669.3266,
672.1627, and 622.08MHz.
Non-FEC ratio 3
Table 4: FEC PLL Ratio Dividers Look-up Table (LUT)
Note 1: The phase detector frequency (Fpd, which is calculated as
Fref/Rfec) should be above 1.5 MHz to prevent spurs on the
output clock. To ensure the PLL remains locked when using a
recovered clock (such as in loop timing mode), the phase
detector frequency should ideally be about 20MHz, or at least
less than 50 MHz.
Note 2: These table selections use the same or similar Mfec divider
values as the complementary selections noted. This allows the
use of the same loop filter component values and resulting PLL
loop bandwidth and damping factor values for complementary
selections. Complementary selections can be actively
switched in a given application.
• The Mfin feedback divider enables the actual input
reference clock to be the “base” input frequency
divided by 1, 4, 8, or 32. Therefore, for the base input
frequency of 622.08MHz, the actual input reference
clock frequencies can be: 622.08, 155.52, 77.76, and
19.44MHz. (See Table 3 on pg. 3.)
Note 3: In non-FEC applications, these settings can be used optimize
phase detector frequency or to actively change PLL loop
bandwidth.
M2006-02 Datasheet Rev 1.0
3 of 8
Revised 13Jul2004
Integrated Circuit Systems, Inc. ● Networking & Communications ● www.icst.com ● tel (508) 852-5400
M2006-02
Integrated
Circuit
Systems, Inc.
VCSO BASED FEC CLOCK PLL
P r o d u c t D a t a S h e e t
The PLL
Relationship Among Frequencies and Dividers
The PLL uses a phase detector and configurable
dividers to synchronize the output of the VCSO with
selected reference clock.
The VCSO center frequency must be specified at time
of order. The relationship between the VCSO (Fvcso)
frequency, the Mfin divider, the Mfec divider, the Rfec
divider, and the input reference frequency (Fin) is:
The “Mfin Divider” and “Mfec Divider” divide the VCSO
frequency, feeding the result into the phase detector.
Mfec
Rfec
-------------
Fvcso = Fin × Mfin ×
The selected input reference clock is divided by the
“Rfec Divider”. The result is fed into the other input of
the phase detector.
As an example, for the M2006-02-622.0800, the non-FEC
and inverse-FEC PLL ratios in Table 4 enable use with
these corresponding input reference frequencies:
The phase detector compares its two inputs. It then
outputs pulses to the loop filter as needed to increase or
decrease the VCSO frequency and thereby match and
lock the divider output’s frequency and phase to those
of the input reference clock.
M2006-02-622.0800
VCSO Clock
BMa2s0e06In-0p2-u62t2R.0e8f0.01
Frequency (MHz)
622.0800
=
Frequency (MHz)
FEC Ratio
÷
1
/
/
/
/
1
Due to the narrow tuning range of the VCSO
238
237
236
255
255
255
666.5143
669.3266
672.1627
622.08
(+200ppm), appropriate selection of all of the following
are required for the PLL be able to lock: VCSO center
frequency, input frequency, and divider selections.
Table 6: Example FEC PLL Rations and Input Reference Frequencies
Note 1: Input reference clock (“Fin”) can be the base frequency
shown divided by “Mfin” (as shown in Table 3 on pg. 3).
Maintaining PLL Lock:
The narrow tuning range of the VCSO requires that the
input reference frequency must remain suitable for the
current look-up table selection. For example, when
switching between “Inverse FEC ratio” and “Non-FEC
ratio” look-up table selections (see Table 4 on pg. 3), the
input reference frequency must change accordingly in
order for the PLL to lock.
Outputs
The M2006-02 provides a total of two differential
LVPECL output pairs: FOUT1 and FOUT0. Because each
output pair has its own P divider, the FOUT1 pair and the
FOUT0 can output the two different frequencies at the
same time. For example, FOUT1 can output 155.52MHz
while FOUT0 outputs 622.08MHz.
An out-of-lock condition due to an inappropriate
configuration will typically result in the VCSO
operating at its lower or upper frequency rail,
which is approximately 200ppm above or below
the nominal VCSO center frequency.
Any unused output should be left unconnected
(floating) in the system application. This will
minimize output switching current and therefore
minimize noise modulation of the VCSO.
M2006-02 Datasheet Rev 1.0
4 of 8
Revised 13Jul2004
Integrated Circuit Systems, Inc. ● Networking & Communications ● www.icst.com ● tel (508) 852-5400
M2006-02
Integrated
Circuit
Systems, Inc.
VCSO BASED FEC CLOCK PLL
P r o d u c t D a t a S h e e t
The various “Non-FEC ratio” settings can be used to
actively change PLL loop bandwidth in a given
application. See “FEC PLL Ratio Dividers Look-up
Table (LUT)” on pg. 3.
External Loop Filter
To provide stable PLL operation, and thereby a low jitter
output clock, the M2006-02 requires the use of an
external loop filter. This is provided via the provided
filter pins (see Figure 4).
Consult factory for external loop filter component
values.
Due to the differential signal path design, the
implementation requires two identical complementary
RC filters as shown here.
PLL Simulator Tool Available
RLOOP CLOOP
RPOST
A free PC software utility is available on the ICS website
(www.icst.com). The M2000 Timing Modules PLL
Simulator is a downloadable application that simulates
PLL jitter and wander transfer characteristics. This
enables the user to set appropriate external loop
component values in a given application.
CPOST
CPOST
RLOOP CLOOP
nOP_IN OP_OUT
RPOST
OP_IN
nOP_OUT
nVC
VC
4
9
8
5
6
7
Go to the SAW PLL Simulator Software web page at
www.icst.com/products/calculators/m2000filterSWdesc.htm
Figure 4: External Loop Filter
PLL bandwidth is affected by the “Mfec” value and the
“Mfin” value, as well as the VCSO frequency.
1
ABSOLUTE MAXIMUM RATINGS
Symbol Parameter
Rating
Unit
VI
Inputs
-0.5 to VCC +0.5
V
VO
VCC
TS
Outputs
-0.5 to VCC +0.5
4.6
V
V
Power Supply Voltage
Storage Temperature
-45 to +100
oC
Table 7: Absolute Maximum Ratings
Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional operation of product at these conditions
or any conditions beyond those listed in Recommended Conditions of Operation, DC Characteristics, or
AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect product reliability
.
RECOMMENDED CONDITIONS OF OPERATION
Symbol Parameter
Min
Typ
Max Unit
3.135
3.3
3.465
VCC
Positive Supply Voltage
V
TA
Ambient Operating Temperature
oC
oC
0
Commercial
Industrial
+70
+85
-40
Table 8: Recommended Conditions of Operation
M2006-02 Datasheet Rev 1.0
5 of 8
Revised 13Jul2004
Integrated Circuit Systems, Inc. ● Networking & Communications ● www.icst.com ● tel (508) 852-5400
M2006-02
Integrated
Circuit
Systems, Inc.
VCSO BASED FEC CLOCK PLL
P r o d u c t D a t a S h e e t
ELECTRICAL SPECIFICATIONS
DC Characteristics
Unless stated otherwise, VCC
= 3.3V +5 = 622-675MHz,
%,TA = 0 oC to +70 oC (commercial), TA = -40 oC to +85 oC (industrial), FVCSO = FOUT
LVPECL outputs terminated with 50Ω to VCC - 2V
Symbol Parameter
Power Supply VCC Positive Supply Voltage
Min
3.135
Typ
3.3
Max Unit Conditions
3.465
V
175
225
ICC
VP-P
VCMR
CIN
IIH
Power Supply Current
mA
V
0.15
0.5
All
Differential
Inputs
Peak to Peak Input Voltage
Common Mode Input
DIF_REF0, nDIF_REF0,
DIF_REF1, nDIF_REF1
V
- .85
V
cc
4
Input Capacitance
pF
VCC = VIN
3.456V
=
Differential
Inputs with
Pull-down
Input High Current (Pull-down)
Input Low Current (Pull-down)
Internal Pull-down Resistance
Input High Current (Pull-up)
Input Low Current (Pull-up)
150 µA
µA
DIF_REF0, DIF_REF1
IIL
-5
50
50
R
kΩ
pulldown
VIN
=
5
Differential
Inputs with
Pull-up
IIH
IIL
µA
µA
0 to 3.456V
nDIF_REF0, nDIF_REF1
-150
R
Internal Pull-up Resistance
Input High Voltage
kΩ
pullup
REF_SEL, FIN_SEL1, FIN_SEL0,
FEC_SEL3, FEC_SEL2,
FEC_SEL1, FEC_SEL0,
P1_SEL, P0_SEL
2
All LVCMOS VIH
/ LVTTL
V
+ 0.3 V
cc
0.8
VIL
Input Low Voltage
-0.3
V
Inputs
CIN
4
Input Capacitance
pF
VCC = VIN
3.456V
=
LVCMOS /
LVTTL
IIH
Input High Current (Pull-down)
150 µA
REF_SEL, FIN_SEL1, FIN_SEL0,
P1_SEL, P0_SEL
IIL
R
Input Low Current (Pull-down)
Internal Pull-down Resistance
Input High Current (Pull-up)
-5
µA
kΩ
Inputs with
Pull-down
LVCMOS /
LVTTL
50
50
pulldown
VCC = 3.456V
IN = 0 V
IIH
5
µA
V
FEC_SEL3, FEC_SEL2,
FEC_SEL1, FEC_SEL0
IIL
R
Input Low Current (Pull-up)
Internal Pull-up Resistance
Output High Voltage
-150
µA
kΩ
Inputs with
Pull-up
pullup
Differential
Outputs
VOH
VOL
VP-P
V
- 1.4
- 2.0
V
V
- 1.0 V
cc
cc
FOUT0, nFOUT0,
FOUT1, nFOUT1
Output Low Voltage
V
- 1.7 V
cc
cc
1
0.4
0.85
Peak to Peak Output Voltage
V
Table 9: DC Characteristics
Note 1: Single-ended measurement. See Figure 5, Output Rise and Fall Time, on pg. 7.
M2006-02 Datasheet Rev 1.0
6 of 8
Revised 13Jul2004
Integrated Circuit Systems, Inc. ● Networking & Communications ● www.icst.com ● tel (508) 852-5400
M2006-02
Integrated
Circuit
Systems, Inc.
VCSO BASED FEC CLOCK PLL
P r o d u c t D a t a S h e e t
ELECTRICAL SPECIFICATIONS
AC Characteristics
(CONTINUED)
Unless stated otherwise, VCC
= 3.3V +5 = 622-675MHz,
%,TA = 0 oC to +70 oC (commercial), TA = -40 oC to +85 oC (industrial), FVCSO = FOUT
LVPECL outputs terminated with 50Ω to VCC - 2V
Symbol Parameter
Min
Typ
Max
Unit Test Conditions
Input
Frequency
Range
FIN
Input Frequency
DIF_REF0, nDIF_REF0,
DIF_REF1, nDIF_REF1
10
700
MHz
FOUT0, nFOUT0,
FOUT1, nFOUT1
Output
Frequency
FFOUT
APR
Output Frequency
Range
100
700
MHz
Commercial
Industrial
±120
±50
±200
±150
800
ppm
VCSO Pull-Range
ppm
KVCO
RIN
VCO Gain
kHz/V
PLL Loop
Constants
50
Internal Loop Resistor
kΩ
1
700
BWVCSO VCSO Bandwidth
kHz
Φn
Single Side Band
Phase Noise
1kHz Offset
10kHz Offset
-72
-94
dBc/Hz
Fin=19.44 MHz
dBc/Hz
Mfin=32, Mfec=1, Rfec=1
PhaseNoise
and Jitter
@622.08MHz
100kHz Offset
12kHz to 20MHz
50kHz to 80MHz
P0, P1 = 1
-123
0.5
dBc/Hz
ps rms
ps rms
%
J(t)
tPW
Jitter (rms)
@622.08MHz
0.5
2
Output Duty Cycle
FOUT0, nFOUT0,
40
50
60
45
50
55
P0, P1 = 4
%
FOUT1, nFOUT
1
2
200
200
450
450
500
500
tR
tF
Output Rise Time
ps
ps
20% to 80%
20% to 80%
FOUT0, nFOUT0,
FOUT1, nFOUT1
2
Output Fall Time
Table 10: AC Characteristics
Note 1: Parameters needed for PLL Simulator software; see PLL Simulator Tool Available on pg. 5.
Note 2: See Parameter Measurement Information on pg. 7.
PARAMETER MEASUREMENT INFORMATION
Output Rise and Fall Time
Output Duty Cycle
nFOUT
FOUT
80%
80%
VP-P
tPW
20%
t
F
20%
(Output Pulse Width)
Clock Output
t
R
tPERIOD
t
PW
odc =
t
PERIOD
Figure 6: Output Duty Cycle
Figure 5: Output Rise and Fall Time
M2006-02 Datasheet Rev 1.0
7 of 8
Revised 13Jul2004
Integrated Circuit Systems, Inc. ● Networking & Communications ● www.icst.com ● tel (508) 852-5400
P r o d u c t D a t a S h e e t
M2006-02
VCSO BASED FEC CLOCK PLL
Integrated
Circuit
Systems, Inc.
DEVICE PACKAGE - 9 x 9mm CERAMIC LEADLESS CHIP CARRIER
Mechanical Dimensions:
Refer to the M2006-02 product web page at
www.icst.com/products/summary/m2006-02.htmfor
application notes, including recommended PCB
footprint, solder mask, and furnace profile.
Figure 7: Device Package - 9 x 9mm Ceramic Leadless Chip Carrier
Standard VCSO Output Frequencies (MHz)*
Consult ICS for the availablityofotherVCSOfrequencies
ORDERING INFORMATION
Part Numbering Scheme
622.0800
625.0000
627.3296
644.5313
666.5143
669.1281
669.3120
669.3266
669.6429
670.8386
672.1600
690.5692
Part Number:
M2006-02-xxx.xxxx
Device Number
Temperature
0
to +70 o
C
(commercial)
“I-”==- 40 to +85 o
C (industrial)
VCSO Frequency (MHz)
See Table 11, right. Consult ICS for other frequencies.
Table 11: Standard VCSO Output Frequencies (MHz)
Note *: Fout can equal Fvcso divided by: 1 or 4
Figure 8: Part Numbering Scheme
Consult ICS for the availability of other PLL frequencies.
Example Part Numbers
PLL Frequency (MHz)
Temperature
Order Part Number
commercial
industrial
M2006-02- 622.0800
622.08
M2006-02
M2006-02- 625.0000
M2006-02 625.0000
M2006-02- 669.3266
M2006-02 669.3266
M2006-02- 669.6429
M2006-02 669.6429
I622.0800
commercial
industrial
commercial
industrial
commercial
industrial
625.00
I
669.3266
669.6429
I
I
Table 12: Example Part Numbers
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS)
assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would
result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial
applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary
environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any
circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or
critical medical instruments.
M2006-02 Datasheet Rev 1.0
8 of 8
Revised 13Jul2004
Integrated Circuit Systems, Inc. ● Networking & Communications ● www.icst.com ● tel (508) 852-5400
相关型号：
SI9130DB
5- and 3.3-V Step-Down Synchronous ConvertersWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1-E3
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135_11
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9136_11
Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130CG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130LG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130_11
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137DB
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137LG
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9122E
500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
©2020 ICPDF网 联系我们和版权申明