M2065-12I690.5692LF [IDT]
Support Circuit, 1-Func, CQCC36, 9 X 9 MM, CERAMIC, LCC-36;
| 型号： | M2065-12I690.5692LF |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Support Circuit, 1-Func, CQCC36, 9 X 9 MM, CERAMIC, LCC-36 ATM 异步传输模式 电信 ATM集成电路 SONET集成电路 SDH集成电路 电信集成电路 电信电路 |
| 文件： | 总12页 (文件大小：458K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
P r e l i m i n a r y I n f o r m a t i o n
Integrated
Circuit
Systems, Inc.
M2060/61/62
M2065/66/67
VCSO FEC PLL FOR SONET/OTN
GENERAL DESCRIPTION
PIN ASSIGNMENT (9 x 9 mm SMT)
The M2060/61/62 and M2065/66/67 are VCSO (Voltage
Controlled SAW Oscillator) based
clock PLLs designed for FEC clock
ratio translation in 10Gb optical
systems such as OC-192 or 10GbE.
They support FEC (Forward Error
Correction) clock multiplication
FIN_SEL0
FEC_SEL0
FEC_SEL1
LOL
P_SEL0
P_SEL1
nFOUT0
FOUT0
GND
nFOUT1
FOUT1
VCC
28
29
30
31
18
17
16
15
14
13
12
11
10
ratios, both forward (mapping) and
M2060
Series
inverse (de-mapping). Multiplication ratios are
pin-selected from pre-programming look-up tables.
NBW
VCC
32
33
34
35
36
( T o p V i e w )
DNC
DNC
FEATURES
DNC
GND
◆ Integrated SAW delay line; Output of 15 to 700 MHz *
◆ Low phase jitter < 0.5 ps rms typical
(12kHz to 20MHz or 50kHz to 80MHz)
◆ Pin-selectable PLL divider ratios support FEC ratios
• M2060/65: OTU1 (255/238) and OTU2 (255/237) Mapping
• M2061/66: OTU1 (238/255) or OTU2 (237/255) De-mapping
• M2062/67: OTU1 (238/255) and OTU2 (237/255) De-mapping
Figure 1: Pin Assignment
◆ LVPECL clock output (CML and LVDS options available)
Example I/O Clock Frequency Combinations
Using M2061-11-622.0800 FEC De-Map Ratios
◆ Reference clock inputs support differential LVDS,
LVPECL, as well as single-ended LVCMOS, LVTTL
FEC De-Map
Base Input Rate 1
(MHz)
Output Clock
(either output)
MHz
PLL Ratio
◆ Loss of Lock (LOL) output pin
Mfec / Rfec
◆ Narrow Bandwidth control input (NBW pin) to adjust
loop bandwidth
1/1
622.0800
666.5143
669.3266
622.08
or
155.52
◆ Hitless Switching (HS) options with or without Phase
Build-out (PBO) available to enable SONET (GR-253)
/SDH (G.813) MTIE and TDEV compliance during
reference clock reselection
237/255
238/255
Table 1: Example I/O Clock Frequency Combinations
Note 1: Input reference clock can be the base frequency shown
divided by “Mfin” (as shown in Tables 3 and 4 on pg. 3).
◆ Single 3.3V power supply
* Specify VCSO center frequency at time of order.
◆ Small 9 x 9 mm SMT (surface mount) package
SIMPLIFIED BLOCK DIAGRAM
Loop
Filter
M2060 Series
NBW
LOL
MUX
Phase
Detector
DIF_REF0
0
Rfec
Div
nDIF_REF0
VCSO
DIF_REF1
nDIF_REF1
1
Mfin Div
(1, 4, 8, 32) or
( 1, 4, 8, 16)
Mfec Div
REF_SEL
Mfec and Rfec
Divider
2
FEC_SEL1:0
FOUT0
LUT
P Divider
nFOUT0
TriState
FOUT0: 1, 4, 8, 32 or TriState
FOUT1: 1, 4, 8 or TriState
2
Mfin Divider
LUT
FOUT1
FIN_SEL1:0
P_SEL2:0
nFOUT1
3
P Divider
LUT
Figure 2: Simplified Block Diagram
M2060/61/62 M2065/66/67 Datasheet Rev 0.4
Revised 30Jul2004
M2060/61/62 VCSO FEC PLL for SONET/OTN
Integrated Circuit Systems, Inc. ● Networking & Communications ● www.icst.com ● tel (508) 852-5400
M2060/61/62, M2065/66/67
Integrated
Circuit
Systems, Inc.
VCSO FEC PLL FOR SONET/OTN
P r e l i m i n a r y I n f o r m a t i o n
PIN DESCRIPTIONS
Number
1, 2, 3, 10, 14, 26
Name
GND
I/O
Ground
Configuration
Description
Power supply ground connections.
4
9
OP_IN
nOP_IN
Input
External loop filter connections.
See Figure 5, External Loop Filter, on pg. 8.
5
8
nOP_OUT
OP_OUT
Output
6
7
nVC
VC
Input
11, 19, 33
VCC
Power
Power supply connection, connect to +3.3V.
12
13
FOUT1
nFOUT1
Output No internal terminator
Output No internal terminator
Clock output pair 1. Differential LVPECL.
15
16
FOUT0
nFOUT0
Clock output pair 0. Differential LVPECL.
17
18
25
P_SEL1
P_SEL0
P_SEL2
Post-PLL , P divider selection. LVCMOS/LVTTL. See Table 8,
P Divider Look-Up Table (LUT), on pg. 4.
1
Input
Input
Input
Input
Internal pull-down resistor
2
20
21
nDIF_REF1
DIF_REF1
Biased to Vcc/2
Reference clock input pair 1. Differential LVPECL or LVDS.
1 Resistor bias on inverting terminal supports TTL or LVCMOS.
Internal pull-down resistor
Internal pull-down resistor
Reference clock input selection. LVCMOS/LVTTL:
Logic 1 selects DIF_REF1, nDIF_REF1.
Logic 0 selects DIF_REF0, nDIF_REF0.
1
22
REF_SEL
2
23
24
nDIF_REF0
DIF_REF0
Biased to Vcc/2
Reference clock input pair 0. Differential LVPECL or LVDS.
Resistor bias on inverting terminal supports TTL or LVCMOS.
1
Internal pull-down resistor
Internal pull-down resistor
27
28
FIN_SEL1
FIN_SEL0
Input clock frequency selection. LVCMOS/LVTTL. See
Tables 3 and 4 Mfin Divider Look-Up Tables (LUT) on pg. 3.
1
Input
Input
29
30
FEC_SEL0
FEC_SEL1
Mfec and Rfec divider value selection. LVCMOS/ LVTTL.
See Tables 5, 6, and 7 on pg. 3.
1
Internal pull-down resistor
Loss of Lock indicator output. Asserted when internal PLL is
3
not tracking the input reference for frequency and phase.
Logic 1 indicates loss of lock.
31
LOL
Output
Input
Logic 0 indicates locked condition.
Narrow Bandwidth enable. LVCMOS/LVTTL:
Logic 1 - Narrow loop bandwidth, RIN = 2100kΩ.
Logic 0 - Wide bandwidth, RIN = 100kΩ.
Internal nodes. Connection to these pins can cause erratic
device operation.
1
32
NBW
DNC
Internal pull-UP resistor
34, 35, 36
Do Not Connect.
Table 2: Pin Descriptions
Note 1: For typical values of internal pull-down and pull-UP resistors, see DC Characteristics on pg. 10.
Note 2: Biased toVcc/2, with 50kΩ to Vcc and 50kΩ to ground. See Differential Inputs Biased to VCC/2 on pg. 10.
Note 3: See LVCMOS Output in DC Characteristics on pg. 10.
M2060/61/62 M2065/66/67 Datasheet Rev 0.4
2 of 12
Revised 30Jul2004
Integrated Circuit Systems, Inc. ● Networking & Communications ● www.icst.com ● tel (508) 852-5400
M2060/61/62, M2065/66/67
Integrated
Circuit
Systems, Inc.
VCSO FEC PLL FOR SONET/OTN
P r e l i m i n a r y I n f o r m a t i o n
DETAILED BLOCK DIAGRAM
RLOOP CLOOP
RPOST
External
Loop Filter
Components
CPOST
CPOST
RLOOP CLOOP
nOP_IN OP_OUT
RPOST
OP_IN
nOP_OUT
nVC
VC
M2060 Series
Hitless Switching (HS) Opt.
HS with Phase Build-out Opt.
NBW
LOL
MUX
Phase
Detector
SAW Delay Line
RIN
RIN
DIF_REF0
nDIF_REF0
Phase
Locked
Loop
(PLL)
0
Rfec
Div
DIF_REF1
nDIF_REF1
Loop Filter
Amplifier
Phase
Shifter
1
VCSO
Mfin Divider
1,4,8,32 Options
Mfec Div
REF_SEL
Mfec/Rfec Divider
FEC_SEL1:0
FOUT0
LUT
nFOUT0
P Divider
1,4,8,32
Options
TriState
Mfin Divider
LUT
FOUT1
nFOUT1
FIN_SEL1:0
P_SEL2:0
P Divider
LUT
Figure 3: Detailed Block Diagram
Mfec and Rfec Divider Look-Up Tables (LUTs)
DIVIDER SELECTION TABLES
The FEC_SEL pins select the Mfec/Rfec divider ratio. The
look-up tables vary by device variant. The Mfec and
Rfec values also establish phase detector frequency.
A lower phase detector frequency improves jitter
tolerance and lowers loop bandwidth.
Mfin Divider Look-Up Tables (LUT)
The FIN_SEL1:0 pins select the feedback divider value
(“Mfin”), which sets the overall PLL ratio range. Since
the VCSO frequency is fixed, this allows input reference
selection. The look-up tables vary by device variant.
M2060/65: FEC Map LUT, OTU1 (255/238) and OTU2 (255/237)
Fvcso =
FEC_SEL1:0
0
Base Input
Mfec Rfec
Base Output
Rate (MHz)
Description
M2060/61/62: Mfin Value LUT (Includes Divide by 32)
Rate (MHz)
1
Mfin
Sample Input Reference Freq. (MHz) Options
FIN_SEL1:0
1
2
For M2060 or M2065 with Fvcso = 666.5143 (OTU1 FEC rate):
255/238 OC-48 to OTU1 encode
For M2060 , M2061 & M2062
Value
0
0
0
1
15 14
15 15
622.08 666.5143
666.5143 666.5143
0 0
0 1
1 0
1 1
32
8
4
1
19.44
77.76
155.52
622.08
OTU1 repeater or jitter attenuator
For M2060 or M2065 with Fvcso = 669.3266 (OTU2 FEC rate):
255/237 OC-192 to OTU2 encode
1
1
0
1
85 79
85 85
622.08 669.3266
669.3266 669.3266
Table 3: M2060/61/62: Mfin Value LUT (Includes Divide by 32)
OTU2 repeater or jitter attenuator
Note 1: For M2060 with Fvcso = 666.5143 or 669.3266
Note 2: For M2061 and M2062 with Fvcso = 622.0800.
Table 5: M2060/65: FEC Map LUT, OTU1 (255/238) and OTU2 (255/237)
M2061/66: FEC De-map LUT, OTU1 (238/255) or OTU2 (237/255)
Use this option for either OTU1 or OTU2 de-mapping
applications, but not both.
M2065/66/67: Mfin Value LUT (Includes Divide by 16)
Mfin
Sample Input Reference Freq. (MHz) Options
FIN_SEL1:0
1
2
For M2065 , M2066 & M2067
Value
0 0
0 1
1 0
1 1
16
8
4
1
38.88
77.76
155.52
622.08
Fvcso =
FEC_SEL1:0
0
Base Input
Mfec Rfec
Base Output
Rate (MHz)
Description
Rate (MHz)
1
For M2061 or M2066 with Fvcso = 622.08 (OTU1 or OTU2 FEC rate):
237/255 OTU2 to OC-192 decode
0
0
1
1
0
1
0
1
79 85
79 79
14 15
14 14
669.3266 622.08
Table 4: M2065/66/67: Mfin Value LUT (Includes Divide by 16)
Note 1: For M2065 with Fvcso = 666.5143 or 669.3266
Note 2: For M2066 and M2067 with Fvcso = 622.0800.
OC-192 repeater or jitter attenuator
238/255 OTU1 to OC-48 decode
OC-48 repeater or jitter attenuator
622.08
666.5143 622.08
622.08
622.08
622.08
Table 6: M2061/66: FEC De-map LUT, OTU1 (238/255) or OTU2 (237/255)
M2060/61/62 M2065/66/67 Datasheet Rev 0.4
3 of 12
Revised 30Jul2004
Integrated Circuit Systems, Inc. ● Networking & Communications ● www.icst.com ● tel (508) 852-5400
M2060/61/62, M2065/66/67
Integrated
Circuit
Systems, Inc.
VCSO FEC PLL FOR SONET/OTN
P r e l i m i n a r y I n f o r m a t i o n
M2062/67: FEC De-map LUT, Both OTU1 and OTU2
Use this option for both OTU1 or OTU2 de-mapping
applications. The Mfec divider value is kept nearly
constant to maintain similar loop bandwidth using one
set of external filter component values.
FUNCTIONAL DESCRIPTION
The M206x Series is a PLL (Phase Locked Loop) based
clock generator that generates output clocks synchro-
nized to one of two selectable input reference clocks.
An internal high "Q" SAW delay line provides low jitter
signal performance and establishes the output
frequency of the VCSO (Voltage Controlled SAW
Oscillator). In a given M206x Series device, the VCSO
center frequency is fixed. A common center frequency
is 622.08MHz, for SONET or SDH optical network
applications. The VCSO center frequency is specified at
time of order (see “Ordering Information” on pg. 12).
The VCSO has a guaranteed tuning range of ±120 ppm
(commercial temperature grade).
Fvcso =
FEC_SEL1:0
0
Base Input
Mfec Rfec
Base Output
Rate (MHz)
Description
Rate (MHz)
1
For M2062 or M2067 with Fvcso = 622.08 (OTU1 or OTU2 FEC rate):
237/255 OTU2 to OC-192 decode
0
0
1
1
0
1
0
1
79 85
79 79
84 90
84 84
669.3266 622.08
OC-192 repeater or jitter attenuator
238/255 OTU1 to OC-48 decode
OC-48 repeater or jitter attenuator
622.08
666.5143 622.08
622.08 622.08
622.08
Table 7: M2062/67: FEC De-map LUT, Both OTU1 and OTU2
P Divider Look-Up Table (LUT)
Pin selectable dividers are used within the PLL and
for the output clock. This enables tailoring of device
functionality and performance. The FEC feedback and
reference dividers (the “Mfec Divider” and “Rfec
Divider”) provide the multiplication ratios necessary to
accomodate clock translation for both forward and
inverse Forward Error Correction. The Mfec and Rfec
dividers also control the phase detector frequency. The
feedback divider (labeled “Mfin Divider”) provides the
broader division options needed to accomodate various
reference clock frequencies.
The P_SEL2:0 pins select the P divider values, which set
the output clock frequencies. P divider values of 1, 4, 8,
or 32 are available, plus a TriState mode. A P divider of
value of 1 will provide a 669.3266MHz output when using
a 669.3266MHz VCSO, for example. The outputs can be
placed into the valid state combinations as listed in
Table 8. (They cannot be set independently to any of the
available output frequencies.)
M2060-622.0800 or M2065-622.0800
P Value
forFOUT0 forFOUT1
Output Frequency (MHz)
P_SEL2:0
FOUT0
FOUT1
For example, the M2062-11-622.0800 (see “Ordering
Information” on pg. 12) has a 622.08MHz VCSO
frequency:
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
32
32
1
4
8
1
4
1
1
8
4
4
19.44 622.08
19.44 155.52
622.08 622.08
155.52 622.08
77.76 77.76
155.52 155.52
77.76 155.52
N/A
• The FEC de-mapper PLL ratios (in Tables 6 and 7)
enable the M2062-11-622.0800 to accept “base” input
reference frequencies of: 666.5143 (OTU1), 669.3266
(OTU2), and 622.08MHz (OC-192).
4
8
• The Mfin feedback divider enables the actual input
reference clock to be the base input frequency
divided by 1, 4, 8, or 32 (or 16). Therefore, for the base
input frequency of 622.08MHz, the actual input
reference clock frequencies can be: 622.08, 155.52,
77.76, and 19.44 or 38.88MHz. (See Tables 3 and 4 on
pg. 3.)
TriState TriState
N/A
Table 8: P Divider Look-Up Table (LUT)
General Guidelines for Phase Detector Frequency
The phase detector frequency (Fpd) is equal to the
input reference frequency (Fref) divided by the Rfec
divider value, or:
Fpd = Fref / Rfec
Key to Device Variants and Look-up Table Options
Device
General guidelines:
Look-up Table Option
Variant
Mfin Lookup Table is:
Mfec Look-up Table is:
• A lower phase detector frequency should be used for
loop timing applications to assure PLL tracking,
especially during GR-253 jitter tolerance testing. The
recommended maximum phase detector frequency
for loop timing mode is 19.44MHz.
M2060
M2061
M2062
M2065
M2066
M2067
Table 5 (FEC mapper LUT)
Table 6 (FEC de-mapper LUT)
Table 7 (FEC de-mapper LUT)
Table 5 (FEC mapper LUT)
Table 6 (FEC de-mapper LUT)
Table 7 (FEC de-mapper LUT)
Table 3
(includes divider value 32)
Table 4
(includes divider value 16)
• When LOL is to be used for system health monitoring,
the phase detector frequency should be 5MHz or
greater. Low phase detector frequencies make LOL
overly sensitive, and higher phase detector
frequencies make LOL less sensitive. The LOL pin
should not be used during loop timing mode.
Table 9: Key to Device Variants and Look-up Table Options
The P divider scales the VCSO output enabling lower
output frequency selections (Table 8).
M2060/61/62 M2065/66/67 Datasheet Rev 0.4
4 of 12
Revised 30Jul2004
Integrated Circuit Systems, Inc. ● Networking & Communications ● www.icst.com ● tel (508) 852-5400
M2060/61/62, M2065/66/67
Integrated
Circuit
Systems, Inc.
VCSO FEC PLL FOR SONET/OTN
P r e l i m i n a r y I n f o r m a t i o n
The M206x Series includes a Loss of Lock (LOL)
indicator, which provides status information to system
management software. A Narrow Bandwidth (NBW)
control pin is provided as an additional mechanism for
adjusting PLL loop bandwidth without affecting the
phase detector frequency.
Differential Inputs
Differential LVPECL inputs are connected to both
reference input pins in the usual manner. The external
load termination resistors shown in Figure 4 (the 127Ω
and 82Ω resistors) is ideally suited for both AC and DC
coupled LVPECL reference clock lines. These provide
the 50Ω load termination and the VTT bias voltage.
Options are available for Hitless Switching (HS) with or
without Phase Build-out (PBO). They provide SONET/
SDH MTIE and TDEV compliance during a reference
clock reselection.
Single-ended Inputs
Single-ended inputs (LVCMOS or LVTTL) are
connected to the non-inverting reference input pin
(DIF_REF0 or DIF_REF1). The inverting reference input pin
(nDIF_REF0 or nDIF_REF1) must be left unconnected.
Input Reference Clocks
Two clock reference inputs and a selection mux is
provided. Either reference clock input can accept a
differential clock signal (such as LVPECL or LVDS) or
a single-ended clock input (LVCMOS or LVTTL on the
non-inverting input).
In single-ended operation, when the unused inverting
input pin (nDIF_REF0 or nDEF_REF1) is left floating (not
connected), the input will self-bias at VCC/2.
A single-ended reference clock on the unselected
reference input can cause an increase in output
clock jitter. For this reason, differential reference
inputs are preferred; interference from a differential
input on the non-selected input is minimal.
PLL Operation
The M2060/61/62 and M2065/66/67 are complete clock
PLLs. They use a phase detector and configurable
dividers to synchronize the output of the VCSO with the
selected reference clock.
Configuration of a single-ended input has been
facilitated by biasing nDIF_REF0 and nDEF_REF1 to Vcc/2,
with 50kΩ to Vcc and 50kΩ to ground. The input clock
structure, and how it is used with either
LVCMOS/LVTTL inputs or a DC- coupled LVPECL
clock, is shown in Figure 4.
The PLL will work correctly, meaning it will phase-lock
the VCSO output to the input reference clock, when the
internal phase detector inputs are able to run at the
same frequency. This means the PLL dividers must be
set appropriately and a suitable reference frequency
must be chosen for the intended output frequency.
When the PLL is not set up appropriately, the VCSO is
forced to its upper or lower operating limit which is typi-
cally about 200 ppm above or below the VCSO center
frequency. See “APR, VCSO Absolute Pull-Range” row,
in the AC Characteristics table on pg. 11.
.
DIF_REF0
LVCMOS/
LVTTL
VCC
MUX
Ω
50k
Ω
50k
0
nDIF_REF0
X
VCC
In normal phase-locked condition, the instantaneous
phase error is measured by the phase detector and is
converted to charge pump current pulses. These
current pulses are then integrated by the external loop
filter to create a VCSO control voltage. The loop filter
acts as a low pass filter to remove unwanted reference
clock jitter above a determined frequency or PLL
bandwidth. For reference phase jitter frequencies within
the loop bandwidth, phase jitter amplitude is passed on
to the output clock according to the PLL loop frequency
response curve.
Ω
50k
1
127Ω
DIF_REF1
VCC
VCC
Ω
Ω
50k
82
LVPECL
Ω
Ω
Ω
127
50k
nDIF_REF1
REF_SEL
82
50k
Ω
Figure 4: Input Reference Clocks
The relationship between the nominal VCSO center
frequency (Fvcso), the Mfin divider, the Mfec divider,
the Rfec divider, and the input reference frequency (Fin)
is:
Mfec
Rfec
-------------
Fvcso = Fin × Mfin ×
M2060/61/62 M2065/66/67 Datasheet Rev 0.4
5 of 12
Revised 30Jul2004
Integrated Circuit Systems, Inc. ● Networking & Communications ● www.icst.com ● tel (508) 852-5400
M2060/61/62, M2065/66/67
Integrated
Circuit
Systems, Inc.
VCSO FEC PLL FOR SONET/OTN
P r e l i m i n a r y I n f o r m a t i o n
The Mfec, Rfec, and Mfin dividers can be set by pin
configuration using the input pins FEC_SEL1, FEC_SEL0,
FIN_SEL1, and FIN_SEL0.
Loss of Lock Indicator (LOL) Output Pin
Under normal device operation, when the PLL is locked,
the LOL Phase Detector drives LOL to logic 0. Under
circumstances when the VCSO cannot fully phase lock
to the input (as measured by a greater than 4 ns
discrepancy between the feedback and reference clock
rising edges at the LOL Phase Detector) the LOL output
goes to logic 1. The LOL pin will return back to logic 0
when the phase detector error is less than 2 ns. The
loss of lock indicator is a low current LVCMOS output.
Post-PLL Divider
The M2060/61/62 and M2065/66/67 also feature a
post-PLL (P) divider.
Through use of the P divider, the device’s output
frequency (Fout) can be that of the VCSO (such as
622.08MHz) or the VCSO frequency divided by 4, 8 or 32
(common optical reference clocks in SONET and SDH
systems).
Guidelines for Using LOL
In a given application, the magnitude of peak-to-peak
jitter at the phase detector will usually increase as the
Rfec divider is increased. If the LOL pin will be used to
detect an unusual clock condition, or a clock fault, the
FEC_SEL1:0 pins should be set to provide a phase
detector frequency of 5MHz or greater (the phase
detector frequency is equal to Fin divided by the Rfec
divider). Otherwise, false LOL indications may result. A
phase detector frequency of 10MHz or greater is
desirable when reference jitter is over 500ps, or when
the device is used within a noisy system environment.
LOL should not be used when the device is used in a
loop timing application.
The P_SEL2:0 pins select the value for the P divider. (See
Table 8 on pg. 4.)
Accounting for the P divider, the complete relationship
between the input clock reference frequency (Fin) and
output clock frequency (Fout) is defined as:
Mfin × Mfec
Fvcso
---------------------------------
Fout =
= Fin ×
-------------------
Rfec × P
P
Due to the narrow tuning range of the VCSO (+120ppm
guaranteed), appropriate selection of all of the following
are required for the PLL be able to lock: VCSO center
frequency, input frequency, and divider selections.
TriState
The TriState feature puts the LVPECL output driver into
a high impedance state, effectively disconnecting the
driver from the FOUT and nFOUT pins of the device. In
TriState, the M206x Series is not driving the output
clock net with a defined logic level. The impedance of
the clock net is then set to 50Ω by the external circuit
resistors. The 50Ω impedance level of the LVPECL
TriState allows manufacturing In-circuit Test to drive the
clock net with an external LVPECL source to validate
the integrity of clock net and the clock load.
Any unused output (single-ended or differential) should
be left unconnected (floating) in system application.
This minimizes output switching current and therefore
minimizes noise modulation of the VCSO.
Narrow Bandwidth (NBW) Control Pin
A Narrow Loop Bandwidth control pin (NBW pin) is
included to enable adjustment of the PLL loop
bandwidth. In wide bandwidth mode (NBW=0), the
internal resistor Rin is 100kΩ. With the NBW pin
asserted (NBW=1), the internal resistor Rin is changed to
2100kΩ. This lowers the loop bandwidth by a factor of
about 21 (2100 / 100) and lowers the damping factor by
about 4.6 (the square root of 21), assuming the same
external loop filter component values.
M2060/61/62 M2065/66/67 Datasheet Rev 0.4
6 of 12
Revised 30Jul2004
Integrated Circuit Systems, Inc. ● Networking & Communications ● www.icst.com ● tel (508) 852-5400
M2060/61/62, M2065/66/67
Integrated
Circuit
Systems, Inc.
VCSO FEC PLL FOR SONET/OTN
P r e l i m i n a r y I n f o r m a t i o n
HS/PBO Operation
Optional Hitless Switching and Phase Build-out
Once triggered, the following HS/PBO sequence
occurs:
The M206x Series is available with a Hitless Switching
feature that is enabled during device manufacturing.
In addition, a Phase Build-out feature is also offered.
These features are offered as device options and are
specified by device order code. Refer to “Ordering
Information” on pg. 12.
1.The HS function disables the PLL Phase Detector
and puts the device into NBW (narrow bandwidth)
mode. The internal resistor Rin is changed to
2100kΩ . See Narrow Bandwidth (NBW) Control Pin
on pg. 6.
The Hitless Switching feature (with or without Phase
Build-out) is designed for applications where switching
occurs between two stable system reference clocks. It
should not be used in loop timing applications, or when
reference clock jitter is greater than 1 ns pk-pk. The
Hitless Switching sequence is triggered by the LOL
circuit, which is activated by a 4 ns phase transient. This
magnitude of phase transient can generated by the
CDR (Clock & Data Recovery unit) in loop timing mode,
especially during a system jitter tolerance test. It can
also be generated by some types of Stratum clock
DPLLs (digital PLL), especially those that do not include
a post de-jitter APLL (analog PLL).
2.If included, the PBO function adds to (builds out) the
phase in the clock feedback path (in VCSO clock
cycle increments) to align the feedback clock with
the (new) reference clock input phase.
3.The PLL Phase Detector is enabled, allowing the
PLL to re-lock.
4.Once the PLL Phase Detector feedback and input
clocks are locked to within 2 nsec for 8 consecutive
cycles, a timer (WBW timer) for resuming wide
bandwidth (in 175 nsec) is started.
5.When the WBW timer times out, the device reverts
to wide loop bandwidth mode (i.e., Rin is returned to
100kΩ) and the HS/PBO function is re-armed.
The LOL pin will indicate lock status on a cycle-to-cycle
basis and may be intermittent until PLL phase lock has
fully stabilized.
When the M206x Series is operating in wide bandwidth
mode (NBW=0), the optional Hitless Switching function
puts the device into narrow bandwidth mode during the
Hitless Switching sequence. This allows the PLL to lock
the new input clock phase gradually. With proper
configuration of the external loop filter, the output clock
phase change complies with MTIE and TDEV
specifications for GR-253 (SONET) and ITU G.813
(SDH) during input reference clock changes.
The optional proprietary Phase Build-out (PBO)
function enables the PLL to absorb most of the phase
change of the input clock during reference switching.
The PBO function selects a new VCSO clock edge for
the PLL Phase Detector feedback clock, selecting the
edge closest in phase to the new input clock phase.
This reduces re-lock time, the generation of wander,
and extra output clock cycles.
The Hitless Switching and Phase Build-out functions
are triggered by the LOL circuit. For proper operation,
a low phase detector frequency must be avoided. See
“Guidelines for Using LOL” on pg. 6 for information
regarding the phase detector frequency.
HS/PBO Sequence Trigger Mechanism
The HS function (or the combined HS/PBO function)
is armed after the device locks to the input clock refer-
ence. Once armed, HS is triggered by the occurance of
a Loss of Lock condition. This would typically occur as a
consequence of a clock reference failure, a clock failure
upstream to the M206x Series, or a M206x Series clock
reference mux reselection.
M2060/61/62 M2065/66/67 Datasheet Rev 0.4
7 of 12
Revised 30Jul2004
Integrated Circuit Systems, Inc. ● Networking & Communications ● www.icst.com ● tel (508) 852-5400
M2060/61/62, M2065/66/67
Integrated
Circuit
Systems, Inc.
VCSO FEC PLL FOR SONET/OTN
P r e l i m i n a r y I n f o r m a t i o n
External Loop Filter
To provide stable PLL operation, the M2060/61/62 or
M2065/66/67 requires use of an external loop filter. This
is provided via the provided filter pins (see Figure 5).
The loop filter is implemented as a differential circuit
to minimize system noise interference.
RLOOP CLOOP
RPOST
CPOST
CPOST
RLOOP CLOOP
nOP_IN OP_OUT
RPOST
OP_IN
nOP_OUT
nVC
VC
4
9
8
5
6
7
Figure 5: External Loop Filter
PLL bandwidth is affected by loop filter component
values, “Mfec” and “Mfin” values, and the “PLL Loop
Constants” listed in AC Characteristics on pg. 11.
The FEC_SEL setting can be used to actively change PLL
loop bandwidth in a given application. See “Mfec and
Rfec Divider Look-Up Tables (LUTs)” on pg. 3.
See Table 10, Example Values for Loop Filter External
Components, on pg. 8.
PLL Simulator Tool Available
A free PC software utility is available on the ICS website
(www.icst.com). The M2000 Timing Modules PLL
Simulator is a downloadable application that simulates
PLL jitter and wander transfer characteristics. This
enables the user to set appropriate external loop
component values in a given application.
1
Example Values for Loop Filter External Components
for Particular M206x Series Devices
VCSO Parameters: K
= 800kHz/V, R = 100k
Ω
(pin NBW = 0), VCSO Bandwidth = 700kHz.
VCO
IN
Device
Device Configuration
Example External Component Values
Nominal Performance With These Values
FIN_SEL MRSEL
1:0
FRef
FVCSO
R loop
C loop
R post
C post
PLL Loop Damping Passband
1:0
Bandwidth Factor Peaking(dB)
(MHz)
(MHz)
M2060, M2060 622.08 622.08
1 1
0 1
6.5
5.9
6.5
6.5
0.05
0.06
0.05
0.05
5.6kΩ
243.0kΩ
8.2kΩ
10µF
0.1µF
10µF
10µF
68kΩ
34kΩ
100kΩ
100kΩ
470pF
470pF
470pF
470pF
530Hz
1kHz
M2060, M2065 155.52 669.3266 1 0
1 0 0
0 1
M2061, M2066 77.76 622.08
M2061
0 1
0 0
360Hz
19.44 622.08
1 1
8.2kΩ
360Hz
Table 10: Example Values for Loop Filter External Components
Note 1: KVCO , VCSO Bandwidth, M Divider Value, and External Loop Filter Component Values determine Loop Bandwidth, Damping Factor, and
Passband Peaking. For PLL Simulator software, go to www.icst.com.
Refer to the M206x Series product web page at
www.icst.com/products/summary/m2060-2067.htm
for additional product information.
M2060/61/62 M2065/66/67 Datasheet Rev 0.4
8 of 12
Revised 30Jul2004
Integrated Circuit Systems, Inc. ● Networking & Communications ● www.icst.com ● tel (508) 852-5400
M2060/61/62, M2065/66/67
Integrated
Circuit
Systems, Inc.
VCSO FEC PLL FOR SONET/OTN
P r e l i m i n a r y I n f o r m a t i o n
1
ABSOLUTE MAXIMUM RATINGS
Symbol Parameter
Rating
Unit
VI
Inputs
-0.5 to VCC +0.5
V
VO
VCC
TS
Outputs
-0.5 to VCC +0.5
4.6
V
V
Power Supply Voltage
Storage Temperature
-45 to +100
oC
Table 11: Absolute Maximum Ratings
Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional operation of product at these conditions
or any conditions beyond those listed in Recommended Conditions of Operation, DC Characteristics, or
AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect product reliability
.
RECOMMENDED CONDITIONS OF OPERATION
Symbol Parameter
Min
Typ
Max Unit
VCC
Positive Supply Voltage
3.135
3.3
3.465
V
TA
Ambient Operating Temperature
oC
oC
0
Commercial
Industrial
+70
+85
-40
Table 12: Recommended Conditions of Operation
M2060/61/62 M2065/66/67 Datasheet Rev 0.4
9 of 12
Revised 30Jul2004
Integrated Circuit Systems, Inc. ● Networking & Communications ● www.icst.com ● tel (508) 852-5400
M2060/61/62, M2065/66/67
Integrated
Circuit
Systems, Inc.
VCSO FEC PLL FOR SONET/OTN
P r e l i m i n a r y I n f o r m a t i o n
ELECTRICAL SPECIFICATIONS
DC Characteristics
Unless stated otherwise, VCC
= 3.3V +5 = 622-675MHz,
%,TA = 0 oC to +70 oC (commercial), TA = -40 oC to +85 oC (industrial), FVCSO = FOUT
LVPECL outputs terminated with 50Ω to VCC - 2V
Symbol Parameter
Power Supply VCC Positive Supply Voltage
Min
3.135
Typ
3.3
Max Unit Conditions
3.465
V
175
225
ICC
VP-P
VCMR
CIN
IIH
Power Supply Current
mA
V
0.15
0.5
All
Differential
Inputs
Peak to Peak Input Voltage
Common Mode Input
DIF_REF0, nDIF_REF0,
DIF_REF1, nDIF_REF1
V
- .85
V
cc
4
Input Capacitance
pF
VCC = VIN
3.456V
=
Differential
Inputs with
Pull-down
Input High Current (Pull-down)
Input Low Current (Pull-down)
Internal Pull-down Resistance
Input High Current (Biased) 1
Input Low Current (Biased) 1
150 µA
µA
DIF_REF0, DIF_REF1
IIL
-5
50
R
kΩ
pulldown
VIN
0 to 3.456V
=
150
Differential
Inputs
Biased to
IIH
IIL
µA
nDIF_REF0, nDIF_REF1
-150
µA
R
Biased to Vcc/2 1
kΩ
1
(Note 1)
VCC/2
bias
2
All LVCMOS VIH
/ LVTTL
Input High Voltage
Input Low Voltage
V
+ 0.3 V
cc
REF_SEL, FIN_SEL1, FIN_SEL0,
FEC_SEL1, FEC_SEL0, P_SEL2,
P_SEL1, P_SEL0, NBW
0.8
4
VIL
-0.3
V
Inputs
CIN
Input Capacitance
Input High Current (Pull-down)
pF
VCC = VIN
3.456V
=
LVCMOS /
LVTTL
IIH
150 µA
REF_SEL, FIN_SEL1, FIN_SEL0,
FEC_SEL1, FEC_SEL0, P_SEL2,
P_SEL1, P_SEL0
IIL
R
Input Low Current (Pull-down)
Internal Pull-down Resistance
Input High Current (Pull-UP)
-5
µA
kΩ
Inputs with
Pull-down
LVCMOS /
LVTTL
50
50
pulldown
VCC = 3.456V
IN = 0 V
IIH
5
µA
V
NBW
IIL
R
Input Low Current (Pull-UP)
Internal Pull-UP Resistance
Output High Voltage
-150
µA
kΩ
Inputs with
Pull-UP
pullup
Differential
Outputs
VOH
VOL
VP-P
VOH
VOL
V
- 1.4
- 2.0
V
V
- 1.0 V
cc
cc
FOUT0, nFOUT0,
FOUT1, nFOUT1
Output Low Voltage
V
- 1.7 V
cc
cc
2
0.4
0.85
VCC
0.4
Peak to Peak Output Voltage
Output High Voltage
V
V
V
2.4
IOH= 1mA
IOL= 1mA
LVCMOS
Output
LOL
GND
Output Low Voltage
Table 13: DC Characteristics
Note 1: Biased to Vcc/2, with 50kΩ to Vcc and 50kΩ to ground. See Figure 4, Input Reference Clocks, on pg. 5
Note 2: Single-ended measurement. See Figure 6, Output Rise and Fall Time, on pg. 11.
M2060/61/62 M2065/66/67 Datasheet Rev 0.4
10 of 12
Revised 30Jul2004
Integrated Circuit Systems, Inc. ● Networking & Communications ● www.icst.com ● tel (508) 852-5400
M2060/61/62, M2065/66/67
Integrated
Circuit
Systems, Inc.
VCSO FEC PLL FOR SONET/OTN
P r e l i m i n a r y I n f o r m a t i o n
ELECTRICAL SPECIFICATIONS (CONTINUED)
AC Characteristics
Unless stated otherwise, VCC
=
3.3V +
5
%,TA = 0 oC to +70 oC (commercial), TA = -40 oC to +85 oC (industrial), FVCSO = FOUT
Ω to VCC - 2V
= 622-675MHz,
LVPECL outputs terminated with 50
Symbol Parameter
Min
Typ
Max Unit Conditions
DIF_REF0, nDIF_REF0,
DIF_REF1, nDIF_REF1
10
700
700
FIN
Input Frequency
MHz
MHz
FOUT
APR
Output Frequency
FOUT0, nFOUT0, FOUT1, nFOUT
1
15
Commercial
Industrial
VCSO Absolute
Pull-Range
±120
±50
±200
±150
800
ppm
ppm
KVCO
RIN
VCO Gain
kHz/V
Wide Bandwidth
100
2100
700
Internal Loop Resistor
kΩ
PLL Loop
Constants
1
Narrow Bandwidth
kΩ
BWVCSO VCSO Bandwidth
kHz
Φn
Single Side Band
Phase Noise
1kHz Offset
10kHz Offset
100kHz Offset
-73
dBc/Hz
dBc/Hz
dBc/Hz
Fin=19.44 or
38.88 MHz
-103
-126
Mfin=32 (or 16),
Mfec=Rfec
@622.08MHz
PhaseNoise
and Jitter
0.25
0.25
50
0.5
0.5
55
J(t)
Jitter (rms)
@622.08MHz
12kHz to 20MHz
50kHz to 80MHz
P = 4, 8, or 32
ps
ps
%
2
odc
Output Duty Cycle
FOUT0, nFOUT0,
45
P = 1
40
50
60
%
FOUT1, nFOUT
1
2
200
450
500
tR
tF
Output Rise Time
ps
20% to 80%
20% to 80%
FOUT0, nFOUT0, FOUT1, nFOUT
1
2
200
450
500
Output Fall Time
ps
Table 14: AC Characteristics
Note 1: Parameters needed for PLL Simulator software; see Table 10, Example Values for Loop Filter External Components, on pg. 8.
Note 2: See Parameter Measurement Information on pg. 11.
PARAMETER MEASUREMENT INFORMATION
Output Rise and Fall Time
Output Duty Cycle
nFOUT
FOUT
80%
80%
VP-P
tPW
(Output Pulse Width)
20%
t
F
20%
Clock Output
t
R
tPERIOD
t
PW
odc =
t
PERIOD
Figure 7: Output Duty Cycle
Figure 6: Output Rise and Fall Time
M2060/61/62 M2065/66/67 Datasheet Rev 0.4
11 of 12
Revised 30Jul2004
Integrated Circuit Systems, Inc. ● Networking & Communications ● www.icst.com ● tel (508) 852-5400
P r e l i m i n a r y I n f o r m a t i o n
M2060/61/62, M2065/66/67
VCSO FEC PLL FOR SONET/OTN
Integrated
Circuit
Systems, Inc.
DEVICE PACKAGE - 9 x 9mm CERAMIC LEADLESS CHIP CARRIER
Mechanical Dimensions:
Refer to the M206x Series product web page at
www.icst.com/products/summary/m2060-2067.htm
for recommended PCB footprint, solder mask,
furnace profile, and related information.
Figure 8: Device Package - 9 x 9mm Ceramic Leadless Chip Carrier
*
Standard VCSO Output Frequencies (MHz)
ORDERING INFORMATION
622.0800
625.0000
627.3296
644.5313
666.5143
669.1281
669.3120
669.3266
669.6429
670.8386
672.1600
690.5692
Part Numbering Scheme
Part Number:
M206x-yz-xxx.xxxx
Divider Look-up Table Option
See Table 9, page 4.
Output type
1 = LVPECL
(For CML or LVDS clock output, consult factory)
Hitless Switching / Phase Build-out Options
1 = none
Table 15: Standard VCSO Output Frequencies
2 = Hitless Switching
3 = Hitless Switching with Phase Build-out
Temperature
0
to +70 o
C
(commercial)
“I-”==- 40 to +85 o
C (industrial)
VCSO Frequency (MHz)
See Table 15, right. Consult ICS for other frequencies.
Figure 9: Part Numbering Scheme
Note *: Fout can equal Fvcso divided by: 1, 4, 8, or 32.
Consult ICS for the availability of other VCSO frequencies.
Example Part Numbers
VCSO Frequency (MHz)
Temperature
commercial
industrial
commercial
industrial
Order Part Number (Examples)
M2061-11-622.0800 or M2062-11-622.0800
622.0800
M2061-11
M2060-11-669.3266 or M2065-11-669.3266
M2060-11 669.3266 or M2065-11 669.3266
I622.0800 or M2062-11I622.0800
669.3266
I
I
Table 16: Example Part Numbers
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS)
assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would
result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial
applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary
environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any
circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or
critical medical instruments.
M2060/61/62 M2065/66/67 Datasheet Rev 0.4
12 of 12
Revised 30Jul2004
Integrated Circuit Systems, Inc. ● Networking & Communications ● www.icst.com ● tel (508) 852-5400
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