M906-02-155.5200T [IDT]
CLCC-36, Reel;
| 型号： | M906-02-155.5200T |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | CLCC-36, Reel |
| 文件： | 总8页 (文件大小：322K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
P r e l i m i n a r y I n f o r m a t i o n
Integrated
Circuit
Systems, Inc.
M906-02
VCSO BASED CLOCK GENERATOR
GENERAL DESCRIPTION
PIN ASSIGNMENT (9 x 9 mm SMT)
The M906-02 is a PLL (Phase Locked Loop) based
clock generator that uses an
internal VCSO (Voltage Controlled
SAW Oscillator) to produce a very
low jitter output clock. From the
M906-02-155.5200, an output clock
frequency of 155.52 or 77.76MHz is
provided from six LVPECL clock
XTAL_2
FOUT4
nFOUT4
FOUT5
nFOUT5
VCC
nFOUT2
FOUT2
nFOUT1
FOUT1
GND
nFOUT0
FOUT0
VCC
28
29
18
17
output pairs. (Other frequencies are available; consult
factory.) The accuracy of the output frequency is
assured by the internal PLL that phase-locks the
internal VCSO to the reference input frequency
(19.44MHz for the M906-02-155.5200). The input reference
can either be an external crystal, utilizing the internal
crystal oscillator, or a stable external clock source
such as a packaged crystal oscillator.
30
31
32
33
34
35
36
16
15
14
13
12
11
10
M906-02
( T o p V i e w )
DNC
DNC
DNC
GND
FEATURES
◆ Output clock frequency range 75MHz to 175MHz
(Consult factory for frequency availability)
Figure 1: Pin Assignment
◆ Selectable divider chooses one of two frequencies
◆ Six identical LVPECL output pairs (same frequency)
◆ Jitter 0.7ps rms (at 155.52MHz, over 12kHz-20MHz), typ.
◆ Ideal for OC-48/STM-16 clock reference
◆ Output-to-output skew < 100ps
Example Output Frequency Configurations
(M906-02-155.5200)
Ref Clock
Frequency
(MHz)
VCSO
Frequency
(MHz)
Output
Frequency
(MHz)
P Divider
Value
◆ External XTAL or LVCMOS reference input
◆ Selectable external feed-through clock input
◆ STOP clock control (Logic 1 stops output clocks)
◆ Integrated SAW (surface acoustic wave) delay line
◆ Single 3.3V power supply
1
2
155.52
19.44
155.52
77.76
Table 1: Example Output Frequency Configurations
◆ Small 9 x 9 mm SMT (surface mount) package
SIMPLIFIED BLOCK DIAGRAM
M906-02-155.52 (Other Frequencies Available)
VSCO
External
Crystal
LVPECL
Output
Clock
Pairs
(155.52 or
Frequency
Multiplying
PLL
XTAL
OSC
O
or
Divider
Reference
Clock Input
(19.44MHz)
1
77.76MHz)
External
Loop Filter
Divider
Select
External External
Output
Clock STOP
Control
Clock
Input
Clock
Select
Figure 2: Simplified Block Diagram
M906-02 Datasheet Rev 0.7
Revised 30Jul2004
M906-02 VCSO Based Clock Generator
Integrated Circuit Systems, Inc. ● Networking & Communications ● www.icst.com ● tel (508) 852-5400
M906-02
Integrated
Circuit
Systems, Inc.
VCSO BASED
C
LOCK
G
ENERATOR
P r e l i m i n a r y I n f o r m a t i o n
DETAILED BLOCK DIAGRAM
RLOOP CLOOP
RPOST
External
Loop Filter
Components
CPOST
CPOST
RLOOP CLOOP
nOP_IN OP_OUT
RPOST
M906-02
OP_IN
RIN
nOP_OUT
nVC
VC
FOUT5
nFOUT5
Phase
Detector
SAW Delay Line
XTAL_1 / REF_IN
XTAL_2
XTAL
OSC
FOUT4
nFOUT4
RIN
P Divider
P = 1 or 2
Loop Filter
Amplifier
Phase
Shifter
O
FOUT3
VCSO
nFOUT3
1
M Divider
M = 8
FOUT2
nFOUT2
Phase Locked Loop (PLL)
EXT_CLK
FOUT1
nFOUT1
EN_EXT_CLK
FOUT0
nFOUT0
STOP
FOUT_SEL
Figure 3: Detailed Block Diagram
PIN DESCRIPTIONS
Number
1, 2, 3, 10, 14, 26 GND
Name
I/O
Ground
Configuration
Description
Power supply ground connections.
4
9
OP_IN
nOP_IN
Input
5
8
nOP_OUT
OP_OUT
Output
External loop filter connections. See Figure 5.
6
7
nVC
VC
Input
11, 19, 33
VCC
Power
Power supply connection, connect to +3.3V.
12, 13
15, 16
17, 18
20, 21
29, 30
31, 32
FOUT0, nFOUT0
FOUT1, nFOUT1
FOUT2, nFOUT2
FOUT3, nFOUT3
FOUT4, nFOUT4
FOUT5, nFOUT5
Output
No internal terminator
Clock output pairs, differential LVPECL output
(155.52 or 77.76 MHz for the M906-02-155.5200)
Determines post-PLL divider value:
When FOUT_SEL = 1, P = 1
When FOUT_SEL = 0, P = 2
22
FOUT_SEL
Input
Internal pull-down
1
Logic 1 enables the EXT_CLK input.
Use Logic 0 for normal operation.
23
24
25
EN_EXT_CLK
EXT_CLK
STOP
Input
Input
Input
resistor
External clock feed-through: 0 to 200 MHz
Internal pull-down
1
Logic 1 stops clock outputs.
Use Logic 0 for normal operation.
resistor
External crystal connection. Also accepts
LVCMOS/LVTTL compatible clock source.
27
XTAL_1 / REF_IN
Input
Input
External crystal connection. Leave unconnected
when driving pin 27 with external clock reference.
28
XTAL_2
DNC
Internal nodes. Connection to these pins can
cause erratic device operation.
34, 35, 36
Do Not Connect.
Table 2: Pin Descriptions
Note 1: For typical value of internal pull-down resistor, see DC Characteristics, Pull-down on pg. 6 for typical value.
M906-02 Datasheet Rev 0.7
2 of 8
Revised 30Jul2004
Integrated Circuit Systems, Inc. ● Networking & Communications ● www.icst.com ● tel (508) 852-5400
M906-02
Integrated
Circuit
Systems, Inc.
VCSO BASED
C
LOCK
G
ENERATOR
P r e l i m i n a r y I n f o r m a t i o n
For the M906-02-155.5200 (see “Ordering Information” on pg. 8):
FUNCTIONAL DESCRIPTION
The M906-02 is a PLL (Phase Locked Loop) based
clock generator that generates output clocks
synchronized to an input reference clock.
• VCSO output frequency = 155.52MHz
• M = 8
• Input reference frequency = 19.44MHz
Therefore, for the M906-02-155.5200:
The M906-02 combines the flexibility of a VCSO
(Voltage Controlled SAW Oscillator) with the stability of
a crystal oscillator.
155.52MHz = 8 × 19.44MHz
The VCSO center output frequency of 155.52MHz
enables the product of M × input crystal frequency
to fall within the lock range of the VCSO.
Input Reference
The 19.44MHz input reference can either be an external,
discrete crystal device or a stable external clock source
such as a packaged crystal oscillator:
Post-PLL Divider
The M906-02 also features a post-PLL divider (labeled
“P Divider”) for selecting one of two output frequencies
(e.g., 155.52 or 77.76 MHz).
• If an external crystal is used with the on-chip crystal
oscillator circuit (XTAL OSC), the external crystal
should be a parallel-resonant, fundamental mode
crystal. Apply it to the XTAL_1 / REF_IN and XTAL_2 input
pins. External crystal load capacitors are also
required.
The FOUT_SEL pin determines the P Divider value:
• When FOUT_SEL = 1, P = 1.
• When FOUT_SEL = 0, P = 2.
• If an external LVCMOS/LVTTL clock source is used,
apply it to the XTAL_1 / REF_IN input pin.
External Clock Feed-through
In either case, the reference clock is supplied directly to
the phase detector of the PLL.
The EXT_CLK pin provides an input for an external
single-ended clock that directly drives the LVPECL
clock outputs. This pin is intended for system debugging
and performance evaluation..
The EX_CLK pin is available for a clock feed-through
mode for testing. See “External Clock Feed-through”
on pg. 3.
EN_EXT_CLK Logic 1 enables the EXT_CLK input.
Use Logic 0 for normal operation.
EXT_CLK
Apply an external LVCMOS/LVTTL clock source
for 0 to 200 MHz feed-through operation.
Leave inactive for normal operation.
The PLL
1
The PLL (Phase Locked Loop) includes the phase
detector, the VCSO, and a feedback divider (labeled
“M Divider”).
Note 1: In applications where EXT_CLK is active while the SAW PLL
signal path is enabled, it is necessary to gate the EXT_CLK to
minimize jitter in the LVPECL output pairs. See the PCB Design
Guidelines for ICS SAW PLLs application note at
The feedback divider is a digital circuit that divides the
VCSO output frequency by a numerical value “M” in
order to match the input reference frequency.
www.icst.com/products/appnotes/M000-AN-001.PCBdesign.pdf
STOP Clock
By controlling the frequency and phase of the VCSO,
the phase detector precisely locks the frequency and
phase of the feedback divider output to that of the input
reference. This creates an output frequency that is a
multiple of the reference frequency (which is output
from the VCSO).
The STOP pin puts the output clock into a static condition.
Logic 1 Output clocks are static
Logic 0 Output clocks enabled for normal operation
The relationship between the VCSO output frequency,
the M Divider, and the input reference frequency is
defined as follows:
Fvcso = M × Fxtal
M906-02 Datasheet Rev 0.7
3 of 8
Revised 30Jul2004
Integrated Circuit Systems, Inc. ● Networking & Communications ● www.icst.com ● tel (508) 852-5400
M906-02
Integrated
Circuit
Systems, Inc.
VCSO BASED
C
LOCK
G
ENERATOR
P r e l i m i n a r y I n f o r m a t i o n
External Loop Filter
APPLICATION INFORMATION
This section includes information on the optional
external crystal and on the external loop filter.
To provide stable PLL operation, and thereby a low jitter
output clock, the M906-02 requires the use of an
external loop filter. This is provided via the provided
filter pins (see Figure 5).
The subsections on the loop filter provide example
component values and also briefly describe the SAW
PLL simulator tool and additional application
information available at www.icst.com.
RLOOP CLOOP
RPOST
External Crystal Specifications
CPOST
CPOST
If an external crystal is used with the on-chip crystal
oscillator circuit (XTAL OSC), the external crystal
should have the following general specifications:
Crystal Specifications
RLOOP CLOOP
nOP_IN OP_OUT
RPOST
Parameter
Crystal Type
Min Typ Max Unit
AT-cut quartz
OP_IN
nOP_OUT
nVC
VC
4
9
8
5
6
7
Figure 5: External Loop Filter
Fundamental
Mode of Oscillation
Frequency Range
Equivalent Series Resistance
The loop filter is implemented as a differential circuit
to minimize system noise interference. Due to the
differential signal path design, the implementation
requires two identical complementary RC filters as
shown here. See Table 4, Example External Loop Filter
Component Values, below.
16
40
50
f
MHz
0
ESR
Ω
Spurious Response (non-harmonic)
-40 dBc
CL
Load Capacitance,
parallel load resonant
16
32
pF
0.1
1.0
P
Drive Level
mW
0
Example External Loop Filter Component Values
PLLBandwidth Damping R loop C loop R post C post
Table 3: Crystal Specifications
The external crystal will be applied to the XTAL_1 / REF_IN
and XTAL_2 input pins. External crystal load capacitors
are also required.
(kHz)
0.395
Factor
(kΩ)
(µF)
(kΩ)
(pF)
2.0
2.9
2.4
1.5
4.7
4.70
1.00
0.01
20
20
20
3300
1000
240
Recommended External Crystal Configuration
1.2
M906-02
M9xx-0x
1
10
39.0
Table 4: Example External Loop Filter Component Values
XTAL_1 / REF_IN
XTAL_2
Note 1: Recommended for minimum output jitter when
using a crystal or crystal oscillator reference.
C1
C2
XTAL OSC
XTAL
Refer to the M906-02 product web page at
www.icst.com/products/summary/m906-02.htm for
additional product information.
PLL Simulator Tool Available
Figure 4: Recommended External Crystal Configuration
XTAL Load Capacitance Specification = 18 pF
A free PC software utility is available on the ICS website
(www.icst.com). The M2000 Timing Modules PLL
Simulator is a downloadable application that simulates
PLL jitter and wander transfer characteristics. This
enables the user to set appropriate external loop
component values in a given application.
C1
C2
=
=
27 pF
33 pF
External load capacitors C1 and C2 present a load of 15 pf
to the crystal (they are seen in series by the crystal through
the common ground connection). With the additional of PCB
trace capacitance and M906-02 input capacitance, the total
load to the crystal is about 18 pf.
Refer to the SAW PLL Simulator Software web page at
www.icst.com/products/calculators/m2000filterSWdesc.htm
for additional information.
M906-02 Datasheet Rev 0.7
4 of 8
Revised 30Jul2004
Integrated Circuit Systems, Inc. ● Networking & Communications ● www.icst.com ● tel (508) 852-5400
M906-02
Integrated
Circuit
Systems, Inc.
VCSO BASED
C
LOCK
G
ENERATOR
P r e l i m i n a r y I n f o r m a t i o n
• Instructions for using PLL simulator software
SAW PLL Application Notes Available
• Guidelines for PCB fabrication (including recom-
mended PCB footprint, solder mask, and furnace
profile)
The ICS web site (www.icst.com) also has application
notes on:
• PCB layout guidelines (including special detailed
instructions for preventing issues such as external
reference crosstalk)
Refer to the SAW PLL Application Notes web page at
www.icst.com/products/appnotes/SawPllAppNotes.htm
for application notes and any additional product
information that may become available.
• Any new special device application details that may
become available
1
ABSOLUTE MAXIMUM RATINGS
Symbol Parameter
Rating
Unit
VI
Inputs
-0.5 to VCC +0.5
V
VO
VCC
TS
Outputs
-0.5 to VCC +0.5
4.6
V
V
Power Supply Voltage
Storage Temperature
-45 to +100
oC
Table 5: Absolute Maximum Ratings
Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional operation of product at these conditions
or any conditions beyond those listed in Recommended Conditions of Operation, DC Characteristics, or
AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect product reliability
.
RECOMMENDED CONDITIONS OF OPERATION
Symbol Parameter
Min
Typ
Max Unit
3.135
3.3
3.465
VCC
Positive Supply Voltage
V
TA
Ambient Operating Temperature
oC
oC
0
Commercial
Industrial
+70
+85
-40
Table 6: Recommended Conditions of Operation
M906-02 Datasheet Rev 0.7
5 of 8
Revised 30Jul2004
Integrated Circuit Systems, Inc. ● Networking & Communications ● www.icst.com ● tel (508) 852-5400
M906-02
Integrated
Circuit
Systems, Inc.
VCSO BASED
C
LOCK
G
ENERATOR
P r e l i m i n a r y I n f o r m a t i o n
ELECTRICAL SPECIFICATIONS
DC Characteristics
Unless stated otherwise, VCC
= 3.3V +5 = ,
%,TA = 0 oC to +70 oC (commercial), TA = -40 oC to +85 oC (industrial), FVCSO 155.52MHz 1
LVPECL outputs terminated with 50Ωto VCC - 2V
Symbol Parameter
Power Supply VCC Positive Supply Voltage
Min
3.135
Typ
3.3
Max
3.465
Unit
V
350
ICC
VIH
VIL
IIH
Power Supply Current
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
mA
V
2
Logic Inputs
V +0.3
cc
0.8
150
-0.3
V
FOUT_SEL, EN_EXT_CLK,
EXT_CLK, STOP
µA
µA
V
IIL
-5.0
Reference
Clock
Input
VIH
VIL
IIH
(V / 2 ) +0.5
V +0.3
cc
cc
-0.3
(V / 2 ) +0.5 V
cc
XTAL_1 / REF_IN
(XTAL_2 disconnected)
150
µA
µA
IIL
-5.0
FOUT_SEL,
EN_EXT_CLK, EXT_CLK,
STOP, XTAL_1 / REF_IN
4
All Inputs
Pull-down
CIN
Input Capacitance, All Inputs
pF
EN_EXT_CLK, STOP
51
R
Internal Pull-down Resistor
Output High Voltage
kΩ
V
pulldown
Differential
Output
VOH
VOL
VP-P
V
V
-1.4
-2.0
V
V
-1.0
cc
cc
FOUT, nFOUT (0-5)
Output Low Voltage
-1.7
V
cc
cc
0.6
Peak to Peak Output Voltage
0.85
V
Table 7: DC Characteristics
Note 1: For other VCSO center frequencies, contact ICS
AC Characteristics
Unless implied otherwise, VCC
=
3.3V +
to VCC - 2V
5 = ,
%,TA = 0 oC to +70 oC (commercial), TA = -40 oC to +85 oC (industrial), FVCSO 155.52MHz 1
LVPECL outputs terminated with 50
Ω
Symbol Parameter
Min
75
Typ
Max
175
Unit Test Conditions
1
FOUT
Output Frequency Range
MHz
MHz
ppm
FOUT_SEL=1
19.44
FIN
Nominal Input Frequency, XTAL_1 / REF_IN
VCSO Pull-Range
APR
Φn
+100
+150
Single Side Band
Phase Noise
1kHz Offset
10kHz Offset
100kHz Offset
-100
-110
-134
0.7
dBc/Hz
dBc/Hz
dBc/Hz
ps
@155.52MHz
1.0
55
J(t)
tDC
tR
Jitter (rms)
12kHz to 20MHz
45
50
Output Duty Cycle, High Time
%
FOUT, nFOUT (0-5)
350
350
450
450
550
550
100
200
Output Rise Time
Output Fall Time
Output Skew
ps
20% to 80%
20% to 80%
FOUT, nFOUT (0-5)
Between Any Pair
EXT_CLK
tF
ps
tS
ps
0
EXT_CLK Frequency
MHz
Table 8: AC Characteristics
Note 1: For other VCSO center frequencies, contact ICS
M906-02 Datasheet Rev 0.7
6 of 8
Revised 30Jul2004
Integrated Circuit Systems, Inc. ● Networking & Communications ● www.icst.com ● tel (508) 852-5400
M906-02
Integrated
Circuit
Systems, Inc.
VCSO BASED
C
LOCK
G
ENERATOR
P r e l i m i n a r y I n f o r m a t i o n
DEVICE PACKAGE - 9 x 9mm CERAMIC LEADLESS CHIP CARRIER
Mechanical Dimensions:
Refer to the SAW PLL application notes web page at
www.icst.com/products/appnotes/SawPllAppNotes.htm
for application notes, including recommended PCB
footprint, solder mask, and furnace profile.
Figure 6: Device Package - 9 x 9mm Ceramic Leadless Chip Carrier
M906-02 Datasheet Rev 0.7
7 of 8
Revised 30Jul2004
Integrated Circuit Systems, Inc. ● Networking & Communications ● www.icst.com ● tel (508) 852-5400
P r e l i m i n a r y I n f o r m a t i o n
M906-02
Integrated
Circuit
Systems, Inc.
VCSO BASED
CLOCK
G
ENERATOR
ORDERING INFORMATION
Part Numbering Scheme
Part Number:
Device Number
M906-02-xxx.xx
Temperature
0
to +70 o
C
(commercial)
“I-”==- 40 to +85 o
C (industrial)
VCSO Frequency (MHz)
See Table 9 for example part numbers.
Consult ICS for the availability of VCSO frequencies.
Figure 7: Part Numbering Scheme
Example Part Numbers
For Output Frequencies (MHz)
Temperature
commercial
industrial
commercial
industrial
Order Part Number
M906-02-155.5200
155.52 (and 77.76)
M906-02
M906-02-xxx.xxxx
M906-02 xxx.xxxx
I155.5200
150 to 175 (and 75 to 87.5)
I
Table 9: Example Part Numbers
Consult ICS for the availability of VCSO frequencies
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS)
assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would
result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial
applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary
environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any
circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or
critical medical instruments.
M906-02 Datasheet Rev 0.7
8 of 8
Revised 30Jul2004
Integrated Circuit Systems, Inc. ● Networking & Communications ● www.icst.com ● tel (508) 852-5400
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