MC100ES8011PD [IDT]

Low Skew Clock Driver, 100E Series, 2 True Output(s), 0 Inverted Output(s), ECL, PDSO8, SOIC-8;


型号：	MC100ES8011PD
厂家：	INTEGRATED DEVICE TECHNOLOGY
描述：	Low Skew Clock Driver, 100E Series, 2 True Output(s), 0 Inverted Output(s), ECL, PDSO8, SOIC-8 驱动光电二极管逻辑集成电路
文件：	总6页 (文件大小：216K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

DATA SHEET

Rev 1, 2/2005

MC100ES8011P

Freescale Semiconductor

Technical Data

MC100ES8011P

Low Voltage 1:2 Differential PECL-to

Low Voltage 1:2 Differential

-HSTL Clock Fanout Buffer

MC100ES8011P

PECL-to-HSTL Clock Fanout Buffer

The MC100ES8011P is a low voltage 1:2 Differential PECL-to-HSTL clock

fanout buffer. Designed for the most demanding clock distribution systems, the

MC100ES8011P supports various applications that require the distribution of

precisely aligned differential clock signals. Using SiGe technology and a fully

differential architecture, the device offers very low skew outputs and superior

digital signal characteristics. Target applications for this clock driver are in high

performance clock distribution in computing, networking and telecommunication

systems.

1:2 DIFFERENTIAL PECL TO HSTL

CLOCK FANOUT DRIVER

Features

•

1:2 differential clock fanout buffer

20 ps maximum device skew

SiGe Technology

Supports DC to 625 MHz operation

HSTL compatible differential clock outputs

PECL compatible differential clock inputs

3.3V power supply

D SUFFIX

8-LEAD SOIC PACKAGE

CASE 751-06

Supports industrial temperature range

Standard 8 lead SOIC package

ORDERING INFORMATION

Device

Package

SO-8

MC100ES8011PD

MC100ES8011PDR2

SO-8

V_CC

PIN DESCRIPTION

Function

D, D

ECL Data Inputs

LVDS Data Outputs

Positive Supply

Qn, Qn

V_CC

V_EE

Negative Supply

V_EE

Figure 1. 8-Lead Pinout (Top View) and Logic Diagram

IDT™ Low Voltage 1:2 Differential PECL-to-HSTL Clock Fanout Buffer

MC100ES8011P

Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc

MC100ES8011P

Low Voltage 1:2 Differential PECL-to-HSTL Clock Fanout Buffer

NETCOM

Table 1. Absolute Maximum Ratings⁽¹⁾

Symbol

Parameter

Power Supply Voltage

Conditions

Rating

Unit

V_SUPPLY

Difference between V_CC& V_EE

3.9

V_IN

Input Voltage

V_CC– V_EE≤ 3.6V

V_CC+ 0.3

_EE– 0.3

I_OUT

Output Current

Continuous

Surge

100

T_A

Operating Temperature Range

Storage Temperature Range

–40 to +85

°C

T_STG

–65 to +150

1. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these

conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated

conditions is not implied.

Table 2. DC Characteristics (V_CC= 3.3 V ± 5%; T_J= 0°C to 110°C)⁽¹⁾

Symbol

Characteristic

Min

Typ

Max

Unit

Condition

PECL differential input signals (D, D)

Differential Input Voltage⁽²⁾

V_PP

V_CMR

I_IN

0.15

1.0

Differential Operation

V_{IN =}V_IHor V_IN

Differential Cross Point Voltage⁽³⁾

Input Current

_CC– 0.6

±150

HSTL clock outputs (Q[0:1], Q[0:1])

V_{X, OUT}Output Differential Crosspoint

V_OH

0.68

0.75

0.9

0.4

105

Output High Voltage

Ouput Low Voltage

V_OL

Supply Current

I_CCMaximum Quiescent Supply Current without

output termination current

V_CCpin (core)

1. DC characteristics are design targets and pending characterization.

2. V_PP(DC) is the minimum differential input voltage swing required to maintain device functionality.

3. V_CMR(DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the V_CMR(DC)

range and the input swing lies within the V_PP(DC) specification.

MC100ES8011P

IDT™ Low Voltage 1:2 Differential PECL-to-HSTL Clock Fanout Buffer

MC100ES8011P

Product Group

Freescale Semiconductor

Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc

MC100ES8011P

Low Voltage 1:2 Differential PECL-to-HSTL Clock Fanout Buffer

NETCOM

Table 3. AC Characteristics (V_CC= 3.3 V ± 5%; T_J= 0°C to 110°C)^{(1) (2)}

Symbol

Characteristic

Min

Typ

Max

Unit

Condition

PECL differential input signals (D, D)

Differential Input Voltage (peak-to-peak)⁽³⁾

V_PP

0.2

1.0

Differential Cross Point Voltage⁽⁴⁾

Input Frequency

V_CMR

_CC– 0.6

f_CLK

t_PD

625

940

MHz

Differential

Propagation Delay D to Q[0:1]

600

760

Differential

HSTL clock outputs (Q[0:1], Q[0:1])

V_{X, OUT}

V_OH

Output Differential Crosspoint

Output High Voltage

0.68

0.75

0.9

0.5

V_OL

Ouput Low Voltage

V_O(P-P)

t_SK(O)

t_SK(PP)

t_SK(P)

t_JIT(CC)

t_r/ t_f

Differential Output Voltage (peak-to-peak)

Output-to-Output Skew

0.5

340

Differential

Output-to-Output Skew (part-to-part)

Output Pulse Skew

Output Cycle-to-Cycle Jitter

Output Rise/Fall Times

150

800

20% to 80%

1. AC characteristics are design targets and pending characterization.

2. AC characteristics apply for parallel output termination of 50Ω to V_TT.

3. V_PP(AC) is the minimum differential PECL input voltage swing required to maintain AC characteristics including tpd and device-to-device

skew.

4. V_CMR(AC) is the crosspoint of the differential PECL input signal. Normal AC operation is obtained when the crosspoint is within the V_CMR

(AC) range and the input swing lies within the V_PP(AC) specification. Violation of V_CMR(AC) or V_PP(AC) impacts the device propagation

delay, device and part-to-part skew.

MC100ES8011P

IDT™ Low Voltage 1:2 Differential PECL-to-HSTL Clock Fanout Buffer

MC100ES8011P

Product Group

Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc

Freescale Semiconductor

MC100ES8011P

Low Voltage 1:2 Differential PECL-to-HSTL Clock Fanout Buffer

NETCOM

Z_O= 50Ω

R_T= 50Ω

Differential Pulse

Generator

Z = 50Ω

DUT

MC100ES8011P

R_T= 50Ω

V_TT=GND

Figure 2. MC100ES8011P AC Test Reference

V_DIF=0.8V

V_CMR=V_CC–1.3V

Q[0–1]

t_PD(D to Q[0–1])

Figure 3. MC100ES8011P AC Reference Measurement Waveform (PECL Input)

MC100ES8011P

IDT™ Low Voltage 1:2 Differential PECL-to-HSTL Clock Fanout Buffer

MC100ES8011P

Product Group

Freescale Semiconductor

Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc

MC100ES8011P

Low Voltage 1:2 Differential PECL-to-HSTL Clock Fanout Buffer

NETCOM

PACKAGE DIMENSIONS

NOTES:

1. DIMENSIONING AND TOLERANCING PER ASME

Y14.5M, 1994.

2. DIMENSIONS ARE IN MILLIMETER.

3. DIMENSION D AND E DO NOT INCLUDE MOLD

PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.

5. DIMENSION B DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBAR

PROTRUSION SHALL BE 0.127 TOTAL IN EXCESS

OF THE B DIMENSION AT MAXIMUM MATERIAL

CONDITION.

0.25

X 45˚

MILLIMETERS

DIM

MIN

1.35

0.10

0.35

0.19

4.80

3.80

MAX

1.75

0.25

0.49

0.25

5.00

4.00

SEATING

PLANE

1.27 BSC

0.10

5.80

0.25

0.40

0˚

6.20

0.50

1.25

7˚

0.25

D SUFFIX

8-LEAD SOIC PACKAGE

CASE 751-06

MC100ES8011P

IDT™ Low Voltage 1:2 Differential PECL-to-HSTL Clock Fanout Buffer

MC100ES8011P

Product Group

Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc

Freescale Semiconductor

MPCC10902E45S98011P

PART NUMBERS

INSERT PRODUCT NAME AND DOCUMENT TITLE

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NETCOM

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