MK2049-11SI [IDT]
Clock Generator, 56MHz, PDSO20, 0.300 INCH, SOIC-20;
| 型号： | MK2049-11SI |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Clock Generator, 56MHz, PDSO20, 0.300 INCH, SOIC-20 光电二极管 |
| 文件： | 总13页 (文件大小：166K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MK2049-11
Communications Clock PLL
GENERAL DESCRIPTION
PIN ASSIGNMENT
The MK2049-11 is designed to serve as a pin
NC
X2
1
20
19
18
17
16
15
14
13
12
11
NC
compatible, performance-improved replacement for the
MK2049-01 when using the 19.44 / 38.88 MHz output
selection. For pin compatibility when using other output
frequencies please refer to the MK2049-10.
2
FS1
X1
3
CAP2
GND
CAP1
VDD
GND
ICLK
FS3
VDD
VDD
VDD
GND
CLK2
CLK1
8K
4
5
The MK2049-11 is a VCXO (Voltage Controlled Crystal
Oscillator) based clock generator that produces a pin
selectable set of common telecommunications
reference frequencies. The output clock is phase
locked to an 8kHz (frame rate) input reference clock.
6
7
8
9
10
FS2
Features
For new 3.3V logic applications, please refer to the
following products:
• Pin compatible upgrade for the MK2049-01 when
using the 19.44 / 38.88 MHz output selection
• Single 5V power supply
• 20 pin SOIC package
• Industrial temperature range
• VCXO-based clock generator
MK2049-34/35/36
MK2058-01
MK2059-01
MK2069-01/02/03/04
• Configurable jitter attenuation characteristics,
excellent for use as a Stratum source de-jitter circuit
Block Diagram
C1
CL
CL
Optional Crystal Load Caps
C2
RZ
External Pullable Crystal
CAP2
CAP1 X1
X2
Phase
Detector
Reference
Divider
Reference
Divider
Output
Divider
ICLK
VCXO
VCO
CLK2
CLK1
(used in buffer
mode only)
Divide
by 2
Charge
Pump
Feedback
Divider
Feedback
Divider (N)
Translator
PLL
VCXO
PLL
8k
3
Divider Value
Look-up Table
FS3:1
MDS 2049-11 C
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MK2049-11
Communications Clock PLL
OUTPUT FREQUENCY SELECTION TABLE
Input
Clock
(ICLK)
Input Selection
Output Clocks
Crystal
Freq
(MHz)
Notes
FS3
FS2
FS1
CLK1
(MHz)
CLK2
(MHz)
8K
8 kHz
8 kHz
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1.544
17.184
19.44
3.088
34.368
38.88
8 kHz
8 kHz
8 kHz
8 kHz
n/a
12.352
11.456
12.96
12.96
12.352
11.456
10.24
ICLK
1
2
1
8 kHz
8 kHz
25.92
51.84
1.544 MHz
34.368 MHz
8 kHz
1.544
3.088
1
2
17.184
10.24
34.368
20.48
n/a
8 kHz
n/a
10-14 MHz
2x ICLK
4x ICLK
Note 1: This output frequency selection provides full pin compatibility with the ICS2049-01. Please note that the
external crystal frequency must be changed. Please review the external component values as well (see
recommendations table on page 6).
Note 2: These output frequency combinations are also provided by the MK2049-01, however the MK2049-11 does
not provide full pin compatibility with these selections (an alternate input is selection is required). For full pin
compatibility with these output frequency combinations, please refer to the MK2049-10.
MDS 2049-11 C
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MK2049-11
Communications Clock PLL
Pin Descriptions
Pin
Pin
Pin
Pin Description
Number
Name
Type
1
2
3
4
5
6
7
8
NC
-
-
-
No internal connection, may be tied high or low, or left floating.
Crystal Output. Connect this pin to the external reference crystal.
Crystal Input. Connect this pin to the external reference crystal.
X2
X1
VDD
VDD
VDD
GND
CLK2
Power Power Supply. Connect to +5V.
Power Power Supply. Connect to +5V.
Power Power Supply. Connect to +5V.
Power Ground.
Output Clock output, frequency determined by status of FS3:1 per table on
page 2.
9
CLK1
Output Clock output, frequency determined by status of FS3:1 per table on
page 2.
10
11
8k
Output 8.000kHz Clock Output, applicable modes only, refer to table on page 2.
FS2
Input
Input
Input
Frequency selection input. Determines output clock frequencies per
table on page 2. Internal pull-up, will assume logic high when
unconnected.
12
FS3
Frequency selection input. Determines output clock frequencies per
table on page 2. Internal pull-up, will assume logic high when
unconnected.
13
14
15
16
17
18
19
ICLK
GND
VDD
CAP1
GND
CAP2
FS1
Input Clock Connection.
Power Ground.
Power Power Supply. Connect to +5V.
-
Loop Filter Connection. Refer to Block Diagram on page 1.
Power Ground.
-
Loop Filter Connection. Refer to Block Diagram on page 1.
Input
Frequency selection input. Determines output clock frequencies per
table on page 2. Internal pull-up, will assume logic high when
unconnected.
20
NC
-
No internal connection, may be tied high or low, or left floating.
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MK2049-11
Communications Clock PLL
Setting the VCXO PLL Loop Response.
Functional Description
The VCXO PLL loop response is determined both by
fixed device characteristics and by other characteristics
set by the user. This includes the values of RZ, C1, and
C2 as shown in the Block Diagram on page 1.
The MK2049-11 is a PLL (Phased Locked Loop) based
clock generator that generates output clocks
synchronized to an input reference clock. It contains
two cascaded PLL’s with table selected divider ratios.
The VCXO PLL loop bandwidth is approximated by:
The first PLL is VCXO-based and uses an external
pullable crystal as part of the normal “VCO” (voltage
controlled oscillator) function of the PLL. The use of a
VCXO assures a low phase noise clock source even
when a low PLL loop bandwidth is implemented. A low
loop bandwidth is needed when the input reference
frequency at the phase detector is low, or when jitter
attenuation of the input reference is desired.
RZ × ICP × KO
NBW(VCXO PLL) = ---------------------------------
2π × N
Where:
RZ = Value of resistor RZ in loop filter in Ohms
ICP = Charge pump current in amps = 50 µA
(fixed, not adjustable)
The second PLL is used to translate or multiply the
frequency of the VCXO PLL. The Translator PLL uses
an on-chip VCO for output clock generation and is
configured with high loop bandwidth.
KO = VCXO Gain in Hz/V
(see table on page 8)
N = XTAL frequency / input clock frequency
(see 4th column of table on page 6)
The divide values of the divider blocks within both PLLs
are set through table selection.
The above equation calculates the “normalized” loop
bandwidth (denoted as “NBW”) which is approximately
equal to the - 3dB bandwidth. NBW does not take into
account the effects of damping factor or the second
pole imposed by C2. It does, however, provide a useful
approximation of filter performance.
External components are used to configure the VCXO
PLL loop response. This serves to maximize loop
stability and to achieve the desired input clock jitter
attenuation characteristics.
To prevent jitter on the output clocks due to modulation
of the VCXO PLL by the phase detector frequency, the
following general rule should be observed:
Application Information
The MK2049-11 is a mixed analog / digital integrated
circuit that is sensitive to PCB (printed circuit board)
layout and external component selection. Used
properly, the device will provide the same high
performance expected from a canned VCXO-based
hybrid timing device, but at a lower cost. To help avoid
unexpected problems, the guidance provided in the
sections below should be followed.
f(Input Frequency)
----------------------------------------
NBW(VCXO PLL) ≤
20
.
The PLL loop damping factor is determined by:
RZ
DF(VCLK) = ------ ×
2
ICP × C1 × KO
---------------------------------
N
Where:
C1 = Value of capacitor C1 in loop filter in
Farads
In general, the loop damping factor should be 0.7 or
greater to ensure output stability. A higher damping
factor will create less peaking in the passband and will
further assure output stability with the presence of
system and power supply noise. A damping factor of 4
or greater will assure a passband peak less then 0.2dB
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MK2049-11
Communications Clock PLL
(see also notes below regarding C2) which may be
required for network clock wander transfer compliance.
A high damping factor may also increase output clock
jitter when there is excess digital noise in the system
application, due to the reduced ability of the PLL to
respond to and therefore compensate for phase noise
ingress.
Loop Filter Response Software
ICS has a PC-based program available that simulates
VCXO PLL loop response characteristics. This can be
used instead of the above bandwidth and damping
factor equations. The user enters external loop filter
component values and other listed device
characteristics. The program generates a PLL
frequency response graph, which translates to jitter
attenuation characteristics. Normalized bandwidth
(NBW) and damping factor values are also calculated.
To obtain this free software please contact the
applications department of ICS, MicroClock Division, at
(408) 297-1201.
Notes on setting the value of C
2
As another general rule, the following relationship
should be maintained between components C1 and C2
in the loop filter:
C
1
20
-----
C =
2
VCXO Gain (K ) vs. XTAL Frequency
O
C2 establishes a second pole in the VCXO PLL loop
filter. For higher damping factors (> 1), calculate the
value of C2 based on a C1 value that would be used for
a damping factor of 1. This will prevent excessive
baseband peaking and loop instability that can lead to
output jitter.
6000
5000
4000
3000
2000
1000
C2 also dampens VCXO input voltage modulation by
the charge pump correction pulses. A C2 value that is
too low will result in increased output phase noise at
the phase detector frequency due to this. In extreme
cases where input jitter is high, charge pump current is
high, and C2 is too small, the VCXO input voltage can
hit the supply or ground rail resulting in non-linear loop
response.
The best way to set the value of C2 is to use the filter
response software available from ICS (please refer to
the following section). C2 should be increased in value
until it just starts affecting the passband peak.
10
15
20
25
30
Crystal Frequency, MHz
MDS 2049-11 C
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MK2049-11
Communications Clock PLL
Recommended Loop Filter Values Vs. Output Frequency Range Selection
VCXO PLL
Approximate
Loop
Bandwidth
(-3dB point)
Input
Clock
FS3:1 (ICLK)
External
Crystal
Freq
‘N’
(feedback
divider)
Value
1544
Approximate
Damping
Factor
RZ
C1
C2
(MHz)
8 kHz
8 kHz
8 kHz
12.352
11.456
12.96
12.96
12.352
000
001
010
011
100
2.7 MΩ
2.7 MΩ
2.7 MΩ
2.7 MΩ
47 kΩ
0.1 µF
0.1 µF
0.1 µF
0.1 µF
0.1 µF
1 µF
330 pF
330 pF
330 pF
330 pF
4.7 nF
47 nF
40 Hz
40 Hz
40 Hz
40 Hz
180 Hz
90 Hz
400 Hz
4
4
4
4
1
1432
1620
1620
8
8 kHz
1.544 MHz
Filter Option for Above Mode
34.368
MHz
22 kΩ
24 kΩ
1.4
1
11.456
101
2
0.1 µF
4.7 nF
Filter Option for Above Mode
11 kΩ
2.7 MΩ
43 kΩ
18 kΩ
1 µF
0.1 µF
0.1 µF
1 µF
47 nF
330 pF
4.7 nF
47 nF
180 Hz
40 Hz
220 Hz
100 Hz
1.4
4
1
8 kHz
10-14 MHz
10.24
ICLK
110
111
1280
6
Filter Option for Above Mode
1.4
Loop Filter Capacitor Type
Power Supply Considerations
Loop filter capacitors C1 and C2 should be film type.
This includes the PPS polymer film type made by
Panasonic, or metal poly types made by MuRata or
Cornell Dublier.
As with any integrated clock device, the MK2049-11
has a special set of power supply requirements:
• The feed from the system power supply must be
filtered for noise that can cause output clock jitter.
Power supply noise sources include the system
switching power supply or other system components.
The noise can interfere with various internal device
circuit blocks such as the VCO or phase detector.
The Panasonic ECP-U and ECH-U series capacitors
are typically used on the ICS MK20xx demo boards
and are found to work well. These devices are
available from Digi-Key.
• Each VDD pin must be decoupled individually to
prevent power supply noise generated by one device
circuit block from interfering with another circuit
block.
Other acceptable capacitor types include those with
C0G or NP0 dielectric.
Avoid high-K dielectrics like Z5U and X7R (these are
acceptable for the decoupling capacitors, however).
The loop capacitors must have a high dielectric
resistance to avoid leakage-induced phase noise. For
this reason, DO NOT use any type of polarized or
electrolytic capacitors. Microphonics (mechanical
board vibration) will also induce output phase noise.
High-K dielectrics like Z5U and X7R have piezoelectric
properties that convert mechanical vibration into
voltage noise that interferes with VCXO operation.
• Clock noise from device VDD pins must not get onto
the PCB power plane or system EMI problems may
result.
This above set of requirements is served by the circuit
illustrated in the Recommended Power Supply
Connection, below. The main features of this circuit are
as follows:
• Only one connection is made to the PCB power
plane.
For additional questions, please contact your ICS
Sales FAE or contact ICS MicroClock applications at
(408) 297-1201.
• The capacitors and ferrite chip (or ferrite bead) on
the common device supply form a lowpass ‘pi’ filter
that remove noise from the power supply as well as
clock noise back toward the supply. The bulk
MDS 2049-11 C
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MK2049-11
Communications Clock PLL
capacitor should be a tantalum type, 1 µF minimum.
The other capacitors should be ceramic type.
Quartz Crystal
The MK2049-11 operates by phase-locking the VCXO
circuit to the input signal at the ICLK input. The VCXO
consists of the external crystal and the integrated
VCXO oscillator circuit. To achieve the best
• The power supply traces to the individual VDD pins
should fan out at the common supply filter to reduce
interaction between the device circuit blocks.
• The decoupling capacitors at the VDD pins should be
ceramic type and should be as close to the VDD pin
as possible. There should be no via’s between the
decoupling capacitor and the supply pin.
performance and reliability, a crystal device with the
recommended parameters (shown below) must be
used, and the layout guidelines discussed in the
following section shown must be followed.
The frequency of oscillation of a quartz crystal is
determined by its cut and by the load capacitors
connected to it. The MK2049-11 incorporates variable
load capacitors on-chip which “pull” or change the
frequency of the crystal. The crystals specified for use
with the MK2049-11 are designed to have zero
frequency error when the total of on-chip + stray
capacitance is 14pF. To achieve this, the layout should
use short traces between the MK2049-11 and the
crystal.
Recommended Power Supply Connection
VDD
Pin
Connection Via to
5V Power Plane
VDD
Pin
Ferrite
Chip
Recommended Crystal Parameters:
VDD
Pin
Operating Temperature Range
Commercial Applications
Industrial Applications
Initial Accuracy at 25°C
Temperature Stability
Aging
0 to 70°C
-40 to 85°C
±20 ppm
±30 ppm
±20 ppm
14 pF
VDD
Pin
Load Capacitance
Shunt Capacitance, C0
C0/C1 Ratio
Equivalent Series Resistance
7 pF Max
250 Max
35 Ω Max
Note: Crystals used in production should be screened
for 3rd overtone modes and spurs over the range of (3x
crystal frequency) +/- 100ppm, when measured at the
nominal parallel resonant frequency. Failure to do so
may cause locking problems in a small percentage of
production systems at certain input frequencies.
Series Termination Resistor
Output clock PCB traces over 1 inch should use series
termination to maintain clock signal integrity and to
reduce EMI. To series terminate a 50Ω trace, which is a
commonly used PCB trace impedance, place a 33Ω
resistor in series with the clock line as close to the clock
output pin as possible. The nominal impedance of the
clock output is 20Ω.
Crystal Tuning Load Capacitors
The crystal traces should include pads for small
capacitors from X1 and X2 to ground, shown as CL in
the Block Diagram on page 1. These capacitors are
optional and may be later used to center the total load
capacitor adjustment range imposed on the crystal.
The load adjustment range includes stray PCB
capacitance that varies with board layout. Because the
typical telecom reference frequency is accurate to less
MDS 2049-11 C
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MK2049-11
Communications Clock PLL
than 32 ppm, the MK2049-11 may operate properly
without these adjustment capacitors. However, ICS
recommends that these capacitors be included to
minimize the effects of variation in individual crystals,
included those induced by temperature and aging. The
value of these capacitors (typically 0-4 pF) is
determined once for a given board layout, using the
procedure described in the section titled “Optimization
of Crystal Load Capacitors”.
6) Because each input selection pin includes an
internal pull-up device, those inputs requiring a logic
high state (“1”) can be left unconnected. The pins
requiring a logic low state (“0”) can be connected
directly to ground.
Optional Crystal Shielding
The crystal and connection traces to pins X1 and X2
are sensitive to noise pickup. In applications that
especially sensitive to noise, such as SONET or G-Bit
ethernet transceivers, some or all of the following
crystal shielding techniques may be considered. This is
especially important when the MK2049-11 is placed
near high speed logic or signal traces, and when the
VCXO loop bandwidth is below 10 Hz.
PCB Layout Recommendations
For optimum device performance and lowest output
phase noise, the following guidelines should be
observed.
1) The metal layer underneath the crystal section
should be the ground layer. Remove all other layers
that are above. This ground layer will help shield the
crystal circuit from other system noise sources. As an
alternative, all layers underneath the crystal can be
removed, however this is not recommended if there are
adjacent PCBs that can induce noise into the
unshielded crystal circuit.
1) Each 0.01µF decoupling capacitor should be
mounted on the component side of the board as close
to the VDD pin as possible. No via’s should be used
between the decoupling capacitor and VDD pin. The
PCB trace to VDD pin should be kept as short as
possible, as should the PCB trace to the ground via.
Distance of the ferrite chip and bulk decoupling from
the device is less critical.
2) Add a through-hole for the optional third lead offered
by the crystal manufacturer (case ground). The
requirement for this third lead can be made at
prototype evaluation. The crystal is less sensitive to
system noise interference when the case is grounded.
2) The loop filter components must also be placed
close to the CAP1 and CAP2 pins. C2 should be
closest to the device. Coupling of noise from other
system signal traces should be minimized by keeping
traces short and away from active signal traces. Use of
vias should be avoided.
3) Add a ground trace around the crystal circuit to
shield from other active traces on the component layer.
3) The external crystal should be mounted as close the
device as possible, on the component side of the
board. This will keep the crystal PCB traces short
which will minimize parasitic load capacitance on the
crystal, and noise pickup. The crystal traces should be
spaced away from each other and should use minimum
trace width. There should be no signal traces near the
crystal or the traces. Also refer to the Optional Crystal
Shielding section that follows.
The external crystal is particularly sensitive to other
system clock sources that are at or near the crystal
frequency since it will try to lock to the interfering clock
source. This can adversely affect crystal operation if
the VCXO loop bandwidth is low, such as under 10 Hz.
It is good practice in general to keep the crystal away
from other clock sources.
4) To minimize EMI the 33Ω series termination resistor,
if needed, should be placed close to the clock output.
The ICS Applications Note MAN05 may also be
referenced for additional suggestions on layout of the
crystal section.
5) All components should be on the same side of the
board, minimizing vias through other signal layers (the
ferrite bead and bulk decoupling capacitor may be
mounted on the back). Other signal traces should be
routed away from the MK2049-11. This includes signal
traces on PCB just underneath the device, or on layers
adjacent to the ground plane layer used by the device.
Optimization of Crystal Load
Capacitors
MDS 2049-11 C
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MK2049-11
Communications Clock PLL
The concept behind the crystal load capacitors is
introduced on page 7. To determine the need for and
value of these capacitors, you will need a PC board of
your final layout, a frequency counter capable of less
than 1 ppm resolution and accuracy, two power
supplies, and some samples of the crystals which you
plan to use in production, along with measured initial
accuracy for each crystal at the specified crystal load
capacitance, CL.
Circuit Troubleshooting
1) IF CLK1 or CLK2 does not lock to ICLK
First check for locking between ICLK and the 8k output.
If locking does not occur:
1.1) Ensure the table selection is made and that the
proper crystal frequency is in use.
1.2) Ensure ICLK is within lock range (within about 100
ppm of the nominal input frequency, limited by pull
range of the external crystal). If in doubt, tweak the
ICLK frequency up and down to see if the 8k output
locks.
To determine the value of the crystal capacitors:
1. Connect VDD of the MK2049-11 to 5V. Connect pin 5
to the second power supply. Adjust the voltage on pin 5
to 0V. Measure and record the frequency of the CLK
output.
1.3) Ensure ICLK jitter is not excessive. If ICLK jitter is
excessive device may not lock. Also see item 2.1
below.
2. Adjust the voltage on pin 5 to 5V. Measure and
record the frequency of the same output.
1.4) Clean the PCB. The VCXO PLL loop filter is very
sensitive to board leakage, especially when the VCXO
PLL phase detector frequency is in the low kHz range.
If organic solder flux is used (most common today)
scrub the PCB board with detergent and water and
then blow and bake dry. Inorganic solder flux (Rosen
core) requires solvent. See also section 2 below.
To calculate the centering error:
(f5V – ftarget) + (f0V – ftarget
)
Error = 106x -------------------------------------------------------------------------- – errorxtal
2 × ftarget
Where:
ftarget = nominal crystal frequency
errorxtal =actual initial accuracy (in ppm) of the crystal
being measured
2) If There is Excessive Jitter on the 8k output,
or CLK1 and CLK2 outputs
2.1) The problem may be an unstable input reference
clock. An unstable ICLK will not appear to jitter when
ICLK is used as the oscilloscope trigger source. In this
condition, the device clock outputs may appear to be
unstable since the jitter from ICLK (the trigger source)
has been removed by the trigger circuit of the scope.
If the centering error is less than ±15 ppm, no
adjustment is needed. If the centering error is more
than 15 ppm negative, the PC board has too much
stray capacitance and will need to be redone with a
new layout to reduce stray capacitance. (The crystal
may be re-specified to a lower load capacitance
instead. Contact ICS MicroClock for details.) If the
centering error is more than 15 ppm positive, add
identical fixed centering capacitors from each crystal
pin to ground. The value for each of these caps (in pF)
is given by:
2.2) The instability may be caused by VCXO PLL loop
filter leakage. Refer to item 1.4 above.
2.3) Output clock jitter can also be caused by poor
power supply decoupling. Ensure a bulk decoupling
capacitor is in place.
2.4) Ensure that the VCXO PLL loop damping is
sufficient. It should be at least 0.7, preferably 1.0 or
higher.
External Capacitor =
2 x (centering error)/(trim sensitivity)
Trim sensitivity is a parameter which can be supplied
by your crystal vendor. If you do not know the value,
assume it is 30 ppm/pF. After any changes, repeat the
measurement to verify that the remaining error is
acceptably low (less than ±15ppm).
2.5) Ensure that the 2nd pole in the VCXO PLL loop
filter is set sufficiently. In general, C2 should be equal to
C1/20. If C2 is too high, passband peaking will occur
and loop instability may occur. If C2 is set too low,
excessive VCXO modulation by the charge correction
pulses may occur.
MDS 2049-11 C
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MK2049-11
Communications Clock PLL
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the MK2049-11. These ratings,
which are standard values for ICS industrial rated parts, are stress ratings only. Functional operation of the
device at these or any other conditions above those indicated in the operational sections of the
specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can
affect product reliability. Electrical parameters are guaranteed only over the recommended operating
temperature range.
Item
Rating
Supply Voltage, VDD
All Inputs and Outputs
7V
-0.5V to VDD+0.5V
-40 to +85°C
-65 to +150°C
175°C
Ambient Operating Temperature
Storage Temperature
Junction Temperature
Soldering Temperature
260°C
Recommended Operation Conditions
Parameter
Min.
Typ.
Max.
+85
Units
°C
Ambient Operating Temperature
Power Supply Voltage (measured in respect to GND)
-40
+4.75
+5
+5.25
V
MDS 2049-11 C
10
Revision 021402
Integrated Circuit Systems, Inc. ● 525 Race Street San Jose, CA 95126 ● tel (408) 295-9800 ● www.icst.com
MK2049-11
Communications Clock PLL
DC Electrical Characteristics
Unless stated otherwise, VDD = 5V ±5%, Ambient Temperature -40 to +85°C
Parameter
Operating Voltage
Symbol
VDD
IDD
Conditions
Min.
Typ.
5
Max. Units
4.75
5.25
30
V
mA
µA
V
Supply Current
Outputs unloaded
20
Chrage Pump Current
ICP
50
Input High Voltage; ICLK, FS3,
FS2, FS1
VIH
2
VDD +
0.4
Input Low Voltage; ICLK, FS3,
FS2, FS1
VIL
-0.4
0.8
V
Input Pull-Up Resistor (Note 1)
Input High Voltage; ICLK
RPU
VIH
200
kΩ
VDD/2+1
VDD +
0.4
V
VDD/2-1
+10
Input Low Voltage; ICLK
VIL
IIH
-0.4
-10
-10
V
Input High Current (Note 1)
Input Low Current (Note 1)
Input Capacitance, except X1
VIH = VDD
VIL = 0
µA
µA
pF
V
IIL
+10
CIN
VOH
7
Output High Voltage (CMOS
Level)
IOH = -4 mA
VDD-0.4
2.4
Output High Voltage
VOH
VOL
IOS
IOH = -8 mA
IOL = 8 mA
V
V
Output Low Voltage
0.4
Output Short Circuit Current
±100
mA
V
VCXO Control Voltage at pin
CAP2
VXC
0
VDD
Note 1: All logic select inputs (FS3, FS2, and FS1) have an internal pull-up resistor.
MDS 2049-11 C
11
Revision 021402
Integrated Circuit Systems, Inc. ● 525 Race Street San Jose, CA 95126 ● tel (408) 295-9800 ● www.icst.com
MK2049-11
Communications Clock PLL
AC Electrical Characteristics
Unless stated otherwise, VDD = 5V ±5%, Ambient Temperature -40 to +85° C
Parameter
Symbol
Conditions
Min.
Typ. Max. Units
VCXO Crystal Pull Range
fXP
Using recommended
crystal
±115
±150
ppm
MHz
nsec
UI
Crystal Frequency Range
Input Clock Pulse Width
Phase Detector Jitter Tolerance
Input Clock Period Jitter
fXTAL
tID
Using recommended
crystal
8
14
Positive or Negative
Pulse
10
tJT
1 UI = phase detector
period
0.4
tOJ
Peak-to-peak
200
250
400
ps
ps
Intrinsic Output Timing Jitter,
Filtered
500Hz-1.3MHz (OC-3)
tOJf
Derived from phase
noise characteristics,
peak-to-peak 6 sigma
Intrinsic Output Timing Jitter,
Filtered
65kHz-5MHz (OC-3)
tOJf
tOJf
tOJf
Derived from phase
noise characteristics,
peak-to-peak 6 sigma
150
250
150
50
ps
ps
ps
%
Intrinsic Output Timing Jitter,
Filtered
1kHz-5MHz (OC-12)
Derived from phase
noise characteristics,
peak-to-peak 6 sigma
Intrinsic Output Timing Jitter,
Filtered
250kHz-5MHz (OC-12)
Derived from phase
noise characteristics,
peak-to-peak 6 sigma
Output Duty Cycle (% high time);
CLK1, CLK2
tOD
tOH
Measured at VDD/2,
CL=15pF
44
65
Output High Time, 8k Output
Measured at VDD/2,
CL=15pF
0.5
VCLK
Period
Output Rise Time
tOR
tOF
0.8 to 2.0V, CL=15pF
2.0 to 0.8V, CL=15pF
1.5
1.5
20
2
2
ns
ns
Ω
Output Fall Time
Nominal Output Impedance
ZOUT
Note: Input to output clock skew is not controlled.
MDS 2049-11 C
12
Revision 021402
Integrated Circuit Systems, Inc. ● 525 Race Street San Jose, CA 95126 ● tel (408) 295-9800 ● www.icst.com
MK2049-11
Communications Clock PLL
Package Output and Package Dimensions
SOIC 300 mil (wide body) SOIC
(Package dimensions are kept current with JEDEC Publication No. 95.)
Inches
Min
Millimeters
Symbol
Max
0.104
--
Min
--
Max
2.65
--
A
A1
A2
B
--
Index
Area
0.0040
0.081
0.013
0.007
0.496
0.291
0.10
2.05
0.33
0.18
0.100
0.020
0.013
2.55
0.51
0.33
C
D
E
E
0.512 12.60 13.00
0.299 7.40 7.60
1.27 Basic
0.419 10.00 10.65
H
e
0.050 Basic
H
h
0.394
0.010
0.016
0×
0.029
0.050
8×
0.25
0.40
0×
0.75
1.27
8×
L
a
1
2
h x 45o
D
A
A1
α
C
L
e
B
Ordering Information
Part / Order Number
Marking
Shipping
Package
Temperature
packaging
MK2049-11SI
MK2049-11SI
MK2049-11SI
Tubes
20 pin SOIC
20 pin SOIC
-40 to +85° C
-40 to +85° C
MK2049-11SITR
Tape and Reel
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS)
assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would
result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial
applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary
environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any
circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or
critical medical instruments.
MDS 2049-11 C
13
Revision 021402
Integrated Circuit Systems, Inc. ● 525 Race Street San Jose, CA 95126 ● tel (408) 295-9800 ● www.icst.com
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