MK74CG117AFTR [IDT]

Clock Generator, CMOS, PDSO48;


型号：	MK74CG117AFTR
厂家：	INTEGRATED DEVICE TECHNOLOGY
描述：	Clock Generator, CMOS, PDSO48 光电二极管外围集成电路
文件：	总8页 (文件大小：197K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

DATASHEET

16 OUTPUT LOW SKEW CLOCK GENERATOR

MK74CG117A

Description

Features

The MK74CG117A is a monolithic CMOS high-speed,

low-skew clock driver that includes an on-chip PLL. Ideal for

communications and other systems that require a large

number of high-speed clocks, the unique combination of

PLL and 16 low-skew outputs can eliminate oscillators and

low-skew buffers from systems.

• 48-pin SSOP (300 mil) package

• On-chip PLL generates output clocks up to 90 MHz from

a simple crystal or clock input

• 16 low-skew outputs

• Output skew less than 350 ps on rising edges

• Ability to configure as

The device has a number of built-in multipliers, making it

possible to run from one inexpensive, low-frequency

crystal, and produce high-frequency clock outputs. Another

selection allows the chip to run as a divider, dividing the

input clock by two (or 4 using the mode select).

– 16 clocks at full-frequency

– 12 at full and 4 at half-frequency

– 8 at full and 8 at half-frequency

The device also has a buffered reference output, allowing

multiple devices to be easily driven from one clock source.

• Tri-state mode for Output Enable function

• 3.3 V 5ꢀ supply voltage

Block Diagram

VDD

Clock 1

Clock 2

S2:0

Clock

Synthesis

and Mode

Select

M1:0

Circuitry

Clock 16

REF

X1/ICLK

Crystal or

clock input

Crystal

Ocsillator

The crystal requires external capacitors for

accurate tuning of the clock

GND

IDT™ / ICS™ 16 OUTPUT LOW SKEW CLOCK GENERATOR

MK74CG117A REV F 082704

MK74CG117A

16 OUTPUT LOW SKEW CLOCK GENERATOR

CLOCK SYNTHESIZER

Pin Assignment

VDD

X1/ICLK

CLK16

VDD

GND

CLK15

CLK14

GND

REF

GND

CLK1

CLK2

VDD

CLK3

CLK4

GND

CLK13

CLK12

VDD

CLK11

CLK10

CLK9

VDD

GND

CLK8

CLK7

CLK5

CLK6

VDD

48-pin (300 mil) SSOP

IDT™ / ICS™ 16 OUTPUT LOW SKEW CLOCK GENERATOR

MK74CG117A REV F 082704

MK74CG117A

16 OUTPUT LOW SKEW CLOCK GENERATOR

CLOCK SYNTHESIZER

Pin Descriptions

Pin Number

Pin Name Pin Type

Pin Description

1, 15, 16, 24, 30, 35, 36, 45, 46

VDD

X1/ICLK

Power Connect to VDD.

Connect to a crystal input or clock.

Connect to a crystal or leave unconnected for clock

input.

4, 5, 21, 29, 44

6, 7, 11, 12, 19, 20, 27, 28, 40, 41

8, 10, 48

GND

—

No connect. Nothing is connected to these pins.

Power Connect to ground.

S2, S1, S0

REF

Input

Multiplier select pins. See table 2.

Output Crystal oscillator buffered reference clock output.

Output Clock 1-4. Can be either full or half-speed per Table 1.

13, 14, 17, 18

CLK1 - 4

22, 23, 25, 26, 31, 32, 33, 37

CLK5 - 12 Output Clock outputs 5-12. At full (1x) speed unless tri-stated

per Table 1.

34, 39

M0, M1

Input

Mode Select pins. Selects tri-state or speed of outputs

per Table 1.

38, 42, 43, 47

CLK13 - 16 Output Clock 13-16. Can be either full or half-speed per Table

3) An optimum layout is one with all components on the

same side of the board, thus minimizing vias through other

External Components

signal layers. Other signal traces should be routed away

from the MK74CG117A device. This includes signal traces

located underneath the device, or on layers adjacent to the

ground plane layer used by the device.

The MK74CG117A requires a minimum number of external

components for proper operation.

Decoupling Capacitor

A decoupling capacitor of 0.1µF must be connected

between each VDD and GND. Connect the capacitor as

close to these pins as possible. For optimum device

performance, mount the decoupling capacitor on the

component side of the PCB. Avoid the use of vias in the

decoupling circuit.

Crystal Information

The crystal used should be a fundamental mode (do not use

third overtone), parallel resonant crystal. The oscillator has

internal caps that provide the proper load for a crystal with

C = 18 pF. The value of these capacitors is given by the

following equation:

PCB Layout Recommendations

For optimum device performance and lowest output phase

noise, observe the following guidelines:

Crystal caps (pF) = (C - 18) x 2

1) Mount the 0.01µF decoupling capacitor on the

component side of the board as close to the VDD pin as

possible. No vias should be used between the decoupling

capacitor and VDD pin. The PCB trace to the VDD pin and

the PCB trace to the ground via should be kept as short as

possible.

2) To minimize EMI, place the 33Ω series-termination

resistor (if needed) close to the clock output.

IDT™ / ICS™ 16 OUTPUT LOW SKEW CLOCK GENERATOR

MK74CG117A REV F 082704

MK74CG117A

16 OUTPUT LOW SKEW CLOCK GENERATOR

CLOCK SYNTHESIZER

Power Dissipation, Termination, and Operating

Frequency

Table 2. Multiplier Selections (Input and CLK

Frequencies in MHz)

As with all clock drivers, the power dissipated by the

MK74CG117A is affected by the external loading on the

output pins. This consists of the capacitance of the load that

is being driven, as well as the PC board trace itself. Since

this capacitance must be charged and discharged with each

cycle of the output clock, as the frequency goes up, so does

the power required. Operating below the specified

maximum output clock frequency shown in Table 2 will keep

the MK74CG117A power dissipation within acceptable

limits.

S2 S1 S0 Input Multiplier CLK Out Comments

33–50

0.5

16.5–25

Divider

only; no

PLL

20–50

16–40

10–45

8–36

1.25

20–50

20–90

26.7–90

32–90

40–90

PLL

2.5

3.333

8–27

8–22.5

8–18

External series termination resistors must be used in series

with each output. These resistors serve two purposes: The

first is to match the source impedance to the line (PC board

trace) that is being driven. This will minimize reflections that

cause non-linear transitions on the output clock waveform.

The output impedance of the MK74CG117A is

Figure 1. External Termination

approximately 20Ω; assuming a 50Ω line, then a 33Ω

resistor should be used at each output as shown in Figure 1.

33 ohm

MK74CG117

Output

To load

Table 1. Tri-state and Mode Select

M1 M0

Mode

Max

CLK(1x) CLK/2(0.5x) Output

Freq.

As speeds rise, the limiting factor in device operation

becomes the power generated by having a large number of

drivers in one package. Using the external termination

resistors reduces the power dissipated within the device,

allowing output frequencies up to 100 MHz.

Alloutputs,

including

REF,

tri-stated

12 @ 1x,

4 @ 0.5x

CLK1–12

CLK5–12

CLK13–16 83.3 MHz

0.8

Note that the maximum operating frequency of the

MK74CG117A is determined by the Mode selected from

Table 1 and the Multiplier selected from Table 2. For output

frequencies above 83.3 MHz, all 16 outputs must be at the

same frequency (M1=M0=1).

8 @ 1x,

8 @ 0.5x

CLK1–4,

13–16

83.3 MHz

1.25

16 outputs CLK1–16

@ 1x

None

90 MHz

When operating with a combination of 1X and 0.5X outputs,

the output frequency cannot exceed 83.3 MHz.

IDT™ / ICS™ 16 OUTPUT LOW SKEW CLOCK GENERATOR

MK74CG117A REV F 082704

MK74CG117A

16 OUTPUT LOW SKEW CLOCK GENERATOR

CLOCK SYNTHESIZER

Absolute Maximum Ratings

Stresses above the ratings listed below can cause permanent damage to the MK74CG117A. These ratings, which

are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of the device, at

these or any other conditions, above those indicated in the operational sections of the specifications is not implied.

Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical

parameters are guaranteed only over the recommended operating temperature range.

Item

Supply Voltage, VDD (referenced to GND)

All Inputs and Outputs (referenced to GND)

Ambient Operating Temperature

Storage Temperature

Rating

7 V

0.5 V to VDD+0.5 V

0 to +70°C

-65 to +150°C

125°C

Junction Temperature

Soldering Temperature

260°C

Recommended Operation Conditions

Parameter

Min.

Typ.

Max.

+70

Units

°C

Ambient Operating Temperature

Power Supply Voltage (measured in respect to GND)

+3.14

3.47

DC Electrical Characteristics

Unless stated otherwise, VDD = 3.3 V ±±%, Ambient Temperature 0 to +70°C

Parameter

Symbol

VDD

Conditions

Min.

Typ.

3.3

Max.

Units

Operating Voltage

3.14

3.47

Supply Current (at 50

MHz)

IDD

No load

pin 2

Input High Voltage,

ICLK

VDD-1

VDD/2

Input Low Voltage,

ICLK

pin 2

Output High Voltage

= -8 mA

VDD-0.4

2.0

= -12 mA

= 12 mA

Output Low Voltage,

3.3 V

0.4

Short Circuit Current

Input Capacitance

Each output

S0, S1, FRSEL pins

IDT™ / ICS™ 16 OUTPUT LOW SKEW CLOCK GENERATOR

MK74CG117A REV F 082704

MK74CG117A

16 OUTPUT LOW SKEW CLOCK GENERATOR

CLOCK SYNTHESIZER

AC Electrical Characteristics

Unless stated otherwise, VDD = 3.3 V ±±%, Ambient Temperature 0 to +70° C, C = 15 pF

Parameter

Input Clock Frequency

Input Crystal Frequency

Symbol

Conditions

Min.

Typ. Max. Units

See table 2

Except when S2=S1=1

M1=M0=1

MHz

Output Clock Frequency (see

tables 1, 2)

Output Clock Duty Cycle

At VDD/2

ꢀ

Output Clock Rising Edge Skew

VDD=3.3 V, Note 2

VDD=3.3 V

200

300

350

Absolute Clock Period Jitter,

except REF

Absolute Clock Period Jitter, REF

Output Clock Rise Time

VDD=3.3 V

500

1.5

0.8 to 2.0 V, Note 1

2.0 V to 0.8 V, Note 1

100 MHz output clock

83.3 MHz output clock

Output Clock Fall Time

1.5

Maximum Load per Total of 16

Outputs, with 33 Ω termination,

Note 3

240

320

Note 1: Based upon characterization data with a 33 Ω series termination resistor and 15 pF capacitor to ground.

Note 2: Between any two outputs with equal loading.

Note 3: Additional load may be driven with the addition of an external heat sink. Contact ICS for details.

Thermal Characteristics for 48-pin SSOP

Parameter

Symbol

Conditions

Min.

Typ. Max. Units

Thermal Resistance Junction to Ambient

Still air

°C/W

1 m/s air flow

3 m/s air flow

Thermal Resistance Junction to Case

IDT™ / ICS™ 16 OUTPUT LOW SKEW CLOCK GENERATOR

MK74CG117A REV F 082704

MK74CG117A

16 OUTPUT LOW SKEW CLOCK GENERATOR

CLOCK SYNTHESIZER

Package Outline and Package Dimensions (48-pin SSOP, 300 Mil. Body)

Package dimensions are kept current with JEDEC Publication No. 95

Millimeters

Inches

Min

Symbol

Min

2.41

0.20

0.13

15.75

10.03

7.40

Max

2.80

0.40

0.34

0.25

16.00

10.68

7.60

Max

.110

.016

.0135

.010

.630

.420

.299

.095

.008

.005

.620

.395

.291

INDEX

AREA

1 2

0.635 BASIC

0.025 BASIC

0.38

0.50

0°

0.64

1.02

8°

.015

.020

0°

.025

.040

8°

- C -

SEATING

PLANE

aaa C

Ordering Information

Part / Order Number

Marking

MK74CG117A

Shipping Packaging

Tubes

Package

48-pin SSOP

Temperature

0 to +70° C

MK74CG117AF

MK74CG117AFT

MK74CG117A

Tape and Reel

48-pin SSOP

0 to +70° C

While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Inc. (ICS) assumes

no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No

other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications

such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not

recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS

does not authorize or warrant any ICS product for use in life support devices or critical medical instruments.

IDT™ / ICS™ 16 OUTPUT LOW SKEW CLOCK GENERATOR

MK74CG117A REV F 082704

MK74CG117A

16 OUTPUT LOW SKEW CLOCK GENERATOR

CLOCK SYNTHESIZER

Innovate with IDT and accelerate your future networks. Contact:

www.IDT.com

For Sales

800-345-7015

408-284-8200

Fax: 408-284-2775

For Tech Support

Corporate Headquarters

Integrated Device Technology, Inc.

6024 Silver Creek Valley Road

San Jose, CA 95138

Asia Pacific and Japan

Integrated Device Technology

Singapore (1997) Pte. Ltd.

Reg. No. 199707558G

435 Orchard Road

Europe

IDT Europe, Limited

Prime House

Barnett Wood Lane

Leatherhead, Surrey

United Kingdom KT22 7DE

+44 1372 363 339

United States

800 345 7015

#20-03 Wisma Atria

+408 284 8200 (outside U.S.)

Singapore 238877

+65 6 887 5505

Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered

trademarks used to identify products or services of their respective owners.

Printed in USA

MK74CG117AFTR [IDT]

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