MK74CG117BFILFT [IDT]
Clock Generator, 100MHz, CMOS, PDSO48, 0.300 INCH, SSOP-48;型号: | MK74CG117BFILFT |
厂家: | INTEGRATED DEVICE TECHNOLOGY |
描述: | Clock Generator, 100MHz, CMOS, PDSO48, 0.300 INCH, SSOP-48 时钟 光电二极管 外围集成电路 晶体 |
文件: | 总8页 (文件大小:197K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
DATASHEET
16 OUTPUT LOW SKEW CLOCK GENERATOR
MK74CG117B
Description
Features
The MK74CG117B is a monolithic CMOS high speed,
low-skew clock driver that includes an on-chip PLL. Ideal for
communications and other systems that require a large
number of high-speed clocks, the unique combination of
PLL and 16 low-skew outputs can eliminate oscillators and
low skew buffers from systems.
• 48-pin SSOP (300 mil) package, Pb free
• On-chip PLL generates output clocks up to 100 MHz from
a simple crystal or clock input
• 16 low-skew outputs
• Output skew less than 250 ps on rising edges
• Ability to configure as:
The device has a number of built in multipliers, making it
possible to run from one inexpensive, low frequency crystal,
and produce high frequency clock outputs. Another
selection allows the chip to run as a divider, dividing the
input clock by two (or 4 using the mode select).
– 16 clocks at full frequency
– 12 at full and 4 at half frequency
– 8 at full and 8 at half frequency
The device also has a buffered reference output, allowing
multiple devices to be easily driven from one clock source.
• Tri-state mode for Output Enable function
• 3.3 V 5ꢀ supply voltage
• Industrial temperature version available
Block Diagram
VDD
9
3
Clock 1
Clock 2
S2:0
Clock
Synthesis
and Mode
Select
2
M1:0
Circuitry
Clock 16
REF
X1/ICLK
Crystal or
clock input
Crystal
Ocsillator
X2
10
The crystal requires external capacitors for
accurate tuning of the clock
GND
IDT™ 16 OUTPUT LOW SKEW CLOCK GENERATOR
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MK74CG117B
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MK74CG117B
16 OUTPUT LOW SKEW CLOCK GENERATOR
CLOCK SYNTHESIZER
Pin Assignment
VDD
X1/ICLK
X2
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1
S0
2
CLK16
VDD
VDD
NC
3
NC
4
NC
5
GND
GND
S2
6
CLK15
CLK14
GND
GND
M1
7
8
REF
S1
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
GND
GND
CLK1
CLK2
VDD
VDD
CLK3
CLK4
GND
GND
NC
CLK13
CLK12
VDD
VDD
M0
CLK11
CLK10
CLK9
VDD
NC
GND
GND
CLK8
CLK7
CLK5
CLK6
VDD
48-pin (300 mil) SSOP
IDT™ 16 OUTPUT LOW SKEW CLOCK GENERATOR
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MK74CG117B
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MK74CG117B
16 OUTPUT LOW SKEW CLOCK GENERATOR
CLOCK SYNTHESIZER
Pin Descriptions
Pin
Pin
Pin Type
Pin Description
Number
Name
1, 15, 16, 24, 30, 35, 36, 45, 46
VDD
X1/ICLK
X2
Power Connect to VDD.
2
3
XI
Connect to a crystal input or clock.
XO
Connect to a crystal, or leave unconnected for clock
input.
4, 5, 21, 29, 44
NC
—
No connect. Nothing is connected to these pins.
6, 7, 11, 12, 19, 20, 27, 28, 40, 41
GND
Power Connect to ground.
8, 10, 48
9
S2, S1, S0
REF
Input
Multiplier select pins. See table 2.
Output Crystal oscillator buffered reference clock output.
13, 14, 17, 18
CLK1 - 4
Output Clock 1 - 4. Can be either full or half speed per Table
1.
22, 23, 25, 26, 31, 32, 33, 37
34, 39
CLK5 - 12
M0, M1
Output Clock outputs 5 - 12. At full (1x) speed unless
tristated per Table 1.
Input
Mode Select pins. Selects tri-state or speed of
outputs per Table 1.
38, 42, 43, 47
CLK13 - 16 Output Clock 13 - 16. Can be either full or half speed per
Table 1.
2) To minimize EMI, place the 33Ω series-termination
resistor (if needed) close to the clock output.
External Components
The MK74CG117B requires a minimum number of external
components for proper operation.
3) An optimum layout is one with all components on the
same side of the board, thus minimizing vias through other
signal layers. Other signal traces should be routed away
from the MK74CG117B device. This includes signal traces
located underneath the device, or on layers adjacent to the
ground plane layer used by the device.
Decoupling Capacitor
A decoupling capacitor of 0.1µF must be connected
between each VDD and GND. Connect the capacitor as
close to these pins as possible. For optimum device
performance, mount the decoupling capacitor on the
component side of the PCB. Avoid the use of vias in the
decoupling circuit.
Crystal Information
The crystal used should be a fundamental mode (do not use
third overtone), parallel resonant crystal. The oscillator has
internal caps that provide the proper load for a crystal with
PCB Layout Recommendations
For optimum device performance and lowest output phase
noise, observe the following guidelines:
C = 18 pF. The value of these capacitors is given by the
L
following equation:
Crystal caps (pF) = (C - 18) x 2
L
1) Mount the 0.01µF decoupling capacitor on the
component side of the board as close to the VDD pin as
possible. No vias should be used between the decoupling
capacitor and VDD pin. The PCB trace to the VDD pin and
the PCB trace to the ground via should be kept as short as
possible.
IDT™ 16 OUTPUT LOW SKEW CLOCK GENERATOR
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16 OUTPUT LOW SKEW CLOCK GENERATOR
CLOCK SYNTHESIZER
Power Dissipation, Termination, and Operating
Frequency
Table 2. Multiplier Selections (Input and CLK
Frequencies in MHz)
As with all clock drivers, the power dissipated by the
MK74CG117B is affected by the external loading on the
output pins. This consists of the capacitance of the load that
is being driven, as well as the PC board trace itself. Since
this capacitance must be charged and discharged with each
cycle of the output clock, as the frequency goes up. so does
the power required. Operating below the specified
maximum output clock frequency shown in Table 2 will keep
the MK74CG117B power dissipation within acceptable
limits.
S2 S1 S0 Input Multiplier CLK Out Comments
0
0
0
33–50
0.5
16.5–25
Divider
only; no
PLL
0
0
0
1
1
1
1
0
1
1
0
0
1
1
1
0
1
0
1
0
1
20–50
16–40
10–50
8–40
1
1.25
2
20–50
20–50
PLL
PLL
PLL
PLL
PLL
PLL
PLL
20–100
20–100
26.7–100
32–100
40–90
2.5
3.333
4
8–30
8–25
External series termination resistors must be used in series
with each output. These resistors serve two purposes: The
first is to match the source impedance to the line (PC board
trace) that is being driven. This will minimize reflections that
cause non-linear transitions on the output clock waveform.
The output impedance of the MK74CG117B is
8–20
5
Figure 1. External Termination
approximately 20Ω; assuming a 50Ω line, then a 33Ω
resistor should be used at each output as shown in Figure 1.
33 ohm
MK74CG117
Output
To load
Table 1. Tri-state and Mode Select
M1 M0
Mode
at
at
Max
CLK(1x) CLK/2(0.5x) Output
Freq.
As speeds rise, the limiting factor in device operation
becomes the power generated by having a large number of
drivers in one package. Using the external termination
resistors reduces the power dissipated within the device,
allowing output frequencies up to 100 MHz.
0
0
Alloutputs,
including
REF,
Z
Z
tri-stated
0
1
1
1
0
1
12 @ 1x,
4 @ 0.5x
CLK1–12
CLK5–12
CLK13–16 83.3 MHz
0.8
Note that the maximum operating frequency of the
MK74CG117A is determined by the Mode selected from
Table 1 and the Multiplier selected from Table 2. For output
frequencies above 83.3 MHz, all 16 outputs must be at the
same frequency (M1=M0=1).
8 @ 1x,
8 @ 0.5x
CLK1–4,
13–16
83.3 MHz
1.25
16 outputs CLK1–16
@ 1x
None
100 MHz
When operating with a combination of 1X and 0.5X outputs,
the output frequency cannot exceed 83.3 MHz.
IDT™ 16 OUTPUT LOW SKEW CLOCK GENERATOR
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MK74CG117B
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16 OUTPUT LOW SKEW CLOCK GENERATOR
CLOCK SYNTHESIZER
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the MK74CG117B. These ratings, which
are standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device, at
these or any other conditions, above those indicated in the operational sections of the specifications is not implied.
Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical
parameters are guaranteed only over the recommended operating temperature range.
Item
Supply Voltage, VDD (referenced to GND)
All Inputs and Outputs (referenced to GND)
Ambient Operating Temperature
Storage Temperature
Rating
7 V
0.5 V to VDD+0.5 V
-40 to +85° C
-65 to +150° C
125°C
Junction Temperature
Soldering Temperature
260°C
Recommended Operation Conditions
Parameter
Min.
Typ.
Max.
+85
Units
° C
Ambient Operating Temperature
Power Supply Voltage (measured in respect to GND)
-40
+3.0
3.63
V
DC Electrical Characteristics
Unless stated otherwise, VDD = 3.3 V 10%, Ambient Temperature -40 to +85°C
Parameter
Symbol
VDD
Conditions
Min.
Typ.
3.3
Max.
Units
V
Operating Voltage
3.14
3.47
Supply Current (at 50
MHz)
IDD
No load
pin 2
63
mA
Input High Voltage,
ICLK
V
VDD-1
VDD/2
VDD/2
V
V
IH
Input Low Voltage,
ICLK
V
pin 2
1
IL
Output High Voltage
Output High Voltage
V
V
I
= -8 mA
OH
VDD-0.4
2.0
V
V
V
OH
I
I
= -12 mA
= 12 mA
OH
OH
OL
Output Low Voltage,
3.3 V
V
0.4
6
OL
Short Circuit Current
Input Capacitance
Each output
35
7
mA
pF
C
S0, S1, FRSEL pins
IN
IDT™ 16 OUTPUT LOW SKEW CLOCK GENERATOR
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MK74CG117B
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MK74CG117B
16 OUTPUT LOW SKEW CLOCK GENERATOR
CLOCK SYNTHESIZER
AC Electrical Characteristics
Unless stated otherwise, VDD = 3.3 V 10%, Ambient Temperature 0 to +85° C, C = 15 pF
L
Parameter
Input Clock Frequency
Input Crystal Frequency
Symbol
Conditions
Min.
Typ. Max. Units
See table 2
Except when S2=S1=1
M1=M0=1
8
20
MHz
MHz
Output Clock Frequency (see
tables 1, 2)
100
Output Clock Duty Cycle
At VDD/2
45
50
55
ꢀ
ps
ps
Output Clock Rising Edge Skew
VDD=3.3 V, Note 2
VDD=3.3 V
150
300
250
Absolute Clock Period Jitter,
except REF
Absolute Clock Period Jitter, REF
Output Clock Rise Time
VDD=3.3 V
500
1.5
ps
ns
ns
pF
pF
t
0.8 to 2.0 V, Note 1
2.0 V to 0.8 V, Note 1
100 MHz output clock
83.3 MHz output clock
2
R
Output Clock Fall Time
t
1.5
2
F
Maximum Load per Total of 16
Outputs, with 33 Ω termination,
Note 3
240
320
Note 1: Based upon characterization data with a 33 Ω series termination resistor and 15 pF capacitor to ground.
Note 2: Between any two outputs with equal loading.
Note 3: Additional load may be driven with the addition of an external heat sink. Contact IDT for details.
Thermal Characteristics for 48-pin SSOP
Parameter
Symbol
Conditions
Min.
Typ. Max. Units
Thermal Resistance Junction to Ambient
θ
Still air
80
67
54
45
° C/W
° C/W
° C/W
° C/W
JA
θ
1 m/s air flow
3 m/s air flow
JA
θ
JA
Thermal Resistance Junction to Case
θ
JC
IDT™ 16 OUTPUT LOW SKEW CLOCK GENERATOR
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MK74CG117B
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MK74CG117B
16 OUTPUT LOW SKEW CLOCK GENERATOR
CLOCK SYNTHESIZER
Package Outline and Package Dimensions (48-pin SSOP, 300 Mil. Body)
Package dimensions are kept current with JEDEC Publication No. 95
48
Millimeters
Inches
Min
Symbol
Min
2.41
0.20
0.20
0.13
15.75
10.03
7.40
Max
2.80
0.40
0.34
0.25
16.00
10.68
7.60
Max
.110
.016
.0135
.010
.630
.420
.299
A
A1
b
.095
.008
.008
.005
.620
.395
.291
E1
E
INDEX
AREA
c
D
E
1 2
E1
e
0.635 BASIC
0.025 BASIC
D
h
L
0.38
0.50
0°
0.64
1.02
8°
.015
.020
0°
.025
.040
8°
α
A
A2
A1
c
- C -
e
SEATING
PLANE
b
L
aaa C
Ordering Information
Part / Order Number
Marking
Shipping Packaging
Tubes
Package
Temperature
0 to +70° C
0 to +70° C
-40 to +85° C
-40 to +85° C
MK74CG117BFLF
MK74CG117BFLFT
MK74CG117BFILF
MK74CG117BFILFT
74CG117BFLF
74CG117BFLF
74CG117BFILF
74CG117BFILF
48-pin SSOP
48-pin SSOP
48-pin SSOP
48-pin SSOP
Tape and Reel
Tubes
Tape and Reel
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Inc. (IDT)
assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from
its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other
applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are
not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT
does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
IDT™ 16 OUTPUT LOW SKEW CLOCK GENERATOR
7
MK74CG117B
REV E 122209
MK74CG117B
16 OUTPUT LOW SKEW CLOCK GENERATOR
CLOCK SYNTHESIZER
Innovate with IDT and accelerate your future networks. Contact:
www.IDT.com
For Sales
800-345-7015
408-284-8200
Fax: 408-284-2775
For Tech Support
www.idt.com/go/clockhelp
Corporate Headquarters
Integrated Device Technology, Inc.
www.idt.com
© 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device
Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered
trademarks used to identify products or services of their respective owners.
Printed in USA
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