MPC940LACR2 [IDT]
LOW VOLTAGE 1:18 CLOCK DISTRIBUTION CHIP; 低电压1:18时钟分配芯片
| 型号： | MPC940LACR2 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | LOW VOLTAGE 1:18 CLOCK DISTRIBUTION CHIP |
| 文件： | 总11页 (文件大小：1067K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LOW VOLTAGE 1:18 CLOCK DISTRIBUTION CHIP
MPC940L
The MPC940L is a 1:18 low voltage clock distribution chip with 2.5 V or 3.3 V LVCMOS
output capabilities. The device features the capability to select either a differential
LVPECL or an LVCMOS compatible input. The 18 outputs are 2.5 V or 3.3 V LVCMOS
compatible and feature the drive strength to drive 50 Ω series or parallel terminated
transmission lines. With output-to-output skews of 150 ps, the MPC940L is ideal as a
clock distribution chip for the most demanding of synchronous systems. The 2.5 V outputs
also make the device ideal for supplying clocks for a high performance microprocessor
based design. For a similar device at a lower price/performance point, the reader is
referred to the MPC9109.
MPC940L
LOW VOLTAGE
1:18 CLOCK
DISTRIBUTION CHIP
•
•
•
•
•
•
•
LVPECL or LVCMOS Clock Input
2.5 V LVCMOS Outputs for Pentium II Microprocessor Support
150 ps Maximum Output-to-Output Skew
Maximum Output Frequency of 250 MHz
32-Lead LQFP Packaging
32-Lead Pb-Free Package Available
Dual or Single Supply Device:
FA SUFFIX
32-LEAD LQFP PACKAGE
CASE 873A-04
•
•
•
Dual VCC Supply Voltage, 3.3 V Core and 2.5 V Output
Single 3.3 V VCC Supply Voltage for 3.3 V Outputs
Single 2.5 V VCC Supply Voltage for 2.5 V I/O
With a low output impedance (≈20 Ω), in both the HIGH and LOW logic states, the
AC SUFFIX
32-LEAD LQFP PACKAGE
Pb-FREE PACKAGE
CASE 873A-04
output buffers of the MPC940L are ideal for driving series terminated transmission lines.
With a 20 Ω output impedance the 940L has the capability of driving two series terminated
lines from each output. This gives the device an effective fanout of 1:36. If a lower output
impedance is desired please see the MPC942 data sheet.
The differential LVPECL inputs of the MPC940L allow the device to interface directly
with a LVPECL fanout buffer like the MC100EP111 to build very wide clock fanout trees
or to couple to a high frequency clock source. The LVCMOS input provides a more standard interface for applications requiring only a
single clock distribution chip at relatively low frequencies. In addition, the two clock sources can be used to provide for a test clock
interface as well as the primary system clock. A logic HIGH on the LVCMOS_CLK_SEL pin will select the LVCMOS level clock input. All
inputs of the MPC940L have internal pullup/pulldown resistors so they can be left open if unused.
The MPC940L is a single or dual supply device. The device power supply offers a high degree of flexibility. The device can operate
with a 3.3 V core and 3.3 V output, a 3.3 V core and 2.5 V outputs as well as a 2.5 V core and 2.5 V outputs. The 32-lead LQFP package
was chosen to optimize performance, board space and cost of the device. The 32-lead LQFP has a 7x7 mm body size with a conservative
0.8 mm pin spacing.
Pentium II is a trademark of Intel Corporation.
IDT™ / ICS™ 1:18 CLOCK DISTRIBUTION CHIP
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MPC940L REV 7 JUNE 5, 2007
MPC940L
LOW VOLTAGE 1:18 CLOCK DISTRIBUTION CHIP
LOGIC DIAGRAM
PECL_CLK
0
1
PECL_CLK
Q0
LVCMOS_CLK
16
Q1–Q16
Q17
LVCMOS_CLK_SEL
(Internal Pulldown)
Pinout: 32-Lead LQFP (Top View)
24 23 22 21 20 19 18 17
GNDO
Q5
25
26
27
28
29
30
31
32
16
15
14
13
12
11
10
9
VCCO
Q12
FUNCTION TABLE
LVCMOS_CLK_SEL
Input
0
1
PECL_CLK
LVCMOS_CLK
Q4
Q13
Q3
Q14
MPC940L
VCCO
Q2
GNDO
Q15
POWER SUPPLY VOLTAGES
Supply Pin
Voltage Level
VCCI
VCCO
2.5 V or 3.3 V ± 5%
2.5 V or 3.3 V ± 5%
Q1
Q16
Q0
Q17
1
2
3
4
5
6
7
8
Table 1. Pin Configurations
Pin
PECL_CLK
PECL_CLK
LVCMOS_CLK
LVCMOS_CLK_SEL
Q0–Q17
I/O
Type
Function
Input
LVPECL
Reference Clock Input
Input
Input
LVCMOS
LVCMOS
LVCMOS
Supply
Alternative Reference Clock Input
Selects Clock Source
Output
Clock Outputs
VCCO
Output Positive Power Supply
Core Positive Power Supply
Output Negative Power Supply
Core Negative Power Supply
VCCI
Supply
GNDO
Supply
GNDI
Supply
IDT™ / ICS™ 1:18 CLOCK DISTRIBUTION CHIP
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MPC940L REV 7 JUNE 5, 2007
MPC940L
LOW VOLTAGE 1:18 CLOCK DISTRIBUTION CHIP
Table 2. Absolute Maximum Ratings(1)
Symbol
VCC
VI
Parameter
Min
–0.3
–0.3
Max
3.6
Unit
V
Supply Voltage
Input Voltage
Input Current
VDD + 0.3
±20
V
IIN
mA
°C
TStor
Storage Temperature Range
–40
125
1. Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or
conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute-maximum-rated conditions is
not implied.
Table 3. DC Characteristics (TA = 0° to 70°C, VCCI = 3.3 V ±5%; VCCO = 3.3 V ±5%)
Symbol
VIH
Characteristic
Input HIGH Voltage
Min
Typ
Max
VCCI
Unit
V
Condition
CMOS_CLK
CMOS_CLK
PECL_CLK
PECL_CLK
2.4
VIL
Input LOW Voltage
0.8
V
VPP
VCMR
VOH
VOL
IIN
Peak-to-Peak Input Voltage
Common Mode Range
Output HIGH Voltage
Output LOW Voltage
Input Current
500
VCCI – 1.4
2.4
1000
mV
V
VCCI – 0.6
V
IOH = –20 mA
IOL = 20 mA
0.5
V
±200
µA
pF
pF
Ω
CIN
Input Capacitance
4.0
10
Cpd
Power Dissipation Capacitance
Output Impedance
per output
ZOUT
ICC
18
23
28
Maximum Quiescent Supply Current
0.5
1.0
mA
Table 4. AC Characteristics (TA = 0° to 70°C, VCCI = 3.3 V ±5%; VCCO = 3.3 V ±5%)
Symbol
Fmax
Characteristic
Maximum Input Frequency
Min
Typ
Max
Unit
MHz
ns
Condition
250
tPLH
Propagation Delay
Propagation Delay
Output-to-Output Skew
Part-to-Part Skew
Part-to-Part Skew
Part-to-Part Skew
Output Duty Cycle
Output Rise/Fall Time
PECL_CLK ≤ 150 MHz
2.0
1.8
2.7
2.5
3.4
3.0
CMOS_CLK ≤ 150 MHz
tPLH
tsk(o)
tsk(pp)
tsk(pp)
tsk(pp)
DC
PECL_CLK > 150 MHz
CMOS_CLK > 150 MHz
2.0
1.8
2.9
2.4
3.7
3.2
ns
ps
ns
ns
ps
PECL_CLK
CMOS_CLK
150
150
PECL_CLK ≤ 150 MHz
CMOS_CLK ≤ 150 MHz
1.4
1.2
Note (1)
Note (1)
Note (2)
PECL_CLK > 150 MHz
CMOS_CLK > 150 MHz
1.7
1.4
PECL_CLK
CMOS_CLK
850
750
fCLK < 134 MHz
f
45
40
50
50
55
60
%
%
Input DC = 50%
Input DC = 50%
CLK ≤ 250 MHz
tr, tf
0.3
1.1
ns
0.5 – 2.4 V
1. Across temperature and voltage ranges. Includes output skew.
2. For specific temperature and voltage. Includes output skew.
IDT™ / ICS™ 1:18 CLOCK DISTRIBUTION CHIP
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MPC940L REV 7 JUNE 5, 2007
MPC940L
LOW VOLTAGE 1:18 CLOCK DISTRIBUTION CHIP
Table 5. DC Characteristics (TA = 0° to 70°C, VCCI = 3.3 V ±5%; VCCO = 2.5 V ±5%)
Symbol
VIH
Characteristic
Input HIGH Voltage
Min
Typ
Max
VCCI
Unit
V
Condition
CMOS_CLK
CMOS_CLK
PECL_CLK
PECL_CLK
2.4
VIL
Input LOW Voltage
0.8
V
VPP
VCMR
VOH
VOL
IIN
Peak-to-Peak Input Voltage
Common Mode Range
Output HIGH Voltage
Output LOW Voltage
Input Current
500
VCCI – 1.4
1.8
1000
mV
V
VCCI – 0.6
V
IOH = –12 mA
IOL = 12 mA
0.5
V
±200
µA
pF
pF
Ω
CIN
Input Capacitance
4.0
10
Cpd
Power Dissipation Capacitance
Output Impedance
per output
ZOUT
ICC
23
Maximum Quiescent Supply Current
0.5
1.0
mA
Table 6. AC Characteristics (TA = 0° to 70°C, VCCI = 3.3 V ±5%; VCCO = 2.5 V ±5%)
Symbol
Fmax
Characteristic
Maximum Input Frequency
Min
Typ
Max
Unit
MHz
ns
Condition
250
tPLH
Propagation Delay
Propagation Delay
Output-to-Output Skew
Part-to-Part Skew
Part-to-Part Skew
Part-to-Part Skew
Output Duty Cycle
Output Rise/Fall Time
PECL_CLK ≤ 150 MHz
2.0
1.7
2.8
2.5
3.5
3.0
CMOS_CLK ≤ 150 MHz
tPLH
tsk(o)
tsk(pp)
tsk(pp)
tsk(pp)
DC
PECL_CLK > 150 MHz
CMOS_CLK > 150 MHz
2.0
1.8
2.9
2.5
3.8
3.3
ns
ps
ns
ns
ps
PECL_CLK
CMOS_CLK
150
150
PECL_CLK ≤ 150 MHz
CMOS_CLK ≤ 150 MHz
1.5
1.3
Note (1)
Note (1)
Note (2)
PECL_CLK > 150 MHz
CMOS_CLK > 150 MHz
1.8
1.5
PECL_CLK
CMOS_CLK
850
750
fCLK < 134 MHz
f
45
40
50
50
55
60
%
%
Input DC = 50%
Input DC = 50%
CLK ≤ 250 MHz
tr, tf
0.3
1.2
ns
0.5 – 1.8 V
1. Across temperature and voltage ranges. Includes output skew.
2. For specific temperature and voltage. Includes output skew.
IDT™ / ICS™ 1:18 CLOCK DISTRIBUTION CHIP
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MPC940L REV 7 JUNE 5, 2007
MPC940L
LOW VOLTAGE 1:18 CLOCK DISTRIBUTION CHIP
Table 7. DC Characteristics (TA = 0° to 70°C, VCCI = 2.5 V ±5%; VCCO = 2.5 V ±5%)
Symbol
VIH
Characteristic
Input HIGH Voltage
Min
Typ
Max
VCCI
Unit
V
Condition
CMOS_CLK
CMOS_CLK
PECL_CLK
PECL_CLK
2.0
VIL
Input LOW Voltage
0.8
V
VPP
VCMR
VOH
VOL
IIN
Peak-to-Peak Input Voltage
Common Mode Range
Output HIGH Voltage
Output LOW Voltage
Input Current
500
VCCI – 1.0
1.8
1000
mV
V
VCCI – 0.6
V
IOH = –12 mA
IOL = 12 mA
0.5
V
±200
µA
pF
pF
Ω
CIN
Input Capacitance
4.0
10
Cpd
Power Dissipation Capacitance
Output Impedance
per output
ZOUT
ICC
18
23
28
Maximum Quiescent Supply Current
0.5
1.0
mA
Table 8. AC Characteristics (TA = 0° to 70°C, VCCI = 2.5 V ±5%; VCCO = 2.5 V ±5%)
Symbol
Fmax
Characteristic
Maximum Input Frequency
Min
Typ
Max
Unit
MHz
ns
Condition
200
tPLH
Propagation Delay
Propagation Delay
Output-to-Output Skew
Part-to-Part Skew
Part-to-Part Skew
Part-to-Part Skew
Output Duty Cycle
Output Rise/Fall Time
PECL_CLK ≤ 150 MHz
2.6
2.3
4.0
3.1
5.2
4.0
CMOS_CLK ≤ 150 MHz
tPLH
tsk(o)
tsk(pp)
tsk(pp)
tsk(pp)
DC
PECL_CLK > 150 MHz
CMOS_CLK > 150 MHz
2.8
2.3
3.8
3.1
5.0
4.0
ns
ps
ns
ns
ns
PECL_CLK
CMOS_CLK
200
200
PECL_CLK ≤ 150 MHz
CMOS_CLK ≤ 150 MHz
2.6
1.7
Note (1)
Note (1)
Note (2)
PECL_CLK > 150 MHz
CMOS_CLK > 150 MHz
2.2
1.7
PECL_CLK
CMOS_CLK
1.2
1.0
fCLK < 134 MHz
f
45
40
50
50
55
60
%
%
Input DC = 50%
Input DC = 50%
CLK ≤ 200 MHz
tr, tf
0.3
1.2
ns
0.5 - 1.8 V
1. Across temperature and voltage ranges. Includes output skew.
2. For specific temperature and voltage. Includes output skew.
IDT™ / ICS™ 1:18 CLOCK DISTRIBUTION CHIP
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MPC940L REV 7 JUNE 5, 2007
MPC940L
LOW VOLTAGE 1:18 CLOCK DISTRIBUTION CHIP
MPC940L DUT
ZO = 50Ω
ZO = 50Ω
Pulse
Generator
Z = 50Ω
RT = 50Ω
RT = 50Ω
VTT
VTT
Figure 1. LVCMOS_CLK MPC940L AC Test Reference for VCC = 3.3 V and VCC = 2.5 V
MPC940L DUT
ZO = 50Ω
Differential Pulse
Generator
ZO = 50Ω
Z = 50Ω
RT = 50Ω
RT = 50Ω
VTT
VTT
Figure 2. PECL_CLK MPC940L AC Test Reference for VCC = 3.3 V and VCC = 2.5 V
VCC
PCLK_CLK
PCLK_CLK
V
CC ÷ 2
VCMR
LVCMOS_CLK
Q
VPP
GND
VCC
VCC
VCC÷2
V
CC ÷ 2
Q
GND
GND
tPD
tPD
Figure 4. LVCMOS Propagation Delay (tPD
)
Figure 3. Propagation Delay (tPD) Test Reference
Test Reference
VCC
VCC
V
CC ÷ 2
V
CC ÷ 2
GND
GND
VOH
tP
T0
V
CC ÷ 2
GND
DC = tP/T0 x 100%
tSK(O)
The time from the PLL controlled edge to the non controlled
edge, divided by the time between PLL controlled edges,
expressed as a percentage.
The pin-to-pin skew is defined as the worst case difference
in propagation delay between any two similar delay paths
within a single device.
Figure 6. Output-to-Output Skew TSK(O)
Figure 5. Output Duty Cycle (DC)
VCC = 3.3 V VCC = 2.5 V
VCC = 3.3 V VCC = 2.5 V
2.4
1.8 V
0.6 V
2.0
0.8
1.7 V
0.7 V
0.55
tF
tR
tF
tR
Figure 7. Output Transition Time Test Reference
Figure 8. Input Transition Time Test Reference
IDT™ / ICS™ 1:18 CLOCK DISTRIBUTION CHIP
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MPC940L REV 7 JUNE 5, 2007
MPC940L
LOW VOLTAGE 1:18 CLOCK DISTRIBUTION CHIP
PACKAGE DIMENSIONS
CASE 873A-04
ISSUE C
32-LEAD LQFP PACKAGE
IDT™ / ICS™ 1:18 CLOCK DISTRIBUTION CHIP
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MPC940L REV 7 JUNE 5, 2007
MPC940L
LOW VOLTAGE 1:18 CLOCK DISTRIBUTION CHIP
PACKAGE DIMENSIONS
PAGE 2 OF 3
CASE 873A-04
ISSUE C
32-LEAD LQFP PACKAGE
IDT™ / ICS™ 1:18 CLOCK DISTRIBUTION CHIP
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MPC940L REV 7 JUNE 5, 2007
MPC940L
LOW VOLTAGE 1:18 CLOCK DISTRIBUTION CHIP
PACKAGE DIMENSIONS
PAGE 3 OF 3
CASE 873A-04
ISSUE C
32-LEAD LQFP PACKAGE
IDT™ / ICS™ 1:18 CLOCK DISTRIBUTION CHIP
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MPC940L REV 7 JUNE 5, 2007
MPC940L
LOW VOLTAGE 1:18 CLOCK DISTRIBUTION CHIP
Ordering Information
Table 9. Ordering Information
Part/Order Number
MPC940LFA
Marking
MPC940L
Package
Shipping Packaging
Tray
Termperature
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
32 Lead LQFP
MPC940LFAR2
MPC940LAC
MPC940L
32 Lead LQFP
2500 Tape & Reel
Tray
MPC940LAC
MPC940LAC
Lead-Free, 32 Lead LQFP
Lead-Free, 32 Lead LQFP
MPC940LACR2
2500 Tape & Reel
IDT™ / ICS™ 1:18 CLOCK DISTRIBUTION CHIP
10
MPC940L REV 7 JUNE 5, 2007
MPC940L
LOW VOLTAGE 1:18 CLOCK DISTRIBUTION CHIP
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+408 284 8200 (outside U.S.)
+65 6 887 5505
© 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device
Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered
trademarks used to identify products or services of their respective owners.
Printed in USA
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