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MPC962305D-1R2 [IDT]

Low-Cost, 3.3V Zero Delay Buffer; 低成本， 3.3V零延迟缓冲器
MPC962305D-1R2
型号： MPC962305D-1R2
厂家： INTEGRATED DEVICE TECHNOLOGY    INTEGRATED DEVICE TECHNOLOGY
描述：

Low-Cost, 3.3V Zero Delay Buffer
低成本， 3.3V零延迟缓冲器

逻辑集成电路 光电二极管 驱动
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Low-Cost, 3.3V Zero Delay Buffer  
MPC962305  
NRND  
DATASHEET  
NRND – Not Recommend for New Designs  
The MPC962309 is a zero delay buffer designed to distribute high-speed  
clocks. Available in a 16-pin SOIC or TSSOP package, the device accepts one  
reference input and drives nine low-skew clocks. The MPC962305 is the 8-pin  
version of the MPC962309 which drives five outputs with one reference input.  
The -1H versions of these devices have higher drive than the -1 devices and can  
operate up to 100/-133 MHz frequencies. These parts have on-chip PLLs which  
lock to an input clock presented on the REF pin. The PLL feedback is on-chip and  
is obtained from the CLOCKOUT pad.  
MPC962305  
MPC962309  
EF SUFFIX  
8-LEAD SOIC PACKAGE  
Pb-FREE PACKAGE  
CASE 751-06  
Features  
EJ SUFFIX  
8-LEAD TSSOP PACKAGE  
Pb-FREE PACKAGE  
CASE 948J-01  
•
•
•
•
•
•
•
1:5 LVCMOS zero-delay buffer (MPC962305)  
1:9 LVCMOS zero-delay buffer (MPC962309)  
Zero input-output propagation delay  
Multiple low-skew outputs  
EF SUFFIX  
16-LEAD SOIC PACKAGE  
Pb-FREE PACKAGE  
CASE 751B-05  
250 ps max output-output skew  
700 ps max device-device skew  
Supports a clock I/O frequency range of 10 MHz to 133 MHz,  
compatible with CPU and PCI bus frequencies  
•
Low jitter, 200 ps max cycle-cycle, and compatible with Pentium® based  
systems  
•
•
Test Mode to bypass PLL (MPC962309 only. See Table 3)  
EJ SUFFIX  
16-LEAD TSSOP PACKAGE  
Pb-FREE PACKAGE  
CASE 948F-01  
8-pin SOIC or 8-pin TSSOP package (MPC962305);16-pin SOIC or 16-pin  
TSSOP package (MPC962309), all Pb-free  
•
•
•
•
•
Single 3.3 V supply  
Ambient temperature range: –40C to +85C  
Compatible with the CY2305, CY23S05, CY2309, CY23S09  
Spread spectrum compatible  
Not Recommend for New Designs  
Use replacement part IDT2305  
•
The MPC962309 has two banks of four outputs each, which can be controlled by the Select Inputs as shown in Table 3. Bank  
B can be tri-stated if all of the outputs are not required. Select inputs also allow the input clock to be directly applied to the outputs  
for chip and system testing purposes.  
The MPC962305 and MPC962309 PLLs enters a power down state when there are no rising edges on the REF input. During  
this state, all of the outputs are in tristate, the PLL is turned off, and there is less than 25.0 A of current draw for the device. The  
PLL shuts down in one additional case as shown in Table 3.  
Multiple MPC962305 and MPC962309 devices can accept the same input clock and distribute it throughout the system. In this  
situation, the difference between the output skews of two devices will be less than 700 ps.  
All outputs have less than 200 ps of cycle-cycle jitter. The input-to-output propagation delay on both devices is guaranteed to  
be less than 350 ps and the output-to-output skew is guaranteed to be less than 250 ps.  
The MPC962305 and MPC962309 are available in two/three different configurations, as shown on the ordering information  
page. The MPC962305-1/MPC962309-1 are the base parts. High drive versions of those devices, MPC962305-1H and  
MPC962309-1H, are available to provide faster rise and fall times of the base device.  
Pentium II is a trademark of Intel Corporation.  
MPC962305 REVISION 8 JANUARY 8, 2013  
1
©2013 Integrated Device Technology, Inc.  
MPC962305 Data Sheet  
LOW-COST, 3.3V ZERO DELAY BUFFEr  
Block Diagram  
Pin Configuration  
SOIC/TSSOP  
Top View  
CLKOUT  
PLL  
REF  
CLKOUT  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
MUX  
CLKA1  
CLKA2  
VDD  
GND  
CLKB1  
CLKB2  
S2  
CLKA4  
CLKA3  
VDD  
CLKA1  
CLKA2  
CLKA3  
CLKA4  
REF  
GND  
CLKB4  
CLKB3  
S1  
CLKB1  
CLKB2  
CLKB3  
CLKB4  
SOIC/TSSOP  
Top View  
S2  
S1  
Select Input  
Decoding  
REF  
CLKOUT  
1
2
3
4
8
7
6
5
CLK2  
CLK1  
GND  
CLK4  
VDD  
CLK3  
Table 1. Pin Description for MPC962309  
Pin  
Signal  
REF(1)  
Description  
1
Input reference frequency, 5 V-tolerant input  
Buffered clock output, Bank A  
Buffered clock output, Bank A  
3.3 V supply  
2
CLKA1(2)  
CLKA2(2)  
VDD  
3
4
5
GND  
Ground  
6
CLKB1(2)  
CLKB2(2)  
S2(3)  
Buffered clock output, Bank B  
Buffered clock output, Bank B  
Select input, bit 2  
7
8
9
S1(3)  
Select input, bit 1  
10  
CLKB3(2)  
CLKB4(2)  
GND  
Buffered clock output, Bank B  
Buffered clock output, Bank B  
Ground  
11  
12  
13  
VDD  
3.3 V supply  
14  
CLKA3(2)  
CLKA4(2)  
CLKOUT(2)  
Buffered clock output, Bank A  
Buffered clock output, Bank A  
Buffered output, internal feedback on this pin  
15  
16  
1. Weak pull-down.  
2. Weak pull-down on all outputs.  
3. Weak pull-ups on these inputs.  
Table 2. Pin Description for MPC962305  
Pin  
Signal  
REF(1)  
Description  
Input reference frequency, 5 V-tolerant input  
1
2
CLK2(2)  
CLK1(2)  
GND  
Buffered clock output  
Buffered clock output  
Ground  
3
4
5
CLK3(2)  
Buffered clock output  
3.3 V supply  
6
VDD  
7
CLK4(2)  
CLKOUT(2)  
Buffered clock output  
Buffered clock output, internal feedback on this pin  
8
1. Weak pull-down.  
2. Weak pull-down on all outputs.  
MPC962305 REVISION 8 JANUARY 8, 2013  
2
©2013 Integrated Device Technology, Inc.  
MPC962305 Data Sheet  
LOW-COST, 3.3V ZERO DELAY BUFFEr  
Table 3. Select Input Decoding for MPC962309  
CLKOUT(1)  
Driven  
S2  
0
S1  
0
CLOCK A1–A4  
Three-State  
Driven  
CLOCK B1–B4  
Three-State  
Three-State  
Driven  
Output Source  
PLL Shutdown  
PLL  
PLL  
N
N
Y
N
0
1
Driven  
1
0
Driven  
Driven  
Reference  
PLL  
1
1
Driven  
Driven  
Driven  
1. This output is driven and has an internal feedback for the PLL. The load on this output can be adjusted to change the skew between the  
reference and output.  
Table 4. Maximum Ratings  
Characteristics  
Value  
0.5 to +3.9  
0.5 to VDD+0.5  
0.5 to 5.5  
65 to +150  
150  
Unit  
V
Supply Voltage to Ground Potential  
DC Input Voltage (Except Ref)  
DC Input Voltage REF  
V
V
Storage Temperature  
C  
C  
V
Junction Temperature  
Static Discharge Voltage (per MIL-STD-883, Method 3015)  
>2000  
Table 5. Operating Conditions for MPC962305-X and MPC962309-X Industrial Temperature Devices  
Parameter  
Description  
Min  
3.0  
Max  
3.6  
85  
30  
10  
7
Unit  
V
VDD  
TA  
Supply Voltage  
Operating Temperature (Ambient Temperature)  
Load Capacitance, below 100 MHz  
Load Capacitance, from 100 MHz to 133 MHz  
Input Capacitance  
40  
C  
pF  
pF  
pF  
CL  
CL  
CIN  
Table 6. Electrical Characteristics for MPC962305-X and MPC962309-X Industrial Temperature Devices(1)  
Parameter  
Description  
Input LOW Voltage(2)  
Test Conditions  
Min  
Max  
Unit  
VIL  
0.8  
V
Input HIGH Voltage(2)  
Input LOW Current  
VIH  
IIL  
2.0  
V
A  
A  
V
VIN = 0 V  
VIN = VDD  
50.0  
100.0  
0.4  
IIH  
Input HIGH Current  
Output LOW Voltage(3)  
VOL  
IOL = 8 mA (1)  
IOH = 12 mA (1H)  
Output HIGH Voltage(3)  
VOH  
IOH = 8 mA (1)  
2.4  
V
IOL = 12 mA (1H)  
IDD (PD mode)  
IDD  
Power Down Supply Current  
Supply Current  
REF = 0 MHz  
25.0  
35.0  
A  
Unloaded outputs at 66.67 MHz,  
SEL inputs at VDD  
mA  
1. All parameters are specified with loaded outputs.  
2. REF input has a threshold voltage of VPP/2.  
3. Parameter is guaranteed by design and characterization. Not 100% tested in production.  
MPC962305 REVISION 8 JANUARY 8, 2013  
3
©2013 Integrated Device Technology, Inc.  
MPC962305 Data Sheet  
LOW-COST, 3.3V ZERO DELAY BUFFEr  
Table 7. Switching Characteristics for MPC962305-1 and MPC962309-1 Industrial Temperature Devices(1)  
Parameter  
Name  
Test Conditions  
Min  
Typ  
Max  
Unit  
t1  
Output Frequency  
30-pF load  
10-pF load  
10  
10  
100  
MHz  
MHz  
133.33  
Duty Cycle(2) = t2 t1  
Measured at 1.4 V, FOUT = 66.67 MHz  
40.0  
50.0  
60.0  
%
Rise Time(2)  
t3  
t4  
Measured between 0.8 V and 2.0 V  
Measured between 0.8 V and 2.0 V  
All outputs equally loaded  
2.50  
2.50  
250  
ns  
ns  
ps  
ps  
Fall Time(2)  
Output to Output Skew(2)  
t5  
t6A  
Delay, REF Rising Edge to  
CLKOUT Rising Edge(2)  
Measured at VDD/2  
0
5
0
350  
t6B  
Delay, REF Rising Edge to  
CLKOUT Rising Edge(2)  
Measured at VDD/2. Measured in PLL Bypass Mode,  
MPC962309 device only  
1
8.7  
ns  
Device to Device Skew(2)  
Cycle to Cycle Jitter(2)  
PLL Lock Time(2)  
t7  
tJ  
Measured at VDD/2 on the CLKOUT pins of devices  
Measured at 66.67 MHz, loaded outputs  
700  
200  
1.0  
ps  
ps  
tLOCK  
Stable power supply, valid clock presented on REF pin  
ms  
1. All parameters are specified with loaded outputs.  
2. Parameter is guaranteed by design and characterization. Not 100% tested in production.  
Table 8. Switching Characteristics for MPC962305-1H and MPC962309-1H Industrial Temperature Devices(1)  
Parameter  
Name  
Test Conditions  
Min  
Typ  
Max  
Unit  
t1  
Output Frequency  
30-pF load  
10-pF load  
10  
10  
100  
MHz  
MHz  
133.33  
Duty Cycle(2) = t2 t1  
Duty Cycle(2) = t2 t1  
Rise Time(2)  
Measured at 1.4 V, FOUT = 66.67 MHz  
Measured at 1.4 V, FOUT < 50 MHz  
Measured between 0.8 V and 2.0 V  
Measured between 0.8 V and 2.0 V  
All outputs equally loaded  
40.0  
45.0  
50.0  
55.0  
60.0  
55.0  
1.50  
1.50  
250  
%
%
t3  
t4  
ns  
ns  
ps  
ps  
Fall Time(2)  
Output to Output Skew(2)  
t5  
t6A  
Delay, REF Rising Edge to  
CLKOUT Rising Edge(2)  
Measured at VDD/2  
0
5
0
350  
t6B  
Delay, REF Rising Edge to  
CLKOUT Rising Edge(2)  
Measured at VDD/2. Measured in PLL Bypass Mode,  
MPC962309 device only  
1
1
8.7  
ns  
Device to Device Skew(2)  
Output Slew Rate(2)  
Cycle to Cycle Jitter(2)  
PLL Lock Time(2)  
t7  
t8  
Measured at VDD/2 on the CLKOUT pins of devices  
Measured between 0.8 V and 2.0 V using Test Circuit #2  
Measured at 66.67 MHz, loaded outputs  
700  
ps  
V/ns  
ps  
tJ  
200  
1.0  
tLOCK  
Stable power supply, valid clock presented on REF pin  
ms  
1. All parameters are specified with loaded outputs.  
2. Parameter is guaranteed by design and characterization. Not 100% tested in production.  
MPC962305 REVISION 8 JANUARY 8, 2013  
4
©2013 Integrated Device Technology, Inc.  
MPC962305 Data Sheet  
LOW-COST, 3.3V ZERO DELAY BUFFEr  
APPLICATIONS INFORMATION  
VCC  
VCC  
1.4 V  
CCLK  
GND  
VCC 2  
GND  
VCC  
VCC  
1.4 V  
VCC 2  
FB_IN  
GND  
GND  
t5  
t6  
The pin-to-pin skew is defined as the worst case difference in propagation  
delay between any similar delay path within a single device  
Figure 1. Output-to-Output Skew tSK(O)  
Figure 2. Static Phase Offset Test Reference  
VCC  
1.4 V  
VCC  
GND  
DEVICE 1  
VCC 2  
t2  
GND  
VCC  
t1  
VCC 2  
DEVICE 2  
DC = t2/t1 x 100%  
GND  
t7  
The time from the PLL controlled edge to the non-controlled  
edge, divided by the time between PLL controlled edges,  
expressed as a percentage  
Figure 3. Output Duty Cycle (DC)  
Figure 4. Device-to-Device Skew  
VCC = 3.3 V  
2.0  
tJ = |tN–tN+1  
|
tN  
tN+1  
0.8  
The variation in cycle time of a signal between adjacent cycles,  
over a random sample of adjacent cycle pairs  
t4  
t3  
Figure 5. Cycle-to-Cycle Jitter  
Figure 6. Output Transition Time Test Reference  
MPC962305 REVISION 8 JANUARY 8, 2013  
5
©2013 Integrated Device Technology, Inc.  
MPC962305 Data Sheet  
LOW-COST, 3.3V ZERO DELAY BUFFEr  
Test Circuit #1  
Test Circuit #2  
VDD  
VDD  
1 K   
0.1 F  
0.1 F  
0.1 F  
0.1 F  
CLKOUT  
OUTPUTS  
GND  
OUTPUTS  
GND  
CLKOUT  
CLOAD  
1 K   
10 pF  
VDD  
GND  
VDD  
GND  
Test Circuit for all parameters except t8  
Test Circuit for t8, Output slew rate on –1H, –5 device  
Table 9. Ordering Information  
Ordering Code  
Package Type  
MPC962305D-1  
8-pin 150-mil SOIC  
MPC962305D-1R2  
MPC962305EF-1  
8-pin 150-mil SOIC - Tape and Reel  
8-pin 150-mil SOIC (Pb-free)  
MPC962305EF-1R2  
MPC962305D-1H  
MPC962305D-1HR2  
MPC962305EF-1H  
MPC962305EF-1HR2  
MPC962305DT-1H  
MPC962305DT-1HR2  
MPC962305EJ-1H  
MPC962305EJ-1HR2  
MPC962309D-1  
8-pin 150-mil SOIC (Pb-free) - Tape and Reel  
8-pin 150-mil SOIC  
8-pin 150-mil SOIC - Tape and Reel  
8-pin 150-mil SOIC (Pb-free)  
8-pin 150-mil SOIC (Pb-free) - Tape and Reel  
8-pin 150-mil TSSOP  
8-pin 150-mil TSSOP - Tape and Reel  
8-pin 150-mil TSSOP (Pb-free)  
8-pin 150-mil TSSOP (Pb-free) - Tape and Reel  
16-pin 150-mil SOIC  
MPC962309D-1R2  
MPC962309EF-1  
16-pin 150-mil SOIC - Tape and Reel  
16-pin 150-mil SOIC (Pb-free)  
MPC962309EF-1R2  
MPC962309D-1H  
MPC962309D-1HR2  
MPC962309EF-1H  
MPC962309EF-1HR2  
MPC962309DT-1H  
MPC962309DT-1HR2  
MPC962309EJ-1H  
MPC962309EJ-1HR2  
16-pin 150-mil SOIC (Pb-free) - Tape and Reel  
16-pin 150-mil SOIC  
16-pin 150-mil SOIC - Tape and Reel  
16-pin 150-mil SOIC (Pb-free)  
16-pin 150-mil SOIC (Pb-free) - Tape and Reel  
16-pin 4.4-mm TSSOP  
16-pin 4.4-mm TSSOP - Tape and Reel  
16-pin 4.4-mm TSSOP (Pb-free)  
16-pin 4.4-mm TSSOP (Pb-free) - Tape and Reel  
MPC962305 REVISION 8 JANUARY 8, 2013  
6
©2013 Integrated Device Technology, Inc.  
MPC962305 Data Sheet  
LOW-COST, 3.3V ZERO DELAY BUFFEr  
PACKAGE DIMENSIONS  
PAGE 1 OF 2  
CASE 751-07  
ISSUE U  
8-LEAD SOIC PLASTIC PACKAGE  
MPC962305 REVISION 8 JANUARY 8, 2013  
7
©2013 Integrated Device Technology, Inc.  
MPC962305 Data Sheet  
LOW-COST, 3.3V ZERO DELAY BUFFEr  
PACKAGE DIMENSIONS  
PAGE 2 OF 2  
CASE 751-07  
ISSUE U  
8-LEAD SOIC PLASTIC PACKAGE  
MPC962305 REVISION 8 JANUARY 8, 2013  
8
©2013 Integrated Device Technology, Inc.  
MPC962305 Data Sheet  
LOW-COST, 3.3V ZERO DELAY BUFFEr  
PACKAGE DIMENSIONS  
PAGE 1 OF 2  
CASE 751B-05  
ISSUE L  
16-LEAD SOIC PLASTIC PACKAGE  
MPC962305 REVISION 8 JANUARY 8, 2013  
9
©2013 Integrated Device Technology, Inc.  
MPC962305 Data Sheet  
LOW-COST, 3.3V ZERO DELAY BUFFEr  
PACKAGE DIMENSIONS  
PAGE 2 OF 2  
CASE 751B-05  
ISSUE L  
16-LEAD SOIC PLASTIC PACKAGE  
MPC962305 REVISION 8 JANUARY 8, 2013  
10  
©2013 Integrated Device Technology, Inc.  
MPC962305 Data Sheet  
LOW-COST, 3.3V ZERO DELAY BUFFEr  
PACKAGE DIMENSIONS  
PAGE 1 OF 3  
CASE 948F-01  
ISSUE B  
16-LEAD TSSOP PLASTIC PACKAGE  
MPC962305 REVISION 8 JANUARY 8, 2013  
11  
©2013 Integrated Device Technology, Inc.  
MPC962305 Data Sheet  
LOW-COST, 3.3V ZERO DELAY BUFFEr  
PACKAGE DIMENSIONS  
PAGE 2 OF 3  
CASE 948F-01  
ISSUE B  
16-LEAD TSSOP PLASTIC PACKAGE  
MPC962305 REVISION 8 JANUARY 8, 2013  
12  
©2013 Integrated Device Technology, Inc.  
MPC962305 Data Sheet  
LOW-COST, 3.3V ZERO DELAY BUFFEr  
PACKAGE DIMENSIONS  
PAGE 3 OF 3  
CASE 948F-01  
ISSUE B  
16-LEAD TSSOP PLASTIC PACKAGE  
MPC962305 REVISION 8 JANUARY 8, 2013  
13  
©2013 Integrated Device Technology, Inc.  
MPC962305 Data Sheet  
LOW-COST, 3.3V ZERO DELAY BUFFEr  
PACKAGE DIMENSIONS  
PAGE 1 OF 3  
CASE 948J-01  
ISSUE B  
8-LEAD TSSOP PLASTIC PACKAGE  
MPC962305 REVISION 8 JANUARY 8, 2013  
14  
©2013 Integrated Device Technology, Inc.  
MPC962305 Data Sheet  
LOW-COST, 3.3V ZERO DELAY BUFFEr  
PACKAGE DIMENSIONS  
PAGE 2 OF 3  
CASE 948J-01  
ISSUE B  
8-LEAD TSSOP PLASTIC PACKAGE  
MPC962305 REVISION 8 JANUARY 8, 2013  
15  
©2013 Integrated Device Technology, Inc.  
MPC962305 Data Sheet  
LOW-COST, 3.3V ZERO DELAY BUFFEr  
PACKAGE DIMENSIONS  
PAGE 3 OF 3  
CASE 948J-01  
ISSUE B  
8-LEAD TSSOP PLASTIC PACKAGE  
MPC962305 REVISION 8 JANUARY 8, 2013  
16  
©2013 Integrated Device Technology, Inc.  
MPC962305 Data Sheet  
LOW-COST, 3.3V ZERO DELAY BUFFEr  
Revision History Sheet  
Rev  
Table  
Page  
Description of Change  
Date  
8
1
NRND – Not Recommend for New Designs  
1/8/13  
MPC962305 REVISION 8 JANUARY 8, 2013  
17  
©2013 Integrated Device Technology, Inc.  
MPC962305 Data Sheet  
LOW-COST, 3.3V ZERO DELAY BUFFEr  
We’ve Got Your Timing Solution  
6024 Silver Creek Valley Road Sales  
Technical Support  
800-345-7015 (inside USA)  
netcom@idt.com  
San Jose, California 95138  
+408-284-8200 (outside USA) +480-763-2056  
Fax: 408-284-2775  
www.IDT.com/go/contactIDT  
DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document,  
including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not  
guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the  
suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any  
license under intellectual property rights of IDT or any third parties.  
IDT’s products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to signifi-  
cantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT.  
Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or their respective third  
party owners.  
Copyright 2013. All rights reserved.  

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VISHAY

SI9130CG-T1-E3

 Pin-Programmable Dual Controller - Portable PCs

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SI9130LG-T1-E3

 Pin-Programmable Dual Controller - Portable PCs

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VISHAY

SI9130_11

 Pin-Programmable Dual Controller - Portable PCs

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SI9137

 Multi-Output, Sequence Selectable Power-Supply Controller for Mobile Applications

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SI9137DB

 Multi-Output, Sequence Selectable Power-Supply Controller for Mobile Applications

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SI9137LG

 Multi-Output, Sequence Selectable Power-Supply Controller for Mobile Applications

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SI9122E

 500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification Drivers

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