U62H64JK20L [IDT]
Standard SRAM, 8KX8, 20ns, CMOS, PDSO28;
| 型号： | U62H64JK20L |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Standard SRAM, 8KX8, 20ns, CMOS, PDSO28 静态存储器 光电二极管 内存集成电路 |
| 文件： | 总8页 (文件大小：115K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
U62H64
Fast 8K x 8 SRAM
Latch-up immunity > 200 mA
Packages: PDIP28 (300 mil)
SOJ28 (300 mil)
the outputs DQ0 - DQ7. After the
address change, the data outputs
go High-Z until the new read infor-
mation is available. The data out-
puts have no preferred state. If the
memory is driven by CMOS levels
in the active state, and if there is no
change of the address, data input
and control signals W or G, the ope-
rating current (at IO = 0 mA) drops to
the value of the operating current in
the Standby mode. The Read cycle
is finished by the falling edge of E2
or W, or by the rising edge of E1,
respectively.
Features
Fast 8192 x 8 bit static CMOS
RAM
20 ns, 25 ns, 35 ns Access Times
Bidirectional data inputs and
data outputs
Description
The U62H64 is a static RAM manu-
factured using a CMOS process
technology with the following ope-
rating modes:
Three-state outputs
Data retention current
at 3 V: < 10 µA (standard)
Standby current standard < 30 µA
Standby current low power (L)
< 5 µA
TTL/CMOS-compatible
Automatic reduction of power
dissipation in long
Read or Write cycles
Power supply voltage 5 V
Operating temperature ranges:
0 to 70 °C
-25 to 85 °C
-40 to 85 °C
Quality assessment according to
CECC 90000, CECC 90100 and
CECC 90111
- Read
- Write
- Standby
- Data Retention
The memory array is based on a
6-transistor cell.
The circuit is activated by the rising
edge of E2 (at E1 = L), or the falling
edge of E1 (at E2 = H). The Data retention is guaranteed down
address and control inputs open to 2 V.
simultaneously.
According to the information of W inputs consist of NOR gates, so that
and G, the data inputs, or outputs, no pull-up/pull-down resistors are
are active. During the active state required. This gate circuit allows to
(E1 = L and E2 = H), each address achieve low power standby require-
change leads to a new Read or ments by activation with TTL-levels
Write cycle. In a Read cycle, the too.
With the exception of E1 and E2, all
data outputs are activated by the
falling edge of G, afterwards the
data word read will be available at
ESD protection > 2000 V
(MIL STD 883C M3015.7)
Pin Configuration
Pin Description
n.c.
A12
A7
1
VCC
28
27
26
25
24
23
22
21
20
19
18
17
16
15
2
W (WE)
E2 (CE2)
A8
3
A6
4
Signal Name Signal Description
A5
5
A9
A0 - A12
Address Inputs
Data In/Out
A4
6
A11
DQ0 - DQ7
A3
7
G (OE)
A10
PDIP
SOJ
Chip Enable 1
Chip Enable 2
Output Enable
Write Enable
Power Supply Voltage
Ground
E1
A2
8
E2
A1
9
E1 (CE1)
DQ7
G
A0
10
11
12
13
14
W
DQ0
DQ1
DQ2
VSS
DQ6
VCC
VSS
DQ5
DQ4
not connected
n.c.
DQ3
Top View
1
December 12, 1997
U62H64
Block Diagram
A6
Memory Cell
Array
A7
A8
A9
A10
A11
A12
128 Rows
64 x 8 Columns
A0
A1
A2
A3
A4
A5
DQ0
DQ1
DQ2
Sense Amplifier/
Write Control Logic
DQ3
DQ4
DQ5
Address
Change
Detector
Clock
Generator
DQ6
DQ7
E2
E1
VSS
W
G
VCC
Truth Table
Operating Mode
E1
E2
W
G
DQ0 - DQ7
*
H
L
L
L
L
*
*
*
*
*
High-Z
High-Z
Standby/not
selected
Internal Read
Read
H
H
H
H
H
L
H
L
*
High-Z
Data Outputs Low-Z
Data Inputs High-Z
Write
H or L
*
Characteristics
All voltages are referenced to VSS = 0 V (ground).
All characteristics are valid in the power supply voltage range and in the operating temperature range specified.
Dynamic measurements are based on a rise and fall time of ≤ 3 ns, measured between 10 % and 90 % of VI, as well as
input levels of VIL = 0 V and VIH = 3 V. The timing reference level of all input and output signals is 1.5 V,
with the exception of the tdis-times and t -times, in which cases transition is measured ± 200 mV from steady-state voltage.
en
Maximum Ratings
Symbol
Min.
Max.
Unit
Power Supply Voltage
Input Voltage
VCC
VI
-0.3
-0.3
-0.3
7
V
V
V
VCC + 0.5
VCC + 0.5
Output Voltage
VO
Ta
Operating Temperature
C-Type
G-Type
K-Type
0
-25
-40
70
85
85
°C
°C
°C
Storage Temperature
Tstg
-55
125
300
°C
Output Short-Circuit Current
at VCC = 5 V and VO = 0 V*
|IOS
|
mA
* Not more than 1 output should be shorted at one time. Duration of the short circuit should not exceed 30 s.
2
December 12, 1997
U62H64
Recommended
Symbol
Conditions
Min.
Max.
Unit
Operating Conditions
Power Supply Voltage
Data Retention Voltage
Input Low Voltage *
VCC
VCC(DR)
VIL
4.5
2.0
5.5
-
V
V
V
-0.3
2.2
0.8
Input High Voltage
VIH
VCC + 0.3
V
* -2 V at Pulse Width 10 ns
Electrical Characteristics
Symbol
Conditions
Min.
Max.
Unit
Supply Current - Operating Mode
ICC(OP) VCC
=
=
=
=
=
=
5.5 V
0.8 V
2.2 V
20 ns
25 ns
35 ns
VIL
VIH
tcW
tcW
tcW
70
55
50
mA
mA
mA
Supply Current - Standby Mode
(CMOS level)
ICC(SB) VCC
= 5.5 V
VE1 = VE2 = VCC - 0.2 V
Standard
Low Power (L)
30
5
µA
µA
Supply Current - Standby Mode
(TTL level)
ICC(SB)1 VCC
= 5.5 V
5
mA
VE1 = VE2 = 2.2 V
(typ. 2)
Supply Current - Data Retention
Mode (Standard)
ICC(DR) VCC(DR)
= 3 V
10
µA
VE1 = VE2 = VCC(DR) - 0.2 V
Output High Voltage
Output Low Voltage
VOH
VOL
VCC
IOH
VCC
IOL
= 4.5 V
= -4.0 mA
= 4.5 V
2.4
-
-
V
V
0.4
= 8.0 mA
Output High Current
Output Low Current
IOH
IOL
VCC
VOH
VCC
VOL
= 4.5 V
= 2.4 V
= 4.5 V
= 0.4 V
-
-4.0
-
mA
mA
8.0
Input High Leakage Current
Input Low Leakage Current
IIH
IIL
VCC
VIH
VCC
VIL
= 5.5 V
= 5.5 V
= 5.5 V
-
2
-
µA
µA
-2
=
0 V
Output Leakage Current
High at Three-State Outputs
IOHZ
IOLZ
VCC
VOH
VCC
VOL
= 5.5 V
= 5.5 V
= 5.5 V
-
2
-
µA
µA
Low at Three-State Outputs
-2
=
0 V
3
December 12, 1997
U62H64
Symbol
Min.
25
Max.
25
Unit
Switching Characteristics
Alt.
IEC
20
35
20
35
Time to Output in Low-Z from
E1 LOW or E2 HIGH
G LOW
tLZCE
tLZOE
tLZWE
ten(E)
ten(G)
ten(W)
5
0
0
5
0
0
5
0
0
ns
ns
ns
W HIGH
Cycle Time
Write Cycle Time
Read Cycle Time
tWC
tRC
tcW
tcR
20
20
25
25
35
35
ns
ns
Access Time
E1 LOW or E2 HIGH to Data Valid
G LOW to Data Valid
Address to Data Valid
tACE
tOE
tAA
ta(E)
ta(G)
ta(A)
20
10
20
25
12
25
35
15
35
ns
ns
ns
Pulse Widths
Write Pulse Width
Chip Enable to End of Write
tWP
tCW
tw(W)
tw(E)
15
15
15
20
20
25
ns
ns
Setup Times
Address Setup Time
Chip Enable to End of Write
Write Pulse Width
Data Setup Time
tAS
tCW
tWP
tDS
tsu(A)
tsu(E)
tsu(W)
tsu(D)
0
0
0
ns
ns
ns
ns
15
15
10
20
15
10
25
20
15
Data Hold Time
Address Hold from End of Write
tDH
tAH
th(D)
th(A)
0
0
0
0
0
0
ns
ns
Output Hold Time from Address Change
tOH
tv(A)
5
5
5
ns
E1 HIGH or E2 LOW to Output in
High-Z
W LOW to Output in High-Z
G HIGH to Output in High-Z
tHZCE
tHZWE
tHZOE
tdis(E)
tdis(W)
tdis(G)
8
8
8
10
10
10
15
15
12
ns
ns
ns
E1 LOW or E2 HIGH to Power-Up
E1 HIGH or E2 LOW to Power-Down
tPU
tPD
0
0
0
ns
ns
20
25
35
Data Retention Mode E1-Controlled
Data Retention Mode E2-Controlled
VCC
VCC
E2
4.5 V
4.5 V
VCC(DR) ≥ 2 V
V
CC(DR) ≥ 2 V
2.2 V
2.2 V
Data Retention
trec
tDR
tDR
Data Retention
trec
E1
0.8 V
0.8 V
0 V
0 V
V
E1(DR) ≥ VCC(DR) - 0.2 V or VE1(DR) ≤ 0.2 V
V
V
E2(DR) ≥ VCC(DR) - 0.2 V or VE2(DR) ≤ 0.2 V
CC(DR) - 0.2 V ≤ VE1(DR) ≤ VCC(DR) + 0.3 V
VE2(DR) ≤ 0.2 V
Chip Deselect to Data Retention Time
Operating Recovery Time at VCC(DR)
tDR
:
min 0 ns
min tcR
trec
:
4
December 12, 1997
U62H64
Test Configuration for Functional Check
5 V
VCC
A0
A1
A2
A3
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
A4
481
A5
VIH
A6
A7
A8
A9
A10
A11
A12
VIL
V
O
30 pF1)
E1
E2
W
255
VSS
G
1) In measurement of tdis(E), tdis(W), tdis(G), ten(E), ten(W), ten(G) the capacitance is 5 pF.
Capacitance
Conditions
Symbol
Min.
Max.
Unit
V
CC = 5.0 V
Input Capacitance
CI
8
pF
VI = VSS
f
= 1 MHz
Output Capacitance
CO
10
pF
Ta = 25°C
All pins not under test must be connected with ground by capacitors.
IC Code Numbers
Example
U62H64
D
G
20
L
Type
Package
D = PDIP
J = SOJ
Operating Temperture Range
Power Consumption
= Standard
L = Low Power
C
G
K
=
0 to 70 °C
= -25 to 85 °C
= -40 to 85 °C
Access Time
20 = 20 ns
25 = 25 ns
35 = 35 ns
The date of manufacture is given by the last 4 digits of the mark, the first 2 digits indicating the year, and the last
2 digits the calendar week.
5
December 12, 1997
U62H64
Read Cycle 1 (during Read cycle: E1 = G = VIL, E2 = W = VIH, Ai-controlled)
tcR
Ai
Addresses Valid
ta(A)
Output Data
Valid
Previous
Data Valid
DQi
Output
tv(A)
Read Cycle 2 (during Read cycle: W = VIH, G-, E1- or E2-controlled)
tcR
Ai
Addresses Valid
ta(E)
tsu(A)
ten(E)
tdis(E)
tdis(E)
E1
E2
ta(E)
tsu(A)
ten(E)
ta(G)
G
tdis(G)
ten(G)
DQi
Output
High-Z
Output Data
Valid
tPU
*
tPD*
ICC(OP)
ICC(SB)
50 %
50 %
* The same applies to E1
Write Cycle 1 (W-controlled)
tcW
Addresses Valid
tsu(E)
Ai
th(A)
E1
E2
tsu(E)
tw(W)
tsu(D)
tsu(A)
W
th(D)
DQi
Input
Input Data
Valid
tdis(W)
ten(W)
High-Z
DQi
Output
G
6
December 12, 1997
U62H64
Write Cycle 2 (E1-controlled)
tcW
Addresses Valid
tw(E)
Ai
tsu(A)
th(A)
E1
E2
tsu(E)
tsu(W)
W
tsu(D)
th(D)
DQi
Input
Input Data
Valid
tdis(W)
ten(E)
DQi
High-Z
Output
G
Write Cycle 3 (E2-controlled)
tcW
Addresses Valid
tsu(E)
Ai
th(A)
E1
E2
tsu(A)
tw(E)
tsu(W)
W
th(D)
tsu(D)
DQi
Input
Input Data
Valid
tdis(W)
ten(E)
DQi
Output
High-Z
G
L- or H-level
undefined
7
December 12, 1997
Memory Products 1998
Fast 8K x 8 SRAM U62H64
LIFE SUPPORT POLICY
ZMD products are not designed, intended, or authorized for use as components in
systems intend for surgical implant into the body, or other applications intended to
support or sustain life, or for any other application in which the failure of the ZMD
product could create a situation where personal injury or death may occur.
Components used in life-support devices or systems must be expressly authorized
by ZMD for such purpose.
The information describes the type of component and shall not be considered as
assured characteristics.
Terms of delivery and rights to change design reserved.
Zentrum Mikroelektronik Dresden GmbH
Grenzstraße 28 • D-01109 Dresden• P. O.B. 800134 •D-01101 Dresden•Germany
Phone: +49 351 88 22-3 06 • Fax: +49 351 88 22-3 37 • Email: sales@zmd.de
Internet Web Site: http://www.zmd.de
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