U62H64SA35 [ZMD]
AUTOMOTIVE FAST 8K X 8 SRAM; 汽车快速8K ×8 SRAM
| 型号： | U62H64SA35 |
| 厂家： | 
Zentrum Mikroelektronik Dresden AG |
| 描述： | AUTOMOTIVE FAST 8K X 8 SRAM |
| 文件： | 总9页 (文件大小：163K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
U62H64
Automotive Fast 8K x 8 SRAM
Features
Description
! Fast 8192 x 8 bit static CMOS
RAM
The U62H64 is a static RAM manu-
factured using a CMOS process
technology with the following ope-
rating modes:
change of the address, data input
and control signals W or G, the
operating current (at IO = 0 mA)
drops to the value of the operating
current in the Standby mode. The
Read cycle is finished by the falling
edge of E2 or W, or by the rising
edge of E1, respectively.
! 35 ns Access Time
! Bidirectional data inputs and data
outputs
- Read
- Write
- Standby
! Three-state outputs
! Data retention mode at Vcc > 2V
! Data retention current at 2 V:
< 3 µA (K-Type)
- Data Retention
The memory array is based on a
6-transistor cell.
The circuit is activated by the rising
edge of E2 (at E1 = L), or the falling
edge of E1 (at E2 = H). The
address and control inputs open
simultaneously.
Data retention is guaranteed down
to 2 V.
< 50 µA (A-Type)
! Standby current
With the exception of E1 and E2,
all inputs consist of NOR gates, so
that no pull-up/pull-down resistors
<
5 µA (K-Type)
< 100 µA (A-Type)
! TTL/CMOS-compatible
! Automatic reduction of power
dissipation in long Read or Write
cycles
According to the information of W
and G, the data inputs, or outputs,
are active. In a Read cycle, the
data outputs are activated by the
falling edge of G, afterwards the
data word read will be available at
the outputs DQ0 - DQ7. After the
address change, the data outputs
go High-Z until the new read infor-
mation is available. The data out-
puts have no preferred state. If the
memory is driven by CMOS levels
in the active state, and if there is no
are required.
This gate circuit
allows to achieve low power
standby requirements by activation
with TTL-levels too.
! Power supply voltage 5 V
! Operating temperature ranges
-40 to 85 °C
-40 to 125 °C
! QS 9000 Quality Standard
! ESD protection > 2000 V
(MIL STD 883C M3015.7)
! Latch-up immunity > 200 mA
! Package: SOP28 (300 mil)
Pin Configuration
Pin Description
1
2
3
4
5
6
7
8
VCC
n.c.
A12
A7
A6
A5
A4
A3
A2
A1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
W (WE)
E2 (CE2)
A8
A9
A11
G (OE)
A10
E1 (CE1)
DQ7
DQ6
DQ5
Signal Name Signal Description
A0 - A12
DQ0 - DQ7
Address Inputs
Data In/Out
Chip Enable 1
Chip Enable 2
Output Enable
Write Enable
Power Supply Voltage
Ground
E1
E2
G
W
VCC
VSS
SOP
9
10
11
12
13
14
A0
DQ0
DQ1
DQ2
VSS
not connected
n.c.
DQ4
DQ3
Top View
April 20, 2004
1
U62H64
Block Diagram
A6
A7
A8
A9
Memory Cell
Array
128 Rows
A10
64 x 8 Columns
A11
A12
A0
A1
A2
A3
A4
A5
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
Sense Amplifier/
Write Control Logic
Address
Change
Detector
Clock
DQ6
DQ7
Generator
E2
E1
VSS
W
G
VCC
Truth Table
Operating Mode
E1
E2
W
G
DQ0 - DQ7
*
H
L
L
L
L
*
*
*
*
*
High-Z
High-Z
High-Z
Standby/not selected
Internal Read
Read
H
H
H
H
H
L
H
L
*
Data Outputs Low-Z
Data Inputs High-Z
Write
H or L
*
2
April 20, 2004
U62H64
Characteristics
All voltages are referenced to VSS = 0 V (ground).
All characteristics are valid in the power supply voltage range and in the operating temperature range specified.
Dynamic measurements are based on a rise and fall time of ≤ 5 ns, measured between 10 % and 90 % of VI, as well as
input levels of VIL = 0 V and VIH = 3 V. The timing reference level of all input and output signals is 1.5 V,
with the exception of the tdis-times and ten-times, in which cases transition is measured ± 200 mV from steady-state voltage.
a
Absolute Maximum Ratings
Symbol
Min.
Max.
Unit
Power Supply Voltage
Input Voltage
VCC
VI
-0.3
-0.3
-0.3
7
V
V
V
b
b
VCC + 0.5
VCC + 0.5
Output Voltage
VO
Ta
Operating Temperature
K-Type
A-Type
-40
-40
85
°C
125
°C
Storage Temperature
Tstg
-65
150
200
°C
Output Short-Circuit Current
|IOS
|
mA
c
at VCC = 5 V and VO = 0 V
a
Stresses greater than those listed under „Absolute Maximum Ratings“ may cause permanent damage to the device. This is a stress rating
only, and functional operation of the device at condition above those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability
b
c
Maximum voltage is 7 V
Not more than 1 output should be shorted at the same time. Duration of the short circuit should not exceed 30 s.
Recommended
Symbol
Conditions
Min.
Max.
Unit
Operating Conditions
Power Supply Voltage
Data Retention Voltage
VCC
4.5
2.0
5.5
V
V
VCC(DR)
-
d
Input Low Voltage
VIL
VIH
-0.3
2.2
0.8
V
V
Input High Voltage
VCC + 0.3
d
-2 V at Pulse Width 10 ns or -1 V at Pulse Width 50 ns
April 20, 2004
3
U62H64
Electrical Characteristics
Symbol
Conditions
Min.
Max.
Unit
Supply Current - Operating Mode
ICC(OP)
VCC
VIL
= 5.5 V
= 0.8 V
= 2.2 V
VIH
tcW
=
35 ns
50
mA
Supply Current - Standby Mode
(CMOS level)
ICC(SB)
VCC
= 5.5 V
VE1 = VE2 = VCC - 0.2 V
K-Type
5
µA
µA
A-Type
100
Supply Current - Standby Mode
(TTL level)
ICC(SB)1 VCC
= 5.5 V
5
mA
V
E1 = VE2 = 2.2 V
(typ. 2)
Supply Current - Data Retention Mode
ICC(DR)
VCC(DR)
= 2.0 V
VE1 = VE2 = VCC(DR) - 0.2 V
K-Type
A-Type
3
µA
µA
50
Output High Voltage
Output Low Voltage
VOH
VOL
VCC
IOH
= 4.5 V
2.4
-
-
V
V
= -4.0 mA
= 4.5 V
VCC
0.4
I
= 8.0 mA
OL
Output High Current
Output Low Current
IOH
IOL
VCC
VOH
VCC
VOL
= 4.5 V
= 2.4 V
= 4.5 V
= 0.4 V
-
-4.0
-
mA
mA
8.0
Input High Leakage Current
Input Low Leakage Current
IIH
IIL
VCC
VIH
VCC
VIL
= 5.5 V
= 5.5 V
= 5.5 V
-
2
-
µA
µA
-2
=
0 V
Output Leakage Current
High at Three-State Outputs
IOHZ
IOLZ
VCC
VOH
VCC
VOL
= 5.5 V
= 5.5 V
= 5.5 V
-
2
-
µA
µA
Low at Three-State Outputs
-2
=
0 V
4
April 20, 2004
U62H64
Symbol
Unit
Min.
Max.
Switching Characteristics
Alt.
IEC
Time to Output in Low-Z from
E1 LOW or E2 HIGH
G LOW
tLZCE
tLZOE
tLZWE
ten(E)
ten(G)
ten(W)
5
0
0
ns
ns
ns
W HIGH
Cycle Time
Write Cycle Time
Read Cycle Time
tWC
tRC
tcW
tcR
35
35
ns
ns
Access Time
E1 LOW or E2 HIGH to Data Valid
G LOW to Data Valid
Address to Data Valid
tACE
tOE
tAA
ta(E)
ta(G)
ta(A)
35
15
35
ns
ns
ns
Pulse Widths
Write Pulse Width
Chip Enable to End of Write
tWP
tCW
tw(W)
tw(E)
20
25
ns
ns
Setup Times
Address Setup Time
Chip Enable to End of Write
Write Pulse Width
Data Setup Time
tAS
tCW
tWP
tDS
tsu(A)
tsu(E)
tsu(W)
tsu(D)
0
ns
ns
ns
ns
25
20
15
Data Hold Time
tDH
tAH
th(D)
th(A)
0
0
ns
ns
Address Hold from End of Write
Output Hold Time from Address Change
tOH
tv(A)
5
ns
E1 HIGH or E2 LOW to Output in High-Z
W LOW to Output in High-Z
tHZCE
tHZWE
tHZOE
tdis(E)
tdis(W)
tdis(G)
15
15
12
ns
ns
ns
G HIGH to Output in High-Z
E1 LOW or E2 HIGH to Power-Up
E1 HIGH or E2 LOW to Power-Down
tPU
tPD
0
ns
ns
35
Data Retention Mode E2-Controlled
Data Retention Mode E1-Controlled
VCC
E2
VCC
4.5 V
0 V
4.5 V
V
CC(DR) ≥ 2 V
V
CC(DR) ≥ 2 V
trec
tDR
Data Retention
2.2 V
2.2 V
E1
0.8 V
0.8 V
tDR
trec
Data Retention
0 V
V
V
E1(DR) ≥ VCC(DR) - 0.2 V or VE1(DR) ≤ 0.2 V
E2(DR) ≤ 0.2 V
V
V
E2(DR) ≥ VCC(DR) - 0.2 V or VE2(DR) ≤ 0.2 V
CC(DR) - 0.2 V ≤ VE1(DR) ≤ VCC(DR) + 0.3 V
Chip Deselect to Data Retention Time
Operating Recovery Time at VCC(DR)
tDR
trec
:
:
min 0 ns
min tcR
April 20, 2004
5
U62H64
Test Configuration for Functional Check
5 V
VCC
A0
A1
A2
A3
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
A4
481
A5
VIH
VIL
A6
A7
A8
A9
A10
A11
A12
VO
30 pF e
E1
E2
W
255
VSS
G
e In measurement of tdis(E), tdis(W), tdis(G), ten(E), ten(W), ten(G) the capacitance is 5 pF.
Capacitance
Conditions
VCC = 5.0 V
Symbol
Min.
Max.
Unit
Input Capacitance
CI
8
pF
VI = VSS
f
= 1 MHz
Output Capacitance
CO
10
pF
Ta = 25 °C
All pins not under test must be connected with ground by capacitors.
Ordering Code
Example
U62H64
S
K
35
L
Type
Leadfree Option
blank= Standard Package
Package
G1 = Leadfree Green Package f
S = SOP28 (300 mil)
Power Consumption
Operating Temperature Range
K = -40 to 85 °C
blank= Standard (only A-Type)
L
= Low Power (only K-Type)
A = -40 to 125 °C
Access Time
35 = 35 ns
f on special request
Device Marking (example)
ZMD
Product specification
Date of manufacture
U62H64SK
35L C 0425
(The first 2 digits indicating
the year, and the last 2
digits the calendar week.)
Assembly location and
trace code
1 ZZ
G1
Internal Code
Leadfree Green Package
6
April 20, 2004
U62H64
Read Cycle 1 (during Read cycle: E1 = G = VIL, E2 = W = VIH, A -controlled)
i
tcR
Ai
Addresses Valid
ta(A)
DQi
Previous Data Valid
tv(A)
Output Data Valid
Output
Read Cycle 2 (during Read cycle: W = VIH, G-, E1- or E2-controlled)
tcR
Ai
Addresses Valid
ta(E)
ten(E)
tsu(A)
E1
tdis(E)
tdis(E)
tsu(A)
ta(E)
ten(E)
E2
G
ta(G)
tdis(G)
ten(G)
DQi
High-Z
Output Data Valid
Output
*
tPU
*
tPD
ICC(OP)
ICC(SB)
50 %
50 %
* The same applies to E1
Write Cycle 1 (W-controlled)
tcW
Ai
Addresses Valid
tsu(E)
th(A)
E1
E2
W
tsu(E)
tw(W)
tsu(A)
tsu(D)
th(D)
DQi
Input Data Valid
ten(W)
High-Z
Input
tdis(W)
DQi
Output
G
April 20, 2004
7
U62H64
Write Cycle 2 (E1-controlled)
tcW
Ai
Addresses Valid
tw(E)
tsu(A)
th(A)
E1
E2
E2
W
tsu(E)
tsu(W)
tsu(D)
th(D)
DQi
Input Data Valid
Input
tdis(W)
ten(E)
DQi
High-Z
Output
G
Write Cycle 3 (E2-controlled)
tcW
Addresses Valid
tsu(E)
Ai
th(A)
E1
tsu(A)
tw(E)
E2
W
tsu(W)
tsu(D)
th(D)
DQi
Input Data Valid
Input
tdis(W)
ten(E)
High-Z
DQi
Output
G
L- or H-level
undefined
The information describes the type of component and shall not be considered as assured characteristic. Terms of
delivery and rights to change design reserved.
8
April 20, 2004
U62H64
LIFE SUPPORT POLICY
ZMD products are not designed, intended, or authorized for use as components in systems intended for surgical
implant into the body, or other applications intended to support or sustain life, or for any other application in which
the failure of the ZMD product could create a situation where personal injury or death may occur.
Components used in life-support devices or systems must be expressly authorized by ZMD for such purpose.
LIMITED WARRANTY
The information in this document has been carefully checked and is believed to be reliable. However Zentrum
Mikroelektronik Dresden AG (ZMD) makes no guarantee or warranty concerning the accuracy of said information
and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon it.
The information in this document describes the type of component and shall not be considered as assured charac-
teristics.
ZMD does not guarantee that the use of any information contained herein will not infringe upon the patent, trade-
mark, copyright, mask work right or other rights of third parties, and no patent or licence is implied hereby. This
document does not in any way extent ZMD’s warranty on any product beyond that set forth in its standard terms and
conditions of sale.
ZMD reserves terms of delivery and reserves the right to make changes in the products or specifications, or both,
presented in this publication at any time and without notice.
April 20, 2004
Zentrum Mikroelektronik Dresden AG
Grenzstraße 28 • D-01109 Dresden •P. O. B. 80 01 34 • D-01101 Dresden • Germany
Phone: +49 351 8822 306 • Fax: +49 351 8822 337 • Email: memory@zmd.de • http://www.zmd.de
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