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ZADC5125NIS28T [IDT]

A/D Converter;
ZADC5125NIS28T
型号： ZADC5125NIS28T
厂家： INTEGRATED DEVICE TECHNOLOGY    INTEGRATED DEVICE TECHNOLOGY
描述：

A/D Converter
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Data Sheet  
Rev. 1.1 / July 2010  
ZADC5125/5123/5121  
12-Bit, 1Msps, Simultaneous Sampling ADC Family  
ZADC5125/5123/5121  
12-Bit, 1Msps, Simultaneous Sampling ADC Family  
All members of the ZADC512x family provide soft-  
ware-selectable power-down modes that can be pro-  
grammed to automatically shut down the IC at the  
end of a conversion. Accessing the serial interface  
automatically powers up the IC. A quick turn-on time  
allows the device to be shut down between conver-  
sions.  
Brief Description  
The ZADC512x family is a set of low power, 12-bit,  
simultaneous sampling, successive approximation  
analog-to-digital (A/D) converters with up to 1Msps  
conversion rate. It provides up to 6 fully differential  
or up to 10 pseudo differential input channels, high-  
bandwidth track/hold and a synchronous serial inter-  
face.  
Features  
The ADCs operate in a supply voltage range from  
+ 2.7V to + 5.25V where the analog (AVDD) and  
digital (DVDD) power domains can vary independ-  
ently in this range.  
Dual Core Simultaneous Sampling (1Msps)  
SNR: 71dB, THD: -81dB  
Configurable Unipolar / Bipolar output coding  
Flexible Supply Ranges 2.7V to 5.25V  
Three different Power-Down Modes  
Programmable digital threshold and alarm levels  
Digital anti-bouncing filter  
The analog inputs are software configurable for uni-  
polar/bipolar and single-ended/differential operation.  
The serial interface connects directly to SPI™/  
(QSPI™ and MICROWIRE™) devices without exter-  
nal logic. In addition the device provides digital  
threshold level comparators and configurable Alarm  
Outputs that can be used to quickly react on Over-  
load or Out of Range conditions in the analog input  
signal as well as for automatic voltage range switch-  
ing purposes.  
Internal: 2.5V Reference or External: 1V to AVDD  
Low Power Consumption  
-
-
-
< 28 mW (1 Msps, 5.25 V supply)  
< 14 mW (1 Msps, 2.7V supply)  
< 1 μA (full power-down mode)  
SPITM / QSPITM / MICROWIRETM - compatible  
4 Wire Serial Interface  
The ZADCS512xV versions are equipped with a  
highly accurate internal 2.5V reference with an addi-  
tional external ±1.5% voltage adjustment range.  
20 / 24 / 28-Pin SSOP  
ZADC512x  
CHA0+  
Available in ZADC5121  
CHA0-  
ALARM AP  
CHA1+  
CHA1-  
CHA2+  
CHA2-  
S/H + ADC  
Dig Comp A  
Dig Filters A  
Available in ZADC5123  
Available in ZADC5125  
ALARM AN  
Register file  
CONV  
nCS  
Interface Logic  
&
Control Machine  
SCLK  
DIN  
DOUTA  
DOUTB  
CHB0+  
CHB0-  
CHB1+  
CHB1-  
CHB2+  
CHB2-  
Available in ZADC5121  
ALARM BP  
ALARM BN  
Available in ZADC5123  
Available in ZADC5125  
S/H + ADC  
Dig Comp B  
Dig Filters B  
DVDD  
AVDD  
DGND  
AGND  
+1.25V  
Reference  
VREF  
x2  
VREF_adj  
Available in ZADC512xV Versions only  
© 2010 Zentrum Mikroelektronik Dresden AG — Rev. 1.1  
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner.  
The information furnished in this publication is PRELIMINARY and subject to changes without notice.  
ZADC5125/5123/5121  
12-Bit, 1Msps, Simultaneous Sampling ADC Family  
Ordering Information  
Order Code  
ZADC5125VIS28T  
ZADC5125NIS28T  
ZADC5123VIS24T  
ZADC5123NIS24T  
ZADC5121VIS20T  
ZADC5121NIS20T  
12  
12  
12  
12  
12  
12  
10 1000  
10 1000  
-25°C to +85°C  
-25°C to +85°C  
-25°C to +85°C  
-25°C to +85°C  
-25°C to +85°C  
-25°C to +85°C  
± 1 LSB  
± 1 LSB  
± 1 LSB  
± 1 LSB  
± 1 LSB  
± 1 LSB  
± 1 LSB  
± 1 LSB  
± 1 LSB  
± 1 LSB  
± 1 LSB  
± 1 LSB  
28 SSOP Tube  
28 SSOP Tube  
24 SSOP Tube  
24 SSOP Tube  
20 SSOP Tube  
20 SSOP Tube  
6
6
2
2
1000  
1000  
1000  
1000  
ZMDI Contact  
Sales and Further Information  
www.zmdi.com  
ZMD AG, Japan Office  
sales@zmdi.com  
ZMD Far East, Ltd.  
Zentrum Mikroelektronik  
ZMD America, Inc.  
Dresden AG (ZMD AG)  
Grenzstrasse 28  
01109 Dresden  
201 Old Country Road  
Suite 204  
Melville, NY 11747  
USA  
2nd Floor, Shinbashi Tokyu Bldg. 3F, No. 51, Sec. 2,  
4-21-3, Shinbashi, Minato-ku  
Tokyo, 105-0004  
Japan  
Keelung Road  
11052 Taipei  
Taiwan  
Germany  
Phone +49 (0)351.8822.7.232  
Phone +1.(631) 549-2666  
Phone +81.3.6895.7410  
Phone +886.2.2377.8189  
Fax  
+49(0)351.8822.87.232  
Fax  
+1.(631) 549-2882  
Fax  
+81.3.6895.7301  
Fax  
+886.2.2377.8199  
DISCLAIMER: This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Zentrum Mikroelektronik Dresden AG  
(ZMD AG) assumes no obligation regarding future manufacture unless otherwise agreed to in writing. The information furnished hereby is believed to be true and accurate. However, under  
no circumstances shall ZMD AG be liable to any customer, licensee, or any other third party for any special, indirect, incidental, or consequential damages of any kind or nature whatsoever  
arising out of or in any way related to the furnishing, performance, or use of this technical data. ZMD AG hereby expressly disclaims any liability of ZMD AG to any customer, licensee or any  
other third party, and any such customer, licensee and any other third party hereby waives any liability of ZMD AG for any damages in connection with or arising out of the furnishing, perfor-  
mance or use of this technical data, whether based on contract, warranty, tort (including negligence), strict liability, or otherwise.  
© 2010 Zentrum Mikroelektronik Dresden AG — Rev. 1.1  
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner.  
The information furnished in this publication is PRELIMINARY and subject to changes without notice.  
ZADC5125/5123/5121  
12-Bit, 1Msps, Simultaneous Sampling ADC Family  
Contents  
1
Electrical Characteristics.....................................................................................................................................7  
1.1. Absolute Maximum Ratings..........................................................................................................................7  
1.2. Package Pin Assignment ZADC5125N / ZADC5125V.................................................................................8  
1.3. Package Pin Assignment ZADC5123N / ZADC5123V.................................................................................9  
1.4. Package Pin Assignment ZADC5121N / ZADC5121V...............................................................................10  
1.5. Package Pin Drawing .................................................................................................................................11  
1.6. Electrical Characteristics ............................................................................................................................12  
1.6.1. Analog Input Parameters .....................................................................................................................13  
1.6.2. External Reference Parameters (ZADC512xN / ZADC512xV int. Ref. disabled)................................13  
1.6.3. Internal Reference Parameters (ZADC512xV versions only) ..............................................................14  
1.6.4. Power Requirements............................................................................................................................14  
1.6.5. Digital Pin Parameters .........................................................................................................................15  
2
Detailed Description ..........................................................................................................................................16  
2.1. General operation.......................................................................................................................................16  
2.2. Analog Input................................................................................................................................................17  
2.3. Internal & External Reference ....................................................................................................................19  
2.4. Operation Modes........................................................................................................................................20  
2.4.1. Manual Conversion Mode....................................................................................................................20  
2.4.2. Channel Numbering in Manual Conversion Mode...............................................................................24  
2.4.3. Auto Cycling Conversion Mode............................................................................................................25  
2.4.4. Output Data Format - Conversion........................................................................................................27  
2.4.5. Internal Register Access Mode............................................................................................................28  
2.4.6. Input Data Format – Register Write Access.........................................................................................30  
2.4.7. Output Data Format – Register Read Access .....................................................................................30  
2.4.8. Internal Register Map...........................................................................................................................31  
2.4.9. Device Reset Command ......................................................................................................................35  
2.4.10. Digital Comparator and Alarm Output..................................................................................................36  
2.4.11. Digital Alarm Output Filter....................................................................................................................37  
2.5. Power-Down Management.........................................................................................................................38  
2.5.1. Immediate Full Power-Down Mode......................................................................................................38  
2.5.2. Immediate Fast Power-Down Mode.....................................................................................................38  
2.5.3. Auto Fast Power-Down Mode..............................................................................................................38  
3
Package Drawing ..............................................................................................................................................39  
© 2010 Zentrum Mikroelektronik Dresden AG — Rev. 1.1  
Data Sheet  
July 30, 2010  
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without  
the prior written consent of the copyright owner. The information furnished in this publication is PRELIMINARY and subject to  
changes without notice.  
4 of 40  
ZADC5125/5123/5121  
12-Bit, 1Msps, Simultaneous Sampling ADC Family  
List of Figures  
Figure 1: Package Pin Drawing ZADC512x / ZADC512xV family............................................................................11  
Figure 2: Basic application schematic for ZADC5125V............................................................................................16  
Figure 3: ZADC5125x Differential Inputs..................................................................................................................17  
Figure 4: ZADC5125x Single Ended Inputs..............................................................................................................17  
Figure 5: Equivalent Input Circuit in Sampling Mode ...............................................................................................18  
Figure 6: Reference Adjust Circuit............................................................................................................................19  
Figure 7: SPI transfer in Manual Conversion Mode with two active output lines .....................................................21  
Figure 8: SPI transfer with conversion start Manual Conversion Mode ...................................................................21  
Figure 9: SPI transfer in Manual Conversion Mode with one active output line.......................................................22  
Figure 10: Data transfer in Auto Mode with two active output ports.........................................................................26  
Figure 11: Data transfer in Auto Mode with different number of active channels on both cores..............................26  
Figure 12: Data transfer in Auto Mode with one active output port..........................................................................26  
Figure 13: Output data format for conversion results...............................................................................................27  
Figure 14: Reading internal registers .......................................................................................................................29  
Figure 15: Writing internal registers one by one.......................................................................................................29  
Figure 16: Writing internal registers in block mode ..................................................................................................29  
Figure 17: Data input format for Register Write Access...........................................................................................30  
Figure 18: Data output format for register access....................................................................................................30  
Figure 19: Internal Register Map..............................................................................................................................31  
Figure 20: Configuration Register Content...............................................................................................................32  
Figure 21: Device reset sequence............................................................................................................................35  
Figure 22: Alarm signal output timing when two DOUT lines are selected ..............................................................36  
Figure 23: Alarm signal output timing when only one DOUT line is selected for data output ..................................36  
Figure 24: Package Outline Dimensions ..................................................................................................................39  
© 2010 Zentrum Mikroelektronik Dresden AG — Rev. 1.1  
Data Sheet  
July 30, 2010  
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without  
the prior written consent of the copyright owner. The information furnished in this publication is PRELIMINARY and subject to  
changes without notice.  
5 of 40  
ZADC5125/5123/5121  
12-Bit, 1Msps, Simultaneous Sampling ADC Family  
List of Tables  
Table 1: Absolute Maximum Ratings..........................................................................................................................7  
Table 2: Pin list ZADC5125x ......................................................................................................................................8  
Table 3: Pin list ZADC5123x ......................................................................................................................................9  
Table 4: Pin list ZADC5121x ....................................................................................................................................10  
Table 5: Operating Conditions..................................................................................................................................12  
Table 6: Unipolar versus Bipolar Input Characteristics ............................................................................................18  
Table 7: Control Word content description for Manual Conversion Mode................................................................23  
Table 8: Channel numbering in Single Ended Input Mode.......................................................................................24  
Table 9: Channel numbering in Differential Input Mode...........................................................................................24  
Table 10: Control Word content description for Auto Cycling Conversion Mode.....................................................25  
Table 11: Control Word content description for Register Access Mode...................................................................28  
Table 12: Maximum and minimum comparator threshold values in different modes...............................................34  
Table 13: Control Word content description for Device Reset Command................................................................35  
Table 14: SSOP28 Package Dimensions for ZADC5125x devices (mm)................................................................40  
Table 15: SSOP24 Package Dimensions for ZADC5123x devices (mm)................................................................40  
Table 16: SSOP20 Package Dimensions for ZADC5121x devices (mm)................................................................40  
© 2010 Zentrum Mikroelektronik Dresden AG — Rev. 1.1  
Data Sheet  
July 30, 2010  
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without  
the prior written consent of the copyright owner. The information furnished in this publication is PRELIMINARY and subject to  
changes without notice.  
6 of 40  
ZADC5125/5123/5121  
12-Bit, 1Msps, Simultaneous Sampling ADC Family  
1 Electrical Characteristics  
1.1.  
Absolute Maximum Ratings  
Parameters apply in operation temperature range (-25°C … 85°C) and without time limitations.  
Table 1: Absolute Maximum Ratings  
Symbol  
VDD-GND  
Parameter  
AVDD to AGND, AVDD to DGND  
AGND to DGND  
Min  
-0.3  
-0.3  
-0.3  
-0.3  
-0.3  
-0.3  
Max  
6
Unit Conditions  
V
V
VAGND-DGND  
0.3  
CHA0+, CHA0-, … CHB0+, CHB0- to AGND  
VREF, VREFADJ to AGND  
Digital Inputs to DGND  
AVDD+0.3  
AVDD+0.3  
DVDD+0.3  
DVDD+0.3  
25  
V
V
V
Digital Outputs to DGND  
V
Digital Output Sink Current  
mA  
Iin  
Input current into any pin except supply pins (Latch-Up)  
Electrostatic discharge – Human Body Model (HBM)  
Electrostatic discharge – Charge Device Model (CDM)  
Maximum Junction Temperature  
Operating Temperature Range  
-100  
2000  
500  
100  
mA  
1
VHBM  
VCDM  
V
V
+150  
°C  
JCT  
OP  
Industrial version  
-25  
-65  
+85  
°C  
°C  
°C  
Storage temperature  
+150  
STG  
lead  
Lead Temperature 100%Sn  
JEDEC-J-STD-20C 260  
+300  
Lead Temperature (soldering, 10s)  
Humidity non-condensing  
°C  
2
H
Ptot  
Total power dissipation  
30  
mW  
K/W  
Thermal resistance of Package  
SSOP20 / 5.3mm  
Rthj  
100  
1
2
HBM: C = 100pF charged to VHBM with resistor R = 1.5kin series, valid for all pins  
Level 4 according to JEDEC-020A is guaranteed  
© 2010 Zentrum Mikroelektronik Dresden AG — Rev. 1.1  
Data Sheet  
July 30, 2010  
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without  
the prior written consent of the copyright owner. The information furnished in this publication is PRELIMINARY and subject to  
changes without notice.  
7 of 40  
 
 
 
ZADC5125/5123/5121  
12-Bit, 1Msps, Simultaneous Sampling ADC Family  
1.2. Package Pin Assignment ZADC5125N / ZADC5125V  
Table 2: Pin list ZADC5125x  
Package  
Name  
Direction  
Type  
Description  
pin number  
1
2
3
4
5
6
7
8
nCS  
DIN  
IN  
IN  
CMOS Digital  
CMOS Digital  
Open Drain  
Open Drain  
SUPPLY  
Active Low Chip Select  
Serial Data Input  
ALARM AP  
ALARM AN  
DGND  
OUT  
OUT  
Positive Alarm Output for Converter Core A  
Negative Alarm Output for Converter Core A  
Digital Ground  
AGND  
SUPPLY  
Analog Ground  
VREF  
I/O  
I/O  
Analog  
Reference Buffer Output / External Reference Input  
VREFADJ  
Analog  
Input to Reference Buffer Amplifier,  
n.c. for ZADC5125N Type  
9
CHA0+  
CHA0-  
IN  
IN  
IN  
IN  
IN  
IN  
IN  
IN  
IN  
IN  
IN  
IN  
Analog  
Analog  
Positive Input Analog Channel A0  
Negative Input Analog Channel A0  
Positive Input Analog Channel A1  
Negative Input Analog Channel A1  
Positive Input Analog Channel A2  
Negative Input Analog Channel A2  
Negative Input Analog Channel B2  
Positive Input Analog Channel B2  
Negative Input Analog Channel B1  
Positive Input Analog Channel B1  
Negative Input Analog Channel B1  
Positive Input Analog Channel B0  
Analog VDD  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
CHA1+  
CHA1-  
Analog  
Analog  
CHA2+  
CHA2-  
Analog  
Analog  
CHB2-  
Analog  
CHB2+  
CHB1-  
Analog  
Analog  
CHB1+  
CHB0-  
Analog  
Analog  
CHB0+  
AVDD  
Analog  
SUPPLY  
SUPPLY  
CMOS Digital  
Open Drain  
Open Drain  
CMOS Digital  
CMOS Digital  
CMOS Digital  
DVDD  
Digital VDD  
CONV  
IN  
Start Conversion  
ALARM BN  
ALARM BP  
DOUTB  
DOUTA  
SCLK  
OUT  
OUT  
OUT  
OUT  
IN  
Negative Alarm Output for Converter Core B  
Positive Alarm Output for Converter Core B  
Serial Data Output from Converter Core B  
Serial Data Output from Converter Core A  
Serial Clock Input  
© 2010 Zentrum Mikroelektronik Dresden AG — Rev. 1.1  
Data Sheet  
July 30, 2010  
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without  
the prior written consent of the copyright owner. The information furnished in this publication is PRELIMINARY and subject to  
changes without notice.  
8 of 40  
 
 
ZADC5125/5123/5121  
12-Bit, 1Msps, Simultaneous Sampling ADC Family  
1.3. Package Pin Assignment ZADC5123N / ZADC5123V  
Table 3: Pin list ZADC5123x  
Package  
Name  
Direction  
Type  
Description  
pin number  
1
2
3
4
5
6
7
8
nCS  
DIN  
IN  
IN  
CMOS Digital  
CMOS Digital  
Open Drain  
Open Drain  
SUPPLY  
Active Low Chip Select  
Serial Data Input  
ALARM AP  
ALARM AN  
DGND  
OUT  
OUT  
Positive Alarm Output for Converter Core A  
Negative Alarm Output for Converter Core A  
Digital Ground  
AGND  
SUPPLY  
Analog Ground  
VREF  
I/O  
I/O  
Analog  
Reference Buffer Output / External Reference Input  
VREFADJ  
Analog  
Input to Reference Buffer Amplifier,  
n.c. for ZADC5123N Type  
9
CHA0+  
CHA0-  
IN  
IN  
IN  
IN  
IN  
IN  
IN  
IN  
Analog  
Analog  
Positive Input Analog Channel A0  
Negative Input Analog Channel A0  
Positive Input Analog Channel A1  
Negative Input Analog Channel A1  
Negative Input Analog Channel B1  
Positive Input Analog Channel B1  
Negative Input Analog Channel B1  
Positive Input Analog Channel B0  
Analog VDD  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
CHA1+  
CHA1-  
Analog  
Analog  
CHB1-  
Analog  
CHB1+  
CHB0-  
Analog  
Analog  
CHB0+  
AVDD  
Analog  
SUPPLY  
SUPPLY  
CMOS Digital  
Open Drain  
Open Drain  
CMOS Digital  
CMOS Digital  
CMOS Digital  
DVDD  
Digital VDD  
CONV  
IN  
Start Conversion  
ALARM BN  
ALARM BP  
DOUTB  
DOUTA  
SCLK  
OUT  
OUT  
OUT  
OUT  
IN  
Negative Alarm Output for Converter Core B  
Positive Alarm Output for Converter Core B  
Serial Data Output from Converter Core B  
Serial Data Output from Converter Core A  
Serial Clock Input  
© 2010 Zentrum Mikroelektronik Dresden AG — Rev. 1.1  
Data Sheet  
July 30, 2010  
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without  
the prior written consent of the copyright owner. The information furnished in this publication is PRELIMINARY and subject to  
changes without notice.  
9 of 40  
 
 
ZADC5125/5123/5121  
12-Bit, 1Msps, Simultaneous Sampling ADC Family  
1.4. Package Pin Assignment ZADC5121N / ZADC5121V  
Table 4: Pin list ZADC5121x  
Package  
Name  
Direction  
Type  
Description  
pin number  
1
2
3
4
5
6
7
8
nCS  
DIN  
IN  
IN  
CMOS Digital  
CMOS Digital  
Open Drain  
Open Drain  
SUPPLY  
Active Low Chip Select  
Serial Data Input  
ALARM AP  
ALARM AN  
DGND  
OUT  
OUT  
Positive Alarm Output for Converter Core A  
Negative Alarm Output for Converter Core A  
Digital Ground  
AGND  
SUPPLY  
Analog Ground  
VREF  
I/O  
I/O  
Analog  
Reference Buffer Output / External Reference Input  
VREFADJ  
Analog  
Input to Reference Buffer Amplifier,  
n.c. for ZADC5121N Type  
9
CHA0+  
CHA0-  
IN  
IN  
IN  
IN  
Analog  
Analog  
Positive Input Analog Channel A0  
Negative Input Analog Channel A0  
Negative Input Analog Channel B1  
Positive Input Analog Channel B0  
Analog VDD  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
CHB0-  
Analog  
CHB0+  
AVDD  
Analog  
SUPPLY  
DVDD  
SUPPLY  
Digital VDD  
CONV  
IN  
CMOS Digital  
Open Drain  
Open Drain  
CMOS Digital  
CMOS Digital  
CMOS Digital  
Start Conversion  
ALARM BN  
ALARM BP  
DOUTB  
DOUTA  
SCLK  
OUT  
OUT  
OUT  
OUT  
IN  
Negative Alarm Output for Converter Core B  
Positive Alarm Output for Converter Core B  
Serial Data Output from Converter Core B  
Serial Data Output from Converter Core A  
Serial Clock Input  
© 2010 Zentrum Mikroelektronik Dresden AG — Rev. 1.1  
Data Sheet  
July 30, 2010  
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without  
the prior written consent of the copyright owner. The information furnished in this publication is PRELIMINARY and subject to  
changes without notice.  
10 of 40  
 
 
ZADC5125/5123/5121  
12-Bit, 1Msps, Simultaneous Sampling ADC Family  
1.5. Package Pin Drawing  
nCS  
DIN  
SCLK  
DOUTA  
DOUTB  
ALARM BP  
ALARM BN  
CONV  
ALARM AP  
ALARM AN  
DGND  
AGND  
DVDD  
VREF  
REFADJ  
CHA0+  
CHA0-  
AVDD  
CHB0+  
CHB0-  
CHB1+  
CHB1-  
CHB2+  
CHB2-  
CHA1+  
CHA1-  
CHA2+  
CHA2-  
Figure 1: Package Pin Drawing ZADC512x / ZADC512xV family  
© 2010 Zentrum Mikroelektronik Dresden AG — Rev. 1.1  
Data Sheet  
July 30, 2010  
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without  
the prior written consent of the copyright owner. The information furnished in this publication is PRELIMINARY and subject to  
changes without notice.  
11 of 40  
 
 
ZADC5125/5123/5121  
12-Bit, 1Msps, Simultaneous Sampling ADC Family  
1.6.  
Electrical Characteristics  
Table 5: Operating Conditions  
(VDD = +2.7 V to +5.25 V; fSCLK = 16 MHz (50 % duty cycle); 16 clocks/conversion cycle (1 MSPS); VREF = 2.500 V applied to VREF pin)  
Parameter  
Symbol Conditions  
Min  
Typ  
Max Unit  
DC Accuracy  
Resolution  
12  
Bits  
Relative Accuracy  
No Missing Codes  
Differential Nonlinearity  
Offset Error  
INL  
-1.0  
12  
+1.0  
LSB  
0.4  
NMC  
DNL  
Bits  
-1.0  
-4.0  
-2.5  
+1.0  
+4.0  
+2.5  
LSB  
0.5  
1.5  
1.0  
1.0  
LSB  
Gain Error  
LSB  
Gain Temperature Coefficient  
ppm/°C  
Dynamic Specifications (50 kHz sine-wave input, 5 Vpp, 1 Msps, 16 MHz external clock)  
Signal-to-Noise and Distortion Ratio  
Total Harmonic Distortion  
SINAD  
THD  
60  
71  
-80  
83  
dB  
dB  
dB  
Up to the 5th harmonic  
-76  
Spurious-Free Dynamic Range  
SFDR  
75  
VDD = 5 V  
VDD = 3 V  
39  
35  
)
Full Power Bandwidth ¹  
MHz  
Conversion Rate  
Sampling Time  
(= Track/Hold Acquisition Time)  
Ext. Clock = 16 MHz,  
2 clock cycles acquisition  
tSAMPLE  
tCONV  
0.125  
1000 µs  
Conversion Time  
Aperture Delay  
Ext. Clock = 16 MHz, 13 clocks/conversion  
812.5 ns  
1
ns  
ps  
Aperture Jitter  
< 5  
External Clock Frequency  
1
16  
MHz  
1) Full Power Bandwidth - the frequency at which the reconstructed output basically drops 3 dB  
© 2010 Zentrum Mikroelektronik Dresden AG — Rev. 1.1  
Data Sheet  
July 30, 2010  
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without  
the prior written consent of the copyright owner. The information furnished in this publication is PRELIMINARY and subject to  
changes without notice.  
12 of 40  
 
 
ZADC5125/5123/5121  
12-Bit, 1Msps, Simultaneous Sampling ADC Family  
1.6.1. Analog Input Parameters  
Parameter  
Symbol Conditions  
Min  
Typ  
Max Unit  
Analog Input  
Single-Ended, Unipolar Input Mode  
0 to VREF  
Input Voltage Range  
V
Pseudo-Differential Unipolar Input Mode  
Differential Bipolar Input Mode  
VCM to VCM+VREF  
VCM-VREF to VCM+VREF  
AVDD+  
Absolute input voltage  
Input Capacitance  
VIN  
CHxx+ or CHxx- to AGND  
-0.1  
0.1  
V
15  
pF  
1.6.2. External Reference Parameters (ZADC512xN / ZADC512xV int. Ref. disabled)  
Parameter  
Symbol Conditions  
Min  
Typ  
Max Unit  
AVDD  
V
VREF Input Voltage Range  
0.5  
+ 0.05  
VREF Input Current  
VREF = 2.5V  
150  
16  
180  
µA  
VREF Input Resistance  
k  
Shutdown VREF Input Current  
0.1  
µA  
V
VDD -  
0.5  
VREFADJ Buffer Disable Threshold  
© 2010 Zentrum Mikroelektronik Dresden AG — Rev. 1.1  
Data Sheet  
July 30, 2010  
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without  
the prior written consent of the copyright owner. The information furnished in this publication is PRELIMINARY and subject to  
changes without notice.  
13 of 40  
 
 
ZADC5125/5123/5121  
12-Bit, 1Msps, Simultaneous Sampling ADC Family  
1.6.3. Internal Reference Parameters (ZADC512xV versions only)  
Parameter  
Symbol Conditions  
Min  
Typ  
Max Unit  
Internal Reference at VREF (Reference-Buffer enabled)  
VREF Output Voltage  
TA = +25 °C  
2.490  
2.500  
2.510  
55  
V
VREF Short-Circuit Current  
VREF Temperature Coefficient  
Load Regulation  
mA  
ppm/°C  
mV  
µF  
±15  
±30  
0 to 0.2 mA output load  
0.15  
Capacitive Bypass at VREF  
Capacitive Bypass at REFADJ  
REFADJ Adjustment Range  
1
10  
0.047  
µF  
%
1.5  
External Reference at REFADJ  
Reference Buffer Gain  
REFADJ Input Current  
2.00  
±70  
0.1  
µA  
µA  
Full Power Down  
REFADJ Input Current  
Full Power-Down mode  
Conditions  
1.6.4. Power Requirements  
Parameter  
Symbol  
Min  
2.7  
2.7  
Typ  
Max  
5.25  
5.25  
5.2  
5.0  
700  
1
Unit  
V
Positive Analog Supply Voltage  
Positive Digital Supply Voltage  
AVDD  
DVDD  
V
Operating Mode int. VREF  
3.5  
3.3  
mA  
mA  
AVDD =  
DVDD =  
5.25V  
Operating Mode ext. VREF  
Fast Power-Down  
Positive Supply Current  
I(AVDD)+I(DVDD)  
IDD5.25V  
650  
µA  
Full Power-Down  
Operating Mode int. VREF  
Operating Mode ext. VREF  
Fast Power-Down  
3.3  
3.1  
5.0  
4.8  
700  
1
mA  
mA  
AVDD =  
DVDD =  
2.7V  
Positive Supply Current  
I(AVDD)+I(DVDD)  
IDD2.7V  
650  
µA  
Full Power-Down  
Fully Operational,  
FSample =1 MSPS,  
AVDD = DVDD = 5.25V,  
internal VREF deactivated  
Power Dissipation  
Power Dissipation  
PDextRef  
27.3  
26.3  
mW  
Fully Operational,  
FSample =1 MSPS,  
PDintRef  
mW  
AVDD = DVDD = 5.25V,  
internal VREF activated  
© 2010 Zentrum Mikroelektronik Dresden AG — Rev. 1.1  
Data Sheet  
July 30, 2010  
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without  
the prior written consent of the copyright owner. The information furnished in this publication is PRELIMINARY and subject to  
changes without notice.  
14 of 40  
 
 
ZADC5125/5123/5121  
12-Bit, 1Msps, Simultaneous Sampling ADC Family  
1.6.5. Digital Pin Parameters  
At TA = –25C to +85C  
Parameter  
Symbol Conditions  
Min  
Typ  
Max Unit  
Digital Inputs: DIN, SCLK, nCS, CONV  
VDD = 2.7V  
VDD = 5.25V  
VDD = 2.7V  
VDD = 5.25V  
1.9  
3.7  
V
V
Logic High Level  
Logic Low Level  
VIH  
VIL  
0.7  
1.4  
V
V
Input Leakage  
IIN  
VIN = 0V or VDD  
-50  
50  
nA  
pF  
Input Capacitance  
CIN  
5
Digital Outputs: DOUTA, DOUTB, ALARM AP, ALARM AN, ALARM BP, ALARM BN  
VH  
VL  
IOH = -16mA, VDD = 2.7V  
OH = -16mA, VDD = 5.25V  
2.2  
4.2  
V
V
V
V
High Level Output Voltage  
I
IOL = 16mA, VDD = 2.7V  
IOL = 16mA, VDD = 2.7V  
0.2  
0.4  
Low Level Output Voltage  
High-Impedance-State Output  
Current  
IOZ  
-50  
50  
nA  
Three-State Output Capacitance  
Load Capacitance  
COUT  
CLoad  
nCS = VDD  
5
pF  
pF  
30  
© 2010 Zentrum Mikroelektronik Dresden AG — Rev. 1.1  
Data Sheet  
July 30, 2010  
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without  
the prior written consent of the copyright owner. The information furnished in this publication is PRELIMINARY and subject to  
changes without notice.  
15 of 40  
 
ZADC5125/5123/5121  
12-Bit, 1Msps, Simultaneous Sampling ADC Family  
2
Detailed Description  
2.1.  
General operation  
The ZADC512x family is a set of dual core, simultaneous sampling ADCs that employ the classic successive ap-  
proximation register (SAR) converter structure. The converter architecture is based on a capacitive charge redis-  
tribution DAC merged with a resistor string DAC building a hybrid converter with excellent monotony and DNL  
properties. The Sample & Hold function is inherent to the capacitive DAC. This avoids additional active compo-  
nents in the signal path that could distort the input signal or introduce errors.  
All devices in the ZADC512x family build on the same converter core and differ only in the number of input chan-  
nels and the availability of an internal reference voltage generator. The ZADC512xV versions are equipped with a  
highly accurate internal 1.25V bandgap reference which is available at the VREFADJ pin. The bandgap voltage is  
further amplified by an internal buffer amplifier to 2.50V that is available at pin VREF. All other versions  
(ZADC512xN types) come without the internal reference and the internal buffer amplifier. They require an external  
reference supplied at VREF, with the benefit of lower power consumption.  
A basic application schematic for ZADC5125V is shown in Figure 2. ZADC5125V can also be operated with an  
external reference, if VREFADJ is tied to VDD.  
µC  
ZADC5125V  
nCS  
SCLK  
DOUTA  
DOUTB  
28  
1
2
3
4
5
6
7
DIN  
27  
26  
25  
24  
23  
ALARM AP  
10k  
ALARM AN ALARM BP  
10k  
DGND  
ALARM BN  
CONV  
+2.7V to +5.25V  
AGND  
VREF  
10 µF  
DVDD  
22  
21  
47nF  
AVDD  
VREFADJ  
CHA0+  
8
9
0.1µF  
10µF  
CHB0+ 20  
10 CHA0-  
11 CHA1+  
12 CHA1-  
13 CHA2+  
14 CHA2-  
CHB0-  
CHB1+  
CHB1-  
CHB2+  
CHB2-  
19  
18  
17  
16  
15  
Analog Inputs  
Figure 2: Basic application schematic for ZADC5125V  
© 2010 Zentrum Mikroelektronik Dresden AG — Rev. 1.1  
Data Sheet  
July 30, 2010  
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without  
the prior written consent of the copyright owner. The information furnished in this publication is PRELIMINARY and subject to  
changes without notice.  
16 of 40  
 
 
 
ZADC5125/5123/5121  
12-Bit, 1Msps, Simultaneous Sampling ADC Family  
2.2.  
Analog Input  
The analog input to the converter is fully differential. Both converter input signals are sampled during the acquisi-  
tion period enabling the converter to be used in fully differential applications where both signals can vary over  
time.  
The input signals can be applied in differential or single ended manner. In differential input mode, each input  
channel is connected to a pair of inputs (e.g. CHA0+ and CHA0-, CHB0+ CHB0-). There is a maximum of three  
input channels available per core and a total of 6 input channels per IC for ZADC5125x types (see Figure 3). In  
single ended mode the input channels refer to a common input reference at CH0A+ and CH0B+. Accordingly,  
there is a maximum of 5 input channels available per core and a total of 10 input channels available per IC for  
ZADC5125x types.  
ZADC5125V  
nCS  
SCLK 28  
1
2
3
4
5
6
7
DIN  
DOUTA  
27  
ALARM AP  
DOUTB  
26  
ALARM AN ALARM BP  
25  
24  
23  
DGND  
AGND  
ALARM BN  
CONV  
DVDD  
22  
21  
V
V
REF  
AVDD  
8
9
REFADJ  
CHA0+  
CHB0+ 20  
CHB0- 19  
10 CHA0-  
11 CHA1+  
12 CHA1-  
13 CHA2+  
14 CHA2-  
CHB1+  
CHB1-  
CHB2+  
CHB2-  
18  
17  
16  
15  
Figure 3: ZADC5125x Differential Inputs  
Figure 4: ZADC5125x Single Ended Inputs  
The selection between single ended or differential operation mode is made by software. The respective bit SGL /  
DIFF in the command word defines the behaviour. Besides this the device supports two different conversion  
modes: Unipolar Mode and Bipolar Mode. Table 6 on the following page shows the respective characteristics.  
All input signals at CHA0+ … CHA2- and CHB0+ … CHB2- are generally allowed to swing between –0.2V and  
AVDD+0.2V. There is no general limit for the Common Mode Voltage range of the input signals. It can swing over  
the entire input voltage range of the channels. However, depending on the selected conversion mode and the in-  
put voltage relations the output code range of the converter can be limited.  
To maintain the full output code range the following conditions apply:  
-
-
Unipolar Mode:  
VCOM + VRef  
CM + VRef / 2 < AVDD;  
VCM - VRef / 2 > 0V  
< AVDD  
Differential Mode:  
V
VCM = ½ (Vinp + Vinn)  
© 2010 Zentrum Mikroelektronik Dresden AG — Rev. 1.1  
Data Sheet  
July 30, 2010  
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without  
the prior written consent of the copyright owner. The information furnished in this publication is PRELIMINARY and subject to  
changes without notice.  
17 of 40  
 
 
ZADC5125/5123/5121  
12-Bit, 1Msps, Simultaneous Sampling ADC Family  
Table 6: Unipolar versus Bipolar Input Characteristics  
Mod  
e
Input  
Rang  
e
Output  
Cod-  
ing  
Input Configuration  
Transfer Characteristic  
Uni-  
0 V … Straigh  
polar Vref  
Mode  
t binary  
4095  
1
Vinp  
VRef p-p  
ADC  
COM  
Common  
Voltage  
0
VCOM  
VCOM  
+VRef  
VIN  
Bipo- -Vref  
Two's  
comple  
ment  
lar  
…
2047  
Mode Vref  
V
V
p-p  
inp  
Ref  
ADC  
0
V
Ref p-p  
VCM  
V
inn  
-
-2048  
-VRef  
0
VRef  
VIN  
The average input current on the analog inputs depends on the conversion rate. The signal source must be capa-  
ble of charging the internal sampling capacitors within the acquisition time tACQ to the required accuracy. The  
equivalent input circuit in sampling mode is shown in Figure 5.  
Figure 5: Equivalent Input Circuit in Sampling Mode  
© 2010 Zentrum Mikroelektronik Dresden AG — Rev. 1.1  
Data Sheet  
July 30, 2010  
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without  
the prior written consent of the copyright owner. The information furnished in this publication is PRELIMINARY and subject to  
changes without notice.  
18 of 40  
 
 
ZADC5125/5123/5121  
12-Bit, 1Msps, Simultaneous Sampling ADC Family  
The following equation provides a rough hand calculation for a source impedance RS that is required to settle out  
a DC input signal in a given acquisition time  
tACQ  
RS   
RSW  
7 CIN  
For example, if fSCLK = 16MHz, the acquisition time is tACQmin = 128ns. Thus the output impedance RS of a signal  
source reference to AGND must be less than  
128ns  
RS   
600Ω 990Ω  
7 (5pF 13pF/2)  
If the output impedance of the source is higher than the calculated maximum RS the acquisition time must be ex-  
tended by controlling the CONV input to ensure 12 bit accuracy. Another option is to add a capacitor of >20 nF to  
the individual input. Although this limits the bandwidth of the input signal because an RC low pass filter is build  
together with the source impedance, it may be useful for certain applications.  
The small-signal bandwidth of the input tracking circuitry is 40 MHz. Hence it is possible to digitize high-speed  
transient events and periodic signals with frequencies exceeding the ADC’s sampling rate. This allows the appli-  
cation of certain under-sampling techniques like down conversion of modulated high frequency signals.  
Be aware that under-sampling techniques still require a bandwidth limitation of the input signal to less than the  
Nyquist frequency of the converter to avoid aliasing effects. Also, the output impedance of the input source must  
be very low to achieve the mentioned small signal bandwidth in the overall system.  
2.3. Internal & External Reference  
ZADC512xV family members are equipped with a highly accurate internal 2.5V reference voltage source. The  
voltage is generated from a trimmed 1.25V bandgap with an internal buffer that is set to a gain of 2.00. The band-  
gap voltage is supplied at VREFADJ with an output impedance of 20kΩ. An external capacitor of 47nF at VRE-  
FADJ is useful to further decrease noise on the internal reference.  
The VREFADJ pin also provides an opportunity to externally adjust the bandgap voltage in a limited range (see  
Figure 6) as well as the possibility to overdrive the internal bandgap with an external 1.25V reference. The internal  
bandgap reference and the VREF buffer can be shut down completely by setting VREFADJ to VDD. This reduces  
power consumption of the ZADC512xV devices and allows the supply of an external reference at VREF.  
VDD = +2.7V … +5.25V  
ZADC512xV  
510kΩ  
VREFADJ  
47nF  
Figure 6: Reference Adjust Circuit  
© 2010 Zentrum Mikroelektronik Dresden AG — Rev. 1.1  
Data Sheet  
July 30, 2010  
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without  
the prior written consent of the copyright owner. The information furnished in this publication is PRELIMINARY and subject to  
changes without notice.  
19 of 40  
 
 
ZADC5125/5123/5121  
12-Bit, 1Msps, Simultaneous Sampling ADC Family  
ZADC512xN devices do not contain the internal bandgap or the VREF buffer. An external reference must be sup-  
plied all the time at VREF.  
The value of the reference voltage at VREF sets the input range of the converter and the analog voltage weight of  
each digital code. The size of the LSB (least significant bit) is equal to the value of VREF (reference to AGND)  
divided by 4096. For example at a reference voltage of 2.500V, the voltage level of a LSB is equal to 610μV.  
It is important to know that certain inherent errors in the A/D converter like offset or gain error will appear to in-  
crease at lower reference voltages while the actual performance of the device does not change. For instance a  
static offset error of 1.22mV is equal to 2 LSB at 2.5V reference, while it is equivalent to 5.0 LSB for a reference  
voltage of 1.0V  
Likewise, the uncertainty of the digitized output code will increase with lower LSB size (lower VREF). Once the  
size of an LSB is below the internal noise level, the output code will start to vary around a mean value for constant  
DC input voltages. Such noise can be reduced by averaging consecutive conversions or applying a digital filter.  
The average current consumption at VREF depends on the value of VREF and the sampling frequency. Two ef-  
fects contribute to the current at VREF, a resistive connection from VREF to AGND and charge currents that re-  
sult from the switching and recharging of the capacitor array (CDAC) during sampling and conversion. For an ex-  
ternal reference of 2.5V the input current at VREF is approximately 150µA.  
2.4. Operation Modes  
All devices out of the ZADC512x family are controlled by a 4 or 5-wire serial interface that is compatible to SPI™,  
QSPI™ and MICROWIRE™ devices without external logic.  
There are four different operation modes supported:  
1) Manual Conversion Mode  
2) Auto Cycling Conversion Mode  
3) Internal Register Access mode  
4) Device Reset  
2.4.1. Manual Conversion Mode  
In Manual Mode, the desired input channels for core A and core B (channel number + single ended / differential  
input mode selection) as well as the converter configuration (unipolar / bipolar mode) must transmitted to the de-  
vice via a control word on SPI input DIN before a conversion can be triggered. A control word always starts with a  
leading ‘1’, the so called Start Bit. Any number of logic ‘0’ bits clocked into DIN after nCS turned low (‘0’) has no  
effect until the Start Bit ‘1’ is received. As soon as the 16-bit wide control word is completed, a conversion can be  
started by turning the CONV input from low (‘0’) to high (‘1’).  
The acquisition phase, which is automatically started after receiving the 14th bit in the control word while  
CONV = ‘0’, is stopped immediately on the rising edge of CONV (asynchronous behaviour). The conversion proc-  
ess, however, is started on the next falling edge of SCLK after CONV turned high (see Figure 8). It is required that  
the CONV signal overlaps the falling edge of the SCLK signal by at least 10ns.  
© 2010 Zentrum Mikroelektronik Dresden AG — Rev. 1.1  
Data Sheet  
July 30, 2010  
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without  
the prior written consent of the copyright owner. The information furnished in this publication is PRELIMINARY and subject to  
changes without notice.  
20 of 40  
 
 
ZADC5125/5123/5121  
12-Bit, 1Msps, Simultaneous Sampling ADC Family  
As soon as the conversion is started, output data is provided either in parallel mode on DOUTA and DOUTB or  
block wise serial on DOUTA as shown in Figure 7 and Figure 9. The desired output mode is also defined in the  
control word (bit AB/A).  
After the conversion is completed the converter moves to acquisition state if CONV has turned to low (‘0’) in the  
mean time. In case CONV stays logic high at the output cycle of LSB-1, the start of the acquisition phase is de-  
layed until CONV turns to low (‘0’). Once CONV has turned low, must remain low for at least 3 clock cycles before  
it may turn high again to start the next acquisition. This acquisition delay feature is provided to allow accurate op-  
eration of the converter at very low sample rates.  
Available timing window for rising edge of CONV  
12 bits resolution, 1 MSPS, fclk = 16 MHz  
Condition for maximum speed: 2.0 TSCLK < Tacq < 3.0 TSCLK  
CONV  
1
14 15 16  
Acquisition  
1
15 16  
SCLK  
DIN  
Conversion  
UNI/ SGL/  
TacqMIN = 2 TSCLK (125 ns) ٛ maximum sample rate @16MHz  
1 MSPS (16 clock cycles needed)  
UNI/ SGL/  
BIP DIF  
AB/  
UNI/ SGL/  
BIP DIF  
UNI/ SGL/  
BIP DIF  
AB/  
A
S
0
M1 M0 A2 A1 A0  
B2 B1 B0  
P1 P0  
A
S
0
M1 M0 A2 A1 A0  
B2 B1 B0  
P1 P0  
BIP DIF  
Activation of  
Input-MUX  
LSB  
-1  
LSB  
LSB  
-1  
0
RI MSB  
LSB  
0
0
RI MSB  
0
0
DOUT Values  
Alarm  
Assert / Reset  
Reset  
Assert  
Reset Assert  
Figure 8: SPI transfer with conversion start Manual Conversion Mode  
t1  
t2  
nCS  
CONV  
SCLK  
1
16  
1
16  
DIN  
S
CONTROL WORD 0  
S
CONTROL WORD 1  
S
DOUTA  
DOUTB  
0
0
RI  
RI  
CONVERSION RESULT 0  
CONVERSION RESULT 0  
Figure 7: SPI transfer in Manual Conversion Mode with two active output lines  
© 2010 Zentrum Mikroelektronik Dresden AG — Rev. 1.1  
Data Sheet  
July 30, 2010  
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without  
the prior written consent of the copyright owner. The information furnished in this publication is PRELIMINARY and subject to  
changes without notice.  
21 of 40  
 
 
ZADC5125/5123/5121  
12-Bit, 1Msps, Simultaneous Sampling ADC Family  
Name  
Description  
Width of CONV signal  
Low period of CONV signal before rising edge  
Min.  
Typ.  
Max.  
Unit  
clk  
t1  
t2  
1
3
13  
clk  
Figure 9: SPI transfer in Manual Conversion Mode with one active output line  
A rising edge of the CONV signal is only accepted under certain conditions:  
1) Reception of initial control word is completed and next control word has not yet started or still in Start  
Bit receiving phase  
2) No other conversion is running (output of conversion data is completed + 1 additional CLK cycle ex-  
pired to ensure minimum acquisition time of at least 2 CLK cycles (see Figure 8).  
3) The device is not in Reset or Register Access Mode (see chapters 2.4.5 and 2.4.9)  
If CONV = ‘0’ and no rising edge of CONV occurs even if the above mentioned conditions are fulfilled, the device  
remains in acquisition state and no conversion is started. DOUTx will put out ‘0’ in this case.  
If a rising edge of CONV is received while SCLK is running and no new control word data was received during the  
last conversion, a new conversion with the previous settings is started. This however is only true, if nCS stayed  
low the entire time.  
As soon as nCS toggles high, a running transmission is stopped and the SPI interface is reset. DOUTA and  
DOUTB move to high impedance state and any data on DIN will be ignored. A running conversion, however, is  
not aborted. If nCS goes low again, the next high bit clocked into DIN is recognized as a start bit which immedi-  
ately terminates a possible active conversion.  
© 2010 Zentrum Mikroelektronik Dresden AG — Rev. 1.1  
Data Sheet  
July 30, 2010  
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without  
the prior written consent of the copyright owner. The information furnished in this publication is PRELIMINARY and subject to  
changes without notice.  
22 of 40  
 
ZADC5125/5123/5121  
12-Bit, 1Msps, Simultaneous Sampling ADC Family  
Table 7: Control Word content description for Manual Conversion Mode  
© 2010 Zentrum Mikroelektronik Dresden AG — Rev. 1.1  
Data Sheet  
July 30, 2010  
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without  
the prior written consent of the copyright owner. The information furnished in this publication is PRELIMINARY and subject to  
changes without notice.  
23 of 40  
 
ZADC5125/5123/5121  
12-Bit, 1Msps, Simultaneous Sampling ADC Family  
2.4.2. Channel Numbering in Manual Conversion Mode  
The channel number in Manual Mode is represented by binary combinations as shown at Table 8 and Table 9.  
Table 8: Channel numbering in Single Ended Input Mode  
Table 9: Channel numbering in Differential Input Mode  
In Auto mode each channel has a corresponding bit in Auto Sequence Program Register and Auto Mode Config  
Register. For details see register description in chapter 2.4.8.  
© 2010 Zentrum Mikroelektronik Dresden AG — Rev. 1.1  
Data Sheet  
July 30, 2010  
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the prior written consent of the copyright owner. The information furnished in this publication is PRELIMINARY and subject to  
changes without notice.  
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ZADC5125/5123/5121  
12-Bit, 1Msps, Simultaneous Sampling ADC Family  
2.4.3. Auto Cycling Conversion Mode  
In Auto Cycling Mode, the desired input channels for core A and core B (channel number + single ended / differ-  
ential input mode selection) as well as the converter configuration (unipolar / bipolar mode) must be defined in an  
internal register set before a conversion can be started. The channel sequence and operation modes can be con-  
figured independently for the ADC cores. The available register set is shown in Figure 19 on page 31. The regis-  
ters can be programmed and read back using the Register Access Mode described below.  
Once the registers are setup by the user, an Auto Cycling Control Word must be sent to activate the Auto Cycling  
Conversion Mode in the internal state machine of the IC. The cycle counters will always start on the lowest acti-  
vated channel number (as defined in the register bank) and keep counting upwards at the end of each conversion.  
Once the highest activated channel number is reached, the counter will roll over and select the lowest channel  
number for the next conversion.  
The counters can be reset manually by setting the R/K bit in the Auto Cycling Control Word = ‘1’. This may be  
useful to react on interrupts which require immediate conversion of the highest priority channel. The channel  
counters are also reset by the Device Reset command described in chapter 2.4.9 and on Power-On Reset. The  
status of the channel counters is not affected by the nCS signal.  
Because the cycle counter is incremented automatically at the end of each conversion, it is not necessary to send  
further Auto Cycling Control Words on the SPI interface after the first initialization. DIN must be kept low (‘0’) in  
this case. A new conversion is started on the rising edge of the CONV signal, just as in Manual Mode. The timing  
requirements for the CONV signal remain the same and the output data timing at SDOA an SDOB lines too.  
Sending an Auto Cycling Control Word with R/K bit = ‘0’ (keep counting) has no influence to the counter state,  
once the Auto Mode was activated.  
Table 10: Control Word content description for Auto Cycling Conversion Mode  
© 2010 Zentrum Mikroelektronik Dresden AG — Rev. 1.1  
Data Sheet  
July 30, 2010  
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the prior written consent of the copyright owner. The information furnished in this publication is PRELIMINARY and subject to  
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ZADC5125/5123/5121  
12-Bit, 1Msps, Simultaneous Sampling ADC Family  
Figure 10 shows data transfers operations in Auto Cycling Mode. The symbols k, m, n and p, q, r represent acti-  
vated channels for core A and core B which are consecutively scanned. The channel counters are continuously  
incrementing. If a different number of channels is selected for each core, for example 2 channels for core A and 3  
channels for core B, channels in core A will be scanned more frequently than the channels in core B. This means  
the channel counter with fewer channels will roll-over faster than the channel counter with more channels. This is  
shown in Figure 11.  
Figure 10: Data transfer in Auto Mode with two active output ports  
Figure 11: Data transfer in Auto Mode with different number of active channels on both cores  
Figure 12: Data transfer in Auto Mode with one active output port  
© 2010 Zentrum Mikroelektronik Dresden AG — Rev. 1.1  
Data Sheet  
July 30, 2010  
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the prior written consent of the copyright owner. The information furnished in this publication is PRELIMINARY and subject to  
changes without notice.  
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ZADC5125/5123/5121  
12-Bit, 1Msps, Simultaneous Sampling ADC Family  
If the AB/A bit is set to `0` in the Auto Mode Config Register (see Register Map), conversion data is returned only  
at the DOUTA port. This is shown at Figure 12. In this case additional CONV pulses are also ignored like in the  
Manual Mode, if they occur while a running output process is not yet finished.  
In Auto Cycling Conversion Mode power down functions are not supported.  
2.4.4. Output Data Format - Conversion  
Data sent over the SDO lines has the format shown in Figure 13. The first bit of the 16-bit frame that is returned  
by the device (bit 15) is always ‘0’. The second bit (Bit 14) indicates the reset status of the internal registers. It is  
set to ‘1’ at power on reset and after each software triggered reset of the ZADC512x device. It will remain `1` until  
first write cycle is performed to an internal register. The idea of this bit is to signal a data loss of user configured  
register data that could be caused by EMC or any other interference to the microcontroller. The Frame is com-  
pleted by two zeros.  
In configurations where only DOUTA is used as a single output channel, the output frame format is generally kept  
the same, except that two frames are transmitted one after another for the result of Core A and Core B.  
After Reset of IC  
14  
1
0
0
8
7
DO DO DO DO DO DO DO DO DO DO DO DO  
11 10  
0
0
9
8
7
6
5
4
3
2
1
0
0
When internal registers  
are configured by user  
Figure 13: Output data format for conversion results  
© 2010 Zentrum Mikroelektronik Dresden AG — Rev. 1.1  
Data Sheet  
July 30, 2010  
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the prior written consent of the copyright owner. The information furnished in this publication is PRELIMINARY and subject to  
changes without notice.  
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ZADC5125/5123/5121  
12-Bit, 1Msps, Simultaneous Sampling ADC Family  
2.4.5. Internal Register Access Mode  
In this mode it is possible to access the internal registers of the ADC. Access type can be read or write and can  
be performed over a single register or a certain number of registers in a row (write access only). The mode is se-  
lected if the combination `10` is send after the start bit in the control word.  
Table 11: Control Word content description for Register Access Mode  
In Internal Registers Access Mode only the DOUTA line is used. DOUTB is in tri-state mode (high Z). When a  
write access is performed DOUTA returns zeros, as shown in Figure 15 and Figure 16.  
The specified Address Counter Value C[4:0] determines how many frames will be interpreted as data until a new  
control word is accepted. The data bits are clocked out on the falling edge of SCLK. The register information is  
shifted out with the MSB first. Once the entire register data is shifted out, the remaining bit positions in the 16-bit  
data frame are filled with zeros.  
© 2010 Zentrum Mikroelektronik Dresden AG — Rev. 1.1  
Data Sheet  
July 30, 2010  
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the prior written consent of the copyright owner. The information furnished in this publication is PRELIMINARY and subject to  
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ZADC5125/5123/5121  
12-Bit, 1Msps, Simultaneous Sampling ADC Family  
Figure 14 shows a typical reading sequence. Figure 15 and Figure 16 show the two possible options for register  
write access. Attempts to access invalid registers are processed but have no effect. For example, if counter + ad-  
dress number is higher than the maximum address of the register bank, data for addresses that are not valid, is  
discarded. However, no new start bit is accepted until the counter has reached the specified value.  
Figure 14: Reading internal registers  
Figure 15: Writing internal registers one by one  
Figure 16: Writing internal registers in block mode  
© 2010 Zentrum Mikroelektronik Dresden AG — Rev. 1.1  
Data Sheet  
July 30, 2010  
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the prior written consent of the copyright owner. The information furnished in this publication is PRELIMINARY and subject to  
changes without notice.  
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ZADC5125/5123/5121  
12-Bit, 1Msps, Simultaneous Sampling ADC Family  
2.4.6. Input Data Format – Register Write Access  
Register write access is managed by 16-bit wide data frames per address. Since the internal registers are only 12  
bits wide, the first 12 bits of the 16-bit data frame carry the information to be written to the register. The last 4 bits  
(LSBs) are don’t care and will not be processed by the IC.  
Figure 17: Data input format for Register Write Access  
2.4.7. Output Data Format – Register Read Access  
Register read access is managed by 16-bit wide data frames per address. Since the internal registers are only 12  
bits wide, the first 12 bits of the 16-bit data frame carry the information that is read from the register. The output  
frame starts with a leading ‘0’. The last 3 bits (LSBs) are also set to ‘0’ by the IC.  
Figure 18: Data output format for register access  
© 2010 Zentrum Mikroelektronik Dresden AG — Rev. 1.1  
Data Sheet  
July 30, 2010  
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the prior written consent of the copyright owner. The information furnished in this publication is PRELIMINARY and subject to  
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ZADC5125/5123/5121  
12-Bit, 1Msps, Simultaneous Sampling ADC Family  
2.4.8. Internal Register Map  
The ZADC512x family contains two types of internal registers. The first group stores configuration data. It is rep-  
resented by four registers in the address range from 0x00 to 0x03. The registers are named Auto Mode Config  
Register, Auto Sequence Program Register, Digital Filter Config Register and Alarm Enable Register.  
The second group contains Threshold Level data for the digital comparators. There are two threshold levels avail-  
able per channel. Threshold Register addresses start at 0x04 and end at 0x17.  
All registers can be accessed for reading and writing.  
Register Map  
0x00  
0x01  
0x02  
0x03  
0x04  
0x05  
0x06  
0x07  
0x08  
0x09  
0x0A  
0x0B  
0x0C  
0x0D  
0x0E  
0x0F  
0x10  
0x11  
0x12  
0x13  
0x14  
0x15  
0x16  
0x17  
Auto Mode Config Register  
Auto Sequence Program Register  
Dig Filter Config Register  
Alarm Enable Register  
CHA0 High Threshold  
CHA0 Low Threshold  
CHA1 High Threshold  
CHA1 Low Threshold  
CHA2 High Threshold  
CHA2 Low Threshold  
CHA3 High Threshold  
CHA3 Low Threshold  
CHA4 High Threshold  
CHA4 Low Threshold  
CHB0 High Threshold  
CHB0 Low Threshold  
CHB1 High Threshold  
CHB1 Low Threshold  
CHB2 High Threshold  
CHB2 Low Threshold  
CHB3 High Threshold  
CHB3 Low Threshold  
CHB4 High Threshold  
CHB4 Low Threshold  
C
O
R
E
A
C
O
R
E
B
Figure 19: Internal Register Map  
© 2010 Zentrum Mikroelektronik Dresden AG — Rev. 1.1  
Data Sheet  
July 30, 2010  
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the prior written consent of the copyright owner. The information furnished in this publication is PRELIMINARY and subject to  
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ZADC5125/5123/5121  
12-Bit, 1Msps, Simultaneous Sampling ADC Family  
Figure 20: Configuration Register Content  
Auto Mode Config Register:  
Default value is 0x000. The register is used to configure respective channels in Auto Mode. Detailed bit allocation  
is shown in Figure 20. The bits in this register have the following meaning:  
AB/A  
– The same meaning as in Manual Mode Configuration Word.  
`1` = DOUTA and DOUTB lines are used to output data. `0` - only DOUTA  
CHA SE/D – Core A single ended/differential mode selection. `1` - single ended, `0` - differential  
CHB SE/D – Core B single ended/differential mode selection. `1` - single ended, `0` - differential  
CHA[4:0]  
– Determines unipolar / bipolar operation for the corresponding channel number. Setting CHAx to  
`1` activates the unipolar straight binary code format for the respective channel, `0` in CHAx bit  
activates the bipolar two`s complement format.  
If CHA SE/D is set to `0`, core A is in differential mode. Consequently a maximum of 3 channels is  
available in ZADC5125x Types. In this case, only the bits CHA[2:0] are interpreted. CHA[4:3] are  
accessible, but do not affect the operation of the ADC.  
In differential mode the bit CHA0 corresponds to the pair {CHA0+, CHA0-}, CHA1 to the pair  
{CHA1+, CHA1-}, CHA2 to the pair {CHA2+, CHA2-}.  
If CHA SE/D is set to `1`, core A is in single ended mode. Consequently a maximum of 5 chan-  
nels is available in ZADC5125x Types. In this case the bits CHA[4:0] are active. In single-ended  
mode bit CHA0 corresponds to pair {CHA0+, CHA0-}, CHA1 to pair {CHA0+, CHA1+}, CHA2 to  
pair {CHA0+, CHA1-}, CHA3 to pair {CHA0+, CHA2+}, CHA4 to pair {CHA0+, CHA2-}.  
CHB[4:0]  
– This is equal to CHA[4:0] but only for B channels.  
© 2010 Zentrum Mikroelektronik Dresden AG — Rev. 1.1  
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the prior written consent of the copyright owner. The information furnished in this publication is PRELIMINARY and subject to  
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Data Sheet  
July 30, 2010  
32 of 40  
 
ZADC5125/5123/5121  
12-Bit, 1Msps, Simultaneous Sampling ADC Family  
Auto Sequence Program Register:  
Default value is 0b111110111110. The register is used to activate respective channels in Auto Mode. The bits  
CHA[4:0] and CHB[4:0] have the same relation to physical channels as in the Auto Mode Config Register (see  
above).  
-
-
If set to ‘1’ the respective channel is included in the Auto Cycle Sequence.  
If set to ‘0’ the respective channel is skipped. If the device is forced to Auto Mode without writing any in-  
ternal register, all channels are selected to be converted.  
If the register is cleared (no channel is selected), no conversion will be started, even if the device is ready for a  
conversion and a CONV signal is received. Consequently, the data returned at DOUT is ‘0’. However, this is any-  
way always the case if no conversion is running. The don’t care bit (marked with X) does not affect the device op-  
eration.  
Digital Filter Config Register:  
Default value is 0x000. The register is used to configure the digital filters in both operation modes, Manual Con-  
version Mode and Auto Cycling Conversion Mode. The bits in this register determine the activation of the digital  
filters for corresponding channels. For a detailed description of the filter function refer to chapter 2.4.11 The bits  
CHA[4:0] and CHB[4:0] have the same relation to physical channels as in the Auto Mode Config Register.  
-
-
If set to ‘1’ the filter for the respective channel is activated and the Alarm pins will show the status of the  
related channel filter.  
If set to ‘0’ the digital filter for the respective channel is turned off. The Alarm pins will directly show the  
output of the digital comparator.  
Don’t care bits (marked with X) do not affect the device operation.  
Alarm Enable Register:  
Default value is 0x000. The register is used to configure the Alarm Outputs in both operation modes, Manual Con-  
version Mode and Auto Cycling Conversion Mode. The bits in this register determine the activation of the alarm  
feature for corresponding channels. The bits CHA[4:0] and CHB[4:0] have the same relation to physical channels  
as in the Auto Mode Config Register.  
-
If set to ‘1’ the alarm feature is activated for the respective channel. Depending on the status of the corre-  
sponding bit in the Digital Filter Config Register either the outputs of the digital comparators are visible at  
the Alarm output pins or the output of the filter is available.  
-
If set to ‘0’ the respective digital comparators and the filters are held in reset. The Alarm Output moves to  
High-Z Mode for time of the Alarm output phase of the respective channel.  
Don’t care bits (marked with X) do not affect the device operation.  
© 2010 Zentrum Mikroelektronik Dresden AG — Rev. 1.1  
Data Sheet  
July 30, 2010  
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ZADC5125/5123/5121  
12-Bit, 1Msps, Simultaneous Sampling ADC Family  
High and Low Threshold Registers:  
Two registers are available per channel, fully readable and writable. All threshold registers have a width of 12 bits.  
Default values are 0x000. The user has to care for the correct setting of the threshold register in relation to the  
selected output code (unipolar straight binary vs. bipolar two’s complement). The maximum and minimum thresh-  
old values for the two different modes are shown in the following table.  
Table 12: Maximum and minimum comparator threshold values in different modes  
Unipolar  
0xFFF  
0x000  
Bipolar  
0x7FF  
0x800  
High Threshold  
Low Threshold  
© 2010 Zentrum Mikroelektronik Dresden AG — Rev. 1.1  
Data Sheet  
July 30, 2010  
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ZADC5125/5123/5121  
12-Bit, 1Msps, Simultaneous Sampling ADC Family  
2.4.9. Device Reset Command  
If the control word content is 0b111X_XXXX_XXXX_XXXX it is interpreted as Device Reset. This command can  
be issued like any other control word. It is fully defined by the first three bits of the data frame already. Neverthe-  
less, the reset is performed at the end of the 16-bit frame to avoid confusion in the protocol layer.  
When executing the Device Reset the entire internal logic is reset, Alarm outputs are reset to inactive state, inter-  
nal registers are set to default values and the Reset Indicator flag is activated.  
The Reset Indicator is part of every output word that is returned with conversion results (see above). The Reset  
Indicator flag is reset at the first register write access that is performed after a device reset. The Reset Indicator is  
also activated by Power-On Reset. Thus it can also signal undesired resets of the threshold values after EMC  
events to the MCU.  
If only one DOUT line (DOUTA) is used to output the conversion results, the output process will be cancelled at  
the time when the reset is generated, no matter how many bits are left to be transmitted.  
Table 13: Control Word content description for Device Reset Command  
BIT12 BIT11 BIT10 BIT9 BIT8 BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1  
BIT15 BIT14 BIT13  
MSB  
BIT0  
LSB  
S
1
1
X
X
X
X
X
X
X
X
X
X
X
X
X
BIT  
15(MSB)  
14  
NAME  
DESCRIPTION  
S
1
Start Bit: The first logic `1` bit after CS goes low defines the beginning of the control word  
Mode of Operation: ’11' = Device Reset  
13  
1
12 - 0(LSB)  
X
Don`t care  
Figure 21: Device reset sequence  
© 2010 Zentrum Mikroelektronik Dresden AG — Rev. 1.1  
Data Sheet  
July 30, 2010  
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ZADC5125/5123/5121  
12-Bit, 1Msps, Simultaneous Sampling ADC Family  
2.4.10. Digital Comparator and Alarm Output  
All devices of the ZADC512x family provide digital comparators to detect various overload or out-of-range condi-  
tions in the input signal. There are two comparators per converter core, one to detect exceedance and one to de-  
tect undercut of provided threshold values.  
The comparators are working sequentially bit by bit starting at the MSB in the same manner as the conversion  
result is generated. The comparators are 12 bits wide.  
If the result is higher than the value in high threshold register, or lower than the value in low threshold register, an  
alarm event is issued. An alarm event drives the Alarm outputs high (‘1’). If no alarm event is present, the Alarm  
outputs are in tri-state, requiring an external pull-down resistor. By that, more than one Alarm output can be con-  
nected together.  
The alarm signal is always issued at the falling clock edge of the LSB output. See Figure 22 for details. The signal  
is always cleared at falling edge of the 2nd clock of next output cycle. The alarm output timing for operation on a  
single DOUT line is shown in Figure 23.  
Figure 22: Alarm signal output timing when two DOUT lines are selected  
Figure 23: Alarm signal output timing when only one DOUT line is selected for data output  
© 2010 Zentrum Mikroelektronik Dresden AG — Rev. 1.1  
Data Sheet  
July 30, 2010  
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the prior written consent of the copyright owner. The information furnished in this publication is PRELIMINARY and subject to  
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ZADC5125/5123/5121  
12-Bit, 1Msps, Simultaneous Sampling ADC Family  
2.4.11. Digital Alarm Output Filter  
The outputs of the comparators can additionally be filtered to avoid fail reaction of the microprocessor on noise in  
the signal. If the corresponding bits in Digital Filter Config Register are set, the alarm output filter is activated.  
Every channel has one corresponding bit in the register. If the value of the bit is “0”, the output of the comparators  
is sent to the Alarm Output pins directly without any filtering. If the value is “1”, the comparator outputs are filtered  
with a 3-stage moving average filter.  
The filter is implemented as a 2-bit up-and-down counter without overflow. If an Alarm Event is generated by the  
comparator, the counter is counted up. If a No Alarm Event is generated, the counter is counted down. The reset  
value is 0x0. A filter transition from 0x2 to 0x3 will set the alarm output to ‘1’. A filter transition from 0x1 to 0x0 will  
reset the alarm output to ‘0’.  
If the filter is in state 0x0, the alarm output is always tri-state (tied to ‘0’ by external pull down), in state 0x3, it is  
always ‘1’. The states 0x1 and 0x2 are hysteresis states. The alarm output is either ‘1’ or tri-state in those states.  
The filter is reset, when a write access on the appropriate threshold level register occurs. This is to make sure,  
that after a possible modification of the respective threshold level the filter starts with a cleared status.  
If the filter is switched off, its contents are reset. Hence it will always start with cleared value when it is activated  
again.  
© 2010 Zentrum Mikroelektronik Dresden AG — Rev. 1.1  
Data Sheet  
July 30, 2010  
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ZADC5125/5123/5121  
12-Bit, 1Msps, Simultaneous Sampling ADC Family  
2.5. Power-Down Management  
All devices of the ZADC512x family support three different power-down modes to reduce power consumption in  
idle states.  
1) Immediate Full Power-Down  
2) Immediate Fast Power-Down  
3) Auto Fast Power-Down  
To wake up the IC from any Power-Down state, it is sufficient to send a Start Bit while nCS is LOW. However, the  
turn on time differs between Full Power-Down Mode and Fast Power-Down Mode as described below.  
2.5.1. Immediate Full Power-Down Mode  
All analog components are completely shut off. The current consumption of the device goes down be below 1µA.  
The Full Power-Down Mode is selected by transmitting a Manual Mode Control Word with PD1 = ‘0’, PD0 = ‘0’ on  
the SPI interface. It becomes activated immediately after complete reception of the Control Word.  
The Wake-Up time for the converter itself is < 3µs but the correctness of the result also depends on the settling  
time of the VREF. The internal VREF buffer (ZADC512xV types) provides a settling time of about 9 ms to reach  
12 bit accuracy under the assumption of the recommended external buffer capacitors (VREFADJ = 47nF, VREF =  
4.7µF).  
If VREF is supplied externally at the VREF pin, the turn on time from Full Power-Down mode is < 3µs. Thus, only  
the time of two consecutive dummy conversions is needed in this case to get a correct conversion result after Full  
Power-Down.  
2.5.2. Immediate Fast Power-Down Mode  
In Immediate Fast Power-Down Mode only the comparators which contribute a considerable amount to the overall  
current consumption of the device, are turned off. All other support circuitry is kept alive. This shortens the turn on  
time so that the first conversion after Fast Power-Down is already correct.  
The Fast Power-Down Mode is selected by transmitting a Manual Mode Control Word with PD1 = ‘0’, PD0 = ‘1’ on  
the SPI interface. It becomes activated immediately after complete reception of the Control Word.  
2.5.3. Auto Fast Power-Down Mode  
Auto Fast Power-Down Mode is similar to the Immediate Fast Power-Down Mode, except that the Power-Down  
state becomes activated after completion of the next conversion. The amount of current reduction is equal in both  
Fast Power-Down Modes.  
In Auto Fast Power-Down Mode it is also possible to wake up the device from Power-Down state by generating a  
conversion start at the CONV input while keeping nCS low. It is not needed to send a new control word, if the  
channel configuration does not change.  
© 2010 Zentrum Mikroelektronik Dresden AG — Rev. 1.1  
Data Sheet  
July 30, 2010  
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the prior written consent of the copyright owner. The information furnished in this publication is PRELIMINARY and subject to  
changes without notice.  
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ZADC5125/5123/5121  
12-Bit, 1Msps, Simultaneous Sampling ADC Family  
The CONV signal is expected to stay high (‘1’) as long as the device shall remain in power down state. Once  
CONV turns low the Fast Power-Down state is left with the next rising clock edge of SCLK, executes three Wake-  
Up cycles (3 SCLK clock cycles) and starts the acquisition. As soon as two acquisition cycles have expired, the  
conversion will be started with on the following rising edge of CONV.  
Auto Fast Power-Down mode becomes deactivated as soon as a new Start Bit is received.  
3 Package Drawing  
ZADC5125x devices are delivered in a 28-pin SSOP-package that has the dimensions as shown in Figure 24 and  
Table 14. For ZADC5123x and ZADC5121x devices apply respective 24-pin and 20-pin SSOP-packages. Their  
dimensions are specified in Table 15 and Table 16.  
Figure 24: Package Outline Dimensions  
© 2010 Zentrum Mikroelektronik Dresden AG — Rev. 1.1  
Data Sheet  
July 30, 2010  
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the prior written consent of the copyright owner. The information furnished in this publication is PRELIMINARY and subject to  
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ZADC5125/5123/5121  
12-Bit, 1Msps, Simultaneous Sampling ADC Family  
Table 14: SSOP28 Package Dimensions for ZADC5125x devices (mm)  
Symbol  
A
A1  
A2  
bP  
c
D
E
enom  
0.65  
HE  
LP  
Z
k
10°  
0°  
Maximum  
Minimum  
1.99  
1.73  
0.21  
0.05  
1.78  
1.68  
0.38  
0.25  
0.20  
0.09  
10.33  
10.07  
5.38  
5.20  
7.90  
7.65  
1.22  
0.63  
0.25  
Table 15: SSOP24 Package Dimensions for ZADC5123x devices (mm)  
Symbol  
A
A1  
A2  
bP  
c
D
E
enom  
0.65  
HE  
LP  
Z
k
10°  
0°  
Maximum  
Minimum  
1.99  
1.73  
0.21  
0.05  
1.78  
1.68  
0.38  
0.25  
0.20  
0.09  
8.33  
8.07  
5.38  
5.20  
7.90  
7.65  
0.59  
0.63  
0.25  
Table 16: SSOP20 Package Dimensions for ZADC5121x devices (mm)  
Symbol  
A
A1  
A2  
bP  
c
D
E
enom  
0.65  
HE  
LP  
Z
k
8°  
0°  
Maximum  
Minimum  
1.99  
1.73  
0.21  
0.05  
1.78  
1.68  
0.38  
0.25  
0.20  
0.09  
7.33  
7.07  
5.38  
5.20  
7.90  
7.65  
0.74  
0.63  
0.25  
ZMDI Contact  
Sales and Further Information  
www.zmdi.com  
ZMD AG, Japan Office  
sales@zmdi.com  
ZMD Far East, Ltd.  
Zentrum Mikroelektronik  
Dresden AG (ZMD AG)  
Grenzstrasse 28  
ZMD America, Inc.  
201 Old Country Road  
Suite 204  
2nd Floor, Shinbashi Tokyu Bldg. 3F, No. 51, Sec. 2,  
4-21-3, Shinbashi, Minato-ku  
Tokyo, 105-0004  
Japan  
Keelung Road  
11052 Taipei  
Taiwan  
01109 Dresden  
Germany  
Melville, NY 11747  
USA  
Phone +49 (0)351.8822.7.232  
Phone +1.(631) 549-2666  
Fax +1.(631) 549-2882  
Phone +81.3.6895.7410  
Phone +886.2.2377.8189  
Fax +886.2.2377.8199  
Fax  
+49(0)351.8822.87.232  
Fax  
+81.3.6895.7301  
DISCLAIMER: This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Zentrum Mikroelektronik Dresden AG  
(ZMD AG) assumes no obligation regarding future manufacture unless otherwise agreed to in writing. The information furnished hereby is believed to be true and accurate. However, under  
no circumstances shall ZMD AG be liable to any customer, licensee, or any other third party for any special, indirect, incidental, or consequential damages of any kind or nature whatsoever  
arising out of or in any way related to the furnishing, performance, or use of this technical data. ZMD AG hereby expressly disclaims any liability of ZMD AG to any customer, licensee or any  
other third party, and any such customer, licensee and any other third party hereby waives any liability of ZMD AG for any damages in connection with or arising out of the furnishing, perfor-  
mance or use of this technical data, whether based on contract, warranty, tort (including negligence), strict liability, or otherwise.  
© 2010 Zentrum Mikroelektronik Dresden AG — Rev. 1.1  
Data Sheet  
July 30, 2010  
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without  
the prior written consent of the copyright owner. The information furnished in this publication is PRELIMINARY and subject to  
changes without notice.  
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