ZADCS1022QS14T [IDT]
ADC, Successive Approximation, PDSO14;
| 型号： | ZADCS1022QS14T |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | ADC, Successive Approximation, PDSO14 光电二极管 转换器 |
| 文件： | 总22页 (文件大小：372K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ZADCS1082/1042/1022
10-Bit, 250ksps, Serial Output ADC Family
Datasheet
Features
Description
The ZADCS10x2 family is a set of low power, 10-bit, suc-
cessive approximation analog-to-digital (A/D) converters
with up to 250ksps conversion rate, two up to eight input
channels, high-bandwidth track/hold and synchronous
serial interface.
Single Supply Operation:
+ 2.7V … + 5.25V
Family approach providing
2 / 4 / 8-Channel Single-Ended or
1 / 2 / 4-Channel Differential Inputs
The ADCs operate from a single + 2.7V to + 5.25V supply.
Their analog inputs are software configurable for unipo-
lar/bipolar and single-ended/differential operation.
Up to 250ksps Conversion Rate
± 0.4 LSB INL and DNL
No Missing Codes
The 4-wire serial interface connects directly to SPI™/
(QSPI™ and MICROWIRE™) devices without external
logic.
> 61 dB SINAD
True fully differential Operation
All family devices can use either the external serial-
interface clock or an internal clock to perform successive-
approximation analog-to-digital conversions. The internal
clock can be used to run independent conversions on
more than one device in parallel.
Software-Configurable Unipolar or
Bipolar output coding
Internal 3.3MHz oscillator for independent
operation from external clock
The ZADCS10x2V versions are equipped with a highly
accurate internal 2.5V reference with an additional external
±1.5% voltage adjustment range.
Internal 2.5V Reference
Low Power
-
-
< 1.2mA (250ksps, 5V supply)
< 0.5μA (power-down mode)
All members of the ZADCS10x2 family provide a hard-
wired shut-down pin (nSHDN) pin and software-selectable
power-down modes that can be programmed to automati-
cally shut down the IC at the end of a conversion. Access-
ing the serial interface automatically powers up the IC. A
quick turn-on time allows the device to be shut down be-
tween all conversions.
SPITM / QSPITM / MICROWIRETM - compatible
4-Wire Serial Interface
14 / 16 / 20-Pin SSOP
Applications
Data Acquisition
Industrial Process Control
Portable Data Logging
Battery-Powered Systems
Starterkit
available
Functional Block Diagram
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
Available in
ZADCS1022
SAR
8-Channel
Analog
Available in
ZADCS1042
Comparator
Input
IN+
IN-
nCS
SCLK
DIN
DOUT
SSTRB
+
Serial
Interface
and
Multiplexer
DAC with
inherent
T&H
Available in
ZADCS1082
-
Control
State
COM
nSHDN
x 2.000
Internal
3.3 MHz
Oscillator
Machine
+ 1.25V
Reference
VDD
REFADJ
VREF
DGND
AGND
Available in ZADCS10x2V versions
Copyright © 2010, ZMD AG, Rev. 1.2
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The
Information furnished in this publication is preliminary and subject to changes without notice.
1/22
Datasheet
ZADCS1082/1042/1022 Family
Table of Contents
Page
1
GENERAL DEVICE SPECIFICATION............................................................................................................ 3
1.1
ABSOLUTE MAXIMUM RATINGS (NON OPERATING) ....................................................................................... 3
PACKAGE PIN ASSIGNMENT ZADCS1082 / ZADCS1082V.......................................................................... 4
PACKAGE PIN ASSIGNMENT ZADCS1042 / ZADCS1042V.......................................................................... 5
PACKAGE PIN ASSIGNMENT ZADCS1022 / ZADCS1022V.......................................................................... 6
ELECTRICAL CHARACTERISTICS................................................................................................................... 7
1.2
1.3
1.4
1.5
1.5.1
1.5.2
General Parameters........................................................................................................................ 7
Specific Parameters of ZADCS10x2V versions (with Internal Reference) ................................ 8
Specific Parameters of basic ZADCS10x2 versions (without Internal Reference) ................................. 9
1.5.3 Digital Pin Parameters.................................................................................................................... 9
1.6 TYPICAL OPERATING CHARACTERISTICS.................................................................................................... 10
2
DETAILED DESCRIPTION........................................................................................................................... 12
2.1
GENERAL OPERATION............................................................................................................................... 12
ANALOG INPUT ......................................................................................................................................... 12
INTERNAL & EXTERNAL REFERENCE .......................................................................................................... 14
DIGITAL INTERFACE .................................................................................................................................. 14
POWER DISSIPATION ................................................................................................................................ 19
2.2
2.3
2.4
2.5
3
4
5
6
LAYOUT........................................................................................................................................................ 19
PACKAGE DRAWING.................................................................................................................................. 21
ORDERING INFORMATION......................................................................................................................... 22
ZMDI CONTACT ........................................................................................................................................... 22
Important Notice:
The information furnished herein by ZMDI is believed to
be correct and accurate as of the publication date. How-
ever, ZMDI shall not be liable to any party for any dam-
ages, including but not limited to personal injury, property
damage, loss of profits, loss of use, interruption of busi-
ness, or indirect, special, incidental, or consequential
damages of any kind in connection with or arising out of
the furnishing, performance, or use of the technical data.
No obligation or liability to any third party shall arise from
ZMDI's rendering technical or other services.
ZMDI reserves the right to discontinue production and
change specifications and prices, make corrections,
modifications, enhancements, improvements and other
changes of its products and services at any time without
notice. ZMDI products are intended for use in commercial
applications. Applications requiring extended temperature
range, unusual environmental requirements, or high reli-
ability applications, such as military, medical life-support
or life-sustaining equipment, are specifically not recom-
mended without additional mutually agreed-upon proc-
essing by ZMDI for such applications. ZMDI assumes no
liability for application assistance or customer product
design. Customers are responsible for their products and
applications using ZMDI components.
Products sold by ZMDI are covered exclusively by the
ZMDI’s standard warranty, patent indemnification, and
other provisions appearing in ZMDI’s standard "Terms &
Conditions". ZMDI makes no warranty (express, statutory,
implied and/or by description), including without limitation
any warranties of merchantability and/or fitness for a
particular purpose, regarding the information set forth in
the materials pertaining to ZMDI products, or regarding
the freedom of any products described in such materials
from patent and/or other infringement.
SPI and QSPI are registered trademarks of Motorola, Inc.
MICROWIRE is a registered trademark of National Semi-
conductor Corp.
Please notice that values specified as typical may differ
from product to product. The values listed under min or
max
are
guaranteed
by
design
or
test.
Copyright © 2010, ZMD AG, Rev. 1.2
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The
Information furnished in this publication is preliminary and subject to changes without notice.
2/22
Datasheet
ZADCS1082/1042/1022 Family
1 General Device Specification
1.1 Absolute Maximum Ratings (Non Operating)
Table 1: Absolute Maximum Ratings
Symbol
Parameter
Min
Max
Unit
Note
VDD-GND
VDD to AGND, DGND
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
6
0.3
V
V
VAGND-DGND
AGND to DGND
CH0 – CH7, COM to AGND, DGND
VREF, VREFADJ to AGND
Digital Inputs to DGND
Digital Outputs to DGND
Digital Output Sink Current
VDD+0.3
VDD+0.3
6
V
V
V
VDD+0.3
25
V
mA
Iin
Input current into any pin except supply pins (Latch-Up)
Electrostatic discharge – Human Body Model (HBM)
Maximum Junction Temperature
Operating Temperature Range
ZADCS10x2VIS20 / ZADCS10x2IS20
ZADCS10x2VQS20 / ZADCS10x2QS20
Storage temperature
-100
100
mA
V
1
VHBM
JCT
OP
2000
+150°
°C
-25
-40
-65
+85
+125
+150
°C
°C
°C
°C
STG
lead
H
Lead Temperature 100%Sn
JEDEC-J-STD-20C 260
2
Humidity non-condensing
Ptot
Rthj
Total power dissipation
250
100
mW
K/W
Thermal resistance of Package
SSOP20 / 5.3mm
1
2
HBM: C = 100pF charged to VHBM with resistor R = 1.5k in series, valid for all pins
Level 4 according to JEDEC-020A is guaranteed
Copyright © 2010, ZMD AG, Rev. 1.2
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The
Information furnished in this publication is preliminary and subject to changes without notice.
3/22
Datasheet
ZADCS1082/1042/1022 Family
1.2 Package Pin Assignment ZADCS1082 / ZADCS1082V
Table 2: Pin list
Package
Name
Direction Type
Description
pin number
1
2
3
4
5
6
7
8
9
nCS
IN
CMOS Digital
CMOS Digital
SUPPLY
SUPPLY
Analog
Active Low Chip Select
Serial Data Input
Digital Ground
DIN
IN
DGND
AGND
VREF
COM
CH0
Analog Ground
I/O
IN
IN
IN
IN
IN
IN
IN
IN
IN
I/O
Reference Buffer Output / External Reference Input
Ground reference for analog inputs in single ended mode
Analog Input Channel 0
Analog
Analog
CH1
Analog
Analog Input Channel 1
CH4
Analog
Analog Input Channel 4
10
11
12
13
14
15
16
17
18
19
20
CH5
Analog
Analog Input Channel 5
CH7
Analog
Analog Input Channel 7
CH6
Analog
Analog Input Channel 6
CH3
Analog
Analog Input Channel 3
CH2
Analog
Analog Input Channel 2
REFADJ
VDD
Analog
Input to Reference Buffer Amplifier
Positive Supply
SUPPLY
CMOS Digital
CMOS Digital
CMOS Digital
CMOS Digital
nSHDN
DOUT
SSTRB
SCLK
IN
Active Low Shutdown
OUT
OUT
IN
Serial Data Output
Serial Strobe Output
Serial Clock Input
nCS
SCLK
SSTRB
DOUT
nSHDN
VDD
DIN
DGND
AGND
VREF
COM
CH0
REFADJ on ZADCS1082V,
No connect on ZADCS1082
CH2
CH3
CH6
CH7
CH1
CH4
CH5
Figure 1: Package Pin Assignment for ZADCS1082 & ZADCS1082V
Copyright © 2010, ZMD AG, Rev. 1.2
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The
Information furnished in this publication is preliminary and subject to changes without notice.
4/22
Datasheet
ZADCS1082/1042/1022 Family
1.3 Package Pin Assignment ZADCS1042 / ZADCS1042V
Table 3: Pin list
Package
Name
Direction Type
Description
pin number
1
2
3
4
5
6
7
8
9
nCS
IN
CMOS Digital
CMOS Digital
SUPPLY
Active Low Chip Select
Serial Data Input
Digital Ground
DIN
IN
DGND
AGND
VREF
COM
SUPPLY
Analog Ground
I/O
IN
IN
IN
IN
IN
I/O
Analog
Reference Buffer Output / External Reference Input
Ground reference for analog inputs in single ended mode
Analog Input Channel 0
Analog
CH0
Analog
CH1
Analog
Analog Input Channel 1
CH3
Analog
Analog Input Channel 3
10
11
12
13
14
15
16
CH2
Analog
Analog Input Channel 2
REFADJ
VDD
Analog
Input to Reference Buffer Amplifier
Positive Supply
SUPPLY
nSHDN
DOUT
SSTRB
SCLK
IN
CMOS Digital
CMOS Digital
CMOS Digital
CMOS Digital
Active Low Shutdown
OUT
OUT
IN
Serial Data Output
Serial Strobe Output
Serial Clock Input
nCS
DIN
SCLK
SSTRB
DOUT
nSHDN
VDD
DGND
AGND
VREF
COM
CH0
REFADJ on ZADCS1042V,
No connect on ZADCS1042
CH2
CH3
CH1
Figure 2: Package Pin Assignment for ZADCS1042 & ZADCS1042V
Copyright © 2010, ZMD AG, Rev. 1.2
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The
Information furnished in this publication is preliminary and subject to changes without notice.
5/22
Datasheet
ZADCS1082/1042/1022 Family
1.4 Package Pin Assignment ZADCS1022 / ZADCS1022V
Table 4: Pin list
Package
Name
Direction Type
Description
pin number
1
2
3
4
5
6
7
8
9
nCS
IN
CMOS Digital
CMOS Digital
SUPPLY
Active Low Chip Select
Serial Data Input
Digital Ground
DIN
IN
DGND
AGND
VREF
COM
SUPPLY
Analog Ground
I/O
IN
Analog
Reference Buffer Output / External Reference Input
Ground reference for analog inputs in single ended mode
Analog Input Channel 0
Analog
CH0
IN
Analog
CH1
IN
Analog
Analog Input Channel 1
REFADJ
VDD
I/O
Analog
Input to Reference Buffer Amplifier
Positive Supply
10
11
12
13
14
SUPPLY
nSHDN
DOUT
SSTRB
SCLK
IN
CMOS Digital
CMOS Digital
CMOS Digital
CMOS Digital
Active Low Shutdown
OUT
OUT
IN
Serial Data Output
Serial Strobe Output
Serial Clock Input
nCS
DIN
SCLK
SSTRB
DOUT
nSHDN
VDD
DGND
AGND
VREF
COM
CH0
REFADJ on ZADCS1022V,
No connect on ZADCS1022
CH1
Figure 3: Package Pin Assignment for ZADCS1022 & ZADCS1022V
Copyright © 2010, ZMD AG, Rev. 1.2
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The
Information furnished in this publication is preliminary and subject to changes without notice.
6/22
Datasheet
ZADCS1082/1042/1022 Family
1.5 Electrical Characteristics
1.5.1 General Parameters
(VDD = +2.7V to + 5.25V; fSCLK = 3.3MHz (50% duty cycle); 13 clocks/conversion cycle (250 ksps); VREF = 2.500V applied to VREF pin;
OP = OPmin … OPmax)
Parameter
Symbol Conditions
Min
Typ
10
Max Unit
Bits
DC Accuracy
Resolution
ZADCS1082 / ZADCS1082V
Relative Accuracy
No Missing Codes
INL
ZADCS1042 / ZADCS1042V
ZADCS1022 / ZADCS1022V
LSB
Bits
LSB
0.4
NMC
DNL
10
ZADCS1082 / ZADCS1082V
ZADCS1042 / ZADCS1042V
ZADCS1022 / ZADCS1022V
Differential Nonlinearity
0.4
Offset Error
LSB
0.5
0.5
2.0
2.0
Gain Error
LSB
Gain Temperature Coefficient
ppm/°C
0.25
Dynamic Specifications (10kHz sine-wave input, 0V to 2.500Vpp, 250ksps, 3.3MHz external clock)
Signal-to-Noise + Distortion Ratio SINAD
61
dB
Total Harmonic Distortion
Spurious-Free Dynamic Range
Small-Signal Bandwidth
Conversion Rate
THD
Up to the 5th harmonic
-3dB roll off
-72
dB
SFDR
74
dB
3.8
MHz
Sampling Time
(= Track/Hold Acquisition Time)
Ext. Clock = 3.3MHz, 2.5 clocks/ acquisi-
tion
tACQ
0.758
2.75
µs
Ext. Clock = 3.3MHz, 10 clocks/ conver-
sion
3.03 µs
Conversion Time
tCONV
Int. Clock = 3.3MHz +/- 12% tolerance
3.50 µs
Aperture Delay
30
ns
ps
Aperture Jitter
< 50
External Clock Frequency
Internal Clock Frequency
0.1
3.3
MHz
2.81
3.3
3.58 MHz
Analog Inputs
Unipolar, COM = 0V
0 to VREF
VREF / 2
16
Input Voltage Range, Single-
Ended and Differential
V
Bipolar, COM = VREF/2
Input Capacitance
pF
Copyright © 2010, ZMD AG, Rev. 1.2
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The
Information furnished in this publication is preliminary and subject to changes without notice.
7/22
Datasheet
ZADCS1082/1042/1022 Family
1.5.2 Specific Parameters of ZADCS10x2V versions (with Internal Reference)
(VDD = +2.7V to + 5.25V; fSCLK = 3.3MHz (50% duty cycle); 13 clocks/conversion cycle (250 ksps); OP = OPmin … OPmax
)
Parameter
Symbol Conditions
TA = + 25°C
Min
Typ
Max Unit
Internal Reference at VREF
VREF Output Voltage
2.480 2.500 2.520
30
V
VREF Short-Circuit Current
VREF Temperature Coefficient
Load Regulation
mA
± 30
0.35
± 50 ppm/°C
0 to 0.2mA output load
mV
µF
µF
%
Capacitive Bypass at VREF
Capacitive Bypass at REFADJ
REFADJ Adjustment Range
4.7
0.047
1.5
External Reference at VREF (internal buffer disabled by V(REFADJ) = VDD)
VDD +
V
VREF Input Voltage Range
1.0
50mV
VREF Input Current
VREF = 2.5V
180
14
215 µA
VREF Input Resistance
Shutdown VREF Input Current
11.5
k
0.1
µA
V
VDD-
0.5
REFADJ Buffer Disable Threshold
External Reference at VREF_ADJ
Reference Buffer Gain
2.00
VREF_ADJ Input Current
±80 µA
Full Power Down
VREFADJ Input Current
Full Power-Down mode
0.1
µA
Power Requirements
Positive Supply Voltage
Positive Supply Current
VDD
2.7
5.25
1.0
1.4
300
4.0
1.3
1.6
300
4.0
V
Operating Mode ext. VREF
0.85
1.3
mA
mA
Operating Mode int. VREF
Fast Power-Down
IDD
IDD
IDD
IDD
VDD=3.6V
VDD=5.2V
VDD=3.6V
VDD=5.2V
ZADCS1082VI
ZADCS1042VI
ZADCS1022VI
250
0.5
µA
Full Power-Down
Positive Supply Current
Operating Mode ext. VREF
Operating Mode int. VREF
Fast Power-Down
1.00
1.40
250
0.5
mA
mA
ZADCS1082VI
ZADCS1042VI
ZADCS1022VI
µA
Full Power-Down
Positive Supply Current
Operating Mode ext. VREF
Operating Mode int. VREF
Fast Power-Down
0.85
1.3
1.11) mA
1.51) mA
3501)
ZADCS1082VQ
ZADCS1042VQ
ZADCS1022VQ
250
0.5
µA
Full Power-Down
151)
Positive Supply Current
Operating Mode ext. VREF
Operating Mode int. VREF
Fast Power-Down
1.00
1.40
250
0.5
1.41) mA
1.71) mA
3501)
ZADCS1082VQ
ZADCS1042VQ
ZADCS1022VQ
µA
Full Power-Down
201)
1) relaxed maximum limits are due to wider temperature range of automotive qualified version ZADCS10x2VQ
Copyright © 2010, ZMD AG, Rev. 1.2
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The
Information furnished in this publication is preliminary and subject to changes without notice.
8/22
Datasheet
ZADCS1082/1042/1022 Family
Specific Parameters of basic ZADCS10x2 versions (without Internal Reference)
(VDD = +2.7V to + 5.25V; fSCLK = 3.3MHz (50% duty cycle); 13 clocks/conversion cycle (250 ksps); OP = OPmin … OPmax
)
Parameter
Symbol Conditions
Min
1.0
Typ
Max Unit
External Reference at VREF
VREF Input Voltage Range
VDD +
V
50mV
VREF Input Current
VREF = 2.5V
180
14
215 µA
VREF Input Resistance
11.5
4.7
k
Shutdown VREF Input Current
Capacitive Bypass at VREF
0.1
µA
µF
Power Requirements
Positive Supply Voltage
VDD
2.7
5.25
V
Positive Supply Current
ZADCS1082I, ZADCS1042I,
ZADCS1022I
Operating Mode
Full Power-Down
Operating Mode
Full Power-Down
Operating Mode
Full Power-Down
Operating Mode
Full Power-Down
0.85
0.5
1.0 mA
4.0 µA
1.3 mA
4.0 µA
1.01) mA
151) µA
1.31) mA
201) µA
IDD
IDD
IDD
IDD
VDD = 3.6V
VDD = 5.25V
VDD = 3.6V
VDD = 5.25V
Positive Supply Current
ZADCS1082I, ZADCS1042I,
ZADCS1022I
1.00
0.5
Positive Supply Current
ZADCS1082Q, ZADCS1042Q,
ZADCS1022Q
0.85
0.5
Positive Supply Current
ZADCS1082Q, ZADCS1042Q,
ZADCS1022Q
1.00
0.5
1) relaxed maximum limits are due to wider temperature range of automotive qualified version ZADCS10x2Q
1.5.3 Digital Pin Parameters
(VDD = +2.7V to + 5.25V; fSCLK = 3.3MHz (50% duty cycle); 13 clocks/conversion cycle (250 ksps); OP = OPmin … OPmax
)
Parameter
Symbol Conditions
Min
Typ
Max Unit
Digital Inputs (DIN, SCLK, CS, nSHDN)
VDD = 2.7V
VDD = 5.25V
VDD = 2.7V
VDD = 5.25V
1.9
3.3
V
V
Logic High Level
Logic Low Level
VIH
VIL
0.7
1.4
V
V
V
Hysteresis
VHyst
IIN
0.7
Input Leakage
Input Capacitance
VIN = 0V or VDD
± 0.1
5
± 1.0 µA
pF
CIN
Digital Outptus (DOUT, SSTRB)
VDD = 2.7V
VDD = 5.25V
VDD = 2.7V
VDD = 5.25V
3.5
5.5
4
8.5
mA
Output High Current
IOH
VOH= VDD – 0.5V
VOL= 0.4V
10.8 mA
11.5 mA
15.3 mA
± 1.0 µA
Output Low Voltage
IOL
6.4
Three-State Leakage Current
Three-State Output Capacitance
ILeak
nCS = VDD
nCS = VDD
± 0.1
5
COUT
pF
Copyright © 2010, ZMD AG, Rev. 1.2
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The
Information furnished in this publication is preliminary and subject to changes without notice.
9/22
Datasheet
ZADCS1082/1042/1022 Family
1.6 Typical Operating Characteristics
Integral Nonlinearity vs. Code
1
Differential Nonlinearity vs. Code
1
0.8
0.6
0.4
0.2
0
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1
-0.2
-0.4
-0.6
-0.8
-1
0
128
256
384
512
640
768
896 1024
0
128
256
384
512
640
768
896 1024
Code
Code
IDDstatic vs. Temperature
ZADCS12x2V, internal reference active, at VDD = 3.3V
IDD vs. VDD
1500
1350
1200
1050
900
750
600
450
300
150
0
700
650
600
550
500
IDDactive (converting)
IDDstatic
External VREF
3.4
Internal VREF
4.8
2.7
4.1
VDD (V)
5.5
-40
-20
0
20
40
60
80
100
Temperatur (°C)
Copyright © 2010, ZMD AG, Rev. 1.2
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The
Information furnished in this publication is preliminary and subject to changes without notice.
10/22
Datasheet
ZADCS1082/1042/1022 Family
IDDactive (converting) vs. Temperature
ZADCS12x2V, internal reference active, at VDD = 3.3V
VREF vs. Temperature
1050
1000
950
2.501
2.500
2.499
2.498
900
-25
0
25
50
75
-40
-20
0
20
40
60
80
100
Temperature (°C)
Temperatur (°C)
Copyright © 2010, ZMD AG, Rev. 1.2
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Information furnished in this publication is preliminary and subject to changes without notice.
11/22
Datasheet
ZADCS1082/1042/1022 Family
VREFADJ is tied to VDD.
2 DETAILED DESCRIPTION
2.2 Analog Input
2.1 General Operation
The analog input to the converter is fully differential. Both
converter input signals IN+ and IN– (see Functional Block
diagram at front page) get sampled during the acquisition
period enabling the converter to be used in fully differen-
tial applications where both signals can vary over time.
The ZADCS10x2 family is a set of classic successive
approximation register (SAR) type converters. The archi-
tecture is based on a capacitive charge redistribution
DAC merged with a resistor string DAC building a hybrid
converter with excellent monotonicity and DNL properties.
The Sample & Hold function is inherent to the capacitive
DAC. This avoids additional active components in the
signal path that could distort the input signal or introduce
errors.
The ZADCS10x2 family converters do not require that the
negative input signal be kept constant within ± 0.5LSB
during the entire conversion as is commonly required by
converters featuring pseudo differential operation only.
The input signals can be applied single ended, refer-
enced to the COM pin, or differential, using pairs of the
input channels. The desired configuration is selectable for
every conversion via the Control-Byte received on DIN
pin of the digital interface (see further description below)
All devices in the ZADCS10x2 family build on the same
converter core and differ only in the number of input
channels and the availability of an internal reference
voltage generator. The ZADCS10x2V versions are
equipped with a highly accurate internal 1.25V bandgap
reference which is available at the VREFADJ pin. The
bandgap voltage is further amplified by an internal buffer
amplifier to 2.50V that is available at pin VREF. All other
versions come without the internal reference and the
internal buffer amplifier. They require an external refer-
ence supplied at VREF, with the benefit of considerably
lower power consumption.
A block diagram of the input multiplexer is shown in
Figure 7. Table 5 and Table 6 show the relationship of the
Control-Byte bits A2, A1, A0 and SGL/DIF to the configu-
ration of the analog multiplexer. The entire table applies
only to ZADCS1082 devices. For ZADCS1042 devices bit
A1 is don’t care, for ZADCS1022 devices A1 and A0 are
don’t care.
A basic application schematic for ZADC1082V is shown
in Figure 4, for ZADCS1082 in Figure 5. ZADCS1082V
can also be operated with an external reference, if
Both input signals IN+ and IN– are generally allowed to
swing between –0.2V and VDD+0.2V. However, depend-
ing on the selected conversion mode – uniploar or bipo-
Table 5: Channel selection in Single Ended Mode
(SGL/DIF = HIGH)
Table 6: Channel selection in Differential Mode
(SGL/DIF = LOW)
A2 A1 A0 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 COM
A2 A1 A0 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7
0
1
0
1
0
1
0
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
IN+
IN-
IN-
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
IN+ IN-
IN+
IN+ IN-
IN- IN+
IN+
IN-
IN+ IN-
IN- IN+
IN+
IN-
IN+ IN-
IN+
IN-
IN- IN+
IN+
IN-
IN+
IN-
IN+ IN-
IN- IN+
Figure 4: Basic application schematic for ZADCS1082V
Figure 5: Basic application schematic for ZADCS1082
µC
µC
ZADCS1082V
ZADCS1082
+2.7V to 5.25V
+2.7V to 5.25V
nCS
SCLK
SSTRB
DOUT
nSHDN
VDD
nCS
SCLK
SSTRB
DOUT
nSHDN
VDD
1
2
20
19
18
17
16
15
14
13
12
11
1
2
20
19
18
17
16
15
14
13
12
11
DIN
DIN
DGND
AGND
VREF
COM
CH0
CH1
CH4
CH5
DGND
AGND
VREF
COM
CH0
CH1
CH4
CH5
3
3
4
4
≥ 4.7µF
≥ 4.7µF
5
5
47nF
0.1µF
10µF
0.1µF
10µF
VREFADJ
CH2
n.c.
6
6
CH2
7
7
CH3
CH3
8
8
CH6
CH6
9
9
CH7
CH7
10
10
Single-ended or differential
analog inputs, 0V … +2.5V
Single-ended or differential
analog inputs, 0V … +VREF
Copyright © 2010, ZMD AG, Rev. 1.2
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Information furnished in this publication is preliminary and subject to changes without notice.
12/22
Datasheet
ZADCS1082/1042/1022 Family
Figure 7: Block diagram of input multiplexer
Figure 8: Input voltage range in unipolar mode
VIN+
Shown configuration
A2 … A0 = 0x000
+2.7V to 5.25V
1.5*VREF
0x3FF
CH0
CH1
CH2
CH3
CH4
VREF
Code Range
0.5*VREF
CH5
IN+
Converter
CH6
CH7
0x000
IN-
0V
VDD-VREF VIN-
Figure 9: Input voltage range for fully differen-
tial signals in bipolar mode
VCM
VREF
¾ VREF
VCM Range
COM
¼ VREF
0V
SGL/DIF = HIGH
See Table 5 & Table 6
for Coding Schemes
-VREF/2
0V
+VREF/2
VDIFF
The common mode level of a differential input signal is
calculated VCM = (V(IN+)+ V(IN–)) / 2. To avoid code clip-
ping or over steering of the converter, the common mode
level can change from ¼ VREF … ¾ VREF. Within this
range the peak to peak amplitude of the differential input
signal can be ± VREF/2.
lar – certain input voltage relations can limit the output
code range of the converter.
In unipolar mode the voltage at IN+ must exceed the
voltage at IN– to obtain codes unequal to 0x000. The
entire 10 bit transfer characteristic is then covered by IN+
if IN+ ranges from IN– to (IN– +Vref). Any voltage on
IN+ > (IN– + Vref) results in code 0x3FF. Code 0x3FF is
not reached, if (IN– +Vref) > VDD + 0.2V because the
input voltage is clamped at VDD + 0.2V by ESD protec-
tion devices.
The average input current on the analog inputs depends
on the conversion rate. The signal source must be capa-
ble of charging the internal sampling capacitors (typically
16pF on each input of the converter: IN+ and IN–) within
the acquisition time tACQ to the required accuracy. The
equivalent input circuit in sampling mode is shown in
Figure 6.
The voltage at IN– can range from -0.2V … ½ VREF with-
out limiting the Code Range, assuming the fore men-
tioned VDD condition is true. See also Figure 8 for input
voltage ranges in unipolar conversion mode.
The following equation provides a rough hand calculation
for a source impedance RS that is required to settle out a
In bipolar mode, IN+ can range from (IN– - Vref/2) to (IN–
+ Vref/2) keeping the converter out of code saturation.
For instance, if IN– is set to a constant DC voltage of
Vref/2, then IN+ can vary from 0V to VREF to cover the
entire code range. Lower or higher voltages of IN+ keep
the output code at the minimum or maximum code value.
CHOLD+
RSW
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
IN+
CIN
4pF
16pF
3kΩ
Figure 9 shows the input voltage ranges in bipolar mode
when IN– is set to a constant DC voltage.
AGND
CHOLD-
As explained before, converters out of the ZADCS10x2
family can also be used to convert fully differential input
signals that change around a common mode input volt-
age.
VDC
RSW
COM
Channel
Multiplexer
IN-
CIN
4pF
16pF
3kΩ
The bipolar mode is best used for such purposes since it
allows the input signals to be positive or negative in rela-
tion to each other.
AGND
Figure 6: Equivalent input circuit during sampling
Copyright © 2010, ZMD AG, Rev. 1.2
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Information furnished in this publication is preliminary and subject to changes without notice.
13/22
Datasheet
ZADCS1082/1042/1022 Family
DC input signal referenced to AGND with 10 bit accuracy
in a given acquisition time
The internal bandgap reference and the VREF buffer can
be shut down completely by setting VREFADJ to VDD.
This reduces power consumption of the ZADCS10x2V
devices and allows the supply of an external reference at
VREF.
tACQ
RS
RSW
7 CIN
Basic ZADCS10x2 devices do not contain the internal
bandgap or the VREF buffer. An external reference must
be supplied all the time at VREF.
For example, if fSCLK = 3.3MHz, the acquisition time is
t
ACQ = 758ns. Thus the output impedance of the signal
source RS must be less than
The value of the reference voltage at VREF sets the input
range of the converter and the analog voltage weight of
each digital code. The size of the LSB (least significant
bit) is equal to the value of VREF (reference to AGND)
divided by 1024. For example at a reference voltage of
2.500V, the voltage level of a LSB is equal to 2.441mV.
758ns
RS
3kΩ 2.41kΩ
7 20pF
If the output impedance of the source is higher than the
calculated maximum RS the acquisition time must be
extended by reducing fSCLK to ensure 10 bit accuracy.
Another option is to add a capacitor of >20 nF to the
individual input. Although this limits the bandwidth of the
input signal because an RC low pass filter is build to-
gether with the source impedance, it may be useful for
certain applications.
It is important to know that certain inherent errors in the
A/D converter, like offset or gain error, will appear to
increase at lower reference voltages while the actual
performance of the device does not change. For instance
a static offset error of 2.441mV is equal to 1 LSB at 2.5V
reference, while it is equivalent to 2.5 LSB for a reference
voltage of 1.0V
The small-signal bandwidth of the input tracking circuitry
is 3.8 MHz. Hence it is possible to digitize high-speed
transient events and periodic signals with frequencies
exceeding the ADC’s sampling rate. This allows the ap-
plication of certain under-sampling techniques like down
conversion of modulated high frequency signals.
Likewise, the uncertainty of the digitized output code will
increase with lower LSB size (lower VREF). Once the
size of an LSB is below the internal noise level, the output
code will start to vary around a mean value for constant
DC input voltages. Such noise can be reduced by averag-
ing consecutive conversions or applying a digital filter.
Be aware that under-sampling techniques still require a
bandwidth limitation of the input signal to less than the
Nyquist frequency of the converter to avoid aliasing ef-
fects. Also, the output impedance of the input source
must be very low to achieve the mentioned small signal
bandwidth in the overall system.
The average current consumption at VREF depends on
the value of VREF and the sampling frequency. Two
effects contribute to the current at VREF, a resistive con-
nection from VREF to AGND and charge currents that
result from the switching and recharging of the capacitor
array (CDAC) during sampling and conversion.
2.3 Internal & External Reference
For an external reference of 2.5V the input current at
VREF is approximately 100µA.
ZADCS10x2V family members are equipped with a highly
accurate internal 2.5V reference voltage source. The
voltage is generated from a trimmed 1.25V bandgap with
an internal buffer that is set to a gain of 2.00. The band-
gap voltage is supplied at VREFADJ with an output im-
pedance of 20kΩ. An external capacitor of 47nF at
VREFADJ is useful to further decrease noise on the in-
ternal reference.
2.4 Digital Interface
All devices out of the ZADCS10x2 family are controlled
by a 4-wire serial interface that is compatible to SPI™,
QSPI™ and MICROWIRE™ devices without external
logic.
Any conversion is started by sending a control byte into
DIN while nCS is low. A typical sequence is shown in
Figure 11.
The VREFADJ pin also provides an opportunity to exter-
nally adjust the bandgap voltage in a limited range (see
Figure 10) as well as the possibility to overdrive the inter-
nal bandgap with an external 1.25V reference.
The control byte defines the input channel(s), unipolar or
bipolar operation and output coding, single-ended or
differential input configuration, external or internal con-
version clock and the kind of power down that is activated
after the completion of a conversion. A detailed descrip-
tion of the control bits can be obtained from Table 7.
Figure 10: Reference Adjust Circuit
VDD = +2.7V … +5.25V
As it can also be seen in Figure 11 the acquisition of the
input signal occurs at the end of the control byte for 2.5
clock cycles. Outside this range, the Track & Hold is in
hold mode.
ZADCS10x2V
510kΩ
The conversion process is started, with the falling clock
edge (SCLK) of the eighth bit in the control byte. It takes
twelve clock cycles to complete the conversion and one
additional cycle to shift out the last bit of the conversion
result. During the remaining five clock cycles the output is
filled with zeros in 24-Clock Conversion Mode.
VREFADJ
47nF
Copyright © 2010, ZMD AG, Rev. 1.2
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Information furnished in this publication is preliminary and subject to changes without notice.
14/22
Datasheet
ZADCS1082/1042/1022 Family
Depending on what clock mode was selected, either the
external SPI clock or an internal clock is used to drive the
successive approximation. Figure 12 shows the Timing
for Internal Clock Mode.
Figure 11: 24-Clock External Clock Mode Timing (SPI™, QSPI™ and MICROWIRE™ compatible, fSCLK ≤ 3.3MHz)
nCS
tACQ
1
8
1
8
1
8
SCLK
DIN
UNI/ SGL/
BIP DIF
S
A2 A1 A0
Idle
PD1 PD0
Acquire
(Start)
Conversion
Idle
SSTRB
DOUT
Zero filled
B9 B8 B7 B6 B5 B4 B3
(MSB)
B2
B1 B0
(LSB)
Figure 12: Internal Clock Mode Timing with interleaved Control Byte transmission
nCS
1
8
1
8
1
8
SCLK
DIN
UNI/ SGL/
BIP DIF
UNI/ SGL/
BIP DIF
S
A2 A1 A0
Idle
PD1 PD0
Acquire
S
A2 A1 A0
PD1 PD0
Acquire
(Start)
Conversion
Result Output
SSTRB
DOUT
tCONV
Zero filled
B9 B8 B7 B6 B5 B4 B3
B2
B1 B0
(LSB)
(MSB)
Copyright © 2010, ZMD AG, Rev. 1.2
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Information furnished in this publication is preliminary and subject to changes without notice.
15/22
Datasheet
ZADCS1082/1042/1022 Family
Table 7: Control Byte Format
BIT
Name
Description
7 (MSB)
START
The Start Bit is defined by the first logic ‘1’ after nCS goes low.
6
5
4
A2
A1
A0
Channel Select Bits. Along with SGL/DIF these bits control the setting of the input multi-
plexer. For further details on the decoding see also Table 5 and Table 6.
3
UNI/BIP
Output Code Select Bit. The value of the bit determines conversion mode and output code
format.
‘1’ = unipolar - straight binary coding
‘0’ = bipolar - two’s complement coding
2
SGL/DIF
Single-Ended / Differential Select Bit. Along with the Channel Select Bits A2 .. A0 this bit
controls the setting of the input multiplexer
‘1’ = single ended - all channels CH0 … CH7 measured referenced to COM
‘0’ = differential - the voltage between two channels is measured
1
PD1
PD0
Power Down and Clock Mode Select Bits
0 (LSB)
PD1
PD0
Mode
0
0
1
1
0
1
0
1
Full Power-Down
Fast Power-Down
Internal clock mode
External clock mode
Figure 13: 16-Clock External Clock Mode Conversion
nCS
1
8
1
8
1
8
1
SCLK
DIN
UNI/ SGL/
BIP DIF
UNI/ SGL/
BIP DIF
S
A2 A1 A0
Idle
PD1 PD0
Acquire
S
A2 A1 A0
PD1 PD0
(Start)
Conversion
Idle
Acquire
SSTRB
DOUT
Zero filled
B9 B8 B7 B6 B5 B4 B3
(MSB)
B2
B1 B0
(LSB)
B9 B8
Figure 14: 13-Clock External Clock Mode Conversion
nCS
1
8
13
1
13
1
SCLK
DIN
UNI/ SGL/
BIP DIF
UNI/ SGL/
BIP DIF
S
A2 A1 A0
Idle
PD1 PD0
Acquire
S
A2 A1 A0
PD1 PD0
Acquire
S
A2 A1 A0
Conversion
(Start)
Conversion
SSTRB
DOUT
Zero filled
B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
(MSB) (LSB)
B9 B8 B7 B6 B5 B4 B3 B2
Copyright © 2010, ZMD AG, Rev. 1.2
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Information furnished in this publication is preliminary and subject to changes without notice.
16/22
Datasheet
ZADCS1082/1042/1022 Family
Internal Clock Mode
16-Clocks per Conversion
In Internal Clock Mode, the conversion starts at the falling
clock edge of the eighth control bit just as in External
Clock Mode. However, there are no further clock pulses
required at SCLK to complete the conversion. The con-
version clock is generated by an internal oscillator that
runs at approximately 3.3MHz. While the conversion is
running, the SSTRB signal is driven LOW. As soon as the
conversion is complete, SSTRB is switched to HIGH,
signaling that the conversion result can be read out on
the serial interface.
Interleaving of the data read out process and transmis-
sion of a new Control Byte is also supported for External
Clock Mode operation. Figure 13 shows the transmission
timing for conversion runs using 16 clock cycles per run.
13-Clocks per Conversion
ZADCS10x2 family devices do also support a 13 clock
cycle conversion mode (see Figure 14). This is the fastest
conversion mode possible. In fact, the specified converter
sampling rate of 250ksps will be reached in this mode,
provided the clock frequency is set to 3.3MHz.
To shorten cycle times ZADCS10x2 family devices allow
interleaving of the read out process with the transmission
of a new control byte. Thus it is possible to read the con-
version result and to start a new conversion with just two
consecutive byte transfers, instead of thee bytes that
would have to be send without the interleaving function.
Usually micro controllers do not support this kind of 13 bit
serial communication transfers. However, specifically
designed digital state machines implemented in Field
Programmable Gate Arrays (FPGA) or Application Spe-
cific Integrated Circuits (ASIC) may use this operation
mode.
While the IC is performing a conversion in Internal Clock
Mode, the Chip Select signal (nCS) may be tied HIGH
allowing other devices to communicate on the bus. The
output driver at DOUT is switched into a high impedance
state while nCS is HIGH. The conversion time tCONV may
vary in the specified limits depending on the actual VDD
and temperature values.
Digital Timing
In general the clock frequency at SCLK may vary from
0.1MHz to 3.3MHz. Considering all telegram pauses or
other interruptions of a continuous clock at SCLK, each
conversion must be completed within 1.2ms from the
falling clock edge of the eighth bit in the Control Byte.
Otherwise the signal that was captured during sam-
ple/hold may drop to noticeable affect the conversion
result.
Copyright © 2010, ZMD AG, Rev. 1.2
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Information furnished in this publication is preliminary and subject to changes without notice.
17/22
Datasheet
ZADCS1082/1042/1022 Family
Table 8: Timing Characterisitics (VDD = +2.7V to + 5.25V; OP = OPmin … OPmax
)
Parameter
Symbol Conditions
Min
Typ
Max
Unit
SCLK Periode
tSCLK
303.0
151.5
ns
ns
SCLK Pulse Width High
tSCLKhigh
SCLK Pulse Width Low
DIN to SCLK Setup
DIN to SCLK Hold
tSCLKlow
tDinSetup
tDinHold
151.5
30
ns
ns
ns
ns
10
nCS Fall to SCLK Setup
tnCSSetup
30
SCLK Fall to
DOUT & SSTRB Hold
tOutHold
tOutValid
CLoad = 20pF
CLoad = 20pF
10
ns
ns
ns
SCLK Fall to
DOUT & SSTRB Valid
40
60
60
nCS Rise to
DOUT & SSTRB Disable
tOutDisable CLoad = 20pF
10
nCS Fall to
DOUT & SSTRB Enable
tOutEnable CLoad = 20pF
tnCSHigh
ns
ns
nCS Pulse Width High
100
Figure 15: Detailed Timing Diagram
nCS
tSCLKhigh
tnCSSetup
tSCLK
tSCLKlow
tOutValid
SCLK
tDINsetup
tDINhold
DIN
SSTRB
DOUT
tnCSHigh
tOutEnable
tOutDisable
tOutHold
tOutEnable
Further detailed timing information on the digital interface
is provided in Table 8 and Figure 15.
In bipolar mode a two’s complement coding is applied.
Code transitions occur again halfway between successive
integer LSB values. The transfer function is shown in
Figure 17.
Output Code Format
ZADCS10x2 family devices do all support unipolar and
bipolar operation modes. The digital output code is
straight binary in unipolar mode. It ranges from 0x000 for
an input voltage difference of 0V to 0x3FF for an input
voltage difference of VREF (Full Scale = FS). The first
code transition (0x000 0x001) occurs at a voltage
equivalent to ½ LSB, the last (0x3FE 0x3FF) at
VREF - 1.5 LSB. See also Figure 16 for details.
Copyright © 2010, ZMD AG, Rev. 1.2
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18/22
Datasheet
ZADCS1082/1042/1022 Family
Figure 16: Unipolar Transfer Function
Figure 17: Bipolar Transfer Function
Output Code
Output Code
ZS = V(IN-)
11 … 111
11 … 110
+ FS = ½VREF +V(IN-)
01 … 111
01 … 110
- FS = -½VREF +V(IN-)
VREF
11 … 101
1LSB =
1024
00 … 011
00 … 001
00 … 000
11 … 111
11 … 110
11 … 101
ZS = V(IN-)
FS = VREF +V(IN-)
VREF
1LSB =
1024
00 … 010
00 … 001
00 … 000
10 … 001
10 … 000
0
1
2
3
FS
-FS
ZS
+FS
(ZS)
FS-3/2 LSB
+FS-3/2 LSB
Input Voltage (LSB)
Input Voltage (LSB)
Hardware Power Down
2.5 Power Dissipation
The third power down mode is called Hardware Power-
Down. It is initiated by pulling the nSHDN pin LOW. If this
condition is true, the device will immediately shut down all
circuitry just as in Full Power Down-Mode.
The ZADCS10x2 family offers three different ways to
save operating current between conversions. Two differ-
ent software controlled power down modes can be acti-
vated to automatically shut-down the device after comple-
tion of a conversion. They differ in the amount of circuitry
that is powered down.
The IC wakes up if nSHDN is tied HIGH. There is no
internal pull-up that would allow nSHDN to float during
normal operation. This ensures the lowest possible power
consumption in power down mode.
Software Power Down
Full Power Down Mode shuts down the entire analog part
of the IC, reducing the static IDD of the device to less
than 0.5µA if no external clock is provided at SCLK.
General Power Considerations
Even without activating any power down mode, the de-
vices out of the ZADCS10x2 family reduce their power
consumption between conversions automatically. The
comparator, which contributes a considerable amount to
the overall current consumption of the device, is shut off
as soon as a conversion is ended. It gets turned on at the
start of the next acquisition period. This explains the
difference between the IDDstatic and IDDactive meas-
urements shown in chapter 1.6 Typical Operating Char-
acteristics.
Fast Power Down mode is only useful with ZADCS10x2V
devices if the internal voltage reference is used. During
Fast Power-Down the bandgap and the VREFADJ output
buffer are kept alive while all other internal analog cir-
cuitry is shut down. The benefit of Fast Power Down
mode is a shorter turn on time of the reference compared
to Full Power-Down Mode. This is basically due to the
fact that the low pass which is formed at the VREFADJ
output by the internal 20kΩ resistor and the external
buffer capacitor of 47nF is not discharged in Fast Power-
Down Mode.
The average current consumption of the device depends
very much on the sampling frequency and the type of
protocol used to communicate with the device.
The settling time of the low pass at VREFADJ is about
7 ms to reach 10 bit accuracy. The Fast Power Down
mode omits this settling and reduces the turn on time to
about 200µs.
In order to achieve the lowest power consumption at low
sampling frequencies, it is suggested to keep the conver-
sion clock frequency at the maximum level of 3.3MHz and
to power down the device between consecutive conver-
sions. Figure 18 shows the characteristic current con-
sumption of the ZADCS10x2 family with external refer-
ence supply versus Sampling Rate
To wake up the IC out of either software power down
mode, it is sufficient to send a Start Bit while nCS is
LOW. Since micro controllers can commonly transfer full
bytes per transaction only, a dummy conversion is usually
carried out to wake the device.
3 Layout
In all application cases where an external reference volt-
age is supplied (basic ZADCS10x2 and ZADCS10x2V
with VREFADJ tied to VDD) there is no turn on time to be
considered. The first conversion is already valid. Fast
Power-Down and Full Power-Down Mode do not show
any difference in this configuration.
To achieve optimum conversion performance care must
be taken in design and layout of the application board. It
is highly recommended to use printed circuit boards in-
stead of wire wrap designs and to establish a single point
Copyright © 2010, ZMD AG, Rev. 1.2
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The
Information furnished in this publication is preliminary and subject to changes without notice.
19/22
Datasheet
ZADCS1082/1042/1022 Family
Figure 18: Average Supply Current versus Sampling
Rate
Figure 19: Optimal Power-Supply Grounding System
Optional
R = 10Ω
Current consumption vs. Sample Rate
External Clock Mode, External VREF, fSCLK = 3.3MHz
VDD1
(+2.7 … +5.25V)
VDD
10000
1000
100
10
ZADCS10x2
Family
AGND
COM
DGND
Other
Digital
Circuitry
DGND
DVDD
GND
1
VDD2
1
10
100
1000
Sample Rate (ksps)
star connection ground system towards AGND (see
Figure 19).
logic should be avoided during the sampling phase of the
converter.
For optimal noise performance the star point should be
located very close to the AGND pin of the converter. The
ground return to the power supply should be as short as
possible and low impedance.
The fully differential internal architecture of the
ZADCS10x2 family ensures very good suppression of
power supply noise. Nevertheless, the SAR architecture
is generally sensitive to glitches or sudden changes of the
power supply that occur shortly before the latching of the
comparator output. It is therefore recommended to by-
pass the power supply connection very close to the de-
vice with capacitors of 0.1µF (ceramic) and >1µF (electro-
lytic).
All other analog ground points of external circuitry that is
related to the A/D converter as well as the DGND pin of
the device should be connected to this ground point too.
Any other digital ground system should be kept apart as
far as possible and connect on the power supply point
only.
In case of a noisy supply, an additional series resistor of
5 to 10 ohms can be used to low-pass filter the supply
voltage.
Analog and digital signal domains should also be sepa-
rated as well as possible and analog input signals should
be shielded by AGND ground planes from electromag-
netic interferences. Four-layer PCB boards that allow
smaller vertical distances between the ground plane and
the shielded signals do generally show a better perform-
ance than two-layer boards.
The reference voltage should always be bypassed with
capacitors of 0.1µF (ceramic) and ≥ 4.7µF (electrolytic) as
close as possible to the VREF pin. If VREF is provided by
an external source, any series resistance in the VREF
supply path can cause a gain error of the converter. Dur-
ing conversion, a DC current of about 100µA is drawn
through the VREF pin that could cause a noticeable volt-
age drop across the resistance.
The sampling phase is the most critical portion of the
overall conversion timing for signal distortion. If possible,
the switching of any high power devices or nearby digital
Copyright © 2010, ZMD AG, Rev. 1.2
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The
Information furnished in this publication is preliminary and subject to changes without notice.
20/22
Datasheet
ZADCS1082/1042/1022 Family
4 Package Drawing
ZADCS1082 devices are delivered in a 20-pin SSOP-package that has the dimensions as shown in Figure 20 and Table 9.
ZADCS1042 and ZADCS1022 devices apply respective 16-pin and 14-pin SSOP-packages. Their dimensions are specified
in Table 10 and Table 11.
Figure 20: Package Outline Dimensions
Table 9: Package Dimensions for ZADC1082 devices (mm)
Symbol
A
A1
A2
bP
c
D
E
enom
0.65
HE
LP
0.63
LP
Z
k
θ
Nominal
Maximum
Minimum
1.86
1.99
1.73
0.13
0.21
0.05
1.73
1.78
1.68
0.30
0.38
0.25
0.15
0.20
0.09
7.20
7.33
7.07
5.30
5.38
5.20
7.80
7.90
7.65
4°
8°
0°
0.74
0.25
k
Table 10: Package Dimensions for ZADC1042 devices (mm)
Symbol
A
A1
A2
bP
c
D
E
enom
0.65
HE
Z
θ
4°
Nominal
Maximum
Minimum
1.86
1.99
1.73
0.13
0.21
0.05
1.73
1.78
1.68
0.30
0.38
0.25
0.15
0.20
0.09
6.20
6.07
6.33
5.30
5.38
5.20
7.80
7.90
7.65
0.89
10°
0°
0.63
LP
0.25
k
Table 11: Package Dimensions for ZADC1022 devices (mm)
Symbol
A
A1
A2
bP
c
D
E
enom
0.65
HE
Z
θ
4°
Nominal
Maximum
Minimum
1.86
1.99
1.73
0.13
0.21
0.05
1.73
1.78
1.68
0.30
0.38
0.25
0.15
0.20
0.09
6.20
6.33
6.07
5.30
5.38
5.20
7.80
7.90
7.65
1.22
10°
0°
0.63
0.25
Copyright © 2010, ZMD AG, Rev. 1.2
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The
Information furnished in this publication is preliminary and subject to changes without notice.
21/22
Datasheet
ZADCS1082/1042/1022 Family
5 Ordering Information
Order Code
ZADCS1082VIS20T
ZADCS1082IS20T
ZADCS1042VIS16T
ZADCS1042IS16T
ZADCS1022VIS14T
ZADCS1022IS14T
10
10
10
10
10
10
8
8
4
4
2
2
250
250
250
250
250
250
-25°C to +85°C
-25°C to +85°C
-25°C to +85°C
-25°C to +85°C
-25°C to +85°C
-25°C to +85°C
--
--
--
--
--
--
--
--
--
± 0,4 LSB ± 0,4 LSB
20 SSOP Tube
20 SSOP Tube
16 SSOP Tube
16 SSOP Tube
14 SSOP Tube
14 SSOP Tube
± 0,4 LSB ± 0,4 LSB
± 0,4 LSB ± 0,4 LSB
± 0,4 LSB ± 0,4 LSB
± 0,4 LSB ± 0,4 LSB
± 0,4 LSB ± 0,4 LSB
ZADCS1082VQS20T
ZADCS1082QS20T
ZADCS1042VQS16T
ZADCS1042QS16T
ZADCS1022VQS14T
ZADCS1022QS14T
10
10
10
10
10
10
8
8
4
4
2
2
250
250
250
250
250
250
-40°C to +125°C
-40°C to +125°C
-40°C to +125°C
-40°C to +125°C
-40°C to +125°C
-40°C to +125°C
--
--
--
± 0,4 LSB ± 0,4 LSB
± 0,4 LSB ± 0,4 LSB
± 0,4 LSB ± 0,4 LSB
± 0,4 LSB ± 0,4 LSB
± 0,4 LSB ± 0,4 LSB
± 0,4 LSB ± 0,4 LSB
20 SSOP Tube
20 SSOP Tube
16 SSOP Tube
16 SSOP Tube
14 SSOP Tube
14 SSOP Tube
6 ZMDI Contact
For the most current revision of this document and for additional product information please visit www.zmdi.com.
Sales and Further Information
www.zmdi.com
sales@zmdi.com
ZMD Far East, Ltd.
3F, No. 51, Sec. 2,
Keelung Road
11052 Taipei
Taiwan
Zentrum Mikroelektronik
Dresden AG (ZMD AG)
Grenzstrasse 28
ZMD America, Inc.
8413 Excelsior Drive
Suite 200
ZMD AG, Japan Office
2nd Floor, Shinbashi Tokyu Bldg.
4-21-3, Shinbashi, Minato-ku
Tokyo, 105-0004
Madison, WI 53717
01109 Dresden
Japan
Germany
USA
Phone +49 (0)351.8822.7.772
Phone +01 (608) 829-1987
Phone +81.3.6895.7410
Phone +886.2.2377.8189
Fax
+49(0)351.8822.87.772
Fax
+01 (631) 549-2882
Fax
+81.3.6895.7301
Fax
+886.2.2377.8199
DISCLAIMER: This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Zentrum Mikroelektronik Dresden AG
(ZMD AG) assumes no obligation regarding future manufacture unless otherwise agreed to in writing. The information furnished hereby is believed to be true and accurate. However,
under no circumstances shall ZMD AG be liable to any customer, licensee, or any other third party for any special, indirect, incidental, or consequential damages of any kind or nature
whatsoever arising out of or in any way related to the furnishing, performance, or use of this technical data. ZMD AG hereby expressly disclaims any liability of ZMD AG to any cus-
tomer, licensee or any other third party, and any such customer, licensee and any other third party hereby waives any liability of ZMD AG for any damages in connection with or arising
out of the furnishing, performance or use of this technical data, whether based on contract, warranty, tort (including negligence), strict liability, or otherwise.
Copyright © 2010, ZMD AG, Rev. 1.2
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The
Information furnished in this publication is preliminary and subject to changes without notice.
22/22
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