ZMD31015ACG1-R_技术文档

ZMD31015

RBic_dLite^TMLow-Cost Sensor Signal Conditioner with Diagnostics

Datasheet

PRELIMINARY

Features

The RBic_dLite™ is adjustable to nearly all piezo-resis-

tive bridge sensors. Measured and corrected bridge

values are provided at the SIG™ pin, which can be

configured as an analog voltage output or as a one-

wire serial digital output.

•

Digital compensation of sensor offset, sensitivity,

temperature drift and non-linearity

Programmable analog gain and digital gain; accom-

modates bridges with spans < 1mV/V and high offset

Many diagnostic features on chip (e.g., EEPROM

signature, bridge connection checks, bridge short

detection, power loss detection)

The digital one-wire interface can be used for a simple

PC-controlled calibration procedure to program a set

of calibration coefficients into an on-chip EEPROM.

The calibrated RBic_dLite™ and a specific sensor are

mated digitally: fast, precise, and without the cost

overhead associated with trimming by external

•

Independently programmable high and low clipping

levels

•

24-bit customer ID field for module traceability

Digital calibration and configuration via one-wire

interface – quick and precise

devices or laser. Integrated diagnostics functions

TM

make the RBic_dLite

particularly well suited for

•

Internal temperature compensation reference (no

external components)

automotive applications.

Option for external temperature compensation with

addition of single diode.

•

The RBic_dLite^TMDevelopment Kit is available -

includes the Development Board, SOP8 samples,

software, and documentation.

Output options: rail-to-rail ratiometric analog voltage

(12-bit resolution), absolute analog voltage, digital one-

wire-interface

•

Support for industrial mass calibration is

available

•

Supply voltage 2.7 to 5.5V; with external JFET, 5.5 to

30V

Quick circuit customization possible for large

production volumes

Fast power-up to data out response; output available

5ms after power up

Current consumption depends on programmed sample

rate; 1mA down to 250μA (typical)

Operation temperature: –50°C to +150°C

Fast response time: 1ms (typical)

High voltage protection up to 30V with external JFET¹

No external trimming components required

Application Circuit

V_supply+2.7 V to 5.5 V

V+

•

Vgate

VDD

High accuracy (±0.1% FSO @ -25 to 85°C; ±0.25%

FSO @ -50 to 150°C)

RBic_dLite

Brief Description

OUT/OWI

0.1µF

Sig^TM

The RBic_dLite^TMis a CMOS integrated circuit for highly

accurate amplification and sensor-specific correction

of bridge sensor signals. Digital compensation of

sensor offset, sensitivity, temperature drift and non-

linearity is accomplished via an internal digital signal

processor running a correction algorithm with cali-

bration coefficients stored in a non-volatile EEPROM.

OUT

VBP

/OW

I

VBN

VSS

GND

Typical RBic_dLite^TMApplication Circuit

Preliminary dLite Datasheet, Rev. 0.951, May 23, 2008

Page 1 of 44

consent of the copyright owner. The Information furnished in this publication is preliminary and subject to changes without notice.

ZMD31015

RBic_dLite^TMLow-Cost Sensor Signal Conditioner with Diagnostics

Datasheet

PRELIMINARY

CONTENTS

1

IC CHARACTERISTICS.............................................................................................................................. 4

1.1

1.2

1.3

1.4

ABSOLUTE MAXIMUM RATINGS....................................................................................................... 4

RECOMMENDED OPERATING CONDITIONS................................................................................... 4

ELECTRICAL PARAMETERS.............................................................................................................. 5

ANALOG INPUT VERSUS OUTPUT RESOLUTION........................................................................... 8

2

CIRCUIT DESCRIPTION........................................................................................................................... 10

2.1

2.2

2.2.1

2.2.2

SIGNAL FLOW AND BLOCK DIAGRAM ........................................................................................... 10

ANALOG FRONT END....................................................................................................................... 11

Bandgap/PTAT and PTAT Amplifier ........................................................................................... 11

Bridge Supply .............................................................................................................................. 11

Pre-Amp Block............................................................................................................................. 11

Analog-to-Digital Converter (ADC).............................................................................................. 11

2.2.3

2.2.4

2.3

2.3.1

2.3.2

2.4

2.4.1

2.4.2

2.4.3

DIGITAL SIGNAL PROCESSOR ....................................................................................................... 12

EEPROM..................................................................................................................................... 13

One-Wire Interface – ZACwire™................................................................................................. 13

OUTPUT STAGE................................................................................................................................ 13

Digital-to-Analog Converter (Output DAC) with Programmable Clipping Limits ......................... 13

Output Buffer ............................................................................................................................... 14

Voltage Reference Block............................................................................................................. 14

2.5

CLOCK GENERATOR / POWER-ON RESET (CLKPOR)................................................................. 16

2.5.1

Trimming the Oscillator ............................................................................................................... 16

2.6

DIAGNOSTIC FEATURES................................................................................................................. 17

2.6.1

2.6.2

EEPROM Integrity....................................................................................................................... 17

Sensor Connection Check........................................................................................................... 17

Sensor Short Check .................................................................................................................... 18

Power Loss Detection ................................................................................................................. 18

ExtTemp Connection Checks...................................................................................................... 18

2.6.3

2.6.4

2.6.5

3

FUNCTIONAL DESCRIPTION.................................................................................................................. 19

3.1

3.2

3.2.1

3.2.2

GENERAL WORKING MODE............................................................................................................ 19

ZACWIRE™ COMMUNICATION INTERFACE.................................................................................. 21

Properties and Parameters ......................................................................................................... 21

Bit Encoding ................................................................................................................................ 21

Write Operation from Master to RBic_dLite^TM.................................................................................. 22

RBic_dLite^TMREAD Operations....................................................................................................... 22

High Level Protocol ..................................................................................................................... 25

3.2.3

3.2.4

3.2.5

3.3

COMMAND/DATA PAIR ENCODING ................................................................................................ 26

Preliminary dLite Datasheet, Rev. 0.951, May 23, 2008

Page 2 of 44

written consent of the copyright owner. The Information furnished in this publication is preliminary and subject to changes without notice.

ZMD31015

RBic_dLite^TMLow-Cost Sensor Signal Conditioner with Diagnostics

Datasheet

PRELIMINARY

3.4

3.5

3.6

CALIBRATION SEQUENCE .............................................................................................................. 27

EEPROM BITS ................................................................................................................................... 30

CALIBRATION MATH ........................................................................................................................ 33

3.6.1

3.6.2

3.7

Correction Coefficients................................................................................................................ 33

Interpretation of Binary Numbers for Correction Coefficients ..................................................... 34

READING EEPROM CONTENTS...................................................................................................... 38

4

APPLICATION CIRCUIT EXAMPLES...................................................................................................... 39

4.1

THREE-WIRE RAIL-TO-RAIL RATIOMETRIC OUTPUT................................................................... 39

ABSOLUTE ANALOG VOLTAGE OUTPUT ..................................................................................... 40

THREE-WIRE RATIOMETRIC OUTPUT WITH OVER-VOLTAGE PROTECTION........................... 41

DIGITAL OUTPUT.............................................................................................................................. 41

OUTPUT RESISTOR/CAPACITOR LIMITS....................................................................................... 42

4.2

4.3

4.4

4.5

5

ESD/LATCH-UP-PROTECTION ............................................................................................................... 42

PIN CONFIGURATION AND PACKAGE.................................................................................................. 43

TEST.......................................................................................................................................................... 43

RELIABILITY............................................................................................................................................. 43

CUSTOMIZATION..................................................................................................................................... 44

RELATED DOCUMENTS...................................................................................................................... 44

6

7

8

9

10

Preliminary dLite Datasheet, Rev. 0.951, May 23, 2008

Page 3 of 44

written consent of the copyright owner. The Information furnished in this publication is preliminary and subject to changes without notice.

ZMD31015

RBic_dLite^TMLow-Cost Sensor Signal Conditioner with Diagnostics

Datasheet

PRELIMINARY

1

IC Characteristics

1.1 Absolute Maximum Ratings

PARAMETER

SYMBOL MIN TYP

MAX

6.0

UNITS

V_DD

V_INA

Analog Supply Voltage

-0.3

-50

V

Voltages at Analog I/O – In Pin

Voltages at Analog I/O – Out Pin

V_DD+0.3

150

V_OUTA

T_STOR

V

°C

Storage Temperature Range (≥10 hours)

T_STOR<10h

Storage Temperature Range (<10 hours)

-50

170

1.2 Recommended Operating Conditions

PARAMETER

SYMBOL MIN TYP

MAX

UNITS

Analog Supply Voltage to Gnd

V_DD

2.7

5.5

5.0

7

5.5

V

Analog Supply Voltage (with external JFET

Regulator¹)

V_SUPP

30

V_DD-1.3

150

Common Mode Voltage

V_CM

T_AMB

C_VDD

R_L,OUT

C_L,OUT

R_BR

1

V

Ambient Temperature Range ^2&3

-50

°C

nF

kΩ

nF

kΩ

ms

External Capacitance between V_DDand Gnd

100 220

470

4

Output Load Resistance to V_SSor V_DD

5

Output Load Capacitance⁵

10

15

Bridge Resistance

0.2⁶

100

Power ON Rise Time

t_PON

1

With the previous revision C (ES), the JFET regulation option was not yet available (refer to ZMD31015 Technical Notes – Revision C1

Engineering Samples).

2

3

4

Note that the maximum calibration temperature is 85°C.

If buying die, designers should use caution not to exceed maximum junction temperature by proper package selection.

Only needed for Analog Output Mode; not needed for Digital Output Mode. When a pull-down resistor is used as load resistor, the

power loss detection diagnostic for loss of VSS cannot be assured at RL=5k; RL=10k is recommended for this configuration.

When using the output for digital calibration, no pull down resistor is allowed.

5

6

Using the output for digital calibration, C_L,OUTis limited by the maximum rise time T_ZACrise. See section 1.3.

Note: Minimum bridge resistance is only a factor if using the Bsink feature. The R_DS(ON) of the Bsink transistor is 8 to 10Ω when

operating at VDD=5V. This does give rise to a ratiometricity inaccuracy that becomes greater with low bridge resistances.

Preliminary dLite Datasheet, Rev. 0.951, May 23, 2008

Page 4 of 44

written consent of the copyright owner. The Information furnished in this publication is preliminary and subject to changes without notice.

ZMD31015

RBic_dLite^TMLow-Cost Sensor Signal Conditioner with Diagnostics

Datasheet

PRELIMINARY

1.3 Electrical Parameters

See important footnotes at the end of the following table.

PARAMETER

SYMBOL CONDITIONS

SUPPLY VOLTAGE / REGULATION

MIN

TYP

MAX

UNITS

Supply Voltage

V_DD

I_DD

2.7

5.0

250

5.5

V

At minimum update rate.

At maximum update rate.

Supply Current (varies with

μΑ

update rate¹and output mode)

1000

Temperature Coefficient –

PTAT Source

T_CPTAT

20

100

ppm/K^*

Power Supply Rejection Ratio

Power-On Reset Level

PSRR

POR

60

dB^*

V

1.4

2.6

ANALOG FRONT END (AFE)

Leakage Current Pin VBP,VBN

I_{IN_LEAK}

Sensor connection and short

check must be disabled.

nA

±10

ANALOG TO DIGITAL CONVERTER (ADC)

r_ADC

14

Bit

Resolution

Integral Nonlinearity (INL)

Differential Nonlinearity (DNL)

INL_ADC

Based on ideal slope

-4

-1

+4

+1

LSB²

LSB^*

DNL_ADC

ANALOG OUTPUT PARAMETERS (DAC + BUFFER)

Max current maintaining accuracy

Referenced to V_DD

Max. Output Current

Resolution

I_OUT

Res

2.2

mA

Bit

12

DAC input to output

No missing codes

Absolute Error

E_ABS

DNL

V_OUT

-10

-0.9

95%

+10

+1.5

mV

*

Differential Nonlinearity

Upper Output Voltage Limit

Lower Output Voltage Limit

LSB_11Bit

V_DD

R_L=5kΩ

2.5

40

mV

@5kΩ pull down, 0-1V output

Depends on operating conditions.

Short circuit protection must be

enabled via Diag_cfg (EEPROM

word [102:100]). See section

2.4.2 for details.

Output Short Circuit

Protection Limit

I_SC

3

mA

Preliminary dLite Datasheet, Rev. 0.951, May 23, 2008

Page 5 of 44

written consent of the copyright owner. The Information furnished in this publication is preliminary and subject to changes without notice.

ZMD31015

RBic_dLite^TMLow-Cost Sensor Signal Conditioner with Diagnostics

Datasheet

PRELIMINARY

PARAMETER

SYMBOL CONDITIONS

DIAGNOSTICS

MIN

TYP

MAX

UNITS

Upper diagnostic output level

Lower diagnostic output level

V_DIA,H

V_DIA,L

97.5%

V_DD

2.5%

Pull-up or pull-down³in Analog

Output Mode

Min Load Resistor for power loss

R _{L,OUT_PS}

5

kΩ

EXTERNAL TEMPERATURE MEASUREMENT

ExtTemp Signal Input Range

V_TSE

150

1.9

800

mV

Required External Temperature

Diode Sensitivity

ST_TSE

3.25

mV/K

Temperature Span with External

Temperature Diode

T_{TSE_SP}

-50

150

1.5

°C

SYSTEM RESPONSE

Startup Time

t_STA

ms

Response Time for

Analog Output¹

Determined by the update rate for

T_RES,ADC

1

analog output modes (1kHz)

Response and Transmission

Time for Digital Output

Varies with update rate. Value

T_{RES, DIG}

1.6

ms

given at fastest rate.

Shorted input

V_NOISE,PP

5

Analog Output Noise

Peak-to-Peak

mV

±1LSB

ZACwire™ Serial Interface^*

See important limitations in

R_ZAC,line

ZACwire™ Line Resistance

ZACwire™ Load Capacitance

3.9

kΩ

footnote 4 below table.

See important limitations in

C_ZAC,load

0

1

15

nF

footnote 4 below table.

0

1

Voltage Level Low

Voltage Level High

V_{ZAC_LOW}

V_{ZAC_HIGH}

0.2

V_DD

0.8

Preliminary dLite Datasheet, Rev. 0.951, May 23, 2008

Page 6 of 44

written consent of the copyright owner. The Information furnished in this publication is preliminary and subject to changes without notice.

ZMD31015

RBic_dLite^TMLow-Cost Sensor Signal Conditioner with Diagnostics

Datasheet

PRELIMINARY

PARAMETER

SYMBOL CONDITIONS

TOTAL SYSTEM

MIN

TYP

MAX

UNITS

Power-up to output

Update_rate=1ms

Start-Up-Time

t_STA

t_RESP

f_S

5

2

ms

Hz

mA

%

Response Time

1

1000

1

Update_rate=1ms

Sampling Rate

Update_rate=1ms

Supply Current

I_DD

1.5

0.04

0.2

Bridge input to output

Not using Bsink feature

Overall Linearity Error – Digital

Overall Linearity Error – Analog

Overall Ratiometricity Error

E_LIND

E_LINA

RE_out

AC_outD

0.025

0.1

%

0.035

%

Overall Accuracy – Digital⁵

(only IC, without sensor bridge)

-25°C to 85°C

-50°C to 150°C

±0.1%

%FSO

±0.25%

Overall Accuracy – Analog ^5,6

(only IC, without sensor bridge)

AC_outA

-25°C to 85°C

-40°C to 125°C

-50°C to 150°C

±0.25%

±0.35%

±0.5%

%FSO

* The parameters with an * under “Units” are tested by design.

¹Note: For the previous revision C (ES), the lower update rates (200Hz, 40Hz, and 8Hz) can only be used with the digital output mode

configuration.

²Note: This is ± 4 LSBs for the 14-bit A-to-D conversion. This results in absolute accuracy to 12-bits on the A-to-D result. Non-linearity is

typically better at temperatures less than 125°C.

³When using a pull down resistor as load resistor the power loss detection diagnostic for loss of VSS cannot be assured at RL=5k,

RL=10k is recommended for this configuration.

⁴The rise time must be t_ZAC,rise= 2 R_ZAC,load* C_ZACload≤ 5μs . If using a pull-up resistor instead of the line resistor, it must meet this

specification. The absolute maximum for C_ZACloadis 15nF.

⁵A random additional noise in a very small temperature range (<2°C) or small range of the supply voltage can appear. For more details,

refer to ZMD31015_RBic_dLite_Errata_RevC1_ES.pdf .

⁶Not included is the quantization noise of the DAC. The 12-bit DAC has a quantization noise of ± ½ LSB = 0.61mV (@ 5V VDD) =

0.0125%.

Preliminary dLite Datasheet, Rev. 0.951, May 23, 2008

Page 7 of 44

written consent of the copyright owner. The Information furnished in this publication is preliminary and subject to changes without notice.

ZMD31015

RBic_dLite^TMLow-Cost Sensor Signal Conditioner with Diagnostics

Datasheet

PRELIMINARY

1.4 Analog Input versus Output Resolution

The RBic_dLite™ has a fully differential chopper-stabilized pre-amplifier with 4 programmable gain settings. The

output of the pre-amplifier feeds into a 14-bit charge-balanced ADC. Span, offset, temperature, and non-

linearity correction are performed in the digital domain. Then the resulting corrected bridge value can be

output in analog form through a 12-bit DAC or as a 16-bit serial digital packet. The resolution of the output

depends on the input span (bridge sensitivity) and the analog gain setting programmed. Digital gains can vary

from [0,32). Analog gains available are 6, 24, 48, and 96.

The following tables outline the guaranteed minimum resolution for a given bridge sensitivity range. The

yellow shadowed fields indicate that for these input spans with the selected analog gain setting, the

quantization noise is higher than 0.1% FSO.

Analog Gain 6

Input Span (mV/V)

Allowed Offset

(+/- % of Span)¹

Minimum Guaranteed

Resolution (Bits)

Min

Typ

Max

57.3

80.0

105.8

38%

53%

13.3

13.1

12.9

12.6

12.3

11.9

50.6

43.4

36.1

28.9.5

21.7

70.0

60.0

50.0

40.0

30.0

92.6

79.4

66.1

52.9

39.7

73%

101%

142%

212%

Analog Gain = 24

Input Span (mV/V)

Typ Max

25.0

Allowed Offset

(+/- % of Span)¹

Minimum Guaranteed

Resolution (Bits)

Min

16

36

25%

50%

12.6

12

11

10

9

12.8

6.4

3.2

1.6

0.8

20.0

10.0

5.0

28.8

14.4

7.2

150%

400%

900%

2000%

2.5

3.6

1.2

1.7

8

¹In addition to Tco,Tcg

Preliminary dLite Datasheet, Rev. 0.951, May 23, 2008

Page 8 of 44

written consent of the copyright owner. The Information furnished in this publication is preliminary and subject to changes without notice.

ZMD31015

RBic_dLite^TMLow-Cost Sensor Signal Conditioner with Diagnostics

Datasheet

PRELIMINARY

Analog Gain = 48

Input Span (mV/V)

Typ Max

15.0

Allowed Offset

(+/- % of Span)¹

Minimum Guaranteed

Resolution (Bits)

Min

10.8

19.8

13.2

7.9

3%

35%

13

7.2

4.3

2.9

1.8

1.0

0.72

10.0

6.0

4.0

2.5

1.4

1.0

12.4

11.7

11.1

10.4

9.6

100%

190%

350%

675%

975%

5.3

3.3

1.85

1.32

9.1

¹In addition to Tco,Tcg

Analog Gain = 96

Input Span (mV/V)

Typ Max

6.0

Allowed Offset

(+/- % of Span)¹

Minimum Guaranteed

Resolution (Bits)

Min

4.3

7.9

20%

60%

12.7

12.1

11.4

10.6

10.1

2.9

4.0

2.5

1.4

1.0

5.3

1.8

3.3

140%

300%

450%

1.0

0.72

1.85

1.32

¹In addition to Tco,Tcg

Note: At higher analog gain settings, there will be higher output resolution, but the ability of the RBic_dLite™ to

handle large offsets decreases. This is expected because the offset is also amplified by the analog gain and

can therefore saturate the ADC input.

Preliminary dLite Datasheet, Rev. 0.951, May 23, 2008

Page 9 of 44

written consent of the copyright owner. The Information furnished in this publication is preliminary and subject to changes without notice.

ZMD31015

RBic_dLite^TMLow-Cost Sensor Signal Conditioner with Diagnostics

Datasheet

PRELIMINARY

2

Circuit Description

2.1 Signal Flow and Block Diagram

The RBic_dLite^TMseries of resistive bridge sensor interface ICs were specifically designed as cost-effective

solutions for sensing in building automation, automotive, industrial, office automation and white goods

applications. The RBic_dLite^TMemploys ZMD’s high precision bandgap with proportional-to-absolute-

temperature (PTAT) output; low-power 14-bit analog-to-digital converter (ADC, A2D, A-to-D); and an on-chip

DSP core with EEPROM to precisely calibrate the bridge output signal.

Three selectable outputs, two analog and one digital, offer the ultimate in versatility across many applications.

The RBic_dLiterail-to-rail ratiometric analog V_outsignal (0V to ~5 V V_out@ V_DD=5V) suits most building automa-

tion and automotive requirements (12-bit resolution). Typical office automation and white goods applications

require the 0 to ~1V V_outsignal, which in the RBic_dLite™ is referenced to the internal bandgap. RBic_dLite™ is

capable of running in high-voltage (5.5-30V) systems when combined with an external JFET¹.

Direct interfacing to μP controllers is facilitated via ZMD’s single-wire serial ZACwire^TMdigital interface.

JFET¹

V_SUPPLY= 5.5V to 30V

(Optional if supply is 2.7 to 5.5V)

S

D

V_gate

V_DD

(2.7-5.5V)

0.1µF

Temperature

Reference

PTAT

12-Bit

DAC

V_DD

Regulator

Sensor

Diagnostics

RBic_dLite

™

DUALDAC

A

D

SIG^TM

-

V_BP

+

0V to1 V,

V_BN

ExtTemp

INMUX

14-Bit ADC

PREAMP

Rail-To-Rail

Ratiometric,

OUTBUF1

OWI/ZACwire™

Optional

Bsink

ZACwire^TM

Interface

Power Save

EEPROM

W/ Charge

Pump

Digital

Core

Power Lost

Diagnostic

Optional

Ext. Diode

for Temp.

POR/Oscillator

V_SS

Figure 2.1 – RBic_dLite™ Block Diagram

1

With the previous revision C (ES), the JFET regulation option was not yet available (refer to ZMD31015 Technical Notes – Revision C1

Engineering Samples).

Preliminary dLite Datasheet, Rev. 0.951, May 23, 2008

Page 10 of 44

written consent of the copyright owner. The Information furnished in this publication is preliminary and subject to changes without notice.

ZMD31015

RBic_dLite^TMLow-Cost Sensor Signal Conditioner with Diagnostics

Datasheet

PRELIMINARY

2.2 Analog Front End

2.2.1 Bandgap/PTAT and PTAT Amplifier

The highly linear Bandgap/PTAT section provides the PTAT signal to the ADC, which allows accurate

temperature conversion. In addition, the ultra-low ppm Bandgap provides a stable voltage reference over

temperature for the operation of the rest of the IC. If the bridge is not near the RBic_dLite™, an external diode

can be used for temperature measurement/compensation.

The temperature signal (internal PTAT or external diode) is amplified through a path in the Pre-Amp and fed

to the ADC for conversion. The most significant 12-bits of this converted result are used for temperature

measurement and temperature correction of bridge readings. When temperature is output in Digital Mode,

only the most significant 8 bits are given.

When external temperature is selected, add a diode from the ExtTemp pin to ground. The diode is biased with

approximately 50µA during temperature measurement cycles. The voltage level on ExtTemp is amplified

through the Pre-Amp and converted by the ADC. Ensure that the ExtTemp signal is in the range of 150mV to

800mV to prevent saturation of the ADC. If the selected diode has a sensitivity in the range of 1.9mV/^oC to

3.25mV/^oC, a corrected temperature output (in Digital Mode) can be achieved for a 200^oC temperature span

(-50^oC to 150^oC).

2.2.2 Bridge Supply

The voltage-driven bridge is usually connected to V_DDand ground. As a power savings feature available for

digital output mode only, the RBic_dLite™ also includes a switched transistor to interrupt the bridge current via

pin 1 (Bsink). The transistor switching is synchronized to the analog-to-digital conversion and released after

finishing the conversion. To utilize this feature, the low supply of the bridge should be connected to Bsink

instead of ground.

Depending on the programmable update rate, the average current consumption (including bridge current) can

be reduced to approximately 20%, 5% or 1%.

2.2.3 Pre-Amp Block

The differential signal from the bridge is amplified through a chopper-stabilized instrumentation amplifier with

very high input impedance designed for low noise and low drift. This pre-amp provides gain for the differential

signal and re-centers its DC to V_DD/2. The output of the Pre-Amp block is fed into the ADC. The calibration

sequence performed by the digital core includes an auto-zero sequence to null any drift in the Pre-Amp state

over temperature.

The Pre-Amp can be set to a gain of 6, 24, 48 or 96 through EEPROM.

The inputs to the Pre-Amp from (VBN/VBP pins) can be reversed via an EEPROM configuration bit.

2.2.4 Analog-to-Digital Converter (ADC)

A 14-bit/1ms 2^ndorder charge-balancing ADC is used to convert signals coming from the pre-amplifier. The

converter, designed in full differential switched capacitor technique, is used for converting the various signals

in the digital domain. This principle offers the following advantages:

•

High noise immunity because of the differential signal path and integrating behavior

Independence from clock frequency drift and clock jitter

Fast conversion time due to second order mode

Preliminary dLite Datasheet, Rev. 0.951, May 23, 2008

Page 11 of 44

written consent of the copyright owner. The Information furnished in this publication is preliminary and subject to changes without notice.

ZMD31015

RBic_dLite^TMLow-Cost Sensor Signal Conditioner with Diagnostics

Datasheet

PRELIMINARY

Four selectable values for the zero point of the input voltage allow conversion to adapt to the sensor’s offset

parameter. With the Reverse Input Polarity Mode and the negative digital gain options, this results in seven

possible zero point adjustments (not eight because the -1/2,1/2 offset setting is the same regardless of gain

polarity).

The conversion rate varies with the programmed update rate. The fastest conversation rate is 1k samples/s

and the response time is then 1ms. Based on a best fit, the Integral Nonlinearity (INL) is less than 4 LSB_14Bit

.

2.3 Digital Signal Processor

A digital signal processor (DSP) is used for processing the converted bridge data as well as performing

temperature correction and computing the temperature value for output on the digital channel.

The digital core reads correction coefficients from EEPROM and can correct for the following:

1. Bridge Offset

2. Bridge Gain

3. Variation of Bridge Offset over Temperature (Tco)

4. Variation of Bridge Gain over Temperature (Tcg)

5. A single second order effect (SOT) (Second Order Term)

The EEPROM contains a single SOT that can be applied to correct one and only one of the following:

•

2^ndorder behavior of bridge measurement

2

^ndorder behavior of Tco

^ndorder behavior of Tcg

If the SOT applies to correcting the bridge reading, then the correction formula for the bridge reading is

represented as a two step process as follows:

ZB

BR

= Gain_B [1 + ΔT∗Tcg]∗[BR_Raw - Offset_B + ΔT∗Tco]

= ZB∗(1.25+SOT∗ZB)

Where:

BR

ZB

=

Corrected Bridge reading that is output as digital or analog on SIG^TMpin

Intermediate result in the calculations

Raw Bridge reading from ADC

BR_Raw =

T_Raw

Gain_B

=

Raw Temp reading converted from PTAT signal or external diode

Bridge Gain term

Offset_B =

Bridge Offset term

Tcg

Tco

ΔT

T_SETL

SOT

=

Temperature Coefficient Gain

Temperature Coefficient Offset

(T_Raw - T_SETL

)

T_Raw reading at which low calibration was performed (typically 25°C)

Second Order Term

Preliminary dLite Datasheet, Rev. 0.951, May 23, 2008

Page 12 of 44

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ZMD31015

RBic_dLite^TMLow-Cost Sensor Signal Conditioner with Diagnostics

Datasheet

PRELIMINARY

If the SOT applies to correcting 2^ndorder behavior of Tco then the formula for bridge correction is as follows:

BR = Gain_B[1 + ΔT∗Tcg]∗[BR_Raw - Offset_B + ΔT(SOT∗ΔT + Tco)]

If the SOT applies to correcting 2^ndorder behavior of Tcg then the formula for bridge correction is as follows:

BR = Gain_B[1 + ΔT(SOT∗ΔT + Tcg)]∗[BR_Raw - Offset_B + ΔT∗Tco]

The bandgap reference gives a very linear PTAT signal, so temperature correction can always be

accomplished simply with a linear gain and offset term.

Corrected Temp Reading:

T

= Gain_T∗[T_Raw + Offset_T]

Where:

T_Raw

=

Raw Temperature reading converted from PTAT signal or external diode

Offset_T = Offset Coefficient for Temperature

Gain_T Gain Coefficient for Temperature

=

2.3.1 EEPROM

The EEPROM contains the calibration coefficients for gain and offset, etc., and the configuration bits, such as

output mode, update rate, etc. The RBic_dLite^TMalso offers 3 user-programmable storage bytes for module

traceability. When programming the EEPROM, an internal charge pump voltage is used; therefore a high

voltage supply is not needed. The EEPROM is implemented as a shift register. During an EEPROM read, the

contents are shifted 8 bits before each transmission of one byte occurs. The charge pump is internally

regulated to 12.5 V, and the programming time is 6ms.

See section 2.6.1 regarding EEPROM signatures for verifying EEPROM integrity.

Note: EEPROM writing can only be performed at temperatures lower than 85ºC.

2.3.2 One-Wire Interface – ZACwire™

The IC communicates via a one-wire serial interface. There are different commands available for the

following:

•

Reading the conversion result of the ADC (Get_BR_Raw, Get_T_Raw)

Calibration commands

Reading from the EEPROM (dump of entire contents)

Writing to the EEPROM (trim setting, configuration, and coefficients)

2.4 Output Stage

2.4.1 Digital-to-Analog Converter (Output DAC) with Programmable Clipping Limits

A 12-bit DAC based on sub-ranging resistor strings is used for the digital-to-analog output conversion in the

analog ratiometric and absolute analog voltage modes. Options during calibration configure the system to

operate in either of these modes. The design allows for excellent testability as well as low power consum-

ption. The DAC allows programming a lower and upper clipping limit for the output signal (analog and digital).

The internal 14-bit calculated bridge value is compared against the 14-bit value formed by

Preliminary dLite Datasheet, Rev. 0.951, May 23, 2008

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ZMD31015

RBic_dLite^TMLow-Cost Sensor Signal Conditioner with Diagnostics

Datasheet

PRELIMINARY

{11,Up_Clip_Lim[6:0],11111} for the upper limit and {00,Low_Clip_Lim[6:0],00000} for the lower limit. If the

calculated bridge value is higher than the upper limit or less than the lower limit, the analog output value is

clipped to this value; otherwise it is output as is.

Example for the upper clipping level: If the Up_Clip_Lim[6:0] = 0000000, then the 14-bit value used for

clipping threshold is 11000000011111. This is 75.19% of full scale. Since there are 7 bits of upper clipping

limit, there are 127 possible values between 75.19% and 100%. Therefore the resolution of the clipping limits

0.195%.

Example for the lower clipping level: If the Low_Clip_Lim[6:0] = 1111111, then the 14-bit value used for

clipping threshold is 00111111100000. This is 24.8% of full scale. Since there are 7 bits of lower clipping limit,

there are 127 possible values between 0 and 24.8%. Therefore the resolution of the lower clipping limit is

0.195%.

Figure 2.2 shows the data timing of the DAC output for the update rate setting 00.

Settling Time

64µs

ADC Conversion

768µs

Calculation

160µs

Settling Time

64µs

ADC Conversion

768µs

Calculation

160µs

DAC output

occurs here

DAC output

next update

Figure 2.2 – DAC Output Timing for Highest Update Rate

2.4.2 Output Buffer

A rail-to-rail op amp configured as a unity gain buffer can drive resistive loads (whether pull-up or pull-down)

as low as 5kΩ and capacitances up to 15nF (for pure analog output). In addition, to limit the error due to

amplifier offset voltage, an error compensation circuit is included which tracks and reduces offset voltage to <

1mV. The output of the RBic_dLite^TMoutput can be permanently shorted to VDD or VSS without damaging the

device. The output driver contains a current-limiting block that detects a hard short and limits the current to a

safe level. The short circuit protection current can vary from a minimum of 3mA to a maximum of 40mA

depending on operating conditions. Output short circuit protection can be enabled via Diag_cfg (EEPROM

[102:100]). Enabling this protection is recommended when using the analog output.

2.4.3 Voltage Reference Block

A linear regulator control circuit is included in Voltage Reference Block to interface with an external JFET¹to

allow operation in systems where the supply voltage exceeds 5.5V. This circuit can also be used for over-

voltage protection. The regulator set point has a coarse adjustment via an EEPROM bit (see section 2.3.1)

that can adjust the set point around 5.0 or 5.5V. The 1V trim setting (see below) can also act as a fine adjust

for the regulation setpoint.

1

With the previous revision C (ES), the JFET regulation option was not yet available (refer to ZMD31015 Technical Notes – Revision C1

Engineering Samples).

Preliminary dLite Datasheet, Rev. 0.951, May 23, 2008

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ZMD31015

RBic_dLite^TMLow-Cost Sensor Signal Conditioner with Diagnostics

Datasheet

PRELIMINARY

Note: If using the external JFET for over-voltage protection purposes (i.e., 5V at JFET drain and expecting 5V

at JFET source), there will be a voltage drop across the JFET; therefore ratiometricity will be slightly com-

promised depending on the rds(on) of the chosen JFET. A Vishay J107 is the best choice because it has only

an 8mV drop worst case. If using as regulation instead of over-voltage, a MMBF4392 or BSS169 also works

well.

The Voltage Reference Block uses the absolute reference voltage provided by the bandgap to produce two

regulated on-chip voltage references. A 1V reference is used for the output DAC high reference when the part

is configured in 0-1V Analog Output Mode. For this reason, the 1V reference must be very accurate and

includes trim so that its value can be trimmed within +/- 3mV of 1.00V. The 1V reference is also used as the

on-chip reference for the JFET regulator block. The regulation set point of the JFET regulator can be fine

tuned using the 1V trim.

The 5V reference can be trimmed within +/-15mV. Table 2.1 shows the order of trim codes with 0111 for the

lowest reference voltage and 1000 for the highest reference voltage.

Table 2.1 – 1V Reference Trim (1V vs. Trim for Nominal Process Run)

1Vref/

1Vref

1Vreft

1Vref

5Vref__trim3

5Vref_trim2

5Vref_trim1

5Vref_trim0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Preliminary dLite Datasheet, Rev. 0.951, May 23, 2008

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ZMD31015

RBic_dLite^TMLow-Cost Sensor Signal Conditioner with Diagnostics

Datasheet

PRELIMINARY

2.5 Clock Generator / Power-On Reset (CLKPOR)

If the power supply exceeds 2.5V (maximum), the reset signal de-asserts and the clock generator starts

working at a frequency of approximately 512kHz (±20%). The exact value only influences the conversion

cycle time and communication to the outside world but not the accuracy of signal processing. In addition, to

minimize the oscillator error as the V_DDvoltage changes, an on-chip regulator is used to supply the oscillator

block.

2.5.1 Trimming the Oscillator

Trimming is performed at wafer level, and it is strongly recommended that this not be changed during

calibration because ZACwire^TMcommunication is not guaranteed at different oscillator frequencies.

Table 2.2 – Oscillator Trim Bits

Trimming Bits

Delta Frequency

(KHz)

100

101

+385

+235

110

+140

+65

111

000

001

010

011

Nominal

-40

-76

-110

Example: Programming “011” → the trimmed frequency = nominal value – 110kHz

Preliminary dLite Datasheet, Rev. 0.951, May 23, 2008

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ZMD31015

RBic_dLite^TMLow-Cost Sensor Signal Conditioner with Diagnostics

Datasheet

PRELIMINARY

2.6 Diagnostic Features

The RBic_dLite^TMoffers a full suite of diagnostic features to ensure robust system operation in the most

“mission-critical” applications. If the part is programmed in Analog Output Mode, then diagnostic states are

indicated by an output below 2.5% of VDD or above 97.5% of VDD. If the part is programmed in Digital

Output Mode, then diagnostic states will be indicated by a transmission with a generated parity error. Table

2.3 gives a summary of the diagnostic features, which are explained in detail in the following sections.

EEPROM settings that control diagnostic functions are given in section 3.5.

Table 2.3 – Summary of Diagnostic Features

Detected Fault

Analog

ZACwire^TMDiagnostic

Delay of Detection

Diagnostic Level

EEPROM signature

Loss of bridge positive

Loss of bridge negative

Open bridge connection

Bridge input short

Lower

Upper

Lower

Generates parity error

10ms after power-on

2ms

ExtTemp pin open

300ms

ExtTemp pin shorted to

PWR/GND

ExtTemp pin shorted to

BP/BN¹

Upper

Generates parity error

3ms

Loss of VDD

Loss of VSS

Lower

Upper

Transmissions stop

Dependent on R_Land C_L

2.6.1 EEPROM Integrity

The contents of the EEPROM are protected by an 8-bit LFSR signature (linear feedback shift register). This

signature is regenerated and stored in EEPROM every time EEPROM contents are changed. This signature

is generated and checked for a match after Power-On-Reset prior to entering Normal Operation Mode. If the

generated signature fails to match, the part will output a diagnostic state on the output.

In addition to an extensive temporal and code interlock mechanism used to prevent false writes to the

EEPROM, the RBic_dLite™ offers an EEPROM lock mechanism for high-security applications. When EEPROM

bits 105:103 are programmed with “011” or “110,” this 3-bit field will permanently disable the VPP charge

pump and will not allow further writes to the EEPROM. See Table 2.3 in section 2.6 for more information.

2.6.2 Sensor Connection Check

Four dedicated comparators permanently check the range of the bridge inputs (BP/BN) to ensure they are

within the envelope of 0.8V to 0.85∗VDD during all conversions. The two sensor inputs have a switched

¹A short from ExtTemp to BP/BN might not be detected in some circuit configurations.

Preliminary dLite Datasheet, Rev. 0.951, May 23, 2008

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ZMD31015

RBic_dLite^TMLow-Cost Sensor Signal Conditioner with Diagnostics

Datasheet

PRELIMINARY

ohmic path to ground and if left floating, would be discharged. If any of the wires connecting the bridge break,

this mechanism will detect it and put the ASIC in a diagnostic state. This same diagnostic feature can also

detect a short between BP/BN and the ExtTemp signal if an external diode is being used for temperature

measurement. See Table 2.3 in section 2.6 for more information.

2.6.3 Sensor Short Check

If a short occurs between BP/BN (bridge inputs), it would normally produce an in-range output signal and

therefore would not be detected as a fault. This diagnostic mode, if enabled, will deliberately look for such a

short. After the measurement cycle of the bridge, it will deliberately pull the BP bridge input to ground for

4μsec. At the end of this 4μsec window, it will check to see if the BN input “followed” it down below the 0.8V

comparator checkpoint. If so, a short must exist between BP/BN, and the part will output a diagnostic state.

The bridge will have a minimum of 480μsec recovery time prior to the next measurement. See Table 2.3 in

section 2.6 for more information.

2.6.4 Power Loss Detection

If the power or GND connection to the module containing the sensor bridge and ASIC is lost, the ASIC will

output a diagnostic state if a pull-up or pull-down terminating resistor greater than or equal to 5kΩ is

connected in the final application. This diagnostic mode only works when the part is configured in Analog

Output Mode. See Table 2.3 in section 2.6 for more information.

2.6.5 ExtTemp Connection Checks

When external temperature is selected and connection checking is enabled, the part performs range checking

on the converted temperature value. If the internal ADC reading of the temperature is less than 1/32 of full

scale or greater than 63/64 of full scale then a diagnostic state is asserted. If the ExtTemp pin is shorted to

ground, the ADC reads less than 1/32. Because 100µA is sourced onto the ExtTemp pin during conversions,

it naturally pulls up during these times. If the ExtTemp pin is open, it produces an ADC reading greater than

63/64 of full scale. Both these bad connection conditions would be detected and result in a diagnostic output.

If internal temperature is selected or sensor connection check is not enabled, then this diagnostic check is not

enabled. See Table 2.3 in section 2.6 for more information.

Preliminary dLite Datasheet, Rev. 0.951, May 23, 2008

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ZMD31015

RBic_dLite^TMLow-Cost Sensor Signal Conditioner with Diagnostics

Datasheet

PRELIMINARY

3

Functional Description

3.1 General Working Mode

The command/data transfer takes place via the one-wire SIG™ pin using the ZACwire^TMserial communication

protocol.

After power-on, the IC waits for 1.5ms (= Command window) for the Start_CM command.

Without this command, the Normal Operation Mode (NOM) starts. In this mode, raw bridge values are

converted, and the corrected values are presented on the output in analog or digital format (depending on the

configuration stored in EEPROM).

Command Mode (CM) can only be entered during the 1.5ms command window after Power ON. If the IC

receives the Start_CM command during the command window, it remains in the Command Mode. The CM

allows changing to one of the other modes via command. After command Start_RW, the IC is in the Raw

Mode. Without correction, the raw values are transmitted to the digital output in a predefined order. The RM

can only be stopped by Power OFF. Raw Mode is used by the calibration software for collection of raw bridge

and temperature data so the correction coefficients can be calculated.

If diagnostic features are enabled and a diagnostic fault is detected, diagnostic states are indicated as follows

depending on the programmed mode:

•

In Analog Output Mode:

Diagnostic states are indicated by an output below 2.5% of VDD or above 97.5% of VDD.

•

In Digital Output Mode:

Diagnostic states will be indicated by a transmission with a generated parity error.

For more details see chapter 2.6.

Preliminary dLite Datasheet, Rev. 0.951, May 23, 2008

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ZMD31015

RBic_dLite^TMLow-Cost Sensor Signal Conditioner with Diagnostics

Datasheet

PRELIMINARY

Power

ON

Command

Start_CM

Window (1.5ms)

Send Start_CM

No Command

Start_NOM

Start_RM

Raw Mode

Command Mode

Normal Operation Mode

No commands possible

Measurement cycle

stopped

Measurement cycle

SIG™ pin provides raw

bridge and temperature

values in the format

Conditioning calculation

Full command set

Corrected bridge and

temperature values

Command routine will

be processed after

each command

Bridge_high (1^stByte)

Bridge_low (2^ndByte)

Depending on the con-

figuration, the SIG™ pin is

Temp

(3^rdByte)

• 0V-1V

• Rail-to-rail ratiometric

• Digital output

Diagnostics functions

Error

Detection

Power OFF

Diagnostic State

(See section 1.6)

Figure 3.1 – General Working Mode

Preliminary dLite Datasheet, Rev. 0.951, May 23, 2008

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ZMD31015

RBic_dLite^TMLow-Cost Sensor Signal Conditioner with Diagnostics

Datasheet

PRELIMINARY

3.2 ZACwire™ Communication Interface

3.2.1 Properties and Parameters

Parameter

Symbol

Min Typ Max Unit Comments

1

2

Pull-up resistor

(on-chip)

R_ZAC,pu

30

On-chip pull-up resistor switched on

during Digital Output Mode and during

CM Mode (first 1.5ms after power up)

kΩ

Pull-up resistor

(external)

R_{ZAC,pu_ext}150

If the master communicates via a push-

pull stage, no pull-up resistor is needed;

otherwise, a pull-up resistor with a value

of at least 150Ω must be connected.

Ω

3

t_ZAC,rise

5

Any user RC network included in the

SIG^TMpath must meet this rise time.

μs

ZACwire™ rise time

4

5

R_ZAC,load

3.9

15

Also see section 1.3.

kΩ

ZACwire™line resistance

C_ZAC,load

0

1

nF Also see section 1.3.

ZACwire™ load

capacitance

6

7

Voltage level - low

Voltage level - high

V_ZAC,low

V_ZAC,high

0

1

0.2

V_DDRail-to-rail CMOS driver

0.8

3.2.2 Bit Encoding

Bit Window

125µsec @ 8kHz baud

Duty cycle encoded Manchester:

31.3µsec @ 32kHz baud

Start bit =>

Logic 1 =>

50% duty cycle used

to set up strobe time

Start Bit

75% duty cycle

Logic 1

Logic 0

Logic 0 =>

Stop Bit

25% duty cycle

Stop ½ Bit

(High)

For the time of a half a bit width, the signal level is high.

There is a half stop bit time between bytes in a packet.

Figure 3.2 – Duty Cycle Manchester

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ZMD31015

RBic_dLite^TMLow-Cost Sensor Signal Conditioner with Diagnostics

Datasheet

PRELIMINARY

TM

3.2.3 Write Operation from Master to RBic_dLite

The calibration master sends a 19-bit packet frame to the IC.

S

P

2

Start Bit

19-Bit Frame (WRITE)

Parity Bit Command Byte

or Parity Bit Data Byte

S 7 6 5 4 3 2 1 0 P 7 6 5 4 3 2 1 0 P

Command Bit (Example: Bit 2)

Data Bit (Example: Bit 2)

2

Command Byte

Data Byte

Figure 3.3 – 19-Bit Write Frame

The incoming serial signal will be sampled at a 512kHz clock rate. This protocol is very tolerant to clock skew

and can easily tolerate baud rates in the 6kHz to 48kHz range.

3.2.4 RBic_dLite^TMREAD Operations

The incoming frame will be checked for proper parity on both command and data bytes, as well as for any

edge timeouts prior to a full frame being received.

Once a command/data pair is received, the RBic_dLite^TMwill perform that command. Once the command has

been successfully executed by the IC, it will acknowledge success by transmission of an A5H byte back to the

master. If the master does not receive an A5H transmission within 130ms of issuing the command, it must

assume the command was either improperly received or could not be executed.

S

P

0

Start Bit

1 DATA Byte Packet

10-Bit Byte A5H

Parity Bit Data Byte

Data Bit (Low)

Data Bit (High)

S 1 0 1 0 0 1 0 1 P

1

Data Byte

Figure 3.4 – Read Acknowledge

The RBic_dLite^TMtransmits 10-bit bytes (1 start bit, 8 data, 1 parity). During calibration and configuration,

transmissions are normally either A5H or data. A5H indicates successful completion of a command. There are

two different digital output modes configurable (digital output with temperature and digital output with only

bridge data). During Normal Operation Mode, if the part is configured for digital output of the bridge reading, it

first transmits the high byte of bridge data followed by the low byte. The bridge data is 14-bits in resolution, so

Preliminary dLite Datasheet, Rev. 0.951, May 23, 2008

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ZMD31015

RBic_dLite^TMLow-Cost Sensor Signal Conditioner with Diagnostics

Datasheet

PRELIMINARY

the upper two bits of the high byte are always zero padded. There is a half stop bit time between bytes in a

packet. This means for the time of a half a bit width, the signal level is high.

2 DATA Byte Packet

Digital Bridge Output

S

P

2

Start Bit

Parity Bit Data Byte

Data Bit (Example: Bit 2)

½ Stop Bit

½

Stop

S 0 0 5 4 3 2 1 0 P

Data Byte Bridge High

S 7 6 5 4 3 2 1 0 P

7

Data Byte Bridge Low

½

Stop

Figure 3.5 – Digital Output (NOM) Bridge Readings

The second option for Digital Output Mode is digital output bridge reading with temperature. It will be trans-

mitted as 3 data packets. The temperature byte represents an 8-bit temperature quantity spanning from -50°C

to +150°C.

3 DATA Byte Packet

Digital Bridge Output with Temperature

½

Stop

½

Stop

S 0 0 5 4 3 2 1 0 P

Data Byte Bridge High

S 7 6 5 4 3 2 1 0 P

7

Data Byte Bridge Low

Data Byte Temperature

Figure 3.6 – Digital Output (NOM) Bridge Readings with Temperature

The EEPROM transmission occurs in a packet with 20 data bytes as shown in Figure 3.7.

20 DATA Byte Packet

Read EEPROM

½

Stop

½

Stop

½

S 7 6 5 4 3 2 1 0 P

S 7 6 5 4 3

4 3 2 1 0 P

EEPROM 18

S 7 6 5 4 3 2 1 0 P

S 1 0 1 0 0 1 0 1 P

Data Byte A5H

7

Stop

EEPROM Byte 1

EEPROM Byte 2

EEPROM Byte 19

Figure 3.7 – Read EEPROM Contents

Preliminary dLite Datasheet, Rev. 0.951, May 23, 2008

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ZMD31015

RBic_dLite^TMLow-Cost Sensor Signal Conditioner with Diagnostics

Datasheet

PRELIMINARY

There is a variable idle time between packets. This idle time varies with the update rate setting in EEPROM.

Packet Transmission

(This example shows 2 data packets.)

IDLE

TIME

½

Stop

IDLE

TIME

½

Stop

IDLE

S 0 0 5 4 3

7

TIME

6 5 4 3 2 1 0 P

S 0 0 5 4 3 2 1 0 P

S 7 6 5 4 3 2 1 0 P

S 0 0 5 4 3 2 1 0 P

S 7 6 5 4 3 2 1 0 P

7

Figure 3.8 – Transmission of a Number of Data Packets

Table 3.1 shows the idle time between packets versus update rate. This idle time can vary by nominal +/-15%

between parts and over a temperature range of –50°C to 150°C.

Table 3.1 – Idle Time between Packets versus Update Rate

Update Rate Setting

Idle Time between Packets

00

01

10

11

1ms

4.85ms

22.5ms

118ms

Transmissions from the IC occur at one of two speeds depending on the update rate programmed in

EEPROM. If the user chooses one of the two fastest update rates (1ms or 5ms) then the baud rate of digital

transmission will be 32kHz. If however, the user chooses one of the two slower update rates (25ms or

125ms), then the baud rate of digital transmission will be 8kHz.

The total transmission time for both digital output configurations is shown in Table 3.2.

Table 3.2 – Total Transmission Time for Different Update Rate Settings and Output Configuration

Baud

Rate

Transmission Time –

Bridge Only Readings

Transmission Time –

Bridge & Temperature Readings

Update Rate

Idle Time

1ms (1kHz)

5ms (200Hz)

25ms (40Hz)

125ms (8Hz)

32kHz

8kHz

1.00ms

4.85ms

20.5 bits

31.30µs

1.64ms

31.0 bits

31.30µs

1.97ms

5.82ms

20.5 bits

5.49ms

25.06ms

120.56ms

22.50ms

118.00ms

125.00µs

26.38ms

121.88ms

8kHz

Preliminary dLite Datasheet, Rev. 0.951, May 23, 2008

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ZMD31015

RBic_dLite^TMLow-Cost Sensor Signal Conditioner with Diagnostics

Datasheet

PRELIMINARY

For lower update rates, the output is followed by a power-down as shown in Figure 3.9.

Calculation

160µs

ZACwire™

output

Power Down

Determined by

Update Rate

Power-On

Settling

128µs

Settling time

64µs

ADC

Conversion

768µs

Calculation

160µs

ZACwire™

output

Figure 3.9 – ZACwire™ Output Timing for Lower Update Rates

One can easily program any standard μcontroller to communicate with the RBic_dLite^TM. ZMDA can provide

sample code for a MicroChip PIC μController.

3.2.5 High Level Protocol

The RBic_dLite^TMwill listen for a command/data pair to be transmitted for the 1.5 ms after the de-assertion of its

internal Power On Reset (POR). If a transmission is not received within this time frame, then it will transition

to Normal Operation Mode (NOM). In the NOM, it will output bridge data in 0-1V analog, rail-to-rail ratiometric

analog, or digital depending on how the part is currently configured.

If the RBic_dLite^TMreceives a Start_CM command within the first 1.5 ms after the de-assertion of POR, then it

will go into Command Mode (CM). In this mode, calibration/configuration commands will be executed. The

RBic_dLite^TMwill acknowledge successful execution of commands by transmission of A5H. The calibrating

/configuring master will know a command was not successfully executed if no response is received after

130ms of issuing the command. Once in command interpreting/executing mode, the RBic_dLite^TMwill stay in this

mode until power is removed or a Start NOM (Start Normal Operation Mode) command is received. The

Start_CM command is used as an interlock mechanism to prevent a spurious entry into Command Mode on

power up. The first command received within the 1.5ms window of POR must be a Start_CM command to

enter into command interpreting mode. Any other commands will be ignored.

Preliminary dLite Datasheet, Rev. 0.951, May 23, 2008

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ZMD31015

RBic_dLite^TMLow-Cost Sensor Signal Conditioner with Diagnostics

Datasheet

PRELIMINARY

3.3 Command/Data Pair Encoding

The 2-byte command sent to the RBic_dLite^TMconsists of 1 byte of command information and 1 byte of data

information. Regardless of whether the command requires data or not, 2 bytes MUST be sent. The following

table lists all the command/data pairings. (X=don’t care.)

Command Data

Byte

Description

00H

20H

XXH

5XH

Read EEPROM command via SIG™ pin.¹

DAC Ramp Test Mode. Gain_B[13:3] contains the starting point, and the increment is

(Offset_B/8). The increment will be added every 125µsec.

30H

WDH

Trim/Configure: 3^rdnibble determines what is trimmed/configured. The 4^thnibble is

data to be programmed.

3^rdNibble 4^thNibble Data

Description

W =

0H

1H

2H

3H

4H

5H

6H

DH

Trim oscillator. Least significant 3 bits of data used.

Trim 1V reference. Least significant 4 bits of data used.

Offset Mode. Least significant 4 bits of data used.

Set output mode. Least significant 2 bits used.

Set update rate. Least significant 2 bits used.

Configure JFET regulation²

What

D =

Data

H =

Hex

Program the Tc_cfg register. Least significant 3 bits used.

Most significant bit of data nibble should be 0.

7H

DH

Program EEPROM bits [99:96] {SOT_cfg,Pamp_Gain}

Program EEPROM bits [105:103]:

DH

0x3

0x0,0x1,0x2

0x6

EEPROM locked! Int. PTAT used for temperature

EEPROM unlocked, Int. PTAT used for temperature

EEPROM locked! Ext. diode used for temperature

EEPROM unlocked, Ext. diode used for temperature

0x4,0x5,0x7

EH

DH

Program EEPROM bits [102:100] diag_cfg ³

40H

00H

10H

Start NOM => Ends Command Mode; transition to Normal Operation Mode.

Start_RM = Start the Raw Mode (RM)

In this mode, if Gain_B = 800H and Gain_T = 80H, then the digital output will simply

be the raw values of the ADC for the Bridge reading, and the PTAT conversion.

1

2

For more details, refer to section 3.7.

With the previous revision C (ES), the JFET regulation option was not yet available (refer to ZMD31015 Technical Notes – Revision C1

Engineering Samples).

3

For more details, refer to section 3.5.

Preliminary dLite Datasheet, Rev. 0.951, May 23, 2008

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ZMD31015

RBic_dLite^TMLow-Cost Sensor Signal Conditioner with Diagnostics

Datasheet

PRELIMINARY

Command Data

Byte

Description

50H

60H

70H

80H

90H

A0H

B0H

C0H

90H

Start_CM => Start the Command Mode; used to enter Command Interpret Mode.

Program SOT (2^ndOrder Term)

Program T_SETL(Set the MSB to 0.)

Program Gain_B upper 7-bits (Set the MSB to 0.)

Program Gain_B lower 8-bits

YYH

Program Offset_B upper 6-bits (Set the two MSBs to 0.)

Program Offset_B lower 8-bits

Program Gain_T

D0H

E0H

F0H

08H

18H

28H

38H

48H

Program Offset_T

Program Tco

Program Tcg

Program Upper Clipping Limit (Set the MSB to 0.)

Program Lower Clipping Limit (Set the MSB to 0.)

Program Cust_ID0

Program Cust_ID1

Program Cust_ID2

_

3.4 Calibration Sequence

Although the RBic_dLite^TMIC can work with many different types of resistive bridges, assume a pressure bridge

is being used for the following discussion on calibration.

Calibration essentially involves collecting raw bridge and temperature data from the IC for different known

pressures and temperatures. This raw data can then be processed by the calibration master (typically a PC)

to compute the coefficients, and the calculated coefficients can then be written to the IC.

ZMDA can provide software and hardware with samples to perform the calibration.

Preliminary dLite Datasheet, Rev. 0.951, May 23, 2008

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RBic_dLite^TMLow-Cost Sensor Signal Conditioner with Diagnostics

Datasheet

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There are three main steps to calibration:

1. Assigning a unique identification to the IC. This identification is programmed in EEPROM and can be

used as an index into the database stored on the calibration PC. This database will contain all the raw

values of bridge readings and temperature readings for that part, as well as the known pressure (for

this application) and temperature the bridge was exposed to. This unique identification can be stored

in a concatenation of the following EEPROM registers: Cust_ID0, Cust_ID1, Cust_ID2. These

registers can also form a permanent serial number.

2. Data collection. Data collection involves getting raw data from the bridge at different known pressures

and temperatures. This data is then stored on the calibration PC using the unique identification of the

IC as the index to the database.

3. Coefficient calculation and write. Once enough data points have been collected to calculate all the

desired coefficients then the coefficients can be calculated by the calibrating PC and written to the IC.

Step 1 – Assigning Unique Identification

Assigning a unique identification number is as simple as using the commands Program Cust_ID0, Program

Cust_ID1 and Program Cust_ID2. These three 8-bit registers allow for more than 16 million unique devices.

Gain_B must be programmed to 800H (unity) and Gain_T must be programmed to 80H (unity).

Step 2 – Data Collection

The number of unique (pressure, temperature) points that calibration must be performed at depends on the

customer’s needs. The minimum is a 2-point calibration, and the maximum is a 5-point calibration. To acquire

raw data from the part, set RBic_dLite^TMto enter Raw Mode. This is done by issuing a Start_CM (Start

Command Mode 5090H) command/data pair to the IC followed by a Start_RM (Start Raw Mode 4010H)

command/data pair with the LSB of the upper data nibble set. Now if the Gain_B term has been set to unity

(800H) and the Gain_T term has also been set to unity (80H), then the part will be in the Raw Mode and will

output raw data on its SIG^TMpin instead of corrected bridge and temperature. Capture several of these data

points with the user’s calibration system (16 each of bridge and temperature is recommended) and average

them. Store these raw bridge and temperature settings in the database along with the known pressure and

temperature. The output format during Raw Mode is Bridge_High, Bridge_Low, Temp. Each of these is an 8-

bit quantity. The upper 2-bits of Bridge_High are zero filled. The Temp data (8-bits only) would not be enough

information for accurate temperature calibration. Therefore the upper three bits of temperature information are

not given, but rather assumed known. Therefore effectively 11-bits of temperature information are provided in

this mode.

Step 3 – Coefficient Calculations

The math to perform the coefficient calculation is very complicated and will not be discussed in detail. There is

a rough overview in the “Calibration Math” section. ZMDA will provide software to perform the coefficient

calculation. ZMDA can also provide source code for the algorithms in a C code format. After the coefficients

TM

are calculated, the final step is to write them to the EEPROM of the RBic_dLite

.

Preliminary dLite Datasheet, Rev. 0.951, May 23, 2008

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ZMD31015

RBic_dLite^TMLow-Cost Sensor Signal Conditioner with Diagnostics

Datasheet

PRELIMINARY

The number of calibration points required can be as few as two or as many as five. This depends on the

precision desired and the behavior of the resistive bridge in use.

1. 2-point calibration can be used if only a gain and offset term are needed for a bridge with no

temperature compensation for either term.

2. 3-point calibration would be used to obtain 1^storder compensation for either a Tco or Tcg term but not

both.

3. 3-point calibration could also be used to obtain 2^ndorder correction for the bridge but no temperature

compensation of the bridge output.

4. 4-point calibration would be used to obtain 1^storder compensation for both Tco and Tcg.

5. 4-point calibration could also be used to obtain 1^storder compensation for Tco and a 2^ndorder

correction for the bridge measurement.

6. 5-point calibration would be used to obtain both 1^storder Tco correction and 1^storder Tcg correction,

plus a 2^ndorder correction that could be applied to one and only one of the following: 2^ndorder Tco,

2^ndorder Tcg, or 2^ndorder bridge.

Preliminary dLite Datasheet, Rev. 0.951, May 23, 2008

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ZMD31015

RBic_dLite^TMLow-Cost Sensor Signal Conditioner with Diagnostics

Datasheet

PRELIMINARY

3.5 EEPROM Bits

Programmed through the serial interface:

EEPROM

Range

Description

Osc_Trim

Note

2:0

See the table in the “Trimming the Oscillator” section for

complete data.

100 => Fastest

101 => 3 clicks faster than nominal

110 => 2 clicks faster than nominal

111 => 1 click faster than nominal

000 => Nominal

001 => 1 click slower than nominal

010 => 2 clicks slower than nominal

011 => Slowest

6:3

10:7

1V_Trim/

See the table under “Voltage Reference Block,” section 2.4.3.

JFET_Trim¹

A2D_Offset

The upper two bits are flip polarity and invert bridge input

(negative gain) respectively. If both are used in conjunction,

negative offset modes can be achieved.

00 => normal polarity, positive gain

01 => normal polarity, negative gain

10 => flip polarity, positive gain

11 => flip polarity, negative gain

The lower two bits form the ADC offset selection.

Offset selection:

11 => [-1/2,1/2] mode bridge inputs

10 => [-1/4,3/4] mode bridge inputs

01 => [-1/8,7/8] mode bridge inputs

00 => [-1/16,15/16] mode bridge inputs

1

With the previous revision C (ES), the JFET regulation option was not yet available (refer to ZMD31015 Technical Notes – Revision C1

Engineering Samples).

Preliminary dLite Datasheet, Rev. 0.951, May 23, 2008

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ZMD31015

RBic_dLite^TMLow-Cost Sensor Signal Conditioner with Diagnostics

Datasheet

PRELIMINARY

EEPROM

Range

Description

Note

00 => Digital (3 bytes with parity)

12:11

Output_Select

Bridge High {00,[5:0]}

Bridge Low [7:0]

Temp [7:0]

01 => 0-1V Analog (requires 1kHz update rate)

10 => Rail-to-Rail Ratiometric (requires 1kHz update rate)

11 => Digital (2 bytes with parity) (No Temp)

Bridge High {00,[5:0]}

Bridge Low [7:0]

14:13

16:15

Update_Rate

JFET_cfg

00 => 1 msec (1kHz)

01 => 5 msec (200Hz)¹

10 => 25 msec (40Hz)¹

11 => 125 msec (8 Hz)¹

00 => No JFET regulation (lower power)

01 => No JFET regulation (lower power)

10 => JFET regulation centered around 5.0V²

11 => JFET regulation centered around 5.5V (i.e., over-voltage

protection)²

31:17

Gain_B

Bridge Gain (also see bits 10:7 ):

Gain_B[14] => multiply x 8

Gain_B[13:0] => 14-bit unsigned number representing a

number in the range [0,8)

45:32

53:46

Offset_B

Gain_T

Unsigned 14-bit offset for bridge correction

Temperature gain coefficient used to correct PTAT

or ExtTemp reading

61:54

68:62

Offset_T

T_SETL

Temperature offset coefficient used to correct PTAT

or ExtTemp reading

Stores Raw PTAT or ExtTemp reading at temperature in which

low calibration points were taken

1

With the previous revision C (ES), the lower update rates can only be used with the digital output modes.

²With the previous revision C (ES), the JFET regulation option was not yet available (refer to ZMD31015 Technical Notes – Revision C1

Engineering Samples)

Preliminary dLite Datasheet, Rev. 0.951, May 23, 2008

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ZMD31015

RBic_dLite^TMLow-Cost Sensor Signal Conditioner with Diagnostics

Datasheet

PRELIMINARY

EEPROM

Range

Description

Note

76:69

Tcg

Tco

Coefficient for temperature correction of bridge gain term:

Tcg = 8-bit magnitude of Tcg term. Sign is determined by Tc_cfg

(bits 87:85).

84:77

87:85

Coefficient for temperature correction of bridge offset term.

Tco = 8-bit magnitude of Tco term. Sign and scaling are

determined by Tc_cfg (bits 87:85)

Tc_cfg

This 3-bit term determines options for temperature compensation

of the bridge.

Tc_cfg[2] => If set, Tcg is negative

Tc_cfg[1] => Scale magnitude of Tco term by 8, and if SOT

applies to Tco, scale SOT by 8

Tc_cfg[0] => If set, Tco is negative

95:88

99:96

SOT

2^ndOrder Term. This term is a 7-bit magnitude with sign.

SOT[7] = 1 Î negative

SOT[7] = 0 Î positive

SOT[6:0] = magnitude [0-127]

This term can apply to a 2nd order Tcg, Tco or bridge correction.

(See Tc_cfg above.)

{SOT_cfg,

Bits [99:98] = SOT_cfg

00 = SOT applies to Bridge

01 = SOT applies to Tcg

10 = SOT applies to Tco

11 = Prohibited

Pamp_Gain}

Bits [97:96] = Pre-Amp Gain

00 => 6

01 => 24 (default setting)

10 => 48

11 => 96

102:100

Diag_cfg

This 3-bit term applies to diagnostic features

Diag_cfg[2] Æ enable output short circuit protection.

Diag _cfg[1] Æ enable sensor short checking.

Diag_cfg[0] Æ enables sensor connection checking.

Preliminary dLite Datasheet, Rev. 0.951, May 23, 2008

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ZMD31015

RBic_dLite^TMLow-Cost Sensor Signal Conditioner with Diagnostics

Datasheet

PRELIMINARY

EEPROM

Range

Description

Note

105:103

Lock_ExtTemp

EEPROM lock

011 or 110 => locked

All other => unlocked

When EEPROM is locked, the internal charge pump is disabled

and the EEPROM can never be programmed again.

Bit 105 (the MSB of this field) is also used for selecting external

temperature measurement.

000,001,010,011=>Internal PTAT used for temp

100,101,110,111=>External diode used for temp

112:106

119:113

Up_Clip_Lim

Low_Clip_Lim

7-bit value used to select an upper clipping limit for the output. It

affects both analog and digital output. The 14-bit upper clipping

limit value is comprised of {11,Up_Clip_Lim[6:0],11111}. 127

different clipping levels are selectable between 75.19% and 100%

of VDD.

7-bit value used to select a lower clipping limit for the output. It

affects both analog and digital output. The 14-bit lower clipping

limit value is comprised of {00,Low_Clip_Lim[6:0],00000}. 127

different clipping levels are selectable between 0% and 24.8%

of VDD.

127:120

135:128

143:136

151:144

Cust_ID0

Cust_ID1

Cust_ID2

Signature

Customer ID byte 0

Customer ID byte 1

Customer ID byte 2

8-bit EEPROM signature. Generated through a LFSR¹. This

signature is checked on power-on to ensure integrity of EEPROM

contents.

3.6 Calibration Math

3.6.1 Correction Coefficients

(All terms calculated external to the DUT and then programmed to EEPROM through serial interface.)

Gain_B =

Gain term used to compensate span of Bridge reading

Offset term used to compensate offset of Bridge reading

Offset_B =

¹Linear feedback shift register

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ZMD31015

RBic_dLite^TMLow-Cost Sensor Signal Conditioner with Diagnostics

Datasheet

PRELIMINARY

Gain_T =

Gain term used to compensate span of Temp reading

Offset term used to compensate offset of Temp reading

Offset_T =

SOT =

the following:

1. Bridge measurement

Second Order Term. This term can be applied as a second order correction term for one of

2. Temperature coefficient of offset (Tco)

3. Temperature coefficient of gain (Tcg)

EEPROM bits 99:98 determine what SOT applies to.

T_SETL

=

RAW_PTAT or ExtTemp reading (upper 7-bits) at low temperature at which calibration was

performed (typically at room temp)

Tcg =

Tco =

Temperature correction coefficient of bridge gain term

This term has an 8-bit magnitude and a sign bit (Tc_cfg[2]).

Temperature correction coefficient of bridge offset term

This term has an 8-bit magnitude, a sign bit (Tc_cfg[0]), and a scaling bit (Tc_cfg[1]) which

can multiply its magnitude by 8.

3.6.2 Interpretation of Binary Numbers for Correction Coefficients

BR_Raw should be interpreted as an unsigned number in the set [0,16383] with resolution of 1.

T_Raw should be interpreted as an unsigned number in the set [0,16383] with resolution of 4.

3.6.2.1 Gain_B Interpretation

Gain_B should be interpreted as a number in the set [0,64). The MSB (bit 14) is a scaling bit that will multiply

the effect of the Gain_B[13:0] term by 8. The remaining bits Gain_B[13:0] represent a number in the range of

[0,8) with Gain_B[13] having a weighting of 4, and each subsequent bit has a weighting of ½ the previous bit.

Preliminary dLite Datasheet, Rev. 0.951, May 23, 2008

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ZMD31015

RBic_dLite^TMLow-Cost Sensor Signal Conditioner with Diagnostics

Datasheet

PRELIMINARY

Table 3.3 – Gain_B Weightings

Bit Position

Weighting

13

12

11

.

4

2

1

.

1

2^-10

2^-11

0

Examples:

The binary number 010010100110001 = 4.6489. The scaling number is 0 so there is no multiplication by 8 of

the number represented by Gain_B[13:0].

The binary number 101100010010110 = 24.586. The scaling number is 1 so there is a multiplication by 8 of

the number represented by Gain_B[13:0].

3.6.2.2 Offset_B Interpretation

Offset_B is a 14-bit unsigned binary number. The MSB has a weighting of 8192. The following bits then have

a weighting of: 4096, 2048, 1024 …

Table 3.4 – Offset_B Weightings

Bit Position:

Weighting:

8192

13

12

11

.

4096

2048

.

1

2¹= 2

2⁰= 1

0

For example, the binary number 1111 1111 1100 = 4092.

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ZMD31015

RBic_dLite^TMLow-Cost Sensor Signal Conditioner with Diagnostics

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PRELIMINARY

3.6.2.3 Gain_T Interpretation

Gain_T should be interpreted as a number in the set [0,2). Gain_T[7] has a weighting of 1, and each

subsequent bit has a weighting of ½ the previous bit.

Table 3.5 – Gain_T Weightings

Bit Position

Weighting

7

6

5

.

1

0.5

0.25

.

1

0

2^-6

2^-7

3.6.2.4 Offset_T Interpretation

Offset_T is an 8-bit signed binary number in two’s complement form. The MSB has a weighting of –128. The

following bits then have a weighting of: 64, 32, 16 …

Table 3.6 – Offset_T Weightings

Bit Position

Weighting

-128

7

6

.

64

.

1

0

2¹= 2

2⁰= 1

For example, the binary number 00101001 = 41.

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ZMD31015

RBic_dLite^TMLow-Cost Sensor Signal Conditioner with Diagnostics

Datasheet

PRELIMINARY

3.6.2.5 Tco Interpretation

Tco is specified as having an 8-bit magnitude with an additional sign bit and a scalar bit (Tc_cfg). The scalar

bit when set multiplies the signed Tco by 8.

Tco Resolution: 0.175µV/V/^oC

Tco Range:

+/- 44.6µV/V/^oC (input referred)

If the scaling bit is used, then the above resolution and range are scaled by 8 to give the following:

Tco Scaled Resolution: 1.40µV/V/^oC

(input referred)

+/- 357µV/V/^oC (input referred)

(input referred)

Tco Scaled Range:

3.6.2.6 Tcg Interpretation

Tcg is specified as having an 8-bit magnitude with an additional sign bit (Tc_cfg).

Tcg Resolution: 17.0ppm/^oC

Tcg Range:

+/- 4335ppm/^oC

3.6.2.7 SOT Interpretation

SOT is a second order term that can apply to one and only one of the following: bridge non-linearity

correction, Tco non-linearity correction, or Tcg non-linearity correction.

As it applies to bridge non-linearity correction:

Resolution: 0.25% @ Full Scale

Range:

+25% @ Full Scale to -25% @ Full Scale

(Saturation in internal arithmetic will occur at greater negative non-linearities.)

As it applies to Tcg:

Resolution: 0.3 ppm/(^oC)²

Range:

+/- 38ppm/(^oC)²

As it applies to Tco:

2 settings are possible. It is possible to scale the effect of SOT by 8. If Tc_cfg[1] is set, then both Tco and

SOT’s contribution to Tco are multiplied by 8.

Resolution at unity scaling: 1.51nV/V/(^oC)²

(input referred)

+/- 0.192μV/V/(^oC)²(input referred)

Range:

Resolution at 8x scaling:

Range:

12.1nV/V/(^oC)²

+/- 1.54μV/V/(^oC)²

(input referred)

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RBic_dLite^TMLow-Cost Sensor Signal Conditioner with Diagnostics

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3.7 Reading EEPROM Contents

The contents of the entire EEPROM memory can be read using the Read EEPROM Command (00H). This

command causes the IC to output consecutive bytes on the ZACwire^TM. After each transmission, the

EEPROM contents are shifted 8 bits. The bit order of these bytes is given in the following table.

Table 3.7 – Read EEPROM (Bit Order)¹

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Byte 1

Byte 2

Byte 3

Byte 4

Byte 5

Byte 6

Byte 7

Byte 8:

Byte 9:

Byte 10

Byte 11

Byte 12

Byte 13

Byte 14

Byte 15

Offset_B[7:0]

Gain_T[1:0]

Offset_B[13:8]

Gain_T[7:2]

Offset_T[1:0]

T_SETL[1:0]

Offset_T[7:2]

Tcg[2:0]

T_SETL[6:2]

Tco[2:0]

Tcg[7:3]

Tco[7:3]

Tc_cfg[2:0]

SOT[7:0]

Lock[0]

Diag_cfg[2:0]

SOT_cfg[3:0] *

Lock[2:1]

Up_Clip_Lim[6]

Up_Clip_Lim[5:0]

Low_Clip_Lim[6:0]

Cust_ID0[7:0]

Cust_ID1[7:0]

Cust_ID2[7:0]

Signature[7:0]

Byte 16 A2D_Offset[0]

1V_Trim[3:0] **

Osc_Trim[2:0]

A2D_Offset[3:1]

Byte 17 JFET_cfg[0]*** Update_Rate[1:0]

Output Select[1:0]

Byte 18

Byte 19

Byte 20

Gain_B[6:0]

JFET_cfg[1] ***

Gain_B[14:7]

A5H

* SOT_cfg/Pamp_Gain

** IV_Trim/JFET_Trim

*** Config_JFET_Regulation

¹For the previous revision C (ES), the fields marked in blue text in the table affect the operation of the IC.

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ZMD31015

RBic_dLite^TMLow-Cost Sensor Signal Conditioner with Diagnostics

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PRELIMINARY

4

Application Circuit Examples

The minimum output analog load resistor is R_L= 5kΩ. This optional load resistor can be configured as a pull-

up or pull-down. If it is configured as a pull-down, it cannot be part of the module to be calibrated because this

would prevent proper operation of the ZACwire^TM. If a pull-down load is desired, it must be added to system

after module calibration.

There is no output load capacitance needed.

EEPROM contents: OUTPUT_select, Config_JFET_Regulation, 1V_Trim/JFET-Trim.

4.1 Three-Wire Rail-to-Rail Ratiometric Output

+2.7 to +5.5V

V_supply

1 Bsink

2 VBP

VSS 8

Sig^TM

7

OUT

3 ExtTemp

4 VBN

VDD 6

Vgate 5

Optional

Bsink

0.1µF

Ground

Figure 4.1 – Rail-to-Rail Ratiometric Voltage Output, Temperature Compensation via External Diode

The optional bridge sink allows a power savings of bridge current. The output voltage can be either

a) Rail-to-rail ratiometric analog output V_DD(=Vsupply).

b) 0 to 1V analog output. The absolute voltage output reference is trimmable 1V (+/-2mV) in the 1V Output

Mode via a 4-bit EEPROM field. See section 2.4.3.

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RBic_dLite^TMLow-Cost Sensor Signal Conditioner with Diagnostics

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4.2 Absolute Analog Voltage Output ¹

S

D

+5.5 to +30V

V_supply

BSS169

1 Bsink

2 VBP

VSS 8

Sig^TM

7

OUT

3 ExtTemp

4 VBN

VDD 6

Vgate 5

Optional

Bsink

0.1µF

Ground

Figure 4.2 – Absolute Voltage Output with Temperature Compensation via Internal

Temperature PTAT with External JFET Regulation for all Industry Standard Applications

The output signal range is either

a) 0 to 1V analog output. The absolute voltage output reference is trimmable 1V (+/-2mV) in the 1V Output

Mode via a 4-bit EEPROM field.

b) Rail-to-rail analog output. The on-chip reference for the JFET regulator block is trimmable 5V (+/- ~10mV)

in the Ratiometric Output Mode via a 4-bit EEPROM field See section 2.4.3.

1

With the previous revision C (ES), the JFET regulation option was not yet available (refer to ZMD31015 Technical Notes – Revision C1

Engineering Samples).

Preliminary dLite Datasheet, Rev. 0.951, May 23, 2008

Page 40 of 44

written consent of the copyright owner. The Information furnished in this publication is preliminary and subject to changes without notice.

ZMD31015

RBic_dLite^TMLow-Cost Sensor Signal Conditioner with Diagnostics

Datasheet

PRELIMINARY

4.3 Three-Wire Ratiometric Output with Over-Voltage Protection¹

S

D

+5 to +5.5 V

V_supply

J107

Vishay

1 Bsink

2 VBP

VSS 8

Sig^TM

7

OUT

3 ExtTemp

4 VBN

VDD 6

Vgate 5

Optional

Bsink

0.1µF

Ground

Figure 4.3 – Ratiometric Output, Temperature Compensation via Internal Diode

In this application, the JFET is used for voltage protection. The JFET_cfg (16:15) in EEPROM are configured

to 5.5V. There is an additional maximum error of 8mV caused by the non-zero r_ONof the limiter JFET.

4.4 Digital Output

For all three circuits, the output signal can also be digital. Depending on the output select bits, the bridge

signal or the bridge signal and temperature signal are sent.

For the digital output, no load resistor or load capacity is necessary. No pull down resistor is allowed. If a line

resistor or pull-up resistor is used, the requirement for the rise time must be met (< 5 μs). The IC output

includes an internal pull up resistor of about 30kΩ. The digital output can easily be read by firmware from a

microcontroller, and ZMD can provide the customer with software for developing the interface.

1

With the previous revision C (ES), the JFET regulation option was not yet available (refer to the ZMD31015 Technical Notes –

Revision C1 Engineering Samples).

Preliminary dLite Datasheet, Rev. 0.951, May 23, 2008

Page 41 of 44

written consent of the copyright owner. The Information furnished in this publication is preliminary and subject to changes without notice.

ZMD31015

RBic_dLite^TMLow-Cost Sensor Signal Conditioner with Diagnostics

Datasheet

PRELIMINARY

4.5 Output Resistor/Capacitor Limits

The limits for external components depend on the programmed output mode:

•

Pure Analog Output Mode (calibration is done before)

The only limit is the minimum load resistance of 5kΩ

Pure Digital Output Mode with end-of-line calibration

The RC time constant of the ZACwire™ line must have a rise time < 5µs.

Analog output with digital communication during calibration

The RC time constant of the ZACwire™ line must have a rise time < 5µs.

Warning: Any series line resistance forms a voltage divider in conjunction with the pull-up load device.

If a series line resistance is needed, choose a low value relative to the pull-up load device.

5

ESD/Latch-Up-Protection

All pins have an ESD protection of >4000V and a latch-up protection of ±100mA or of +8V/ –4V (to

VSS/VSSA). ESD protection referenced to the Human Body Model is tested with devices in SOP-8 packages

during product qualification. The ESD test follows the Human Body Model with 1.5kOhm/100pF based on MIL

883, Method 3015.7.

Preliminary dLite Datasheet, Rev. 0.951, May 23, 2008

Page 42 of 44

written consent of the copyright owner. The Information furnished in this publication is preliminary and subject to changes without notice.

ZMD31015

RBic_dLite^TMLow-Cost Sensor Signal Conditioner with Diagnostics

Datasheet

PRELIMINARY

6

Pin Configuration and Package

8

7

6

1

2

3

4

5

Figure 6.1 – RBic_dLite^TMPin-Out Diagram

The standard package of the RBic_dLite^TMis SOP-8 (3.81mm body (150mil) wide) with lead-pitch 1.27mm

(50mil).

Pin-No.

Name

Bsink

Description

Optional ground connection for bridge ground.

Used for power savings

1

2

3

4

VBP

Positive bridge connection

External diode connection

Negative bridge connection

ExtTemp

VBN

Gate control for external JFET regulation/over-

voltage protection

5

6

7

8

Vgate

VDD

Supply voltage (2.7-5.5V)

ZACwire^TMinterface (analog out, digital out,

calibration interface)

SIG™

VSS

Ground supply

7

Test

The test program is based on this datasheet. The final parameters which will be tested during series

production are listed in the tables of section 6.3.

The digital part of the IC includes a scan path, which can be activated and controlled during wafer test. It

guarantees failure coverage of more than 98%. Further test support for testing of the analog parts on wafer

level is included in the DSP.

8

Reliability

A reliability investigation according to the in-house non-automotive standard will be performed.

Preliminary dLite Datasheet, Rev. 0.951, May 23, 2008

Page 43 of 44

written consent of the copyright owner. The Information furnished in this publication is preliminary and subject to changes without notice.

ZMD31015

RBic_dLite^TMLow-Cost Sensor Signal Conditioner with Diagnostics

Datasheet

PRELIMINARY

9

Customization

For high-volume applications, which require an upgraded or downgraded functionality compared to the

ZM31015, ZMD can customize the circuit design by adding or removing certain functional blocks.

For this customization, ZMD has a considerable library of sensor-dedicated circuitry blocks, which enable

ZMD to provide a custom solution quickly. Please contact ZMD for further information.

10 Related Documents

For the most recent revisions of this document and of the related documents, please go to www.zmd.biz

•

ZMD31015 RBic_dLite^TMDie Dimensions and Pad Coordinates

ZMD31015 RBic_dLite^TMDevelopment Kit Documentation

ZMD31015 RBic_dLite^TMApplication Notes – In-Circuit Programming Boards

ZMD31015 RBic_dLite^TMErrata Sheet – Rev C1-ES Engineering Samples

For the most recent revisions of this document and of the related documents, please go to www.zmd.biz . This information applies to a

product under development. Its characteristics and specifications are subject to change without notice. ZMD assumes no obligation

regarding future manufacture unless otherwise agreed in writing. The information furnished hereby is believed to be correct and accurate.

However, ZMD shall not be liable to any customer, licensee or any other third party for any damages in connection with or arising out of

the furnishing, performance or use of this technical data. No obligation or liability to any customer, licensee or any other third party shall

result from ZMD’s rendering of technical or other services.

ZMD AG

Grenzstrasse 28

ZMD America, Inc.

ZMD Far East

For further

information:

201 Old Country Road, Suite 204 1F, No.14, Lane 268

01109 Dresden, Germany

Phone +49 (0)351.8822.7.772

Fax +49 (0)351.8822.87.772

Melville, NY 11747, USA

Phone +01 (631) 549-2666

Fax +01 (631) 549-2882

Sec. 1 Guangfu Road

HsinChu City 300

Taiwan

sales@zmd.de

www.zmd.biz

sales@zmda.com

www.zmd.biz

Phone +886.3.563.1388

Fax +886.3.563.6385

sales@zmd.de

www.zmd.biz

Preliminary dLite Datasheet, Rev. 0.951, May 23, 2008

Page 44 of 44

written consent of the copyright owner. The Information furnished in this publication is preliminary and subject to changes without notice.


型号：	ZMD31015ACG1-R
厂家：	INTEGRATED DEVICE TECHNOLOGY
描述：	Sensor/Transducer,
文件：	总44页 (文件大小：282K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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