ZSPM4551 [IDT]
High-Efficiency Charger for Li-Ion Batteries;
| 型号： | ZSPM4551 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | High-Efficiency Charger for Li-Ion Batteries |
| 文件： | 总29页 (文件大小：463K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ZSPM4551
High-Efficiency Charger
for Li-Ion Batteries
Datasheet
Brief Description
Features
The ZSPM4551 is a DC/DC synchronous switching
lithium-ion (Li-Ion) battery charger with fully inte-
grated power switches, internal compensation, and
full fault protection.
•
VBAT reverse-current blocking
•
Programmable temperature-compensated
termination voltage: 3.94V to 4.18V ± 1%
•
User programmable maximum charge current:
50mA to 1500mA
Its switching frequency of 1MHz enables the use of
small filter components, resulting in smaller board
space and reduced BOM costs.
•
•
•
•
Current mode PWM control in constant voltage
Supervisor for VBAT reported at the NFLT pin
Input supply under-voltage lockout
In Full-Charge Constant-Current Mode, the regula-
tion is for constant current (CC). Once termination
voltage is reached, the regulator operates in voltage
mode. When the regulator is disabled (the EN pin is
low), the device draws 10µA (typical) quiescent
current.
Full protection for over-current, over-temperature,
VBAT over-voltage, and charging timeout
•
•
Charge status indication
I2C™ program interface with EEPROM registers
The ZSPM4551 includes supervisory reporting
through the NFLT (inverted fault) open-drain output
to interface other components in the system. Device
programming is achieved by an I²C™* interface
through the SCL and SDA pins.
Related IDT Smart Power Products
•
ZSPM4121 Ultra-low Power Under-Voltage
Switch
•
ZSPM4141 Ultra-Low-Power Linear Regulator
Benefits
Physical Characteristics
•
Up to 1.5A of continuous output current in Full-
Charge Constant-Current (CC) Mode
•
Wide input voltage range: VBAT + 0.3V (3.5V min.)
to 7.2V
•
High efficiency – up to 92% with typical loads
•
•
Junction operating temperature: -40°C to 125°C
Package: 16-pin PQFN (4mm x 4mm)
Available Support
•
Evaluation Kit
ZSPM4551 Application Circuit
•
Support Documentation
ZSPM4551
VIN
VTH_REF
CIN
RREF
GND
VTHERM
CVDD
RSENSE
LOUT
Battery
VDD
SCL
SW
COUT
RTHM
VSENSE
VDD
RPULLUP
(optional)
SDA
EN
VBAT
NFLT
VDD
RPULLUP
(optional)
PGND
* I2C™ is a trademark of NXP.
© 2016 Integrated Device Technology, Inc.
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January 29, 2016
ZSPM4551
High-Efficiency Charger
for Li-Ion Batteries
Datasheet
ZSPM4551 Block Diagram
EN
VIN
NFLT
VIN
VIN
SCL
SDA
ZSPM4551
I²C™*
Interface
MONITOR
&
CONTROL
Over-Voltage
Protection
VBAT
VBAT
VTH_REF
VTHERM
Oscillator
BATT Thermal
Control
RREF
Ramp
Generator
BATT Current
Control
VIN
S
Vref
Gate
Drive
Backgate
Blocking
SW
Gate Drive
Control
LOUT
RSENSE
BATTERY
Typical Applications
COUT
RTHM
Comparator
Gate
Drive
• Portable battery chargers
• Smart phones
Error Amp
PGND
Compensation
Network
VIN
• Laptops
Current
Control
VDD Regulator
VSENSE
VBAT
• Tablets/e-readers
VDD
GND
CVDD
I²C™*is a trademark of NXP.
Ordering Information
Ordering Code
ZSPM4551AA1W
ZSPM4551AA1R
ZSPM4551KIT
Description
Package
ZSPM4551 High-Efficiency Li-Ion Battery Charger
ZSPM4551 High-Efficiency Li-Ion Battery Charger
ZSPM4551 Evaluation Kit
16-pin PQFN / 7” Reel (1000 parts)
16-pin PQFN / 13” Reel (3300 parts)
Corporate Headquarters
6024 Silver Creek Valley Road
San Jose, CA 95138
Sales
Tech Support
www.IDT.com/go/support
1-800-345-7015 or 408-284-8200
Fax: 408-284-2775
www.IDT.com
www.IDT.com/go/sales
DISCLAIMER Integrated Device Technology, Inc. (IDT) reserves the right to modify the products and/or specifications described herein at any time, without notice, at IDT's sole discretion. Performance
specifications and operating parameters of the described products are determined in an independent state and are not guaranteed to perform the same way when installed in customer products. The
information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT's products for any particular purpose, an
implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property
rights of IDT or any third parties.
IDT's products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be
reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT.
Integrated Device Technology, IDT and the IDT logo are trademarks or registered trademarks of IDT and its subsidiaries in the United States and other countries. Other trademarks used herein are the
property of IDT or their respective third party owners. For datasheet type definitions and a glossary of common terms, visit www.idt.com/go/glossary. All contents of this document are copyright of Integrated
Device Technology, Inc. All rights reserved.
© 2016 Integrated Device Technology, Inc.
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ZSPM4551 Datasheet
Contents
1
ZSPM4551 Characteristics............................................................................................................................... 5
1.1. Absolute Maximum Ratings....................................................................................................................... 5
1.2. Thermal Characteristics............................................................................................................................. 6
1.3. Recommended Operating Conditions ....................................................................................................... 6
1.4. Electrical Characteristics ........................................................................................................................... 7
1.5. I2C™ Interface Timing Requirements...................................................................................................... 10
Functional Description.................................................................................................................................... 11
2.1. Internal Protection ................................................................................................................................... 12
2.1.1. VIN Under-Voltage Lockout .............................................................................................................. 12
2.1.2. Internal Current Limit ........................................................................................................................ 12
2.1.3. Thermal Shutdown............................................................................................................................ 12
2.1.4. VBAT Over-Voltage Protection ......................................................................................................... 12
2.2. Fault Handling.......................................................................................................................................... 13
2.2.1. NFLT Pin Functionality...................................................................................................................... 13
2.2.2. Other Faults ...................................................................................................................................... 13
2.3. Serial Interface ........................................................................................................................................ 15
2.3.1. I2C™ Subaddress Definition ............................................................................................................. 15
2.3.2. I2C™ Bus Operation.......................................................................................................................... 15
2.4. Status and Configuration Registers......................................................................................................... 17
Application Circuits......................................................................................................................................... 22
3.1. Typical Application Circuit ....................................................................................................................... 22
3.2. Selection of External Components .......................................................................................................... 22
3.2.1. COUT Output Capacitor ...................................................................................................................... 22
3.2.2. LOUT Output Inductor ......................................................................................................................... 22
3.2.3. CIN Bypass Capacitor........................................................................................................................ 22
3.2.4. CVDD Bypass Capacitor for VDD Internal Reference Voltage Output ...............................................22
3.2.5. RSENSE Output Sensing Resistor ....................................................................................................... 23
3.2.6. Pull-up Resistors............................................................................................................................... 23
Pin Configuration and Package...................................................................................................................... 23
4.1. ZSPM4551 Package Dimensions............................................................................................................ 23
4.2. Pin-Out Assignments............................................................................................................................... 24
4.3. Pin Description for 16-Pin PQFN (4 x 4 mm) .......................................................................................... 24
4.4. Package Markings ................................................................................................................................... 25
Layout Recommendations.............................................................................................................................. 26
5.1. Multi-Layer PCB Layout........................................................................................................................... 26
5.2. Single-Layer PCB Layout ........................................................................................................................ 27
Ordering Information ...................................................................................................................................... 28
Related Documents........................................................................................................................................ 28
Document Revision History............................................................................................................................ 29
2
3
4
5
6
7
8
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ZSPM4551 Datasheet
List of Figures
Figure 2.1 ZSPM4551 Block Diagram ............................................................................................................... 11
Figure 2.2 Charging State Diagram ................................................................................................................... 14
Figure 2.3 Subaddress in I2C™ Transmission................................................................................................... 15
Figure 2.4 I2C™ Start / Stop Protocol ................................................................................................................ 16
Figure 2.5 I2C™ Data Transmission Timing ...................................................................................................... 16
Figure 3.1 Typical Application Circuit for Charging a Lithium-Ion Battery .........................................................22
Figure 4.1 PQFN-16 Package Dimensions........................................................................................................ 23
Figure 4.2 ZSPM4551 Pin Assignments............................................................................................................ 24
Figure 4.3 Marking Diagram 16-Pin PQFN (4 x 4 mm)...................................................................................... 25
Figure 5.1 Package and PCB Land Configuration for Multi-Layer PCB ............................................................26
Figure 5.2 JEDEC Standard FR4 Multi-Layer Board – Cross-Sectional View...................................................26
Figure 5.3 Conducting Heat Away from the Die using an Exposed Pad Package ............................................27
Figure 5.4 Application Using a Single-Layer PCB ............................................................................................. 28
List of Tables
Table 1.1
Table 1.2
Table 1.3
Table 1.4
Table 1.5
Table 2.1
Table 2.2
Table 2.3
Table 2.4
Table 2.5
Table 2.6
Table 2.7
Table 2.8
Table 2.9
Table 4.1
Absolute Maximum Ratings................................................................................................................ 5
Thermal Characteristics...................................................................................................................... 6
Recommended Operating Conditions ................................................................................................ 6
Electrical Characteristics .................................................................................................................... 7
I2C™ Interface Timing Characteristics.............................................................................................. 10
Register Descriptions (Device Address = 48HEX).............................................................................. 17
STATUS Register—Address 00HEX .................................................................................................. 17
Configuration Register CONFIG1—Address 02HEX .......................................................................... 18
Configuration Register CONFIG2—Address 03HEX .......................................................................... 18
Configuration Register CONFIG3—Address 04HEX .......................................................................... 19
Configuration Register CONFIG4—Address 05HEX .......................................................................... 19
Configuration Register CONFIG5—Address 06HEX .......................................................................... 20
Enable Configuration Register CONFIG_ENABLE—Address 11HEX................................................21
EEPROM Control Register EEPROM_CTRL—Address 12HEX ........................................................21
Pin Description.................................................................................................................................. 24
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ZSPM4551 Datasheet
1
ZSPM4551 Characteristics
Important: Stresses beyond those listed under “Absolute Maximum Ratings” (section 1.1) may cause permanent
damage to the device. These are stress ratings only, and functional operation of the device at these or any other
conditions beyond those indicated under “Recommended Operating Conditions” is not implied. Exposure to
absolute–maximum–rated conditions for extended periods may affect device reliability.
1.1. Absolute Maximum Ratings
Over operating free–air temperature range unless otherwise noted.
Table 1.1
Absolute Maximum Ratings
Parameter
Value 1)
-0.3 to 8
-1 to 8.8
-0.3 to 3.6
-40 to 125
-65 to 150
±2k
Unit
V
VIN, EN, NFLT, SCL, SDA, VTHERM, VTH_REF, VBAT, VSENSE
SW
V
VDD
V
Operating Junction Temperature Range, TJ
Storage Temperature Range, TSTOR
Electrostatic Discharge – Human Body Model 2)
Electrostatic Discharge – Machine Model 2)
Lead Temperature (soldering, 10 seconds)
°C
°C
V
+/-200
V
260
°C
1) All voltage values are with respect to network ground terminal.
2) ESD testing is performed according to the respective JESD22 JEDEC standard.
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ZSPM4551 Datasheet
1.2. Thermal Characteristics
Table 1.2
Thermal Characteristics
Parameter
Symbol
Value 1)
Unit
Thermal Resistance Junction to Air 1)
°C/W
50
θJA
1) Assumes a 4x4mm QFN-16 in 1 in2 area of 2 oz. copper and 25°C ambient temperature.
1.3. Recommended Operating Conditions
Table 1.3
Recommended Operating Conditions
Parameter
Symbol
Min
Typ
Max
Unit
V
BAT + 0.3V
Input Operating Voltage at VIN Pin
VIN
5.3
7.2
V
(3.5V min)
RSENSE
LOUT
COUT
COUT-ESR
CIN
50
4.7
4.7
Sense Resistor
mΩ
µH
µF
mΩ
µF
nF
°C
Output Filter Inductor Typical Value 1)
Output Filter Capacitor Typical Value 2)
Output Filter Capacitor ESR
100
Input Supply Bypass Capacitor Value 3)
VDD Supply Bypass Capacitor Value 2)
Operating Free Air Temperature
Operating Junction Temperature
3.3
70
10
CVDD
TA
100
130
85
-40
-40
TJ
125
°C
1) For best performance, use an inductor with a saturation current rating higher than the maximum VBAT load requirement plus the
inductor current ripple.
2) For best performance, use a low ESR ceramic capacitor.
3) For best performance, use a low ESR ceramic capacitor. If CIN is not a low ESR ceramic capacitor, add a 0.1µF ceramic capacitor in
parallel to CIN.
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ZSPM4551 Datasheet
1.4. Electrical Characteristics
Electrical characteristics TJ = -40°C to 125°C, VIN = 5.3V, (unless otherwise noted)
Table 1.4
Electrical Characteristics
Parameter
Symbol
Condition
Min
Typ
Max
Unit
VIN Supply Voltage
VBAT+0.3V
(3.5V min)
Voltage Input
VIN
5.3
3
7.2
V
Quiescent Current
Normal Mode
ICC-NORM ILOAD = 0A, no switching
mA
EN ≥ 2.2V (HIGH)
Quiescent Current
Disabled Mode
ICC--DISABLE EN = 0V
10
50
µA
VBAT Leakage
Leakage Current From Battery
Reverse Current
IBAT-LEAK EN = 0V, VVBAT = 4.1V
10
10
µA
µA
IBAT-BACK VBAT > VIN, VBAT = 4.1V,
TJ < 85°C
VIN Under-Voltage Lockout
Input Supply Under-Voltage
Threshold
VIN-UV
VIN increasing
3.15
200
V
Input Supply Under-Voltage
Threshold Hysteresis
VIN-UV_HYST
100
0.9
mV
OSC
Oscillator Frequency
NFLT Open Drain Output
High-Level Output Leakage
Low-Level Output Voltage
fOSC
1
1.1
0.4
0.8
MHz
IOH-NFLT
VNFLT = 5.3V
0.1
µA
V
VOL-NFLT INFLT = -1mA
EN/SCL/SDA Input Voltage Thresholds
High Level Input Voltage
Low Level Input Voltage
VIH
VIL
2.2
V
V
Input Hysteresis – EN, SCL,
SDA Pins
VHYST
200
mV
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ZSPM4551 Datasheet
Parameter
Symbol
Condition
Min
Typ
0.1
Max
Unit
µA
µA
µA
µA
µA
µA
V
VEN=VIN
VEN=0V
Input Leakage – EN Pin
IIN-EN
-2.0
55
VSCL=VIN
VSCL=0V
VSDA=VIN
VSDA=0V
ISDA = -1mA
Input Leakage – SCL Pin
Input Leakage – SDA Pin
IIN-SCL
-0.1
0.1
IIN-SDA
-0.1
Low-Level Output Voltage
VOL-SDA
0.4
Thermal Shutdown
Thermal Shutdown Junction
Temperature
TSD
150
2.9
170
10
°C
°C
TSD Hysteresis
TSD-HYST
Pre-Charge End
Pre-charge Voltage Threshold
Pre-charge Voltage Hysteresis
Charge Restart
VPRECHG
VPC-HYST
3.0
70
3.1
V
mV
Voltage Below Termination for
Charging Restart
VRESTART
100
mV
Charging Regulator with LOUT =4.7µH and COUT=4.7µF
Output Current Limit Tolerance
in Full-Charge Mode
IBAT-FC
IBAT is user programmable;
see Table 2.5.
IBAT
10%
-
IBAT
IBAT
10%
+
A
V
Termination Voltage Tolerance
in Top-Off Mode
VBAT-TO
IBAT = 0.1C, 0°C < TJ < 85°C
VBAT
1%
-
VBAT
VBAT
1%
+
VBAT is user programmable;
see section 2.4.
Top-Off Mode Time Out
Full-Charge Timer
Timer Accuracy
tTO
tFC
0
120
1400
+10%
Minutes
Minutes
200
-10%
tACC
High Side Switch On
Resistance
ISW = -1A, TJ=25°C
ISW = 1A, TJ=25°C
200
250
1.5
mΩ
mΩ
RDSON
Low Side Switch On
Resistance
Maximum Output Current
Over-Current Detect
IBAT
A
A
IOCD
HS switch current
2.5
101%
VBAT
102%
VBAT
103%
VBAT
VBAT Over-Voltage Threshold
Maximum Duty Cycle
VBAT-OV
DUTYMAX
98
%
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ZSPM4551 Datasheet
Parameter
Thermistor
VTH_REF Output Voltage
Thermistor: 10KΩ Temperature Thresholds – β=3434K
Symbol
Condition
Min
Typ
Max
Unit
VVTH_REF IVT_REF = 2µA to 100µA
1.8
V
%VTH_REF
%VTH_REF
0°C VTHERM Threshold (0°C)
0°C
Decreasing Temperature
75.6
66.5
0°C VTHERM Threshold with
Hysteresis (10°C)
0°CHYST Increasing Temperature
%VTH_REF
%VTH_REF
%VTH_REF
%VTH_REF
%VTH_REF
%VTH_REF
%VTH_REF
%VTH_REF
10°C VTHERM Threshold
(10°C)
10°C Decreasing Temperature
10°CHYST Increasing Temperature
45°C Increasing Temperature
45°CHYST Decreasing Temperature
50°C Increasing Temperature
50°CHYST Decreasing Temperature
60°C Increasing Temperature
60°CHYST Decreasing Temperature
66.2
65.4
34.5
35.3
30.8
31.5
24.9
30.8
10°C VTHERM Threshold with
Hysteresis (11°C)
45°C VTHERM Threshold
(45°C)
45°C VTHERM Threshold with
Hysteresis (44°C)
50°C VTHERM Threshold
(50°C)
50°C VTHERM Threshold with
Hysteresis (49°C)
60°C VTHERM Threshold
(60°C)
60°C VTHERM Threshold with
Hysteresis (50°C)
Thermistor: 100KΩ Temperature Thresholds – β=4311K
%VTH_REF
%VTH_REF
0°C VTHERM Threshold (0°C)
0°C
Decreasing Temperature
80.5
69.8
0°C VTHERM Threshold with
Hysteresis (10°C)
0°CHYST Increasing Temperature
%VTH_REF
%VTH_REF
%VTH_REF
%VTH_REF
10°C VTHERM Threshold
(10°C)
10°C
10°CHYST Increasing Temperature
45°C Increasing Temperature
45°CHYST Decreasing Temperature
Decreasing Temperature
69.8
68.6
31.3
32.3
10°C VTHERM Threshold with
Hysteresis (11°C)
45°C VTHERM Threshold
(45°C)
45°C VTHERM Threshold with
Hysteresis (44°C)
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ZSPM4551 Datasheet
Parameter
Symbol
Condition
Min
Typ
Max
Unit
%VTH_REF
50°C VTHERM Threshold
(50°C)
50°C
Increasing Temperature
27.0
%VTH_REF
%VTH_REF
%VTH_REF
50°C VTHERM Threshold with
Hysteresis (49°C)
50°CHYST Decreasing Temperature
60°C Increasing Temperature
60°CHYST Decreasing Temperature
27.8
19.4
27.0
60°C VTHERM Threshold
(60°C)
60°C VTHERM Threshold with
Hysteresis (50°C)
1.5. I2C™ Interface Timing Requirements
Electrical characteristics TJ = -40°C to 125°C, VIN = 5.3V. See Figure 2.5 for an illustration of the timing
specifications given in Table 1.5.
Table 1.5
I2C™ Interface Timing Characteristics
Standard Mode
Fast Mode 1)
Parameter
Symbol
Unit
Min
0
Max
Min
Max
I2C™ Clock Frequency
I2C™ Clock High Time
fscl
tsch
tscl
tsp
100
0
0.6
1.3
0
400
kHz
µs
µs
ns
ns
µs
ns
ns
ns
4
I2C™ Clock Low Time
4.7
0
I2C™ Tolerable Spike Time 2)
I2C™ Serial Data Setup Time
I2C™ Serial Data Hold Time
I2C™ Input Rise Time 2)
I2C™ Input Fall Time 2)
50
50
tsds
tsdh
ticr
250
0
250
0
1000
300
300
300
300
ticf
I2C™ Output Fall Time; 10pF to
400pF Bus 2)
tocf
300
I2C™ Bus Free Time Between Stop
and Start
I2C™ Start or Repeated Start Condition
Setup Time
I2C™ Start or Repeated Start Condition
Hold Time
tbuf
tsts
tsth
tsps
4.7
4.7
4
1.3
0.6
0.6
0.6
µs
µs
µs
µs
I2C™ Stop Condition Setup Time 2)
4
1) The I²C™ interface will operate in either standard or fast mode.
2) Parameter not tested in production.
© 2016 Integrated Device Technology, Inc.
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ZSPM4551 Datasheet
2
Functional Description
The ZSPM4551 is a fully-integrated Li-Ion battery charger IC based on a highly-efficient switching topology. It is
configurable for termination voltage, charge current, and additional variables to allow optimum charging conditions
for a wide range of Li-Ion batteries. A 1MHz internal switching frequency facilitates low-cost LC filter
combinations. Figure 2.1 provides a block diagram for the ZSPM4551.
Figure 2.1
ZSPM4551 Block Diagram
EN
VIN
NFLT
VIN
VIN
SCL
SDA
ZSPM4551
I²C™*
Interface
MONITOR
&
CONTROL
Over-Voltage
Protection
VBAT
VBAT
VTH_REF
VTHERM
Oscillator
BATT Thermal
Control
RREF
Ramp
Generator
BATT Current
Control
VIN
S
Vref
Gate
Drive
Backgate
Blocking
SW
Gate Drive
Control
LOUT
RSENSE
BATTERY
COUT
RTHM
Comparator
Gate
Drive
Error Amp
PGND
Compensation
Network
VIN
Current
Control
VDD Regulator
VSENSE
VBAT
VDD
GND
CVDD
I²C™*is a trademark of NXP.
When the battery voltage is below 3.0 volts, the ZSPM4551 enters a pre-charge state and applies a small,
programmable charge current to safely charge the battery to a level for which full-charge current can be applied.
Once the Full-Charge Mode has been initiated, the regulation will be for constant current (CC). When the battery
voltage has increased enough to go into maintenance mode, the PWM control loop will force a constant voltage
across the battery. Once in constant voltage mode, current is monitored to determine when the battery is fully
charged. See Figure 2.2 for a diagram of the charging states.
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ZSPM4551 Datasheet
This regulation voltage as well as the 1C charging current can be set to change based on the battery temperature.
There are four temperature ranges for which the regulation voltage can be set independently: 0°C to 10°C, 10°C
to 45°C, 45°C to 50°C, and 50°C to 60°C. The ZSPM4551 will stop charging if the temperature passes the
descending temperature threshold at 0°C or the ascending threshold at 60°C. These thresholds have 10 degrees
of hysteresis. The intermediate points have 1 degree of hysteresis.
2.1. Internal Protection
2.1.1.
VIN Under-Voltage Lockout
The device is held in the off state until the EN pin voltage is HIGH (≥ 2.2V) and VIN rises to 3.15V (typical). There
is a 200mV hysteresis on this input, which requires the input to fall below 2.95V (typical) before the device will
disable.
2.1.2.
Internal Current Limit
The current through the inductor LOUT is sensed on a cycle-by-cycle basis and if the current limit (IOCD; see sec-
tion 1.4) is reached, the ZSPM4551 will abbreviate the cycle. The current limit is always active when the regulator
is enabled.
2.1.3.
Thermal Shutdown
If the junction temperature of the ZSPM4551 exceeds 170°C (typical), the SW output will tri-state to protect the
device from damage. The NFLT and all other protection circuitry will stay active to inform the system of the failure
mode. Once the device cools to 160°C (typical), the device will attempt to start up again. If the device reaches
170°C, the shutdown/restart sequence will repeat.
2.1.4.
VBAT Over-Voltage Protection
The ZSPM4551 has a battery protection circuit designed to shut down the charging profile if the battery voltage is
greater than the termination voltage. The termination voltage can change based on user programming, so the
protection threshold is set to 2% above the termination voltage. Shutting down the charging profile puts the
ZSPM4551 in a fault condition.
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ZSPM4551 Datasheet
2.2. Fault Handling
2.2.1.
NFLT Pin Functionality
In the event of a battery over-voltage, the battery temperature being outside of the safe charging range, or the full
charge timer expiring, charging stops, and the NFLT pin is pulled low. When the fault condition is no longer
present, the device will enter the INITIALIZE state (see Figure 2.2), but the NFLT pin will remain low until the
STATUS register (00HEX) is read (see Table 2.2). When the STATUS register is read, the NFLT pin will go high
until a new fault is detected.
2.2.2.
Other Faults
When an open thermistor, thermal shut down, VIN under-voltage, or top-off time-out are detected, charging
immediately stops and the corresponding bit in the STATUS register (00HEX) is set. The device enters the
INITIALIZE state until the fault is no longer detected.
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ZSPM4551 Datasheet
Figure 2.2
Charging State Diagram
EN
INITIALIZE STATE
INITIALIZE
Waiting for Valid
Charging Conditions
NO
No Faults &
VBAT < VRESTART
YES
PRE-CHARGE STATE
PRE-CHARGE
Pre-charge Current Limit
NO
VBAT > VPRECHG
Threshold
YES
YES
FULL-CHARGE CONSTANT
CURRENT (CC) MODE
1C CHARGING
1C Current Limit and
Full-Charge Timer
VBAT< VPRECHG
Threshold
NO
NO
VBAT =VTERMINATION
& ICHARGE < IEOC
NO
YES
CONSTANT VOLTAGE MODE
END OF CHARGE
VBAT regulated to
VBAT =
VTERMINATION
VTERMINATION with EOC Timer
YES
NO
ICHARGE < Top
Off End Current
YES
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ZSPM4551 Datasheet
2.3. Serial Interface
The ZSPM4551 features an I2C™ slave interface that offers advanced control and diagnostic features. It supports
standard and fast mode data rates and auto-sequencing, and it is compliant to I2C™ standard version 3.0.
I2C™ operation offers configuration control for termination voltages, charge currents, and charge timeouts. This
configurability allows optimum charging conditions in a wide range of Li-Ion batteries. I2C™ operation also offers
fault and warning indicators. Whenever a fault is detected, the associated status bit in the STATUS register is set
and the NFLT pin is pulled low. Whenever a warning is detected, the associated status bit in the STATUS register
is set, but the NFLT pin is not pulled low. Reading the STATUS register resets the fault and warning status bits,
and the NFLT pin is released after all fault status bits have been reset.
2.3.1.
I2C™ Subaddress Definition
Figure 2.3
Subaddress in I2C™ Transmission
2.3.2.
I2C™ Bus Operation
The ZSPM4551’s I2C™ is a two-wire serial interface; the two lines are serial clock (SCL) and serial data (SDA)
(see Figure 2.4). SDA must be connected to a positive supply (e.g., the VDD pin) through an external pull-up
resistor. The devices communicating on this bus can drive the SDA line low or release it to high impedance. To
ensure proper operation, setup and hold times must be met (see Table 1.5). The device that initiates the I2C™
transaction becomes the master of the bus.
Communication is initiated by the master sending a START condition, which is a high-to-low transition on SDA
while the SCL line is high. After the START condition, the device address byte is sent, most significant bit (MSB)
first, including the data direction bit (read = 1; write = 0). After receiving the valid address byte, the device
responds with an acknowledge (ACK). An ACK is a low on SDA during the high of the ACK-related clock pulse.
On the I2C™ bus, during each clock pulse, only one data bit is transferred. The data on the SDA line must remain
stable during the high pulse of the clock period, as changes in the data line at this time are interpreted as START
or STOP control conditions. A low-to-high transition on SDA while the SCL input is high indicates a STOP
condition and is sent by the master.
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ZSPM4551 Datasheet
Any number of data bytes can be transferred from the transmitter to receiver between the START and the STOP
conditions. Each byte of eight bits is followed by one ACK bit from the receiver. The SDA line must be released by
the transmitter before the receiver can send an ACK bit. The receiver that acknowledges must pull down the SDA
line during the ACK clock pulse, so that the SDA line is stable low during the high pulse of the ACK-related clock
period. When a slave receiver is addressed, it must generate an ACK after each byte is received. Similarly, the
master must generate an ACK after each byte that it receives from the slave transmitter. An end of data is
signaled by the master receiver to the slave transmitter by not generating an acknowledge after the last byte has
been clocked out of the slave. This is done by the master receiver by holding the SDA line high. The transmitter
must then release the data line to enable the master to generate a STOP condition.
Figure 2.4
I2C™ Start / Stop Protocol
See Table 1.5 for the definitions and specifications for the timing parameters labeled in Figure 2.5.
Figure 2.5
I2C™ Data Transmission Timing
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ZSPM4551 Datasheet
2.4. Status and Configuration Registers
Table 2.1
Register
Register Descriptions (Device Address = 48HEX
)
Address
00HEX
N/A
Name
STATUS
Default
Description
Status bit register
0
1
00HEX
N/A
N/A
Register not implemented
Configuration register
2
02HEX
03HEX
04HEX
05HEX
06HEX
N/A
CONFIG1 1)
CONFIG2 1)
CONFIG3 1)
CONFIG4 1)
CONFIG5 1)
N/A
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
N/A
3
Configuration register
4
Configuration register
5
Configuration register
6
Configuration register
7-16
17
18
Registers not implemented
Enable configuration register access
EEPROM control register
11HEX
12HEX
CONFIG_ENABLE
EEPROM_CTRL 1)
00HEX
00HEX
1) CONFIGx and EEPROM_CTRL registers are only accessible when the CONFIG_ENABLE register is written with the EN_CFG bit
set to 1 (see Table 2.8).
Table 2.2
STATUS Register—Address 00HEX
Note: All of the STATUS register bits are READ-only.
DATA BIT
D7
D6
D5
D4
D3
D2
D1
D0
FIELD NAME
BATT_OV
1C_TO
TEMP_0C TEMP_60C
TSD
TOP_TO
VIN_UV
TH_OPEN
FIELD NAME
BIT DEFINITION 1)
BATT_OV
1C_TO
VBAT over-voltage.
Full charge timer has timed out.
TEMP_0C
TEMP_60C
TSD
Thermistor indicates battery temperature < 0°C.
Thermistor indicates battery temperature > 60°C.
Thermal shutdown.
TOP_TO
VIN_UV
Top-off timer has timed out.
VIN under-voltage.
TH_OPEN
Thermistor open (battery not present).
1) Faults are defined as BATT_OV, 1C_TO, TEMP_0C, and TEMP_60C. Warnings are defined as TSD, TOP_TO, VIN_UV, and
TH_OPEN. Faults cause the NFLT pin to be pulled low. Warnings do not cause the NFLT pin to be pulled low. All status bits are
cleared after STATUS register read access. The NFLT pin will go to high impedance (open-drain output) after the STATUS register
has been read and all status bits have been reset.
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Table 2.3
Configuration Register CONFIG1—Address 02HEX
Note: All of the CONFIG1 register bits are READ/WRITE.
DATA BIT
D7
D6
D5
D4
D3
D2
D1
D0
FIELD NAME
PRE_CHRG[1:0]
V_TERM_0_10[2:0]
BIT DEFINITION
V_TERM_10_45[2:0]
FIELD NAME
PRE_CHRG[1:0] 1)
Pre-charging configuration
00BIN – 50 mA
01BIN – 100 mA
10BIN – 185 mA
11BIN – 370 mA
V_TERM_0_10[2:0] 2)
V_TERM_10_45[2:0] 2)
Voltage termination:
0-10°C configuration
000BIN – 3.94 V
001BIN – 4.00 V
010BIN – 4.05 V
011BIN – 4.10 V
100BIN – 4.12 V
101BIN – 4.15 V
110BIN – 4.18 V
Voltage termination:
10-45°C configuration
111BIN – Invalid setting
1) PRE_CHRG Note: Maximum output current when Vout < 3.0 V.
2) V_TERM Note: There are separate settings for battery temperatures 0-10°C, 10-45°C, 45-50°C , and 50-60°C (see Table 2.4 for
45-50°C and 50-60°C). For <0°C and >60°C, charging is disabled and a fault is set.
Table 2.4
Configuration Register CONFIG2—Address 03HEX
Note: All of the CONFIG2 register bits are READ/WRITE.
DATA BIT
D7
D6
D5
D4
D3
D2
D1
D0
FIELD NAME
EOC[1:0]
V_TERM_45_50[2:0]
V_TERM_50_60[2:0]
FIELD NAME
EOC[1:0] 1)
BIT DEFINITION
00BIN – 50 mA
End of charge configuration
01BIN – 100 mA
10BIN – 185 mA
11BIN – 370 mA
V_TERM_45_50[2:0] 2)
V_TERM_50_60[2:0] 2)
Voltage termination:
45-50°C configuration
000BIN – 3.94 V
001BIN – 4.00 V
010BIN – 4.05 V
011BIN – 4.10 V
100BIN – 4.12 V
101BIN – 4.15 V
110BIN – 4.18 V
Voltage termination:
50-60°C configuration
111BIN – Invalid setting
1) EOC Note: Maximum output current when VOUT < 3.0 V.
2) V_TERM Note: There are separate settings for battery temperatures 0-10°C, 10-45°C, 45-50°C, and 50-60°C
(see Table 2.3 for 0-10°C and 10-45°C). For <0°C and >60°C, charging is disabled and a fault is set.
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ZSPM4551 Datasheet
Table 2.5
Configuration Register CONFIG3—Address 04HEX
Note: All of the CONFIG3 register bits are READ/WRITE.
DATA BIT
D7
D6
D5
D4
D3
D2
D1
D0
FIELD NAME
MAX_CHRG_CURR_0_10[3:0]
MAX_CHRG_CURR_10_45[3:0]
FIELD NAME
BIT DEFINITION
Maximum charge current:
MAX_CHRG_CURR_0_10[3:0] 1)
MAX_CHRG_CURR_10_45[3:0] 1)
0000BIN – 50 mA
0001BIN – 100 mA
0010BIN – 200 mA
0011BIN – 300 mA
0100BIN – 400 mA
0101BIN – 500 mA
0110BIN – 600 mA
0111BIN – 700 mA
1000BIN – 800 mA
1001BIN – 900 mA
1010BIN – 1000 mA
1011BIN – 1100 mA
1100BIN – 1200 mA
1101BIN – 1300 mA
1110BIN – 1400 mA
1111BIN – 1500 mA
0-10°C configuration
Maximum charge current;
10-45°C configuration
1) MAX_CHRG_CURR Note: There are separate settings for battery temperatures 0-10°C, 10-45°C, 45-50°C, and 50-60°C
(see Table 2.6 for 45-50°C and 50-60°C). For <0°C and >60°C, charging is disabled and a fault is set.
Table 2.6
Configuration Register CONFIG4—Address 05HEX
Note: All of the CONFIG4 register bits are READ/WRITE.
DATA BIT
D7
D6
D5
D4
D3
D2
D1
D0
FIELD NAME
MAX_CHRG_CURR_45_50[3:0]
MAX_CHRG_CURR_50_60[3:0]
FIELD NAME
BIT DEFINITION
MAX_CHRG_CURR_45_50[3:0] 1)
MAX_CHRG_CURR_50_60[3:0] 1)
Maximum charge current:
45-50°C configuration
0000BIN – 50 mA
0001BIN – 100 mA
0010BIN – 200 mA
0011BIN – 300 mA
0100BIN – 400 mA
0101BIN – 500 mA
0110BIN – 600 mA
0111BIN – 700 mA
1000BIN – 800 mA
1001BIN – 900 mA
1010BIN – 1000 mA
1011BIN – 1100 mA
1100BIN – 1200 mA
1101BIN – 1300 mA
1110BIN – 1400 mA
1111BIN – 1500 mA
Maximum charge current:
50-60°C configuration
1) MAX_CHRG_CURR Note: There are separate settings for battery temperatures 0-10°C, 10-45°C, 45-50°C , and 50-60°C
(see Table 2.5 for 0-10°C and 10-45°C). For <0°C and >60°C, charging is disabled and a fault is set.
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ZSPM4551 Datasheet
Table 2.7
Configuration Register CONFIG5—Address 06HEX
Note: All of the CONFIG5 register bits are READ/WRITE.
DATA BIT
D7
D6
D5
D4
D3
D2
D1
1C_TO[2:0]
D0
FIELD NAME
FIELD NAME
TOP_END 1)
TOP_END
TH
TOP_TO[2:0]
BIT DEFINITION
Top-off end configuration
0BIN – 25 mA
1BIN – 92 mA
TH 2)
Thermistor configuration
0BIN – 10kΩ
1BIN – 100kΩ
TOP_TO[2:0] 3)
Top off timer time out configuration
000BIN – 0 minutes
001BIN – 20 minutes
010BIN – 40 minutes
011BIN – 60 minutes
100BIN – 80 minutes
101BIN – 100 minutes
110BIN – 120 minutes
111BIN – Disable time out timer
1C_TO[2:0] 4)
Full charge timer time out configuration
000BIN – Disable full charge timer
001BIN – 200 minutes
010BIN – 400 minutes
011BIN – 600 minutes
100BIN – 800 minutes
101BIN – 1000 minutes
110BIN – 1200 minutes
111BIN – 1400 minutes
1) TOP_END Note: Charging stops when VVBAT = VTERMINATION and IBAT < TOP_END
2) TH Note: Setting for nominal thermistor and reference resistor value.
3) TOP_TO Note: Timer starts when VBAT = VTERMINATION and IBAT < EOC.
4) 1C_TO Note: Timer starts when VBAT > 3.0V.
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Table 2.8
Enable Configuration Register CONFIG_ENABLE—Address 11HEX
Note: The reset value for all of the CONFIG_ENABLE register bits is 0.
DATA BIT
D7
Not used
R
D6
Not used
R
D5
Not used
R
D4
Not used
R
D3
Not used
R
D2
Not used
R
D1
D0
EN_CFG
R/W
FIELD NAME
READ/WRITE
FIELD NAME
EN_CFG
Not used
R
BIT DEFINITION
Enable-access control bit for configuration registers CONFIG1 through CONFIG5
(addresses 02HEX to 06HEX
0BIN – Disable access
1BIN – Enable access
)
Table 2.9
EEPROM Control Register EEPROM_CTRL—Address 12HEX
Note: The reset value for all of the EEPROM_CTRL register bits is 0.
DATA BIT
D7
Not used
R
D6
Not used
R
D5
Not used
R
D4
Not used
R
D3
Not used
R
D2
Not used
R
D1
Not used
R
D0
EE_PROG
R/W
FIELD NAME
READ/WRITE
FIELD NAME
EE_PROG 1)
BIT DEFINITION
EEPROM program control bit for configuration registers CONFIG1 through CONFIG5
(addresses 02HEX to 06HEX
)
0BIN
1BIN
–
–
Disable EEPROM programming
Enable EEPROM programming with data from configuration registers CONFIG1
through CONFIG5 (addresses 02HEX to 06HEX
)
1) EE_PROG Note: Inputs VIN and EN must be present for 200ms.
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ZSPM4551 Datasheet
3
Application Circuits
3.1. Typical Application Circuit
Figure 3.1
Typical Application Circuit for Charging a Lithium-Ion Battery
ZSPM4551
VIN
VTH_REF
CIN
RREF
GND
VTHERM
CVDD
RSENSE
LOUT
Battery
VDD
SCL
SW
COUT
RTHM
VSENSE
VDD
RPULLUP
(optional)
SDA
EN
VBAT
NFLT
VDD
RPULLUP
(optional)
PGND
3.2. Selection of External Components
Note that the internal compensation is optimized for a 4.7µF output capacitor (COUT) and a 4.7µH output inductor
(LOUT). Table 1.3 provides recommended ranges for most of the following components.
3.2.1.
COUT Output Capacitor
To keep the output ripple low, a low ESR (less than 35mΩ) ceramic capacitor is recommended for the 4.7µF
output filter capacitor. The ESR should not exceed 100mΩ.
3.2.2.
LOUT Output Inductor
For best performance, an inductor with a saturation current rating higher than the maximum VOUT load requirement
plus the inductor current ripple should be used for the 4.7µH output filter inductor.
3.2.3.
CIN Bypass Capacitor
For best performance, a low ESR ceramic capacitor should be used for the 10µF input supply bypass capacitor. If
it is not a low ESR ceramic capacitor, a 0.1µF ceramic capacitor should be added in parallel to CIN.
3.2.4.
CVDD Bypass Capacitor for VDD Internal Reference Voltage Output
For best performance, a low ESR ceramic capacitor should be used for the 100nF bypass capacitor from the VDD
pin to ground.
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ZSPM4551 Datasheet
3.2.5.
RSENSE Output Sensing Resistor
The typical value for the output sensing resistor is 50mΩ.
3.2.6.
Pull-up Resistors
For proper function of the I2C™ interface, the SDA pin must be connected to a positive supply (e.g., the VDD pin)
through an external pull-up resistor.
For proper function of the fault warning signal on the NFLT pin, it must be connected to a positive supply (VDD)
through an external pull-up resistor.
4
Pin Configuration and Package
4.1. ZSPM4551 Package Dimensions
Figure 4.1
PQFN-16 Package Dimensions
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ZSPM4551 Datasheet
4.2. Pin-Out Assignments
Figure 4.2
ZSPM4551 Pin Assignments
12
11
10
9
13
14
15
16
8
7
6
5
SDA
VDD
NFLT
EN
ZSPM4551
PQFN16 4X4
Top View
SW
PGND
PGND
GND
1
2
3
4
4.3. Pin Description for 16-Pin PQFN (4 x 4 mm)
Table 4.1
Pin #
1
Pin Description
Name
Function
Description
SW
Switching Voltage
Node
Connect to 4.7µH (typical) inductor LOUT. Also connect to additional SW
pin 14.
2
3
VIN
Input Voltage
Input voltage. Also connect to CIN. Also connect to additional
VIN pin 11.
VSENSE
Current Sense
Positive Input
Positive input for the current loop.
4
5
VBAT
GND
Output Voltage
GND
Regulator feedback input.
Primary ground for the majority of the device except the low-side power
FET.
6
EN
Enable Input
Inverted Fault
When EN is high (≥ 2.2V), the device is enabled. Ground the pin to
disable the device. Includes internal pull-up.
7
8
NFLT
VDD
Open-drain output.
Internal 3.3V
Connect to a 100nF capacitor to GND.
Supply Output
9
VTHERM
Battery
Negative node for the thermistor, which must be located in close
proximity to the battery.
Temperature
Sensor Minus
Node
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ZSPM4551 Datasheet
Pin #
Name
Function
Battery
Temperature
Sensor Positive
Node
Description
10
VTH_REF
Positive node for the thermistor, which must be located in close
proximity to the battery.
11
12
13
14
VIN
SCL
SDA
SW
Input Voltage
Clock Input
Additional VIN pin for input voltage; connect to VIN pin 2.
I2C™ clock input.
I2C™ data (open-drain output).
Data Input/Output
Switching Voltage
Node
Additional SW pin; connect to SW pin 1.
15
16
PGND
PGND
Power GND
GND supply for internal low-side FET/integrated diode. Also connect to
additional PGND pin 16.
Power GND
GND supply for internal low-side FET/integrated diode. Also connect to
additional PGND pin 15.
4.4. Package Markings
Figure 4.3
Marking Diagram 16-Pin PQFN (4 x 4 mm)
XXXXX:
Lot Number (last five digits)
Pin 1 mark
4551A
O:
XXXXX
oYYWW
YY:
WW:
Year
Work Week
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ZSPM4551 Datasheet
5
Layout Recommendations
To maximize the efficiency of this package for application on a single layer or multi-layer PCB, certain guidelines
must be followed when laying out this part on the PCB.
5.1. Multi-Layer PCB Layout
The following are guidelines for mounting the exposed pad ZSPM4551 on a multi-layer PCB with ground a plane.
In a multi-layer board application, the thermal vias are the primary method of heat transfer from the package
thermal pad to the internal ground plane. The efficiency of this method depends on several factors, including die
area, number of thermal vias, and thickness of copper, etc.
Figure 5.1
Package and PCB Land Configuration for Multi-Layer PCB
Solder Pad (Land Pattern)
Package Thermal Pad
Thermal Vias
Package Outline
Figure 5.2
JEDEC Standard FR4 Multi-Layer Board – Cross-Sectional View
Package Solder
(square)
Component Traces
Pad
1.5038 - 1.5748 mm
Component Trace
(2oz Cu)
2 Plane
1.0142 - 1.0502 mm
Ground Plane
(1oz Cu)
1.5748mm
Thermal Via
4 Plane
0.5246 - 0.5606 mm
Power Plane
(1oz Cu)
Thermal Isolation
Power plane only
0.0 - 0.071 mm Board
Base & Bottom Pad
Package Solder
Pad (bottom trace)
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ZSPM4551 Datasheet
Figure 5.3 is a representation of how the heat can be conducted away from the die using an exposed pad
package. Each application will have different requirements and limitations, and therefore the user should use
sufficient copper to dissipate the power in the system. The output current rating for the linear regulators might
need to be de-rated for ambient temperatures above 85°C. The de-rated value will depend on calculated worst
case power dissipation and the thermal management implementation in the application.
Figure 5.3
Conducting Heat Away from the Die using an Exposed Pad Package
Mold compound
Die
Epoxy Die attach
Exposed pad
Solder
5% - 10% Cu coverage
Single Layer, 2oz Cu
Thermal Vias with Cu plating
90% Cu coverage
Ground Layer, 1oz Cu
Signal Layer, 1oz Cu
Bottom Layer, 2oz Cu
20% Cu coverage
Note: NOT to scale.
5.2. Single-Layer PCB Layout
Layout recommendations for a single-layer PCB: Utilize as much copper area for power management as possible.
In a single-layer board application, the thermal pad is attached to a heat spreader (copper areas) by using a low
thermal impedance attachment method (solder paste or thermal conductive epoxy).
In both of the methods mentioned above, it is advisable to use as much copper trace as possible to dissipate the
heat.
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ZSPM4551 Datasheet
Figure 5.4
Application Using a Single-Layer PCB
Use as much copper area
as possible for heat spread
Package Thermal Pad
Package Outline
Important: If the attachment method is NOT implemented correctly, the functionality of the product is NOT
guaranteed. Power dissipation capability will be adversely affected if the device is incorrectly mounted onto the
circuit board.
6
7
Ordering Information
Ordering Code
Description
Package
ZSPM4551AA1W
ZSPM4551AA1R
ZSPM4551KIT
ZSPM4551 High-Efficiency Charger for Li-Ion Batteries
ZSPM4551 High-Efficiency Charger for Li-Ion Batteries
ZSPM4551 Evaluation Kit
16-pin PQFN / 7” Reel (1000 parts)
16-pin PQFN / 13” Reel (3300 parts)
Related Documents
Document
ZSPM4551 Feature Sheet
ZSPM4551 Evaluation Kit Description
ZSPM4551 Application Note – Li-Ion Battery Charging
Applications
Visit IDT’s website www.IDT.com or contact your nearest sales office for the latest version of these documents.
© 2016 Integrated Device Technology, Inc.
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ZSPM4551 Datasheet
8
Document Revision History
Revision
1.00
Date
Description
December 4, 2012 First release.
1.01
October 3, 2014
January 29, 2016
Revision of specification for VTH_REF output voltage in Table 1.4.
Updates for contact information and imagery on cover and headers.
Changed to IDT branding.
Corporate Headquarters
Sales
Tech Support
www.IDT.com/go/support
6024 Silver Creek Valley Road
San Jose, CA 95138
www.IDT.com
1-800-345-7015 or 408-284-8200
Fax: 408-284-2775
www.IDT.com/go/sales
DISCLAIMER Integrated Device Technology, Inc. (IDT) reserves the right to modify the products and/or specifications described herein at any time, without notice, at IDT's sole discretion. Performance
specifications and operating parameters of the described products are determined in an independent state and are not guaranteed to perform the same way when installed in customer products. The
information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT's products for any particular purpose, an
implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property
rights of IDT or any third parties.
IDT's products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be
reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT.
Integrated Device Technology, IDT and the IDT logo are trademarks or registered trademarks of IDT and its subsidiaries in the United States and other countries. Other trademarks used herein are the
property of IDT or their respective third party owners. For datasheet type definitions and a glossary of common terms, visit www.idt.com/go/glossary. All contents of this document are copyright of Integrated
Device Technology, Inc. All rights reserved.
© 2016 Integrated Device Technology, Inc.
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IDT
ZSPM8025-KIT
True Digital PWM ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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ETC
ZSPM8725-KIT
True Digital PWM ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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IDT
ZSPM8735-KIT
True Digital PWM Controller (Single-Phase, Single-Rail)Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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ETC
ZSPM8825-KIT
True Digital PWM ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
IDT
ZSPM8835-KIT
True Digital PWM Controller (Single-Phase, Single-Rail)Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
ETC
ZSPM9000
Ultra-Compact, High-Performance DrMOS DeviceWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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IDT
ZSPM9000AI1R
Ultra-Compact, High-Performance DrMOS DeviceWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
IDT
ZSPM9010
Ultra-Compact, High-Performance DrMOS DeviceWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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IDT
ZSPM9010ZA1R
Ultra-Compact, High-Performance DrMOS DeviceWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
IDT
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