ZSSC1956 [IDT]
Intelligent Battery Sensor IC;
| 型号： | ZSSC1956 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Intelligent Battery Sensor IC 电池 |
| 文件： | 总215页 (文件大小：2181K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ZSSC1956
Intelligent Battery Sensor IC
Datasheet
Brief Description
Benefits
The ZSSC1956 IC is a dual-channel analog-to-digital
converter (ADC) with an embedded microcontroller
for battery sensing/management in automotive,
industrial, and medical systems.
•
Integrated, precision measurement solution for
accurate prediction of battery state of health
(SOH), state of charge (SOC) or state of function
(SOF)
•
•
•
•
•
•
Flexible wake-up modes allow minimum power
consumption without sacrificing performance
One of the two input channels measures the battery
current IBAT via the voltage drop at the external
shunt resistor. The second input channel measures
the battery voltage VBAT and the temperature. An
integrated flash memory is provided for customer-
specific software; e.g., dedicated algorithms for
calculating the battery state.
No temperature calibration or external trimming
components required
Optimized code density through small instruction
set architecture Thumb®-2 *
Robust power-on-reset (POR) concept for harsh
automotive environments
During Sleep Mode (e.g., engine is off), the system
makes periodic measurements to monitor the dis-
charge of the battery. Measurement cycles are
controlled by the software and include various wake-
up conditions. The ZSSC1956 is optimized for ultra-
low power consumption and draws only 100µA or
less in Low-Power Mode.
Industry’s smallest footprint allows minimal
module size and cost
AEC-Q100 qualified solution
Available Support
•
•
Evaluation Kit
Features
Application Notes
•
High-precision 24-bit sigma-delta ADC (18-bit
with no missing codes); sample rate: 1Hz– 16kHz
Physical Characteristics
•
•
On-chip voltage reference (5ppm/K typical)
Current channel
•
•
•
Wide operation temperature: -40°C to +125°C
Supply voltage: 4.2 to 18V
.
.
.
.
IBAT offset error: ≤ 10mA
IBAT resolution: ≤ 1mA
Small footprint package: PQFN32 5x5 mm
Programmable gain: 4 to 512
Differential input stage input range: ± 300mV
Basic ZSSC1956 Application Circuit
•
•
Voltage channel
To Harness
.
.
Input range: 4 to 28.8V
-
+
Car Chassis Ground
Voltage accuracy: better than ±2mV
Temperature channel
Host
Controller
LIN
VBAT
VDDE
.
.
Internal temperature sensor: ± 2°C
External temperature sensor (NTC)
LIN
Interface
INP
INN
•
•
On-chip precision oscillator (1%) and on-chip
low-power oscillator
ARM® Cortex™-M0* microcontroller:
32-bit core, 10MHz to 20MHz
Rshunt
VDDA
ZSSC1956
Optional
GPIO:
SPI, I²C™,
UART
NTH
NTL
5
GPIO
f
NTC
+
-
VSSA VSSE
•
•
•
•
•
96kB Flash/EE Memory with ECC, 8kB SRAM
LIN2.2 / SAE J2602-2 compliant
Battery
Module Ground
Directly connected to 12V battery supply
Normal Mode current consumption: 10mA to 20mA
Low-Power Mode current consumption: ≤ 100µA
*
The ARM®, Cortex™, and Thumb®-2 trademarks are owned by ARM, Ltd.
The I2C™ trademark is owned by NXP.
© 2016 Integrated Device Technology, Inc.
1
January 29, 2016
ZSSC1956
Intelligent Battery Sensor IC
Datasheet
CAR
UBAT
BODY
ZSSC1956 Stacked Die
Analog
Block
ZSSC1956
WD_TIMER
LP_REG
VDDP_REG
VDDC_REG
SD_ADC
BG_REF
Digital
Block
Block Diagram
OSC
GP_TIMER
VDDA_REG
DIGITAL
FILTER
CONFIG
RESULT
REGISTER
SHUNT
REGISTER
PGA
MUX
RREF
DIGITAL
FILTER
CALIBRATION
DATA PATH
SPI
SD_ADC
+
–
GPIO:
NTC
BATTERY
SPI,
GPIO:
I2C™,
UART
SPI, I2C™, UART
Module
GND
LIN
UART
LIN
RAM
FLASH
µC
LIN_PHYS
SBC
Microcontroller
Typical Application Circuit
Cddp
2.2µF
Cddc
2.2µF
Cddl
10nF
Rbat
BAT+
Rtest
1kΩ
Cbat
100Ω
100nF
Dbat
GSOT36
lin
Clin
220pF
Applications
VBAT VPP VDDP VDDC TEST VSSPC VDDL LIN
• Intelligent battery sensing for automotive
applications; e.g., start/stop systems, e-bikes,
scooters, and e-carts
Ddde
BAS21 2.2Ω
Rdde Cdde1
Cdde2
100nF
VDDE
VSSLIN
TESTH
TESTL
STO
1
10µF
VSSE
VSSA
INP
n.c
.
n.c
.
Cinp
10nF
Chassis
GND
Rinp
sto
tck
• Industrial and medical applications requiring
precise battery SOC, SOH
and SOF monitoring; e.g., emergency
lighting, uninterruptable power supplies,
hospital equipment, alarm systems,
and more
221Ω
Rshunt
Cin
100nF
100µΩ
ZSSC1956
Rinn
INN
TCK
BAT-
221Ω
Cinn
10nF
VSSA
VDDA
TMS
tms
TRSTN
VSSN
trstn
Cdda
Rref
75kΩ
470nF
NTH
NTL GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 TDO TDI
Rntc
10kΩ
Cntc
470pF
gpio0 gpio1 gpio2 gpio3 gpio4 tdo
tdi
Ordering Information
Product Sales Code
Description
ZSSC1956 battery sensing IC – temperature range -40°C to +125°C
Package
ZSSC1956BA3R
PQFN32 5x5 mm (reel)
ZSSC1956KIT V1.0
ZSSC1956 Evaluation Kit: modular evaluation and development board for ZSSC1956, IC samples, and USB cable,
(software and documentation can be downloaded from the product page at www.IDT.com/ZSSC1956)
Corporate Headquarters
6024 Silver Creek Valley Road
San Jose, CA 95138
Sales
Tech Support
www.IDT.com/go/support
1-800-345-7015 or 408-284-8200
Fax: 408-284-2775
www.IDT.com/go/sales
www.IDT.com
DISCLAIMER Integrated Device Technology, Inc. (IDT) reserves the right to modify the products and/or specifications described herein at any time, without notice, at IDT's sole discretion. Performance
specifications and operating parameters of the described products are determined in an independent state and are not guaranteed to perform the same way when installed in customer products. The
information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT's products for any particular purpose, an
implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property
rights of IDT or any third parties.
IDT's products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be
reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT.
Integrated Device Technology, IDT and the IDT logo are trademarks or registered trademarks of IDT and its subsidiaries in the United States and other countries. Other trademarks used herein are the
property of IDT or their respective third party owners. For datasheet type definitions and a glossary of common terms, visit www.idt.com/go/glossary. All contents of this document are copyright of Integrated
Device Technology, Inc. All rights reserved.
© 2016 Integrated Device Technology, Inc.
2
January 29, 2016
ZSSC1956 Datasheet
Contents
1
IC Characteristics ........................................................................................................................................... 12
1.1. Absolute Maximum Ratings..................................................................................................................... 12
1.2. Recommended Operating Conditions ..................................................................................................... 13
1.3. Electrical Parameters .............................................................................................................................. 14
Circuit Description .......................................................................................................................................... 22
2.1. Overview.................................................................................................................................................. 22
2.2. Digital Block Diagram SBC...................................................................................................................... 24
2.3. Block Diagram MCU................................................................................................................................ 25
2.4. System Power States .............................................................................................................................. 26
2.4.1. MCU-ON Power State....................................................................................................................... 26
2.4.2. MCU-SLP Power State ..................................................................................................................... 27
2.4.3. MCU-DEEP Power State .................................................................................................................. 27
2.4.4. LP Power State ................................................................................................................................. 27
2.4.5. ULP Power State............................................................................................................................... 28
2.4.6. OFF Power State .............................................................................................................................. 29
Functional Block Descriptions SBC................................................................................................................ 30
3.1. SPI Communication between the MCU and SBC ................................................................................... 30
3.1.1. SPI Protocol ...................................................................................................................................... 30
3.2. SBC Register Map................................................................................................................................... 32
3.3. SBC Clock and Reset Logic .................................................................................................................... 35
3.3.1. Clocks ............................................................................................................................................... 35
3.3.2. Trimming the Low-Power Oscillator.................................................................................................. 36
3.3.3. Clock Trimming and Configuration Registers ................................................................................... 37
3.3.4. Resets............................................................................................................................................... 39
3.4. SBC Watchdog Timer.............................................................................................................................. 41
3.4.1. Watchdog Registers.......................................................................................................................... 43
3.5. SBC Sleep Timer..................................................................................................................................... 44
3.5.1. Sleep Timer Registers ...................................................................................................................... 46
3.6. SBC Interrupt Controller .......................................................................................................................... 47
3.7. SBC Power Management Unit (PMU) ..................................................................................................... 50
3.7.1. FP State ............................................................................................................................................ 51
3.7.2. LP and ULP States ........................................................................................................................... 52
3.7.3. OFF State.......................................................................................................................................... 60
3.7.4. Registers for Power Configuration and the Discreet Current Measurement Count..........................60
3.8. SBC ADC Unit ......................................................................................................................................... 62
3.8.1. ADC Clocks....................................................................................................................................... 64
3.8.2. ADC Data Path.................................................................................................................................. 68
2
3
© 2016 Integrated Device Technology, Inc.
3
January 29, 2016
ZSSC1956 Datasheet
3.8.3. ADC Operating Modes and Related Registers................................................................................. 73
3.8.4. ADC Control and Conversion Timing................................................................................................ 85
3.8.5. Diagnostic Features .......................................................................................................................... 95
3.8.6. Digital Test Features......................................................................................................................... 96
3.9. SBC LIN Support Logic ........................................................................................................................... 99
3.9.1. LIN Wakeup Detection...................................................................................................................... 99
3.9.2. TXD Timeout Detection................................................................................................................... 100
3.9.3. LIN Short Detection......................................................................................................................... 100
3.9.4. LIN Testing...................................................................................................................................... 101
3.10. SBC OTP............................................................................................................................................... 102
3.11. Miscellaneous Registers........................................................................................................................ 104
3.12. Voltage Regulators ................................................................................................................................ 107
3.12.1. VDDE .............................................................................................................................................. 107
3.12.2. VDDA .............................................................................................................................................. 107
3.12.3. VDDL............................................................................................................................................... 108
3.12.4. VDDP .............................................................................................................................................. 108
3.12.5. VDDC.............................................................................................................................................. 108
Functional Block Descriptions for the MCU.................................................................................................. 109
4.1. Introduction............................................................................................................................................ 109
4.2. Memory Structure .................................................................................................................................. 109
4.2.1. Memory Map ................................................................................................................................... 110
4.2.2. Flash Memory ................................................................................................................................. 111
4.2.3. RAM Memory .................................................................................................................................. 114
4.2.4. System ROM Table......................................................................................................................... 115
4.2.5. Memory Protection.......................................................................................................................... 116
4.3. System Management Unit ..................................................................................................................... 116
4.3.1. Resets............................................................................................................................................. 116
4.3.2. Clocks ............................................................................................................................................. 117
4.3.3. Power Modes .................................................................................................................................. 118
4.3.4. Pin Configuration............................................................................................................................. 119
4.3.5. SMU Module Register Overview..................................................................................................... 123
4.4. Flash Controller ..................................................................................................................................... 125
4.4.1. Commands...................................................................................................................................... 126
4.4.2. Register Overview for Flash Controller........................................................................................... 138
4.5. GPIO...................................................................................................................................................... 141
4.5.1. Normal Functionality ....................................................................................................................... 142
4.5.2. Trigger Functionality ....................................................................................................................... 142
4.5.3. Interrupt Functionality.......................................................................................................................... 142
4
© 2016 Integrated Device Technology, Inc.
4
January 29, 2016
ZSSC1956 Datasheet
4.5.4. Register Overview of GPIO Module .................................................................................................... 143
4.6. 32-Bit Timer ........................................................................................................................................... 145
4.6.1. Timer Mode..................................................................................................................................... 145
4.6.2. Counter Mode ................................................................................................................................. 145
4.6.3. Timer Module Register Overview.................................................................................................... 146
4.7. LIN Communication Control Logic (ahbLIN).......................................................................................... 148
4.7.1. Functional Description .................................................................................................................... 149
4.7.2. Overview of Registers for LIN ahb Controller ................................................................................. 150
4.8. SPIB8..................................................................................................................................................... 163
4.8.1. Introduction ..................................................................................................................................... 163
4.8.2. SPI Signal Description .................................................................................................................... 164
4.8.3. Functional Description .................................................................................................................... 164
4.8.4. Interrupts and Status Flags............................................................................................................. 166
4.8.5. Overview of Registers for SPIB8 .................................................................................................... 167
4.9. SPI in ZSYSTEM2 ................................................................................................................................. 170
4.9.1. Data Transfers ................................................................................................................................ 170
4.9.2. Interrupts and Status Flags............................................................................................................. 171
4.9.3. Example of SPI Transfer Handling.................................................................................................. 172
4.9.4. Register Overview of SPI2.............................................................................................................. 174
4.10. I²C™ in ZSYSTEM2 .............................................................................................................................. 176
4.10.1. External Signal Lines ...................................................................................................................... 176
4.10.2. The I²C™ Bus ................................................................................................................................. 176
4.10.3. Bus Conflicts ................................................................................................................................... 177
4.10.4. Operating as Slave-Only................................................................................................................. 178
4.10.5. Operating as Single Master ............................................................................................................ 180
4.10.6. Operating as Master on a Multi-Master Bus ................................................................................... 181
4.10.7. Error Conditions .............................................................................................................................. 182
4.10.8. Bus States....................................................................................................................................... 182
4.10.9. Status Description........................................................................................................................... 184
4.10.10.Register Overview for I²C™ Module ............................................................................................... 195
4.11. USART in ZSYSTEM2........................................................................................................................... 198
4.11.1. External Signal Lines ...................................................................................................................... 198
4.11.2. Asynchronous Mode ....................................................................................................................... 198
4.11.3. Synchronous Mode ......................................................................................................................... 200
4.11.4. Register Overview of USART ......................................................................................................... 202
ESD / EMC ................................................................................................................................................... 206
5.1. Electrostatic Discharge.......................................................................................................................... 206
5.2. Power System Ripple Factor................................................................................................................. 206
5
© 2016 Integrated Device Technology, Inc.
5
January 29, 2016
ZSSC1956 Datasheet
5.3. Conducted Susceptibility ....................................................................................................................... 206
5.4. Conducted Susceptibility on Power Supply Lines ................................................................................. 207
5.5. Conducted Susceptibility on Signal Lines ............................................................................................. 207
5.6. Conducted Emission.............................................................................................................................. 208
5.7. Application Circuit Example for EMC Conformance.............................................................................. 209
Pin Configuration and Package.................................................................................................................... 210
Ordering Information .................................................................................................................................... 212
Related Documents...................................................................................................................................... 212
8.1. IDT Documents...................................................................................................................................... 212
8.2. Third-Party Related Documents ............................................................................................................ 212
Glossary ....................................................................................................................................................... 213
6
7
8
9
10 Document Revision History.......................................................................................................................... 215
List of Figures
Figure 2.1 IBS Stacked Die Assembly............................................................................................................... 22
Figure 2.2 Functional Block Diagram................................................................................................................. 23
Figure 2.3 Block Diagram of the Digital Section of the SBC.............................................................................. 24
Figure 2.4 Block Diagram of the MCU .............................................................................................................. 25
Figure 2.5 System Power States ....................................................................................................................... 26
Figure 3.1 Read and Write Burst Access to the SBC ........................................................................................ 31
Figure 3.2 Structure of the Watchdog Timer...................................................................................................... 41
Figure 3.3 Structure of the Sleep Timer............................................................................................................. 45
Figure 3.4 Generation of Interrupt and Wake-up............................................................................................... 47
Figure 3.5 LP/ULP State without any Measurements........................................................................................ 53
Figure 3.6 LP/ULP State Performing Only Current Measurements...................................................................54
Figure 3.7 LP/ULP State Performing Current, Voltage, and Temperature Measurements (discCvtCnt==2) 56
Figure 3.8 LP/ULP State Performing Current, Voltage, and Temperature Measurements (discCvtCnt==5) 56
Figure 3.9 LP/ULP State Performing Current, Voltage, and Temperature Measurements (discCvtCnt==1) 57
Figure 3.10 LP/ULP State Performing Continuous Current-Only Measurements ...............................................58
Figure 3.11 Performing Continuous Current and Voltage Measurements during LP/ULP State.........................59
Figure 3.12 Functional Block Diagram of the Analog Measurement Subsystem ................................................63
Figure 3.13 FP ADC Clocking Scheme for sdmPos= sdmPos2= 2; sdmClkDivFp= 1; sdmChopClkDiv=0 65
Figure 3.14 FP ADC Clocking for sdmPos= 1 and sdmPos2= 4; sdmClkDivFp= 1; sdmChopClkDiv=0.....65
Figure 3.15 FP ADC Clocking for sdmPos= 3 and sdmPos2= 0; sdmClkDivFp= 1; sdmChopClkDiv= 0...66
Figure 3.16 FP ADC Clocking for sdmPos= 0 and sdmPos2= 3; sdmClkDivFp= 1; sdmChopClkDiv= 0...66
Figure 3.17 LP/ULP ADC Clocking Scheme; sdmClkDivFp= 5; sdmChopClkDiv= 0 ...................................67
© 2016 Integrated Device Technology, Inc.
6
January 29, 2016
ZSSC1956 Datasheet
Figure 3.18 Functional Block Diagram of the Digital ADC Data Path..................................................................68
Figure 3.19 Data Post Correction ........................................................................................................................ 69
Figure 3.20 Data Representation through Data Post Correction including Over-Range and Overflow Levels...70
Figure 3.21 Common Enable for the “set overrange” and “set overflow” Interrupt Strobes for Current ..............71
Figure 3.22 Individual SRCS................................................................................................................................ 86
Figure 3.23 Individual MRCS (Example for Result Counter of 3) ........................................................................86
Figure 3.24 Continuous SRCS............................................................................................................................. 87
Figure 3.25 Continuous MRCS (Example for Result Counter of 3) .....................................................................87
Figure 3.26 Stopping Continuous SRCS ............................................................................................................. 88
Figure 3.27 Stopping Continuous MRCS (Example for Result Counter of 3)......................................................88
Figure 3.28 Interrupting a Continuous SRCS ...................................................................................................... 89
Figure 3.29 Interrupting a Continuous MRCS (Example for Result Counter of 3)...............................................89
Figure 3.30 Signal Behavior of adcMode............................................................................................................ 90
Figure 3.31 Timing for Current, Voltage, and Internal Temperature Measurements without Chopping for
Different Configurations of the Average Filter .................................................................................. 92
Figure 3.32 Timing for External Temperature Measurements without Chopping when No Average Filter is
Enabled............................................................................................................................................. 93
Figure 3.33 Timing for Current, Voltage, and Internal Temperature Measurements using Chopping –Example
Showing Current (adcCdat) .............................................................................................................. 94
Figure 3.34 Timing for External Temperature Measurements using Chopping...................................................95
Figure 3.35 Using Register adcCaccThfor the Digital ADC BIST......................................................................97
Figure 3.36 Bit Stream of ADC Interface Test at STO Pad ................................................................................. 98
Figure 3.37 Protection Logic of the LIN TXD Line ............................................................................................... 99
Figure 3.38 Waveform Showing the Gating Principle for Non-zero Values of linShortDelay...................... 100
Figure 4.1 Flash Memory Example: BOOT Section of 7 Flash Pages (3.5kB) and PROG Section of 22 Flash
Pages (11kB) .................................................................................................................................. 112
Figure 4.2 Example for ramSplit Address ........................................................................................................ 115
Figure 4.3 System Clocks................................................................................................................................ 117
Figure 4.4 Example for Mapping MOSI of the SPI in ZSYSTEM2 to the GPIO Pads .....................................122
Figure 4.5 Block Writes Examples: from RAM to Flash with/without Wrapping at the Flash Row Boundary..133
Figure 4.6 ahbLIN Block Diagram.................................................................................................................... 148
Figure 4.7 SPIB8 Block Diagram ..................................................................................................................... 163
Figure 4.8 SPI Bus and Status Flags for a Single Byte Transfer.....................................................................165
Figure 4.9 SPI Bus and Status Flags for a Single Byte Transfer.....................................................................171
Figure 4.10 Read Transfer Example.................................................................................................................. 177
Figure 4.11 Write Transfer Example.................................................................................................................. 177
Figure 4.12 Data Format of Asynchronous Transfers........................................................................................ 199
Figure 4.13 Data Format of Synchronous Transfers ......................................................................................... 201
Figure 5.1 Example Application Circuit............................................................................................................ 209
Figure 6.1 PQFN32 Package Drawing of the ZSSC1956................................................................................ 211
© 2016 Integrated Device Technology, Inc.
7
January 29, 2016
ZSSC1956 Datasheet
List of Tables
Table 1.1
Table 1.2
Table 1.3
Table 3.1
Table 3.2
Table 3.3
Table 3.4
Table 3.5
Table 3.6
Table 3.7
Table 3.8
Table 3.9
Absolute Maximum Ratings (referenced to VSSE)........................................................................... 12
Operating Conditions ........................................................................................................................ 13
Electrical Specifications.................................................................................................................... 14
SBC Register Map ............................................................................................................................ 32
Register irefOsc............................................................................................................................ 37
Register irefLpOsc........................................................................................................................ 37
Register lpOscTrim........................................................................................................................ 38
Register lpOscTrimCnt................................................................................................................. 38
Register swRst................................................................................................................................. 40
Register cmdExe............................................................................................................................... 40
Register funcDis............................................................................................................................ 40
Resolution and Maximum Timeout for Prescaler Configurations .....................................................41
Table 3.10 Register wdogPresetVal............................................................................................................... 43
Table 3.11 Register wdogCnt............................................................................................................................ 43
Table 3.12 Register wdogCfg............................................................................................................................ 44
Table 3.13 Register sleepTAdcCmp................................................................................................................. 46
Table 3.14 Register sleepTCmp........................................................................................................................ 46
Table 3.15 Register sleepTCurCnt................................................................................................................. 47
Table 3.16 Register irqStat............................................................................................................................ 49
Table 3.17 Register irqEna............................................................................................................................... 49
Table 3.18 Register pwrCfgFp.......................................................................................................................... 60
Table 3.19 Register pwrCfgLp.......................................................................................................................... 61
Table 3.20 Register gotoPd............................................................................................................................... 62
Table 3.21 Register discCvtCnt...................................................................................................................... 62
Table 3.22 Value for sdmPos2Depending on sdmPosand Desired Clock Delay from SDM to Chop Clocks..65
Table 3.23 Register sdmClkCfgLp.................................................................................................................... 67
Table 3.24 Register sdmClkCfgFp.................................................................................................................... 67
Table 3.25 Register adcCoff............................................................................................................................ 71
Table 3.26 Register adcCgan............................................................................................................................ 71
Table 3.27 Register adcVoff............................................................................................................................ 71
Table 3.28 Register adcVgan............................................................................................................................ 72
Table 3.29 Register adcToff............................................................................................................................ 72
Table 3.30 Register adcTgan............................................................................................................................ 72
Table 3.31 Register adcPoCoGain.................................................................................................................... 72
Table 3.32 Register adcCdat............................................................................................................................ 73
© 2016 Integrated Device Technology, Inc.
8
January 29, 2016
ZSSC1956 Datasheet
Table 3.33 Register adcVdat............................................................................................................................ 74
Table 3.34 Register adcTdat............................................................................................................................ 74
Table 3.35 Register adcRdat............................................................................................................................ 74
Table 3.36 Register adcGain............................................................................................................................ 74
Table 3.37 Register adcCrcl............................................................................................................................ 75
Table 3.38 Register adcCrcv............................................................................................................................ 75
Table 3.39 Register adcVrcl............................................................................................................................ 76
Table 3.40 Register adcVrcv............................................................................................................................ 76
Table 3.41 Register adcCrth............................................................................................................................ 77
Table 3.42 Register adcCtcl............................................................................................................................ 77
Table 3.43 Register adcCtcv............................................................................................................................ 77
Table 3.44 Register adcCaccTh........................................................................................................................ 78
Table 3.45 Register adcCaccu.......................................................................................................................... 78
Table 3.46 Register adcVTh............................................................................................................................... 80
Table 3.47 Register adcVaccu.......................................................................................................................... 80
Table 3.48 Register adcCmax............................................................................................................................ 81
Table 3.49 Register adcCmin............................................................................................................................ 81
Table 3.50 Register adcVmax............................................................................................................................ 81
Table 3.51 Register adcVmin............................................................................................................................ 81
Table 3.52 Register adcTmax............................................................................................................................ 82
Table 3.53 Register adcTmin............................................................................................................................ 82
Table 3.54 Register adcAcmp............................................................................................................................ 83
Table 3.55 Register adcGomd............................................................................................................................ 84
Table 3.56 Register adcSamp............................................................................................................................ 84
Table 3.57 adcModeSettings............................................................................................................................. 85
Table 3.58 Register adcCtrl............................................................................................................................ 91
Table 3.59 Register adcChan............................................................................................................................ 96
Table 3.60 Example Results of BIST.................................................................................................................. 97
Table 3.61 Register adcDiag............................................................................................................................ 98
Table 3.62 Register currentSrcEna............................................................................................................... 98
Table 3.63 Register linCfg............................................................................................................................. 101
Table 3.64 Register linShortFilter........................................................................................................... 102
Table 3.65 Register linShortDelay............................................................................................................. 102
Table 3.66 Register linWuDelay.................................................................................................................... 102
Table 3.67 OTP Memory Map .......................................................................................................................... 103
Table 3.68 Register pullResEna.................................................................................................................... 105
© 2016 Integrated Device Technology, Inc.
9
January 29, 2016
ZSSC1956 Datasheet
Table 3.69 Register versionCode.................................................................................................................. 105
Table 3.70 Register pwrTrim.......................................................................................................................... 106
Table 3.71 Register ibiasLinTrim............................................................................................................... 106
Table 3.72 VDDL Regulator Load Capabilities................................................................................................. 108
Table 4.1
Table 4.2
Table 4.3
Table 4.4
Table 4.5
Table 4.6
Table 4.7
Table 4.8
Table 4.9
Address Map of MCU ..................................................................................................................... 110
Memory Content of the Lower INFO Page ..................................................................................... 113
Memory Content of the Upper INFO Page ..................................................................................... 114
Memory Content of System ROM................................................................................................... 115
Register SYS_CLKCFG– system address 4000 0000HEX ...............................................................123
Register SYS_MEMPORTCFG– system address 4000 0004HEX.......................................................123
Register SYS_MEMINFO– system address 4000 0008HEX .............................................................124
Register SYS_RSTSTAT– system address 4000 000CHEX.............................................................124
List of Commands........................................................................................................................... 127
Table 4.10 Key Format ..................................................................................................................................... 134
Table 4.11 Register FC_RAM_ADDR– system address 4000 0800HEX .............................................................138
Table 4.12 Register FC_FLASH_ADDR– system address 4000 0804HEX .........................................................138
Table 4.13 Register FC_CMD_SIZE– system address 4000 0808HEX .............................................................139
Table 4.14 Register FC_EXE_CMD– system address 4000 080CHEX...............................................................139
Table 4.15 Register FC_IRQ_EN– system address 4000 0810HEX..................................................................140
Table 4.16 Register FC_STAT_CORE– system address 4000 0814HEX ...........................................................140
Table 4.17 Register FC_STAT_PROG– system address 4000 0818HEX ..........................................................141
Table 4.18 Register FC_STAT_DATA– system address 4000 081CHEX...........................................................141
Table 4.19 Register GPIO_DIR– system address 4000 1400HEX....................................................................143
Table 4.20 Register GPIO_IN– system address 4000 1404HEX .....................................................................143
Table 4.21 Register GPIO_OUT– system address 4000 1408HEX....................................................................143
Table 4.22 Register GPIO_SETCLR– system address 4000 140CHEX.............................................................143
Table 4.23 Register GPIO_IRQSTAT– system address 4000 1410HEX ...........................................................144
Table 4.24 Register GPIO_IRQEN– system address 4000 1414HEX ..............................................................144
Table 4.25 Register GPIO_IRQEDGE– system address 4000 1418HEX ..........................................................144
Table 4.26 Register GPIO_TRIGEN– system address 4000 141CHEX............................................................144
Table 4.27 Configuration of Trigger Behavior................................................................................................... 145
Table 4.28 Register T32_CTRL– system address 4000 1000HEX....................................................................146
Table 4.29 Register T32_TRIGSEL– system address 4000 1004HEX .............................................................146
Table 4.30 Register T32_CNT– system address 4000 1008HEX ......................................................................147
Table 4.31 Register T32_REL– system address 4000 100CHEX .....................................................................147
Table 4.32 Register LIN_CFG – system address 4000 1800HEX.....................................................................150
© 2016 Integrated Device Technology, Inc.
10
January 29, 2016
ZSSC1956 Datasheet
Table 4.33 Register LIN_RXDATA – system address 4000 1804HEX ..............................................................153
Table 4.34 Register LIN_TXDATA – system address 4000 1808HEX ..............................................................153
Table 4.35 Register LIN_HEADERLEN – system address 4000 180CHEX .......................................................153
Table 4.36 Register LIN_BAUDRATE– system address 4000 1810HEX ...........................................................154
Table 4.37 Register LIN_BRKLOW– system address 4000 1814HEX ...............................................................155
Table 4.38 Register LIN_HINTERBRKDEL – system address 4000 1818HEX .................................................156
Table 4.39 Register LIN_WAKEUPIDLE – system address 4000 181CHEX .....................................................157
Table 4.40 Register LIN_IREN – system address 4000 1820HEX...................................................................157
Table 4.41 Register LIN_CLI – system address 4000 1824HEX.....................................................................159
Table 4.42 Register LIN_STAT – system address 4000 1828HEX...................................................................161
Table 4.43 Register SPICFG_B8– system address 4000_2000HEX; local address is 00HEX............................167
Table 4.44 Register SPICLKCFG_B8– system address 4000_2004HEX; local address is 08HEX .....................168
Table 4.45 Register SPISTAT_B8 – system address 4000_2008HEX; local address is 04HEX..........................168
Table 4.46 Accessing the FIFO Buffers – system address 4000_XXXXHEX.....................................................169
Table 4.47 Register Z2_SPICFG– system address 4000 1C00HEX .................................................................174
Table 4.48 Register Z2_SPIDATA– system address 4000 1C04HEX...............................................................174
Table 4.49 Register Z2_SPICLKCFG– system address 4000 1C08HEX...........................................................175
Table 4.50 Register Z2_SPISTAT– system address 4000 1C0CHEX ..............................................................175
Table 4.51 Register Z2_I2CCLKRATE– system address 4000 1C20HEX ........................................................195
Table 4.52 Register Z2_I2CCLKRATE2– system address 4000 1C24HEX ......................................................195
Table 4.53 Register Z2_I2CADDR– system address 4000 1C28HEX...............................................................195
Table 4.54 Register Z2_I2CCTRL– system address 4000 1C2CHEX ..............................................................196
Table 4.55 Register Z2_I2CSTAT– system address 4000 1C30HEX...............................................................197
Table 4.56 Register Z2_I2CDATA– system address 4000 1C34HEX...............................................................197
Table 4.57 Register Z2_USARTCFG– system address 4000 1C40HEX.............................................................202
Table 4.58 Register Z2_USARTSTAT– system address 4000 1C44HEX...........................................................203
Table 4.59 Register Z2_USARTDATA– system address 4000 1C48HEX...........................................................204
Table 4.60 Register Z2_USARTIRQEN– system address 4000 1C4CHEX........................................................204
Table 4.61 Register Z2_USARTCLK1– system address 4000 1C50HEX..........................................................205
Table 4.62 Register Z2_USARTCLK2– system address 4000 1C54HEX...........................................................205
Table 5.1
Table 5.2
Table 5.3
Table 5.4
Table 6.1
Conducted Susceptibility ................................................................................................................ 207
Conducted Susceptibility on Power Supply Lines .......................................................................... 207
Conducted Susceptibility on Signal Lines....................................................................................... 207
Conducted Emission....................................................................................................................... 208
IC Pins ............................................................................................................................................ 210
© 2016 Integrated Device Technology, Inc.
11
January 29, 2016
ZSSC1956 Datasheet
1
IC Characteristics
1.1. Absolute Maximum Ratings
Note: The absolute maximum ratings in section 1.1 are stress ratings only. The device might not function or be
operable above the recommended operating conditions given in section 1.2. Stresses exceeding the absolute
maximum ratings might also damage the device. In addition, extended exposure to stresses above the recom-
mended operating conditions might affect device reliability. IDT does not recommend designing to the “Absolute
Maximum Ratings.”
Table 1.1 Absolute Maximum Ratings (referenced to VSSE)
No
Parameter
Symbol
VDDE
Conditions
Min
Max
Unit
V
1.1.1. External power supply
1.1.2. Current sensing, INP pin
1.1.3. Current sensing, INN pin
1.1.4. Voltage sensing, VBAT pin
1.1.5. Voltage sensing, VBAT pin
VSSE-0.3
40
VINP
VSSE-0.3 VDDA+0.3
VSSE-0.3 VDDA+0.3
V
VINN
V
VVBAT
VVBAT
-18
-18
33
40
V
1h over
lifetime
V
1.1.6. Temperature sensing, NTH pin
1.1.7. Temperature sensing, NTL pin
1.1.8. LIN bus interface, LIN pin
1.1.9. LIN bus interface, LIN pin
VNTH
VNTL
VLIN
VLIN
VSSE-0.3 VDDA+0.3
VSSE-0.3 VDDA+0.3
V
V
V
V
-16
-16
33
40
1h over
lifetime
1.1.10. GPIO pins
VGPIO
TA
VSSE-0.3 VDDP+0.3
V
1.1.11. Ambient temperature under bias
1.1.12. Junction temperature
1.1.13. Storage temperature
125
135
°C
°C
°C
Tj
TS
-50
125
© 2016 Integrated Device Technology, Inc.
12
January 29, 2016
ZSSC1956 Datasheet
1.2. Recommended Operating Conditions
Table 1.2 Operating Conditions
No.
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
1.2.1
Operating temperature range
TA
Ambient,
-40
115
°C
RTHP=35K/W
1.2.2
1.2.3
Extended temperature range
TA_Ext
Ambient,
with reduced
accuracies
-40
6
125
18
°C
V
Supply voltage at BAT+
VBAT+
13
terminal 1) for normal operation
Minimum supply voltage at
VDDE pin:
Normal accuracy for
current and temperature
measurements
4.8
4.2
a) When VBAT+ < 6V, i.e.
operation with low battery
Reduced accuracy for
voltage measurements
VDDE_low
1.2.4
V
b) When VBAT+ = VDDE , i.e.
without using Ddde and
Rdde (see Figure 5.1)
Reduced accuracy for all
measurements
1.2.5
1.2.6
Digital input voltage LOW
Digital input voltage HIGH
VIL
VIH
0
0.3*VDDP
VDDP
V
V
0.7*VDDP
1) See application diagram on page 3.
© 2016 Integrated Device Technology, Inc.
13
January 29, 2016
ZSSC1956 Datasheet
1.3. Electrical Parameters
Note: See important notes at the end of the following table. See section 3.7 for definitions of power states.
Table 1.3 Electrical Specifications
No.
Parameter
Symbol
Conditions
Min
Typ
Max Unit
Supply
1.3.1.
Average supply current at
VDDE
IDDE_avg
Normal Mode
20
mA
(FP state, both ADC
ON)
1.3.2.
1.3.3.
Average power dissipation
PDDE_avg
IDDE_slp
Normal Mode,
VDDE=13V
260
65
mW
µA
Average supply current at
VDDE
Sleep Mode
(ULP state, no
measurement)
1.3.4.
1.3.5.
Average supply current at
VDDE
IDDE_cmp
Comparator Mode,
ULP state with wake
up time interval = 30s,
I-ADC only
160
60
µA
µA
Average supply current at
VDDE
IDDE_off
OFF state (no
measurement,
transportation mode)
1.3.6.
1.3.7.
1.3.8.
Internal analog power
supply voltage
VDDA
VDDL
VDDC
2.4
2.5
1.8
1.8
2.6
V
V
V
Internal digital and RAM
power supply voltage
1.62
1.62
1.98
1.98
Internal power supply
voltage for microcontroller
unit (MCU) core
1.3.9.
Internal power supply
voltage (periphery)
VDDP
2.97
3.3
3.63
V
Current Channel
1.3.10. Input signal range 1)
RangeC
Gain = 4
-300
-150
-75
300
150
75
mV
mV
mV
mV
mV
mV
mV
Gain = 8
Gain = 16
Gain = 32
Gain = 64
Gain = 128
Gain = 256
-38
38
-19
19
-9.5
-4.7
9.5
4.7
© 2016 Integrated Device Technology, Inc.
14
January 29, 2016
ZSSC1956 Datasheet
No.
Parameter
Symbol
Conditions
Min
-2.3
-3
Typ
Max Unit
Gain = 512
2.3
+3
mV
nA
nA
1.3.11. Input leakage current 1)
1.3.12. Input offset current 1)
ILEAK_C
TA = 25°C
IOFFSET_C
For input signal <
10mV
0.5
1.5
1.3.13. Conversion rate 1), 2)
RateC
OSRC
Programmable
Programmable
1
16000
256
Hz
1.3.14. Oversampling ratio 1)
32
(Sinc4 decimation filter)
1.3.15. No missing codes 1)
1.3.16. Integral nonlinearity 1), 3), 4), 5)
NMCC
INL
18
Bits
Maximum input range
±10
±3
±60
ppm
of
FSR
1.3.17. PGA gain range 1)
1.3.18. Total gain error 1), 8)
1.3.19. Gain drift 1)
APGA
4
512
1
errPGA_C
-1
%
ppm/°
C
err_driftPGA_C
1.3.20. Offset error after ZSSC1956
calibration 1), 6)
VOFFSET_C
Normal Mode
chop on,
-2
2
µV
external short (VSSA)
Low-Power Mode,
chop on,
-0.6
0.6
µV
external short (VSSA)
1.3.21. Offset error drift 1), 4)
VOFFSET_DRIFT_C Chop on
Chop off
±20
±80
1.1
nV/oC
nV/oC
µVRMS
1.3.22. Output noise with chop on 1),
VNOISE_C
Gain = 512,
10)
conversion rate =
10Hz
Gain = 512,
conversion rate =
1kHz
1.1
µVRMS
Gain = 32, conversion
rate = 1kHz
3
µVRMS
µVRMS
mA
Gain = 4, conversion
rate = 1kHz
11
1.3.23. Current offset 1)
IBAT_offset
Chop on,
10
gain = 512, Rshunt
=
100µΩ
© 2016 Integrated Device Technology, Inc.
15
January 29, 2016
ZSSC1956 Datasheet
No.
Parameter
Symbol
Conditions
Min
Typ
Max Unit
1.3.24. Resolution 1)
IRES
Chop on,
1
mA
gain = 512, Rshunt
=
100µΩ
Voltage Channel
1.3.25. Input signal range
(at VBAT pin) 1)
1.3.26. Input measurement range 1) Rangemeas_V Resistive divider
(1:24)
RangeV
Resistive divider
(1:24)
0
28.8
28.8
1.2
V
V
V
3.6
1.3.27. Input valid range for ADC 1)
RangeADC_V Resistive divider
(1:24)
0.15
1.3.28. Voltage resistive divider
ratio 1)
RatioV
24
±3
1.3.29. Resistor divider mismatch
drift 1)
Ratio_misdrift_v
ppm/º
C
1.3.30. Conversion rate 1), 2)
RateV
OSRV
Programmable
Programmable
1
16000
256
Hz
1.3.31. Oversampling ratio
(Sinc4 decimation filter) 1)
32
1.3.32. No missing codes 1)
1.3.33. Integral nonlinearity 1), 3), 7)
NMCV
INLV
18
Bits
Maximum input range
±10
±60
ppm
of
FSR
1.3.34. Total gain error 1)
errPGA_V
-0.25
0.25
%
(includes resistor divider
mismatch)
1.3.35. Gain drift 1)
err_driftPGA_V
VOFFSET_V
±3
ppm/°
C
1.3.36. Offset error after calibration:
Normal Mode 1), 9)
Chop on
external short
(1.25V)
200
µV
Chop off
1
mV
external short
(1.25V)
1.3.37. Offset error drift 1)
VOFFSET_DRIFT_V Chop on
Chop off
±10
±20
µV/°C
µV/°C
© 2016 Integrated Device Technology, Inc.
16
January 29, 2016
ZSSC1956 Datasheet
No.
Parameter
Symbol
Conditions
Min
Typ
Max Unit
1.3.38. Output noise 1), 10)
VNOISE_V
Chop on
30
50
µVRMS
gain = 1,
conversion rate =10Hz
Chop on
1
mVRMS
gain = 1,
conversion rate =
1kHz
Temperature Channel (External NTC/Reference Resistor)
1.3.39. Voltage drop over NTC
resistor 1)
VNTC
0
0
1.2
1.2
V
V
1.3.40. Voltage drop over reference
resistor 1)
VREF_Res
1.3.41. Conversion rate 1)
RateT
OSRT
Programmable
Programmable
1
16000
256
Hz
1.3.42. Oversampling ratio
(Sinc4 decimation filter) 1)
32
1.3.43. Integral nonlinearity 1), 3)
INLT
Maximum input range
±10
±60
ppm
of
FSR
1.3.44. No missing codes 1)
16
Bit
µV
NMCT
1.3.45. Offset error after ZSSC1956
calibration 1), 9)
VOFFSET_T
Normal Mode,
chop on,
external short (1.25V)
-100
100
2
Normal Mode,
chop off,
-2
mV
external short
(1.25V)
1.3.46. Offset error drift 1)
1.3.47. Output noise 1), 10)
VOFFSET_drift_T Chop on
Chop off
±10
±20
30
µV/oC
µV/oC
µVRMS
VNOISE_T
Chop on,
50
2
gain = 1, conversion
rate =500Hz
1.3.48. Resistor to ground at
NTL pin 1)
GNDRES
120
kΩ
1.3.49. Linearity error of internal
temperature sensor
-2
°C
© 2016 Integrated Device Technology, Inc.
17
January 29, 2016
ZSSC1956 Datasheet
No.
Parameter
Symbol
Conditions
Min
Typ
Max Unit
°C/LSB
1.3.50. Resolution of internal
temperature sensor
Factory calibrated
(self-heating is not
included; it must be
calculated and taken
into account)
1/32
Power-on Reset (POR)
1.3.51. Power-on reset
VPORB
At VDDE
At VDDE
2.75
3.0
300
2.0
3.6
V
mV
V
1.3.52. Power-on-reset hysteresis
1.3.53. Low-voltage flag
1.3.54. VDDP high 1)
HystPORB
At VDDE
At VDDE
At VDDE
low_voltage
vddp_high
HystVDDP_high
1.8
3.9
2.3
4.2
4.05
400
V
1.3.55. VDDP high hysteresis 1)
mV
Low-Power Voltage Reference
1.3.56. Reference bandgap voltage:
low-power
VBGL
1.16
-3
1.32
3
V
%
1.3.57. Accuracy
(including temperature drift)
1.3.58. Temperature coefficient 1)
Low-Power (LP) Oscillator
1.3.59. Frequency
TCVBGL
50
ppm/K
fLPO
125
kHz
%
1.3.60. Accuracy (including
temperature drift) 1)
-3
3
High-Precision Voltage Reference
1.3.61. Reference bandgap voltage:
high-precision
1.3.62. Temperature coefficient 1)
High-Precision (HP) Oscillator
1.3.63. Frequency
VBGH
Uncalibrated
Calibrated
1.16
-20
1.32
V
TCVBGH
±5
20
+20 ppm/K
fHPO
MHz
1.3.64. Accuracy (including
temperature drift) 1)
-1
1
%
LIN Interface
1.3.65. Current limitation for driver
dominant state 1), 11)
IBUS_LIM
LIN spec 2.1
Param 12
40
-1
200
mA
mA
1.3.66. Input leakage current,
IBUS_PAS_dom LIN spec 2.1
Param 13
dominant state, driver off 1),
11)
© 2016 Integrated Device Technology, Inc.
18
January 29, 2016
ZSSC1956 Datasheet
No.
Parameter
Symbol
Conditions
Min
Typ
Max Unit
1.3.67. Input leakage current,
IBUS_PAS_rec LIN spec 2.1
Param 14
20
µA
recessive state, driver off 1),
11)
1.3.68. Control unit disconnected
from ground 1), 11)
1.3.69. VBAT disconnected 1), 11)
IBUS_NO_GND LIN spec 2.1
Param 15
-1
1
mA
µA
IBUS_NO_BAT LIN spec 2.1
Param 16
100
0.4
1.3.70. Receiver dominant state,
VDDE > 7V 1), 11)
VBUSdom
VBUSrec
VBUS_CNT
VHYS
LIN spec 2.1
Param 17
VDDE
VDDE
1.3.71. Receiver recessive state,
VDDE > 7V 1), 11)
LIN spec 2.1
Param 18
0.6
1.3.72. Center of receiver
threshold 1), 11)
LIN spec 2.1
Param 19
0.475
0.5
0.7
0.525 VDDE
0.175 VDDE
1.3.73. Receiver hysteresis
voltage 1), 11)
LIN spec 2.1
Param 20
1.3.74. Voltage drop at serial
diodes 1), 11)
1.3.75. Battery shift 1), 11)
VSerDiode
VShift_BAT
VBUS_GND
LIN spec 2.1
Param 21
0.4
1
0.115
0.115
8
V
LIN spec 2.1
Param 22
VBAT
VBAT
%
1.3.76. Ground shift 1), 11)
LIN spec 2.1
Param 23
1.3.77. Difference between battery
shift and ground shift 1), 11)
VSHIFT_Difference LIN spec 2.1
Param 24
0
1.3.78. LIN pull-up resistor 1), 11)
1.3.79. Duty cycle 1 1), 11)
1.3.80. Duty cycle 2 1), 11)
1.3.81. Duty cycle 3 1), 11)
1.3.82. Duty cycle 4 1), 11)
RSLAVE
LIN spec 2.1
Param 26
20
30
47
kΩ
D1
LIN spec 2.1
Param 27
0.396
D2
LIN spec 2.1
Param 28
0.581
0.590
D3
LIN spec 2.1
Param 29
0.417
D4
LIN spec 2.1
Param 30
© 2016 Integrated Device Technology, Inc.
19
January 29, 2016
ZSSC1956 Datasheet
No.
Parameter
Symbol
Conditions
Min
Typ
Max Unit
1.3.83. Receiver propagation
delay 1), 11)
tRX_pdr
LIN spec 2.1
Param 31
6
µs
1.3.84. Symmetry receiver
propagation delay,
tRX_sym
LIN spec 2.1
Param 32
-2
2
µs
rising/falling edge 1), 11)
1.3.85. Capacitance of slave
node 1), 11)
1.3.86. LIN pin capacitance 1), 11)
CSLAVE
CLIN
LIN spec 2.1
Param 37
250
30
pF
pF
-
-
Microcontroller Platform
1.3.87. MCU start-up time after
Sleep Mode wake up /
POR 1)
80
µs
µs
1.3.88. MCU start-up time
after Standby Mode wake
up 1)
1
eFlash Memory
1.3.89. Memory size 1)
1.3.90. Page size 1)
1.3.91. Access time 1)
1.3.92. Read current 1)
1.3.93. Page erase time 1)
1.3.94. Mass erase time 1)
1.3.95. Endurance 1)
1.3.96. Data retention time 1)
SRAM
96
kB
B
512
35
15
24
24
ns
mA
ms
16
16
ms
10k
10
cycles
years
1.3.97. Memory size 1)
Timer 0 (Sleep Timer)
1.3.98. Time interval 1)
1.3.99. Resolution 1)
8
kB
SLPTI1
SLPTI1res
SLPTI2
Programmable
Programmable
0.1
6553.5
466
s
ms
h
100
1.3.100. Time interval with post-
scaler 1)
© 2016 Integrated Device Technology, Inc.
20
January 29, 2016
ZSSC1956 Datasheet
No.
Parameter
Symbol
Conditions
Min
Typ
Max Unit
Timer 1 (Watchdog Timer)
1.3.101. Time interval 1)
1.3.102. Resolution 1)
WDTI
Programmable
Programmable
8µ
6553.5
100
s
WDTIRES
0.008
ms
1) Not tested in production test; given by design and/or characterization.
2) Conversion rate depends on chopping and OSR settings.
3) Full-scale range (FSR) = 1.2V.
4) For gain setting up to 64.
5) Minimum input voltage I-ADC = -50mV for gain setting 4, 8, 16.
6) Gain setting 16 to 512.
7) Voltage range 7V to 19V.
8) Valid for gain=4, factory calibrated at gain=4, calibration data stored in OTP.
9) Error included in total gain error.
10) Noise can be further reduced by applying averaging.
11) Valid with no additional series resistor.
© 2016 Integrated Device Technology, Inc.
21
January 29, 2016
ZSSC1956 Datasheet
2
Circuit Description
2.1. Overview
The ZSSC1956 intelligent battery sensor IC (IBS) consists of two silicon dies in one package. The dies are
assembled as stacked dies in a PQFN32 5x5 mm package as shown in Figure 2.1. See Figure 2.2 for the
ZSSC1956 block diagram. The System Basis Chip (SBC) contains the high voltage circuits, analog input stage
including peripheral blocks, ΣΔ-ADCs (SD_ADC), digital filtering, and LIN transceiver. The microcontroller chip
(MCU) contains the microcontroller core, memories, and some peripheral blocks. Communication between the
MCU and the SBC is handled by an SPI interface. Internal nodes connecting the MCU and the SBC (i.e., TXD,
RXD, IRQN, CSN, SCLK, MOSI, MISO, MCU_CLK, MCU_RSTN, and RAM_PROTN) are controlled by firmware.
Users can access the internal nodes via the LIN interface and/or external JTAG pins (i.e., TDO, TDI, TRSTN,
TMS, and TCK).
The functions of the SBC are controlled by register settings. The circuit starts after power-on with default register
and calibration settings that can be overwritten by the user software.
Figure 2.1 IBS Stacked Die Assembly
Analog Blocks
SBC Digital
One input channel measures IBAT via the voltage drop at the external shunt resistor. The second channel
measures VBAT and the temperature. By simultaneous measurement of VBAT and IBAT, it is possible to determine
dynamically RBAT, which is correlated with the state of health (SOH) of the battery. By integrating IBAT, it is possible
to determine the state of charge (SOC) of the battery. These are the fundamental parameters for an intelligent
battery sensor. The software for determining these parameters is not part of the ZSSC1956. A flash memory is
provided for the customer-specific software.
The SBC and MCU have different power states designed to minimize power consumption (see section 2.4).
During the Standby and the Sleep Modes (e.g., engine is off), the system periodically measures the values to
monitor the discharge of the battery. Measurement cycles are controlled by the software and are dependent on
the detected events. The ZSSC1956 is designed for low-power consumption during Sleep Mode in the range of
less than 100µA.
© 2016 Integrated Device Technology, Inc.
22
January 29, 2016
ZSSC1956 Datasheet
Figure 2.2 Functional Block Diagram
CAR
BODY
UBAT
ZSSC1956 Stacked Die
Analog
Block
WD_TIMER
LP_REG
VDDP_REG
VDDC_REG
SD_ADC
BG_REF
Digital
Block
OSC
GP_TIMER
VDDA_REG
DIGITAL
FILTER
CONFIG
RESULT
REGISTER
SHUNT
REGISTER
PGA
RREF
DIGITAL
FILTER
CALIBRATION
DATA PATH
SPI
SD_ADC
+
–
MUX
GPIO:
SPI,
NTC
BATTERY
GPIO:
I2C™,
UART
SPI, I2C™, UART
Module
GND
LIN
UART
LIN
RAM
FLASH
µC
LIN_PHYS
SBC
Microcontroller
© 2016 Integrated Device Technology, Inc.
23
January 29, 2016
ZSSC1956 Datasheet
2.2. Digital Block Diagram SBC
In Figure 2.3, the red lines indicate set-interrupt signal paths and the blue lines indicate wake-up signal paths.
TXD, IRQN, CSN, SCLK, MOSI, MISO, MCU_RSTN, RAM_PROTN, MCU_CLK, RXD, and DBGEN are internal
nodes.
Figure 2.3 Block Diagram of the Digital Section of the SBC
TXD
LIN Phy
LIN Ctrl
LPosc
125 kHz
OTP
Irq
Ctrl
HPosc
20 MHz
IRQN
ΣΔ–ADC1
current
CSN
ADC
Unit
SCLK
MOSI
MISO
S
P
I
Register File
ΣΔ–ADC2
volt/temp
trim / config
PMU
Sleep
Timer
MCU_RSTN
RAM_PROTN
MCU_CLK
VDDA
2.5V
LIN
Wakeup
Detect
Clk
Rst
Ctrl
Watch
Dog
Timer
wdReset
power down ctrl
RXD
DBGEN
VDDL
VDDL
1.8V
VDDC
VDDC
VDDP
1.8V
VDDP
3.3V
© 2016 Integrated Device Technology, Inc.
24
January 29, 2016
ZSSC1956 Datasheet
2.3. Block Diagram MCU
In Figure 2.5, the blue lines indicate interrupt signals and the green line indicates trigger signals. The nodes on
the left are internal, and the pads on the right are external.
Figure 2.4 Block Diagram of the MCU
DBGEN
IRQn
TRSTn
TCK
TMS
TDI
ARM subsystem
(CortexM0®, NVIC, SysTick, JTAG,
single-cycle MUL)
TXD
RXD
TDO
ahbLIN
zSystem2
SSN
GPIO00
GPIO01
GPIO02
GPIO03
GPIO04
Master
SPI 2
SPI_CLK
MOSI
Master
SPIB8
I²C™
USART
MISO
GPIO
FlashCtrl
incl. 96KB
flash & ECC
32bit
Timer
8KB
RAM_PROTn
SRAM
MCU_RSTn
MCU_CLK
SMU
© 2016 Integrated Device Technology, Inc.
25
January 29, 2016
ZSSC1956 Datasheet
2.4. System Power States
Six different power states are implemented in the ZSSC1956, which are combinations of the different power
states of the SBC (see section 3.7) and of the MCU (see “Power Modes” in section 4.3). As discussed in the
following sections, other combinations are not allowed.
Figure 2.5 System Power States
MCU-ON
MCU-SLP
MCU-DEEP
LP
ULP
OFF
2.4.1.
MCU-ON Power State
The MCU-ON power state is entered after power-on reset or after wake-up. In this power state, the MCU is in its
Normal Mode and the SBC is in its Full-Power (FP) state (see section 3.7). The SBC powers the MCU and
generates the 20MHz clock for the MCU, which is distributed inside the MCU to the ARM® core as well as to the
peripherals. The base clock for the ADCs in the SBC is 4MHz, which is generated from the 20MHz from the high-
precision oscillator.
In this state, the ARM® core is running and executing the software from flash or RAM. The software can trigger
the system management unit (SMU) (see section 4.3) in the MCU as well as the power management unit (PMU)
(see section 3.7) in the SBC to enter any other power state.
Of the six power states, the MCU-ON state consumes the most power.
© 2016 Integrated Device Technology, Inc.
26
January 29, 2016
ZSSC1956 Datasheet
2.4.2.
MCU-SLP Power State
In MCU-SLP power state, the SBC remains in its FP state, which means that it still powers the MCU and
generates the 20MHz clock for the MCU. Inside the MCU, all peripherals are clocked, but the clock for the ARM®
core is stopped. This power state is intended for scenarios where the ARM® core does not need to execute code
but waits for MCU internal peripherals to finish their programmed tasks; e.g., sending a byte via the LIN interface.
The system can wake up from this power state by an enabled interrupt as well as by an MCU reset generated by
the SBC.
Note: For any SBC interrupt source that will wake up the system, the corresponding interrupt source must be
enabled in the SBC, and the ARM® interrupt line 1 (SBC interrupt) must be enabled in the MCU’s interrupt
controller (NVIC) (see section 4.1).
When the system will enter the MCU-SLP power state from the MCU-ON power state, the software must first
enable the required interrupt sources in the SBC and the MCU and it must set the SLEEPDEEP bit in the ARM®
internal system control register (SCR) to 0 (see the IDT ARM® Cortex™ M0 User Guide). Then the software must
execute the wait-for-interrupt (WFI) instruction to enter the MCU-SLP power state. When any of the enabled
interrupts becomes active, the system returns to the MCU-ON power state and continues the software execution.
Note: Do not send a power-down command to the SBC in advance.
2.4.3.
MCU-DEEP Power State
In MCU-DEEP power state, the SBC remains in its FP state, which means that it still powers the MCU and
generates the 20MHz clock for the MCU. Inside the MCU, the incoming clock is gated, which means that no logic
in the MCU is clocked. This power state is intended for conditions where the SBC will perform high-precision
measurements using the 4MHz clock as the base clock for the ADCs, but the ARM® core will not run its software
and no MCU peripheral is needed. The system can wake up from this power state by an enabled interrupt of the
SBC as well as by an MCU reset generated by the SBC.
Note: For any SBC interrupt source that will wake up the system, the corresponding interrupt source must be
enabled in the SBC, and the ARM® interrupt line 1 (SBC interrupt) must be enabled in the NVIC.
When the system will enter the MCU-DEEP power state from the MCU-ON power state, the software must first
enable the required interrupt sources in the SBC and the MCU and it must set the SLEEPDEEP bit in the ARM®
internal SCR register to 1. Then the software must execute the WFI instruction to enter the MCU-DEEP power
state. When any of the enabled interrupts becomes active, the system returns to the MCU-ON power state and
continues the software execution.
Note: Do not send a power-down command to the SBC in advance.
2.4.4.
LP Power State
The LP power state is the first state where the SBC leaves its FP state. The MCU first enters its DEEPSLEEP
state, but then the SBC stops the MCU clock on the MCU side and disables the high-precision oscillator. For its
ADC operations, the SBC uses the 125kHz clock from the low-power oscillator as the base clock. This power
state is intended for conditions where the SBC will only perform low-power measurements without any operation
by the MCU. The system can wake up from this power state by an enabled interrupt of the SBC as well as by an
MCU reset generated by the SBC.
© 2016 Integrated Device Technology, Inc.
27
January 29, 2016
ZSSC1956 Datasheet
Note: For any SBC interrupt source that will wake up the system, the corresponding interrupt source must be
enabled in the SBC and the ARM® interrupt line 1 (SBC interrupt) must be enabled in the NVIC. The latter is
necessary as the SBC rejects the power-down command when an enabled interrupt source in the SBC is already
active as well as for a final wake up.
When the system will enter the LP power state from the MCU-ON power state, the software must first enable the
required interrupt sources in the SBC and MCU and it must set the SLEEPDEEP bit in the ARM® internal register
SCR to 1. After successful transmission of the corresponding power-down command to the SBC without releasing
the CSN line afterward, the software must then execute the WFI instruction to enter the LP power state. The CSN
line is released by hardware on entering the MCU internal DEEPSLEEP state. The rising edge on the CSN line
triggers the SBC to enter its LP state. When any of the enabled interrupts becomes active, the system returns to
the MCU-ON power state and continues the software execution.
Note: Do not release the CSN line by software at the end of sending a power-down command to avoid the MCU
clock being stopped by SBC at an intermediate state.
2.4.5.
ULP Power State
The ULP power state is similar to the LP state except that the SBC also disables the power for the MCU. The
MCU first enters its DEEPSLEEP state but then the SBC stops the MCU clock on the MCU side and disables the
high-precision oscillator and the voltage regulators for the MCU. For its ADC operations, the SBC uses the 125
kHz clock from the low-power oscillator as its base clock. This power state is intended for conditions where the
SBC will only perform low-power measurements without any operation on the MCU. The system can wake up
from this power state by any enabled interrupt of the SBC. The MCU is reset upon wake up by the SBC to
guarantee correct start up. This means that the software starts again from address 00HEX after wake up, not at the
position where it was stopped.
Note: For any SBC interrupt source that will wake up the system, the corresponding interrupt source must be
enabled in the SBC and the ARM® interrupt line 1 (SBC interrupt) must be enabled in the NVIC. The latter is
necessary as the SBC rejects the power-down command when an enabled interrupt source in the SBC is already
active.
When the system will enter the ULP power state from the MCU-ON power state, the software must first enable the
required interrupt sources in the SBC and MCU and it must set the SLEEPDEEP bit in the ARM® internal register
SCR to 1. After successful transmission of the corresponding power-down command to the SBC without releasing
the CSN line afterward, the software must then execute the WFI instruction to enter the ULP power state. The
CSN line is released by hardware on entering the MCU internal DEEPSLEEP state. The rising edge on the CSN
line triggers the SBC to enter its ULP state. When any of the enabled interrupts becomes active, the system
returns to MCU-ON power state and restarts the software execution.
Note: Do not release the CSN line by software at the end of sending a power-down command to avoid the MCU
clock being stopped by SBC at an intermediate state.
© 2016 Integrated Device Technology, Inc.
28
January 29, 2016
ZSSC1956 Datasheet
2.4.6.
OFF Power State
The OFF state is the state with the lowest power consumption where no measurements can be performed as all
oscillators are stopped. The MCU first enters its DEEPSLEEP state but then the SBC stops the MCU clock on the
MCU side and disables both oscillators and the voltage regulators for the MCU. This power state is intended for
conditions where two measurements will be performed and the system will consume as little power as possible.
The system can wake up from this power state only by receiving a wakeup frame over LIN. The MCU is reset
upon wake up by the SBC to guarantee correct start up. This means that the software starts again from address
00HEX after wake up, not at the position where it was stopped.
Note: For any SBC interrupt source that will wake up the system, the corresponding interrupt source (LIN wakeup
interrupt) must be enabled in the SBC and the ARM® interrupt line 1 (SBC interrupt) must be enabled in the NVIC.
The latter is necessary as the SBC rejects the power-down command when an enabled interrupt source in the
SBC is already active.
When the system will enter the OFF power state from the MCU-ON power state, the software must first enable
the required interrupt sources in the SBC and MCU and it must set the SLEEPDEEP bit in the ARM® internal
register SCR to 1. After successful transmission of the corresponding power-down command to the SBC without
releasing the CSN line afterward, the software must then execute the WFI instruction to enter the OFF power
state. The CSN line is released by hardware on entering the MCU internal DEEPSLEEP state. The rising edge on
the CSN line triggers the SBC to enter its ULP state. When any of the enabled interrupts becomes active, the
system returns to the MCU-ON power state and restarts the software execution.
Note: Do not release the CSN line by software at the end of sending a power-down command to avoid the MCU
clock being stopped by the SBC at an intermediate state.
© 2016 Integrated Device Technology, Inc.
29
January 29, 2016
ZSSC1956 Datasheet
3
Functional Block Descriptions SBC
3.1. SPI Communication between the MCU and SBC
The SBC is fully controllable by the MCU via an integrated four-wire slave SPI interface. It only operates in a
single mode when both the clock polarity and the clock phase are 1 (the clock is high when inactive, data is sent
on the falling SPI clock edge, and data is sampled on the rising SPI clock edge). The accessible registers of the
SBC can be read and/or written via the SPI, and the one-time programmable (OTP) memory in the SBC can be
read via the SPI. Internal status information of the SBC is also returned during the address and length bytes of the
implemented SPI protocol. Read and write burst accesses of up to 128 bytes are supported.
The SPI chip-select line CSN must be low during any transfer until the complete transfer has finished. This is
needed as the CSN input is not only used as an enable signal but also as an asynchronous reset for part of the
SPI front-end. The reason for this is to be able to set the SPI back to a defined state via the MCU as well as to
extract status information without needing to access any register. The CSN input can be kept low between two
transfers. The CSN input must only be driven high for execution of the “go-to-power-down” command after the
required register settings have been completed.
Note: A high level on the CSN input resets the internal SPI state machine.
3.1.1.
SPI Protocol
The SPI slave module only operates with a clock polarity setting of 1 (SCLK is high when no transfer is active; see
CPOL in Table 4.49) and with a clock phase setting of 1 (data is sent on the falling edge; data is sampled on the
rising edge; see CPHA in Table 4.49). For any access, the CSN input must be low. At the end of any read access,
the CSN input can be kept low. For write accesses that change the power mode, the CSN input must be driven
high at the end of the write access; it can be kept low for write accesses to other registers. During an SPI access,
the CSN input must be kept low.
Important: Driving the CSN input high during a read transfer can cause a loss of data.
In each SPI transfer, 1 to 128 bytes can be read or written in one burst access. All bytes are sent and received
with the MSB first. As shown in Figure 3.1, each SPI transfer starts with two bytes sent by the master while the
slave sends back status information in parallel. The first of the two bytes sent by the master is the address byte
containing the first address to be accessed. When multiple bytes are read or written, the received SPI address is
internally incremented for each data byte. The second byte starts with the access type of the transfer (1 = write;
0 = read) followed by the 7-bit length field indicating the number of data bytes that will be read or written. A
special case is the length value of 0, which is interpreted by the slave SPI as 128 bytes.
The status information sent back by the slave during the address and length bytes starts with a fixed value of
AHEX. This can be used to detect whether the connection is still present. The next bits sent are the slave status
word (SSW), which is 12 bits of actual status information.
The 12 SSW bits have the following definitions:
SSW[11]:
Value of the low-voltage flag
SSW[10:8]: Reset status
SSW[7]:
SSW[6]:
SSW[5]:
SSW[4]:
Watchdog active flag
Low-power oscillator trimming circuit active
Voltage/temperature ADC active
Current ADC active
© 2016 Integrated Device Technology, Inc.
30
January 29, 2016
ZSSC1956 Datasheet
SSW[3]:
SSW[2]:
SSW[1]:
SSW[0]:
LIN short protection active
LIN TXD timeout protection active
Readable sleep timer value valid
OTP download procedure active
Note: After the MCU has been reset, the user’s software can read the low-voltage flag and the reset status by a
single-byte transfer (important: send address byte only) to shorten the initialization phase (e.g., when a reset
was caused by a wake-up event) without needing to read or write further bytes including the length byte.
After the address byte and length byte are sent by the master, either the master (write transfer) or the slave (read
transfer) is transmitting data. The slave ignores all incoming bits while it is sending the requested number of data
bytes (read), and the data bytes returned during a write transfer have no meaning. Figure 3.1 shows a read and a
write burst access to the SBC.
Figure 3.1 Read and Write Burst Access to the SBC
Read Access
SCLK
CSN
MOSI
A[7:0]
R
L[6:0]
MISO
SSW[11:0]
D0[7:0]
DL-1[7:0]
Write Access
SCLK
CSN
MOSI
A[7:0]
W
L[6:0]
D0[7:0]
DL-1[7:0]
MISO
SSW[11:0]
Legend:
A: Start address of SPI access
L:
Number of data bytes (0 = 128 bytes)
R: Read access (MSB of second byte is low)
W: Write access (MSB of second byte is high)
SSW: Slave status word
SCLK: SPI clock (SCLK)
© 2016 Integrated Device Technology, Inc.
31
January 29, 2016
ZSSC1956 Datasheet
3.2. SBC Register Map
Table 3.1 defines the registers in the SBC. In the “Access” column, the following abbreviations indicate the
read/write status of the registers: RC = read-clear; RO = read-only; RW = readable and writable; WO = write-only;
W1C = write-one-to-clear. For more details, see the subsequent sections for the individual registers.
Important: There is a distinction between “unused” and “reserved” addresses. No problem occurs when writing to
unused addresses, but writing 00HEX to unused addresses for future expansions is recommended. Reserved
addresses must always be written with the given default value.
Table 3.1 SBC Register Map
Name
irqStat
Address
Order
Default
Access
Short Description
Interrupt status register
00HEX
01HEX
02HEX
03HEX
04HEX
05HEX
06HEX
07HEX
08HEX
09HEX
LSB
MSB
LSB
---
MSB
LSB
---
MSB
LSB
MSB
00HEX
00HEX
00HEX
00HEX
00HEX
00HEX
00HEX
00HEX
00HEX
00HEX
RC
RC
RO
RO
RO
RO
RO
RO
RO
RO
adcCdat
adcVdat
adcRdat
ADC result register of a single current
measurement
ADC result register of a single voltage
measurement
ADC result register of a single temperature
measurement by reading a voltage across the
reference resistor (external temperature
measurement only)
adcTdat
0AHEX
0BHEX
LSB
MSB
00HEX
00HEX
RO
RO
ADC result register of a single temperature
measurement by reading a voltage across the NTC
resistor (external temperature measurement) or a
differential voltage (VPTAT – VBGH; internal
temperature measurement)
adcCaccu
adcVaccu
0CHEX
0DHEX
0EHEX
0FHEX
10HEX
11HEX
12HEX
13HEX
14HEX
15HEX
16HEX
17HEX
18HEX
19HEX
1AHEX
1BHEX
1CHEX
1DHEX
LSB
---
---
MSB
LSB
---
MSB
LSB
MSB
LSB
MSB
LSB
MSB
LSB
MSB
LSB
MSB
---
00HEX
00HEX
00HEX
00HEX
00HEX
00HEX
00HEX
00HEX
80HEX
FFHEX
7FHEX
00HEX
80HEX
FFHEX
7FHEX
00HEX
00HEX
00HEX
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Accumulator register for current measurements
Accumulator register for voltage measurements
adcCmax
adcCmin
adcVmax
adcVmin
adcCrcv
adcCtcv
Maximum current value measured in configured
measurement sequence
Minimum current value measured in configured
measurement sequence
Maximum voltage value measured in configured
measurement sequence
Minimum voltage value measured in configured
measurement sequence
Counter register containing the number of current
measurements
Counter register containing the number of current
measurements greater than or equal to the
threshold
adcVrcv
Unused
1EHEX
1FHEX
---
---
00HEX
00HEX
RO
---
Counter register containing the number of voltage
measurements
---
© 2016 Integrated Device Technology, Inc.
32
January 29, 2016
ZSSC1956 Datasheet
Name
Address
Order
Default
Access
Short Description
Current sleep timer value
sleepTCurCnt
20HEX
21HEX
22HEX - 2FHEX
30HEX
31HEX
32HEX
33HEX
34HEX
35HEX
36HEX
37HEX
38HEX
39HEX
3AHEX
3BHEX
3CHEX
3DHEX
3EHEX
3FHEX
40HEX
41HEX
42HEX
43HEX
44HEX
LSB
MSB
---
LSB
---
MSB
LSB
---
MSB
LSB
---
00HEX
00HEX
00HEX
00HEX
00HEX
80HEX
00HEX
00HEX
00HEX
00HEX
00HEX
80HEX
00HEX
00HEX
00HEX
00HEX
80HEX
00HEX
00HEX
00HEX
00HEX
00HEX
00HEX
00HEX
RO
RO
---
Unused
adcCgan
---
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Digital gain correction for current channel
Digital offset correction for current channel
Digital gain correction for voltage channel
Digital offset correction for voltage channel
adcCoff
adcVgan
adcVoff
MSB
LSB
---
MSB
LSB
MSB
LSB
MSB
LSB
MSB
LSB
MSB
---
adcTgan
adcToff
adcCrcl
adcCrth
adcCtcl
Digital gain correction for temperature channel
Digital offset correction for temperature channel
Number of current measurements before ready
strobe is generated
Absolute current value is compared to this
threshold in Current Threshold Comparator Mode
Number of current measurements greater than or
equal to the threshold before “set interrupt” strobe
is generated
adcVrcl
45HEX
---
00HEX
RW
Number of voltage measurements before ready
strobe is generated
adcVth
46HEX
47HEX
48HEX
49HEX
4AHEX
4BHEX
4CHEX
4DHEX
4EHEX
4FHEX
50HEX
LSB
MSB
LSB
---
---
MSB
---
00HEX
00HEX
00HEX
00HEX
00HEX
00HEX
00HEX
00HEX
30HEX
00HEX
10HEX
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Voltage threshold level for Threshold Comparator
(unsigned) or Accumulator (signed) Modes
Accumulator threshold for current channel
adcCaccth
adcTmax
adcTmin
adcAcmp
Upper threshold for temperature measurement
Lower threshold for temperature measurement
ADC function enable register
---
LSB
MSB
---
adcGomd
Reference voltage and sigma-delta modulator
(SDM) configuration
adcSamp
adcGain
pwrCfgFp
irqEna
51HEX
52HEX
53HEX
54HEX
55HEX
---
---
---
LSB
MSB
---
---
---
---
00HEX
00HEX
00HEX
00HEX
00HEX
00HEX
00HEX
00HEX
00HEX
RW
RW
RW
RW
RW
RW
RW
---
Oversampling and filter configuration
Control register for analog amplifiers
Power configuration register for full-power state
Interrupt enable register
adcCtrl
adcPoCoGain
Unused
discCvtCnt
56HEX
57HEX
ADC control register for full-power (FP) state
Post-correction gain configuration
---
Configuration register for some of the power-down
states
58HEX - 5EHEX
5FHEX
RW
sleepTAdcCmp
60HEX
61HEX
LSB
MSB
00HEX
00HEX
RW
RW
Compare value for ADC trigger timer
© 2016 Integrated Device Technology, Inc.
33
January 29, 2016
ZSSC1956 Datasheet
Name
Address
Order
Default
Access
Short Description
Compare value for sleep timer
sleepTCmp
62HEX
63HEX
64HEX
LSB
MSB
---
00HEX
00HEX
20HEX
RW
RW
RW
pwrCfgLp
Power configuration register for power-down
modes
gotoPd
Unused
cmdExe
Unused
65HEX
66HEX - 67HEX
68HEX
---
---
---
---
00HEX
00HEX
02HEX
00HEX
WO
---
Power-down entrance register
---
WO / RW Command execution register
69HEX
-
---
---
6FHEX
70HEX
71HEX
72HEX
73HEX
wdogCnt
LSB
MSB
LSB
MSB
---
FFHEX
FFHEX
FFHEX
FFHEX
09HEX
00HEX
00HEX
00HEX
52HEX
04HEX
RO
RO
RW
RW
RW
---
RO
RO
RW
RW
Current watchdog counter value
Preset value for watchdog counter
wdogPresetVal
wdogCfg
Unused
lpOscTrimCnt
74HEX
Configuration register for watchdog counter
---
Result counter of low-power oscillator trim circuit
75HEX - 77HEX
78HEX
---
LSB
MSB
---
79HEX
7AHEX
7BHEX
irefLpOsc
lpOscTrim
Trim value for low-power oscillator
Configuration register for trim circuit of low-power
---
oscillator
Unused
7CHEX
7FHEX
80HEX
-
---
00HEX
---
---
swRst
Unused
---
---
00HEX
00HEX
WO
---
Software reset
---
81HEX -
AFHEX
B0HEX
B1HEX
B2HEX
B3HEX
sdmClkCfgLp
sdmClkCfgFp
LSB
MSB
LSB
MSB
18HEX
00HEX
08HEX
90HEX
RW
RW
RW
RW
RW /
W1C
RW
RW
RW
RW
RW
RO
Clock configuration for SDM clock in power-down
state
Clock configuration for SDM clock in full-power
state
linCfg
B4HEX
---
00HEX
Configuration register for LIN control logic
linShortFilter
linShortDelay
linWuDelay
pullResEna
funcDis
B5HEX
B6HEX
B7HEX
B8HEX
B9HEX
BAHEX
BBHEX
BCHEX
BFHEX
C0HEX
C1HEX
C2HEX
C3HEX
C4HEX
C5HEX
C6HEX
C7HEX
C8HEX
C9HEX
---
---
---
---
---
LSB
MSB
---
0FHEX
4FHEX
14HEX
FFHEX
00HEX
00HEX
03HEX
00HEX
Configuration for LIN short de-bounce filter
Configuration for LIN short TX-RX delay
Configuration for LIN wake-up time
Configuration register for pull-down resistors
Disable bits for dedicated functions
Version code
versionCode
RO
---
Unused
-
---
pwrTrim
irefOsc
---
LSB
MSB
---
---
---
---
---
---
---
7CHEX
10HEX
40HEX
10HEX
00HEX
00HEX
00HEX
00HEX
00HEX
00HEX
08HEX
00HEX
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Trim bits for voltage regulators and bandgap
Trim values for high-precision oscillator
ibiasLinTrim
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Bias current trim register for LIN block
---
---
---
---
---
---
---
---
CAHEX
CBHEX
---
---
© 2016 Integrated Device Technology, Inc.
34
January 29, 2016
ZSSC1956 Datasheet
Name
Reserved
Reserved
Reserved
Reserved
adcChan
Address
Order
Default
Access
Short Description
CCHEX
CDHEX
CEHEX
CFHEX
D0HEX
---
---
---
---
---
00HEX
00HEX
00HEX
00HEX
00HEX
RW
RW
RW
RW
RW
---
---
---
---
Analog multiplexer configuration during test/
diagnosis
adcDiag
D1HEX
D2HEX
D3HEX
D4HEX
D5HEX
D6HEX
D7HEX
D8HEX
D9HEX
DAHEX
DBHEX
DCHEX
DDHEX
DEHEX
DFHEX
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
80HEX
00HEX
00HEX
00HEX
00HEX
00HEX
00HEX
00HEX
00HEX
B8HEX
00HEX
00HEX
00HEX
00HEX
00HEX
---
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RO
Enable register for test/diagnosis
Enable register for current sources
---
---
---
---
---
---
---
---
---
---
---
---
---
currentSrcEna
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
OTP
E0HEX - FFHEX
OTP raw data
3.3. SBC Clock and Reset Logic
3.3.1.
Clocks
The SBC contains two different oscillators, a low-power oscillator (LP oscillator) providing a clock of 125kHz with
an accuracy of +/- 3% and a high-precision oscillator (HP oscillator) providing a clock of 20MHz with an accuracy
of +/- 1%. The low-power oscillator is always active except in the OFF state while the high-precision oscillator is
only active in the SBC’s full-power (FP) state. The clock from the high-precision oscillator is routed to the MCU via
the internal MCU_CLK node (see Figure 2.3).
Three different internal clocks are generated from the two clocks from the oscillators for the digital core of the
SBC:
•
•
Low-power clock (lpClk): This clock is directly driven by the low-power oscillator and has a frequency of
125kHz. It is used for the watchdog timer, the sleep timer, and the power management unit.
Divided clock (divClk): This clock is derived from the high-precision oscillator and has a frequency of
4MHz. It is used for the register file, the low-power oscillator trimming circuit, the LIN support logic, and
the OTP controller.
•
Multiplexed clock (muxClk): This clock is identically to the divClk in the full-power (FP) state and
identically to lpClk in the LP and ULP states. It is used for the ADC controller unit and the interrupt
controller.
© 2016 Integrated Device Technology, Inc.
35
January 29, 2016
ZSSC1956 Datasheet
Both oscillators are trimmed during the production test, and the trim values are stored in the OTP memory
(IREF_OSC_0, IREF_OSC_1, IREF_OSC_2, IREF_OSC_3, IREF_LP_OSC; see Table 3.67). As it is
important for correct operation of the MCU that the clock from the high-precision oscillator has the correct
frequency, the two trimming values for the high-precision oscillator are protected by redundancy in the OTP.
Software can check the validity of the trim values and the redundancy bits by reading the OTP raw data directly
from the OTP via the SPI.
Note: The trimming values for both oscillators should also be stored in the MCU so that software is able to check
the validity of the trimming values. On detection of errors in the OTP, software can write the correct values via
SPI.
3.3.2.
Trimming the Low-Power Oscillator
As the clock from the low-power oscillator is less accurate than the clock from the high-precision oscillator, a
trimming circuit is implemented that trims the low-power oscillator using the divided clock divClk. There are two
options for trimming the low-power oscillator. One option is to allow the hardware to update the trim value for the
low-power oscillator automatically so that no user interference is necessary. For this, the user only needs to set
the lpOscTrimEna and lpOscTrimUpd bits to 1 as well as setting the lpOscTrimCfg field as needed (see
Table 3.4). The latter configuration value defines how many low-power clock periods are used for frequency
calculation. While the trimming circuit is faster when fewer periods are used, the result of the frequency
calculation is more accurate when more periods are used. In the first part of the trimming loop, the circuit
determines the frequency of the low-power oscillator. When the measured frequency is too low, the hardware
increments the trim value by 1; if it is too high, the hardware decrements the trim value by 1. Otherwise, the trim
value remains unchanged. After changing the trim value, the hardware measures the (new) frequency. This
algorithm is only stopped when software clears the lpOscTrimEnabit (trimming logic stops after a final update)
or when any low-power state is entered.
The second option is to use the trim circuit only to measure the frequency but to update the trim value by
software. This can be preferable when the target frequency is not equal to 125 kHz. For this, the user only needs
to set the lpOscTrimEnabit to 1 and set the lpOscTrimUpdbit to 0 as well as setting the lpOscTrimCfgfield
as needed. Next, the user must clear the lpOscTrimEnabit without changing the other values in the register and
must wait until the hardware has finished before calculating the frequency (wait until SSW[6]is 0). By reading the
lpOscTrimCnt register, the user can calculate the actual frequency of the low-power oscillator using the
following formula:
fHP
fLP
=
⋅ 2lpOscTrimCfg+2
fHP = 4MHz
(1)
lpOscTrimcnt + 1
After determining the actual frequency, the user can change the trim value for the low-power oscillator
lpOscTrimValas required (see Table 3.3) and re-enable the trimming circuit to check the new frequency.
Note: The trimming circuit can be kept active when going to any low-power state. The PMU interrupts the
trimming circuit on transition to the low-power state and restarts it after wakeup. This is needed as divClk is
stopped in any low-power state.
© 2016 Integrated Device Technology, Inc.
36
January 29, 2016
ZSSC1956 Datasheet
3.3.3.
Clock Trimming and Configuration Registers
3.3.3.1. Register “irefOsc” – Trim Values for the High-Precision Oscillator
Table 3.2 Register irefOsc
Name
Address
Bits
Default
Access
Description
irefTcOscTrim
[4:0]
10000BIN
RW
Trim value to minimize the temperature coefficient of
the high-precision oscillator.
Note: This value is automatically updated by the OTP
controller after an SBC reset.
C1HEX
Unused
irefOscTrim[0]
[6:5]
[7]
00BIN
0BIN
RO
RW
Unused; always write as 0.
Trim value for the high-precision oscillator.
The frequency of the high-precision oscillator
increases (decreases) when this value is incremented
(decremented).
irefOscTrim[8:1]
C2HEX
[7:0]
40HEX
RW
Note: This value is automatically updated by the OTP
controller after an SBC reset.
3.3.3.2. Register “irefLpOsc” – Trim Value for the Low-power Oscillator
Table 3.3 Register irefLpOsc
Name
Address
Bits
Default
Access
Description
lpOscTrimVal
[6:0] 101 0010BIN
RW
Trim value for the low-power oscillator. The frequency
of the low-power oscillator increases (decreases) when
this value is incremented (decremented).
7AHEX
Note: This value is automatically updated by the OTP
controller after an SBC reset.
Unused
[7]
0BIN
RO
Unused; always write as 0.
© 2016 Integrated Device Technology, Inc.
37
January 29, 2016
ZSSC1956 Datasheet
3.3.3.3. Register “lpOscTrim” – Configuration Register for the Low-Power Oscillator Trimming Circuit
Table 3.4 Register lpOscTrim
Name
Address
Bits
Default
Access
Description
lpOscTrimEna
[0]
0BIN
RW
If set to 1, enables the low-power oscillator trimming
circuit.
Note: When the user disables the trimming feature, the
trimming logic continues its operation until it has
finished the current calculation and then stops. The
user can check that the trimming circuit has stopped by
evaluating SSW[6], which is 0 when the trimming circuit
is inactive.
lpOscTrimUpd
lpOscTrimCfg
[1]
0BIN
RW
RW
Update bit for the low-power oscillator trimming circuit.
When set to 1, the trimming circuit is allowed to update
register lpOscTrimVal. When set to 0, no hardware
update is performed.
7BHEX
Note: Do not change while trimming circuit is active.
[3:2]
01BIN
This value selects the number of clock periods of the
low-power oscillator to be used to determine the
frequency.
0
1
2
3
4 clock periods
8 clock periods
16 clock periods
32 clock periods
Note: Do not change while trimming circuit is active.
Unused
[7:3]
00000BIN
RO
Unused; always write as 0.
3.3.3.4. Register “lpOscTrimCnt” – Result Counter of the Low-Power Oscillator Trimming Circuit
Table 3.5 Register lpOscTrimCnt
Name
Address
Bits
Default
Access
Description
lpOscTrimCnt[7:0]
[7:0]
00HEX
RO
Result counter of the low-power oscillator trimming
circuit. This value will only be read when the trimming
circuit is inactive (SSW[6] == 0).
78HEX
lpOscTrimCnt[10:8]
Unused
[2:0]
[7:3]
000BIN
00000BIN
RO
RO
79HEX
Unused; always write as 0.
© 2016 Integrated Device Technology, Inc.
38
January 29, 2016
ZSSC1956 Datasheet
3.3.4.
Resets
The main reset source is the integrated power-on-reset cell, which resets the complete digital core of the SBC
when VDDE drops below 3.0V (typical). There are three other reset sources that reset the complete digital core of
the SBC, except the watchdog timer and its configuration registers.
These additional reset sources are
•
Watchdog reset: This reset occurs when the active watchdog timer expires without being handled by
software.
•
•
Software reset: This reset can be generated by the user by writing the value A9HEX to register swRst.
PMU error reset: This reset occurs if the power management unit goes into an invalid state (e.g., due to
cosmic radiation).
If any of these four resets occurs, the power-on procedure is executed, which powers up the required analog
blocks and starts the download procedure for the OTP. This download procedure transfers the OTP contents into
the appropriate registers if the OTP content is valid. The MCU_RSTN pin is also driven low, resetting the
connected MCU. The MCU reset is released after the power-up procedure has finished.
The MCU is also reset when the system goes to OFF or ULP state because the power supply of the MCU is
disabled in these power-down states. In this case, the MCU reset is released after a wake-up event has occurred
and the MCU power supplies have stabilized.
Another possible reset source for the MCU is VddpReset, which is also generated by the power-on-reset cell
when VDDE drops below 4.05V (typical). In this case, it cannot be guaranteed that VDDP, which is needed for
correct operation of the MCU, is still valid if VDDP is trimmed to a high level of 3.3V.
The digital core of the SBC observes the input from the power-on-reset cell and generates the MCU reset only
when all of the following conditions are true:
•
•
•
VDDP is trimmed to 3.3V (bit vddpTrimof register pwrTrimset to 1).
The ZSSC1956 system is in the full-power (FP) state, and the MCU is clocked.
VDDP reset is not disabled (bit disVddpRstof register funcDisis set to 0; see Table 3.8).
3.3.4.1. The Reset Status
The MCU can easily check the reason for being reset by a single byte transfer to the SBC (SPI address byte only)
and evaluating SSW[10:8] which contains the reason for the last reset (reset status). This value can be
evaluated by the software for different actions after reset:
Reset status 0: In this case, the reset was generated by the power-on-reset cell. Both SBC and MCU are
reset completely.
Reset status 1: The watchdog timer was not handled and has expired (see section 3.4). The MCU and all
SBC logic are reset, except the watchdog timer and its configuration registers.
Reset status 2: Only the MCU is reset due to a wakeup from the ULP or OFF state.
Reset status 3: The software has forced a reset. The MCU and all SBC logic are reset, except the watchdog
timer and its configuration registers.
Reset status 4: VDDP has dropped below 3.3V, and MCU was active. Only the MCU is reset.
Reset status 5: The PMU is in an illegal state. The MCU and all SBC logic are reset, except the watchdog
timer and its configuration registers.
© 2016 Integrated Device Technology, Inc.
39
January 29, 2016
ZSSC1956 Datasheet
3.3.4.2. The Low-Voltage Flag
The low-voltage flag is part of the analog block. After power-on-reset, it has a low level. It can be set by software
by writing the value 1 to bit lvfSetin register cmdExe. It is cleared by the power-on-reset cell when VDDE drops
below 1.9V (typical). When VDDE drops below this threshold, it cannot be guaranteed that VDDL, which is used
as the power supply for the RAM in the MCU, was high enough to guarantee the validity of the RAM contents.
The low-voltage flag is mapped to SSW[11]where software can read its value.
3.3.4.3. Register “swRst” – Software Reset
Table 3.6 Register swRst
Name
Address
Bits
Default
Access
Description
swRst
80HEX
[7:0]
00HEX
WO
Writing A9HEX to this register forces a software reset,
which resets the MCU as well as the SBC digital core
except the watchdog timer and its configuration registers.
Always reads as 0.
3.3.4.4. Register “cmdExe” – Triggering Command Execution by Software
Table 3.7 Register cmdExe
Name
wdogClr
Address
Bits
Default
Access
Description
[0]
0BIN
RW
Writing 1 to this bit clears the watchdog timer. This bit is
cleared by hardware after the watchdog is cleared. As
long as the clear procedure is active, any further writes to
this bit are rejected.
otpDownload
lvfSet
[1]
[2]
1BIN
0BIN
WO
WO
RO
Strobe register; write 1 to start the download procedure
from the OTP; always reads as 0.
Strobe register; write 1 to set the low-voltage flag; always
reads as 0.
68HEX
Unused
[7:3]
00000BIN
Unused; always write as 0.
3.3.4.5. Register “funcDis” – Disabling VDDP Reset and STO Output Pin
Table 3.8 Register funcDis
Name
Address
Bits
Default
Access
Description
disVddpRst
disStoOut
[0]
[1]
0BIN
0BIN
RW
RW
When set to 1, VddpReset does not reset the MCU.
When set to 1, the output driver of the STO pin is
disabled.
B9HEX
Unused
[7:2]
000000BIN
RO
Unused; always write as 0.
© 2016 Integrated Device Technology, Inc.
40
January 29, 2016
ZSSC1956 Datasheet
3.4. SBC Watchdog Timer
The SBC contains a configurable watchdog timer (down counter) for the ZSSC1956 when it is running using the
clock from the low-power oscillator. It is used to recover from an invalid software or hardware state. To avoid a
reset of the system, the watchdog must be periodically serviced. The only part of the system that will not be reset
by the watchdog reset is the watchdog itself and its configuration registers.
Figure 3.2 Structure of the Watchdog Timer
Configurable
Prescaler
1 : 1
1 : 125
1 : 1250
1 : 12500
wdogCnt (register file)
wdIrq (IRQ ctrl)
lpClk
(125 kHz)
16-Bit Down
Counter
==
0?
wdogPrescaleCfg
(register file)
set
&
&
wdogIrqFuncEna (register file)
wdRst (RstCtrl)
set
O
R
By default, the watchdog timer is active starting with a counter value of FFFFHEX and a prescaler of 125. This is
done to guarantee that the boot code of the MCU has enough time to finish. During the initialization phase of the
system, software can disable, reconfigure, and restart the watchdog. Disabling the watchdog before configuration
is required as all write accesses to the register wdogPresetVal and the register wdogCfg except the bits
wdogLock and wdogEna (see Table 3.12) are blocked when the watchdog is active. As it takes multiple low-
power clock cycles until the enable signal is evaluated in the watchdog clock domain, the SSW[7]bit (wdActive)
must be checked to determine if write accesses are possible. To avoid any malfunction during reconfiguration, the
prescaler bit fields are set to 0 and the counter register is set to FFFFHEX at disable.
When the watchdog is disabled, configuration is possible. The register wdogPresetVal contains the value that
will be copied into the down counter in the first enable cycle or when the watchdog timer is serviced via the
wdogClrbit in register cmdExe. The field wdogPrescaleCfgin register wdogCfgconfigures the prescaler. The
resolution and maximum timeout for the watchdog depend on the configuration as shown in Table 3.9.
Table 3.9 Resolution and Maximum Timeout for Prescaler Configurations
wdogPrescaleCfg Setting
Prescaler Configuration
Resolution
8 µs
Maximum Timeout
524 ms
0
1
2
3
1:1
1:125
1 ms
10 ms
100 ms
65.5 s
1:1250
1:12500
655.3 s
6553.5 s
© 2016 Integrated Device Technology, Inc.
41
January 29, 2016
ZSSC1956 Datasheet
As the maximum timeout value might still be too small for some applications, the user can use the wdogPmDisbit
in register wdogCfgto select whether the watchdog timer will be halted during any power-down state (bit set to 1)
or not (bit set to 0).
It is also possible to use the watchdog timer as a wake-up source. When the wdogIrqFuncEna bit in register
wdogCfg is set to 1 and the down counter reaches 0, an interrupt is generated instead of a reset which would
wake up the system and the down counter reloads the preset value and continues its operation. When the
watchdog timer expires for a second time without service, the watchdog reset is generated. If the
wdogIrqFuncEnabit is set to 0, the reset is already generated when the timer expires for the first time.
After reconfiguration, the watchdog timer is re-enabled. To avoid further (accidental) changes to the watchdog
timer configuration registers, the user can set the wdogLockbit in register wdogCfgto 1. If this bit is set, all write
accesses are blocked. The wdogLockbit can only be cleared by a power-on reset.
When a debugger is connected to the system (SBC input DBGEN is 1), the watchdog timer is immediately halted
as handling of the watchdog via the debugger might be too slow; however, the watchdog timer can still be
serviced via the wdogClrbit in register cmdExe(see Table 3.7).
To perform the required periodic servicing of the watchdog timer, the user must write the value 1 to the wdogClr
bit in register cmdExe. To avoid any malfunction if the watchdog is serviced too often, any consecutive write
accesses to the wdogClrbit are blocked until the first clear process has finished.
Important: The preset value programmed to the wdogPresetVal register must never be 00HEX as this would
immediately cause a reset forcing the system into a dead lock. It is strongly recommended that software checks
the programmed reload value before re-enabling the watchdog.
Important: The preset value must not be too small. The user must take into account critical system timings
including power-up times and flash programming/erasing times.
Note: The reconfiguration of the registers wdogPresetVal and wdogCfg, including bits wdogEna and
wdogLock,can be performed in a single SPI burst write access.
© 2016 Integrated Device Technology, Inc.
42
January 29, 2016
ZSSC1956 Datasheet
3.4.1.
Watchdog Registers
3.4.1.1. Register “wdogPresetVal” – Preset Value for the Watchdog Timer
Table 3.10 Register wdogPresetVal
Name
Address
Bits
Default
Access
Description
Lower byte of the preset value of the watchdog timer.
This value is loaded into the lower byte of the
watchdog counter when the watchdog is enabled or
when the watchdog is cleared.
wdogPresetVal[7:0]
72HEX
[7:0]
FFHEX
RW
Note: This bit can only be written when the watchdog
is not locked (wdogLock== 0) and when the
watchdog is inactive (SSW[7] == 0).
Upper byte of the preset value of the watchdog timer.
This value is loaded into the upper byte of the
watchdog counter when the watchdog is enabled or
when the watchdog is cleared.
wdogPresetVal[15:8]
73HEX
[7:0]
FFHEX
RW
Note: This bit can only be written when the watchdog
is not locked (wdogLock== 0) and when the
watchdog is inactive (SSW[7] == 0).
3.4.1.2. Register “wdogCnt” – Present Value of Watchdog Timer
Table 3.11 Register wdogCnt
Name
Address
Bits
Default
Access
Description
wdogCnt[7:0]
wdogCnt[15:8]
70HEX
71HEX
[7:0]
[7:0]
00HEX
00HEX
RO
RO
Lower byte of present watchdog timer value.
Upper byte of present watchdog timer value.
© 2016 Integrated Device Technology, Inc.
43
January 29, 2016
ZSSC1956 Datasheet
3.4.1.3. Register “wdogCfg” – Watchdog Timer Configuration Register
Table 3.12 Register wdogCfg
Name
Address
Bits
Default
Access
Description
wdogEna
Global enable bit for the watchdog timer.
Note: This bit can only be written when the watchdog is
not locked (wdogLock== 0).
[0]
1BIN
RW
wdogPmDis
When this bit is set to 1, PMU stops the watchdog during
any power-down state.
Note: This bit can only be written when the watchdog is
not locked (wdogLock== 0).
[1]
[2]
0BIN
RW
RW
wdogIrqFuncEna
When this bit is set to 1, the watchdog reloads the preset
value when expiring for the first time and generates an
interrupt instead of a reset. A reset will always be
generated when the watchdog timer expires for the
second time.
0BIN
Note: This bit can only be written when the watchdog is
not locked (wdogLock == 0) and when the watchdog is
inactive (SSW[7] == 0).
74HEX
wdogPrescaleCfg
Prescaler configuration:
0
1
2
3
No prescaler active
Prescaler of 125 is active
Prescaler of 1250 is active
Prescaler of 12500 is active
[4:3]
01BIN
RW
Note: This bit can only be written when the watchdog is
not locked (wdogLock== 0) and when the watchdog is
inactive (SSW[7] == 0).
See Table 3.9 for timing details.
Unused
wdogLock
[6:5]
7
00BIN
0BIN
RO
Unused; always write as 0
When this bit is set to 1, all write accesses to the other
bits of this register as well as to the wdogPresetVal
registers are ignored. This bit can only be written to 1
and is only cleared by a power-on reset.
RWS
3.5. SBC Sleep Timer
The integrated sleep timer (up counter) is only active when the system is in any low-power state and it is running
with the 125 kHz clock from the low-power oscillator.
The sleep timer consists of three blocks as illustrated in Figure 3.3:
•
•
•
A fixed prescaler that divides the incoming 125 kHz clock from the low-power oscillator by 12500 to get a
timer resolution of 10 Hz.
A 16-bit counter that generates an interrupt (signal: stIrq) when the timer reaches the programmed
compare value sleepTCmp(see Table 3.14).
A 12-bit counter that triggers the PMU (with signal stAdcTrigger) when the timer reaches the programmed
compare value sleepTAdcCmpto power-up the ADC blocks and to perform measurements if one of the
discrete measurement scenarios are configured (see Table 3.13).
© 2016 Integrated Device Technology, Inc.
44
January 29, 2016
ZSSC1956 Datasheet
Figure 3.3 Structure of the Sleep Timer
sleepTCmp (register file)
stIrq (IRQ ctrl)
16-Bit
Counter
==
?
sleepTCurCnt (register file)
stAdcTrigger (PMU)
lpClk
(125 kHz)
Prescaler
1 : 12500
cntClk
(10 Hz)
12-Bit
Counter
==
?
sleepTAdcCmp (register file)
When the system goes from full-power to any power-down state on request by the user, the prescaler and both
counters are cleared and the 16-bit counter is enabled. Every 100 ms, triggered by the prescaler, the 16-bit
counter is incremented until it reaches the programmed compare value sleepTCmp. When the compare value is
reached, the timer stops and the interrupt controller is triggered to set the corresponding interrupt status flag (see
section 3.6.1.1). The sleep timer is also stopped when the system returns to the full-power (FP) state. The user
can determine the sleep duration by reading the register sleepTCurCnt, which returns the value of the 16-bit
counter.
Note: Although the timer stops and the interrupt status bit is set when the compare value is reached, the system
remains in the power-down state if the corresponding interrupt (bit 1 in irqEna register; see Table 3.17) is not
enabled to drive the interrupt line IRQN.
Equation (2) can be used to determine the correct sleep time to be programmed. The sleep timer expires after
100ms for a compare value of 0, after 200ms for a compare value of 1, and so on.
Sleep Time = 100ms∗
(
sleepTCmp +1
)
(2)
The 12-bit counter that triggers the PMU is only enabled during any power-down state when any discrete
measurement scenario is configured. In this case, the counter is incremented each 100ms triggered by the
prescaler. When the counter reaches the programmed compare value sleepTAdcCmp, a strobe for the PMU is
generated and the 12-bit counter is reset to 0. Then it continues its operation. This counter is only stopped when
the system returns to the full-power state, but it continues to operate when the sleep timer has expired if it was not
enabled to wake up the system.
Equation (3) can be used to determine the correct ADC trigger time to be programmed. The ADC trigger timer
expires after 100ms for a compare value of 0, after 200ms for a compare value of 1, and so on.
In general,
ADC Trigger Time = 100ms∗
(
sleepTAdcCmp +1
)
(3)
Important: When both the sleep timer for wake-up and the ADC trigger timer for discrete measurements are
used, special care must be taken when programming the compare values because when the sleep timer expires,
the wake-up condition has higher priority over an active ADC measurement or an ADC trigger strobe.
© 2016 Integrated Device Technology, Inc.
45
January 29, 2016
ZSSC1956 Datasheet
3.5.1.
Sleep Timer Registers
3.5.1.1. Register “sleepTAdcCmp” – Compare Value for ADC Trigger Timer
Table 3.13 Register sleepTAdcCmp
Name
Addr
Bits
Default
Access
Description
Lower byte of compare value for the ADC trigger timer;
the ADC trigger timer is only active if the system is in LP
or ULP state and any discrete measurement scenario is
configured generating periodic strobes for the PMU.
sleepTAdcCmp[7:0]
60HEX
[7:0]
00HEX
RW
ADC trigger time = 100 ms * (sleepTAdcCmp+ 1)
Upper byte of compare value for ADC trigger timer; ADC
trigger timer is only active when the system is in LP or
ULP state and any discrete measurement scenario is
configured generating periodic strobes for the PMU.
sleepTAdcCmp[15:8]
61HEX
[7:0]
00HEX
RW
ADC trigger time = 100 ms * (sleepTAdcCmp+ 1)
3.5.1.2. Register “sleepTCmp” – Compare Value for Sleep Timer
Table 3.14 Register sleepTCmp
Name
Addr
Bits
Default
Access
Description
sleepTCmp[7:0]
62HEX
[7:0]
00HEX
RW
Lower byte of compare value for sleep timer; sleep timer is
only active if the system is in LP or ULP state.
Sleep time = 100 ms * (sleepTCmp+ 1)
sleepTCmp[15:8]
63HEX
[7:0]
00HEX
RW
Upper byte of compare value for sleep timer; sleep timer is
only active when the system is in LP or ULP state.
Sleep time = 100 ms * (sleepTCmp+ 1)
© 2016 Integrated Device Technology, Inc.
46
January 29, 2016
ZSSC1956 Datasheet
3.5.1.3. Register “sleepTCurCnt” – Current Value of Sleep Timer
Table 3.15 Register sleepTCurCnt
Name
Addr
Bits
Default
Access
Description
sleepTCurCnt[7:0]
20HEX
[7:0]
00HEX
RO
Lower byte of the current sleep timer value. Since the timer
is stopped in full-power (FP) state, the duration of the last
power-down state can be determined:
Sleep time = 100 ms * (sleepTCurCnt + 1)
Note: value is only valid when SSW[1] (sleep timer valid
stValid) is set.
sleepTCurCnt[15:8]
21HEX
[7:0]
00HEX
RO
Upper byte of the current sleep timer value. Since the timer
is stopped in full-power (FP) state, the duration of the last
power-down state can be determined:
Sleep time = 100 ms * (sleepTCurCnt + 1)
Note: value is only valid when SSW[1] (stValid) is set.
3.6. SBC Interrupt Controller
There are 16 different interrupt sources in the SBC system, each having a dedicated interrupt status bit in the
irqStat register (Table 3.16) and a dedicated interrupt enable bit in the irqEna register (see Table 3.17). The
interrupt controller captures each interrupt source in the interrupt status register independently of the interrupt
enable settings. The interrupt controller combines all enabled interrupt status bits into the low-active interrupt
signal that is used to drive the interrupt pin IRQN of the SBC and to wake up the system by the PMU. This means
that interrupt status bits, which can always be set even when disabled, can only generate a wake-up event and
drive the interrupt pin IRQN when they are enabled.
Figure 3.4 Generation of Interrupt and Wake-up
irqStat[0]
&
irqEna[0]
.
.
.
IRQN
O
R
irqStat[15]
wake-up
(PMU)
&
irqEna[15]
© 2016 Integrated Device Technology, Inc.
47
January 29, 2016
ZSSC1956 Datasheet
The user can determine the interrupt reason by reading the interrupt status register. The interrupt status register
is cleared on each read access. Therefore software must ensure that it stores the read interrupt status value if
needed to avoid loss of information.
3.6.1.1. Interrupt Sources
The bit mapping is the same for the interrupt enable register irqEna and the interrupt status register irqStat:
•
•
•
•
•
•
Bit 0: Watchdog Timer Interrupt; status is set by the watchdog timer when the interrupt functionality
of the watchdog timer is enabled and the watchdog timer expires for the first time.
Bit 1: Sleep Timer Interrupt; status is set by the sleep timer when the sleep timer reaches the
programmed compare value.
Bit 2: LIN TXD Timeout Interrupt; status is set by the LIN support logic when the TXD input from the
MCU is low for more than 10.24 ms.
Bit 3: LIN Short Interrupt; status is set by the LIN support logic when a short is detected in the LIN
PHY.
Bit 4: LIN Wakeup Interrupt; status is set by the LIN support logic when a wake-up frame is detected
on the LIN bus.
Bit 5: Current Conversion Result Ready Interrupt; status is set by the ADC unit when a single
current measurement (register adcCrcl == 0) or multiple current measurements defined by
adcCrcl(register adcCrcl!= 0) have been completed and the result is available.
Bit 6: Voltage Conversion Result Ready Interrupt; status is set by the ADC unit when a single
voltage measurement (register adcVrcl== 0) or multiple voltage measurements defined by the
adcVrcl(register adcVrcl!= 0) have been completed and the result is available.
Bit 7: Temperature Conversion Result Ready Interrupt; status is set by the ADC unit when a single
temperature measurement has been completed and the result is available.
Bit 8: Current Comparator Interrupt; status is set by the ADC unit when the Current Threshold
Counter Mode is enabled (register adcAcmp[2:1] != 0) and the absolute value of multiple
(defined by register adcCtcl) current measurements exceeds the programmed current
threshold (register adcCrth).
•
•
•
Note: If the Current Threshold Counter Mode is enabled but adcCtclis 0, this bit is always set
independently of the threshold.
•
•
•
Bit 9: Voltage Comparator Interrupt; status is set by the ADC unit if the VThWuEnabit (adcAcmp[8])
is set to 1 and a single measured voltage or the accumulated voltage measurements (depends
on configured mode) drop below the programmed (register adcVTh) voltage threshold.
Bit 10: Temperature Threshold Interrupt; status is set by the ADC unit when the TWuEna bit
(adcAcmp[10]) is set to 1 and a temperature measurement is outside the specified temperature
interval defined by registers adcTminand adcTmax.
Bit 11: Current Accumulator Threshold Interrupt; status is set by the ADC unit when the
CAccuThEna bit (adcAcmp[3]) is set to 1 and the accumulated current values rise above the
programmed threshold value (register adcCaccTh) for a positive threshold value or fall below
the programmed threshold value for the negative threshold value.
•
•
Bit 12: Current Overflow Interrupt; status is set by the ADC unit when the COvrEnabit (adcAcmp[4])
is set to 1 and the compensated value of a current measurement is outside of the representable
range.
Bit 13: Voltage / Temperature Overflow Interrupt; status is set by the ADC unit when the VTOvrEna
bit (adcAcmp[5]) is set to 1 and the compensated value of a voltage or temperature
measurement is outside of the representable range.
© 2016 Integrated Device Technology, Inc.
48
January 29, 2016
ZSSC1956 Datasheet
•
•
Bit 14: Current Over-Range Interrupt; status is set by the ADC unit when the COvrEna bit
(adcAcmp[4]) is set to 1 and the input from the current ADC is overdriven.
Bit 15: Voltage / Temperature Over-Range Interrupt; status is set by the ADC unit when the
VTOvrEna bit (adcAcmp[5]) is set to 1 and the input from the voltage / temperature ADC is
overdriven.
3.6.1.2. Register “irqStat” – Interrupt Status Register
Table 3.16 Register irqStat
Name
irqStat[7:0]
Address
Bits
Default
Access
Description
00HEX
[7:0]
00HEX
RC
Lower byte of the interrupt status register as defined in
section 3.6.1.1; each bit is set by hardware and cleared
on read access.
irqStat[15:8]
01HEX
[7:0]
00HEX
RC
Upper byte of interrupt status register as defined in
section 3.6.1.1; each bit is set by hardware and cleared
on read access.
Note: To avoid loss of information, the hardware set condition has a higher priority than the read clear condition.
3.6.1.3. Register “irqEna” – Interrupt Enable Register
Table 3.17 Register irqEna
Name
irqEna[7:0]
Address
Bits
Default
Access
Description
54HEX
[7:0]
00HEX
RW
Lower byte of the interrupt enable register as defined in
section 3.6.1.1; only enabled interrupts can drive the
interrupt line and wake up the system; the bit mapping
is the same as for the interrupt status register.
irqEna[15:8]
55HEX
[7:0]
00HEX
RW
Upper byte of the interrupt enable register as defined in
section 3.6.1.1; only enabled interrupts can drive the
interrupt line and wake up the system; the bit mapping
is the same as for the interrupt status register.
Note: The interrupt enable bit for the LIN wake-up interrupt (irqEna[4]) is also used as the enable for the LIN
wake-up frame detector within the PMU.
© 2016 Integrated Device Technology, Inc.
49
January 29, 2016
ZSSC1956 Datasheet
3.7. SBC Power Management Unit (PMU)
The power management unit (PMU) controls placing the SBC into the selected power down state, controlling the
power down signals for the different analog blocks, and controlling the clocks for the digital logic. It also controls
the other digital modules during the power-down state.
The system provides four different power states:
•
•
•
•
FP (Full-Power State):
In this state, all blocks are powered except the ADCs if software has not
enabled them. All internal clocks are active (divClk and muxClk are
4MHz), and the MCU is also powered and clocked. When powered and
enabled by software, the ADC clocks are generated from the clock from
the high-precision oscillator.
LP (Low-Power State):
In this state, the high-precision oscillator and the LIN transmitter are
powered down. The MCU clock is stopped, but the MCU remains
powered. Depending on the selected measurement setup, the ADCs are
also powered down during times of inactivity. Otherwise the ADC clocks
are generated from the clock from the low-power oscillator.
ULP (Ultra-Low-Power State): In this state, the high-precision oscillator and the LIN transmitter are
powered down. The MCU clock is stopped, and the MCU is powered
down. Depending on the selected measurement setup, the ADCs are also
powered down during times of inactivity. Otherwise, the ADC clocks are
generated from the clock from the low-power oscillator.
OFF (Off State):
In this state, all analog blocks except the digital power supply for the SBC
and the RX part of the LIN PHY are powered down. The MCU clock is
stopped, and the MCU is powered down.
To enter any of the power-down states (LP, ULP, or OFF), software must first set the pdState field of register
pwrCfgLp to select the state and enable the interrupts needed as the wakeup source before writing A9HEX to
register gotoPd. Immediately after A9HEX is written to the gotoPd register, the CSN line must be driven high.
Although for all other register accesses, the CSN line can be kept low and the next SPI transfer can follow
immediately, it is mandatory to drive CSN high for the power-down command. Otherwise, the PMU remains in the
FP state.
Important: If no interrupt is enabled, the system can only be awakened by power-on-reset.
Important: The CSN line must be driven high to go to power-down after writing the value A9HEX to register
gotoPd.
The following tasks are always performed on transition to any power-down state by the PMU:
•
•
Both ADCs are stopped. Any active measurement is interrupted. ADC control is transferred to the PMU.
The configuration values that can be configured independently for full-power and power-down states are
switched to the power-down settings.
•
•
•
•
•
The sleep timer is cleared and enabled.
The MCU clock is stopped.
The high-precision oscillator is powered down.
The TX part of the LIN PHY is powered down.
The source for the muxClk changes from divClk to lpClk.
© 2016 Integrated Device Technology, Inc.
50
January 29, 2016
ZSSC1956 Datasheet
When any of the enabled interrupts occurs and the interrupt pin IRQN is driven low, the system wakes up
immediately; any ADC measurement that is active during power-down state is stopped. All mandatory blocks are
powered up, and the system waits for stabilization before re-enabling the MCU clock.
If any of the enabled interrupts is already active on reception of the power-down command or becomes active on
transition to the requested power-down state, the system rejects the power-down command or re-enables those
blocks that are already powered down. Depending on the time when the power-down procedure was interrupted,
it is possible that the sleep timer was not cleared. In this case, the sleep timer valid flag is cleared, signaling that
the sleep timer value in register sleepTCurCntis not valid. This flag is mapped to SSW[1].
3.7.1.
FP State
After the initial power-on reset when the OTP contents are downloaded into the registers and all blocks have
stabilized, the system enters the FP state. In this state, all voltage regulators, both oscillators and the LIN PHY
are powered but the ADCs are still powered down.
Important: Both ADCs are powered down after power-on reset.
To be able to use the ADCs, the user must first power up the required ADCs by programming register pwrCfgFp,
bits pwrAdcI and/or pwrAdcV. The first bit enables the current ADC and the second bit enables the
voltage/temperature ADC. In this register, there are three other bits that can be set by the user, but they should
be handled with care as the system consumes less power when any of these bits is set but the accuracy of the
measurement results is reduced:
•
•
•
lpEnaFp
ulpEnaFp
when set to 1, the bias current for analog blocks is reduced to 10%
when set to 1, the bias current for analog blocks is reduced to 5%
pdRefbufOcFp when set to 1, the offset cancellation circuit in the reference buffer is
powered down
Note: When both lpEnaFpand ulpEnaFPare set to 1, the bias current for analog blocks is reduced to 15%.
Important: These settings are only used in FP state. For configuration for the power-down states, register
pwrCfgLpmust be used.
The settings in register pwrCfgFp are preserved when entering any power-down state by executing the power-
down command. The PMU overrides these settings or switches to the settings made in register pwrCfgLp on
transition to power-down state. When the system wakes up and returns to the FP state, the PMU restores the
settings as configured in pwrCfgFpregardless of whether any ADC was powered in power-down state or not.
© 2016 Integrated Device Technology, Inc.
51
January 29, 2016
ZSSC1956 Datasheet
3.7.2.
LP and ULP States
The LP and ULP power-down states are used to save power while doing measurements with lower accuracy. In
both states, the TX part of the LIN PHY and the high-precision oscillator are powered down and the MCU clock is
stopped. The internal clock muxClk is driven by the low-power oscillator with a frequency of 125 kHz while the
internal clock divClk is stopped. In ULP state, the two voltage regulators VDDP (IO voltage for SBC and MCU)
and VDDC (core voltage for MCU) are powered down. In this case, the RAM_PROTN pad is driven low as the
RAM in the MCU remains powered (connected to VDDL) and the signal RAM_PROTN is used to protect the RAM
inputs. The state of the ADCs and the other analog blocks needed for measurements depends on the configured
measurement setup for the power-down state (see following subsections). The blocks are powered when they are
needed for measurement and powered down when they are not needed for measurement. This is controlled by
the PMU as well as the control signals (start, stop, mode) for the digital ADC unit.
The main configuration register for the power-down behavior is register pwrCfgLp. The field pdStateis used to
select the power-down state to be entered on reception of the power-down command, and the field pdMeas is
used to define the measurement setup to be used during the power-down state.
There are three other bits to configure the power-down behavior:
•
•
•
lpEnaLp
ulpEnaLp
when set to 1, the bias current for analog blocks is reduced to 10%
when set to 1, the bias current for analog blocks is reduced to 5%
pwrRefbufOcLp when set to 1, the offset cancellation circuit in the reference buffer is powered up
Note: When both lpEnaLpand ulpEnaLpare set to 1, the bias current for analog blocks is reduced to 15%.
For the corresponding bits for the FP state, lpEnaFp and ulpEnaFp, the meaning is the same, but the default
settings are different. While there is no bias current reduction during FP state (default setting for both bits is 0),
the default bias current for the LP and ULP states is reduced to 10%. The meaning of the control bit for the offset
cancellation differs: the FP state control bit is a power-down signal; the LP/ULP state control bit is a power-up bit.
While the offset cancellation is enabled by default during the FP state (pdRefbufOcFp == 0), the offset
cancellation is disabled by default during the LP or ULP state (pwrRefbufOcLp == 0). Both bits are configurable
by the user.
On transition to the LP or ULP state, the sleep timer and the ADC trigger timer are cleared. While the sleep timer
is always enabled during power-down states, the ADC trigger timer is only enabled when performing discrete
measurements. When the sleep timer interrupt is enabled, the system wakes up when the sleep timer expires. If
the sleep timer interrupt is not enabled, the sleep timer stops when it expires, but the ADC trigger timer, if enabled
due to the measurement configuration, continues its operation. For wake-up, other interrupts must be enabled;
e.g., LIN wakeup.
Note: The sleep timer is always active during LP and ULP state.
Note: When reading the sleep timer value after wake-up by another enabled interrupt, the sleep timer is only valid
when it has not reached its compare value although the valid flag says valid. Whether the sleep timer is valid can
be determined by the sleep timer status bit.
When the system wakes up and returns to FP state, the sleep timer is stopped. Software can read the sleep timer
value to determine the duration of the power-down state.
© 2016 Integrated Device Technology, Inc.
52
January 29, 2016
ZSSC1956 Datasheet
3.7.2.1. Performing No Measurements during LP/ULP State
When the LP or ULP state has been entered, all analog blocks related to the ADCs are powered down. If the
system goes to power down without performing any measurements, only three different wake-up sources are
possible: the watchdog timer interrupt, the sleep timer interrupt, and the LIN wakeup interrupt.
Important: At least one of these interrupts must be enabled, as otherwise the system can only wake up by a
power-on reset. If no interrupt is enabled, the system cannot wake up.
To go to LP or ULP state without performing measurements, the following tasks must be done:
•
Enable at least one of the following interrupts:
o
o
o
Set irqEna[0]to 1 to enable the watchdog interrupt to wake up the system.
Set irqEna[1]to 1 to enable the sleep timer to wake up the system.
Set irqEna[4] to 1 to enable the LIN wake-up detector and to enable the system to wake up
due to a LIN wakeup frame.
•
•
•
•
•
Configure the sleep timer compare value (register sleepTCmp) if needed.
Set pdStateto 0 or 1 to configure the LP state or to 2 to configure the ULP state.
Set pdMeasto 0 to configure the system to perform no measurements.
Set lpEnaLp, ulpEnaLpand pwrRefbufOcLpas needed.
Write A9HEX to register gotoPdand then drive the CSN line high.
When an enabled interrupt occurs, the system wakes up and the settings from register pwrCfgFp are restored.
When all blocks have stabilized, the MCU clock is re-enabled and if coming out of the ULP state, the MCU reset is
released.
Figure 3.5 LP/ULP State without any Measurements
Note: The sleep timer interrupt is used as the wake-up source in this example, but it could also be the watchdog
timer interrupt or the LIN wakeup interrupt.
I
gotoPd
Command
Wakeup
Due to
Sleep
TImer
Interrupt
t
FP
LP / ULP
FP
© 2016 Integrated Device Technology, Inc.
53
January 29, 2016
ZSSC1956 Datasheet
3.7.2.2. Performing Discrete Measurements of Current during LP/ULP State
The system can be configured to periodically enable the current ADC and to measure the current during the LP or
ULP state. The current ADC can be configured to perform several current measurements during each
measurement phase (indicated by green blocks in Figure 3.6). Upon entering the LP/ULP state and between the
measurements, the current ADC is powered down. The voltage/temperature ADC is powered down for the entire
power-down period. The PMU powers up the current ADC when triggered by the ADC trigger timer. Possible
wake-up sources during this scenario are the watchdog timer interrupt, the sleep timer interrupt, the LIN wakeup
interrupt, or any of the ADC interrupts related to current.
Important: If no interrupt is enabled, the system cannot wake up.
To go to LP or ULP state and perform discrete current measurements, the following tasks must be done:
•
Enable at least one of the following interrupts:
o
o
o
Set irqEna[0]to 1 to enable the watchdog interrupt to wake up the system.
Set irqEna[1]to 1 to enable the sleep timer to wake up the system.
Set irqEna[4] to 1 to enable the LIN wake-up detector and to enable the system to wake up
due to a LIN wakeup frame.
o
Enable any ADC interrupt related to current.
•
•
•
•
•
•
Configure the sleep timer compare value (register sleepTCmp) if needed.
Configure the ADC trigger timer compare value (register sleepTAdcCmp) as needed.
Set pdStateto 0 or 1 to configure LP state or to 2 to configure ULP state.
Set pdMeasto 1 to configure the system to perform discrete current measurements.
Set lpEnaLp, ulpEnaLpand pwrRefbufOcLpas needed.
Write A9HEX to register gotoPdand then drive the CSN line high.
When an enabled interrupt occurs, the system wakes up and the settings from register pwrCfgFp are restored.
When all blocks have stabilized, the MCU clock is re-enabled and if coming out of ULP state, the MCU reset is
released.
Important: If any measurement is active while an enabled interrupt occurs (e.g., the sleep timer expires), the
measurement is interrupted and the system returns to the FP state.
In example shown in Figure 3.6, the first wakeup is by the ADC and the second wake-up is by the sleep timer;
however, the wakeups could be other combinations of the watchdog timer interrupt, sleep timer interrupt, and/or
LIN wakeup interrupt.
Figure 3.6 LP/ULP State Performing Only Current Measurements
I
gotoPd
gotoPd
Command
Command
ADC
Trigger
Time
Wakeup
Due to
Sleep
Current
Wakeup
Current Only
Measurements
Timer
Interrupt
t
FP
LP / ULP
FP
LP / ULP
FP
© 2016 Integrated Device Technology, Inc.
54
January 29, 2016
ZSSC1956 Datasheet
3.7.2.3. Performing Discrete Measurements of Current, Voltage, and Internal Temperature during
LP/ULP State
The system can be configured to periodically enable both ADCs and to measure current, voltage, and internal
temperature or external temperature (see section 3.7.2.4 for external temperature) during the LP or ULP state.
The sequence can be selected in the pdMeas bit field [4:2] in register pwrCfgLp, which also selects whether
internal or external temperature is measured. The period between each measurement is determined by the ADC
trigger timer (sleepTAdcCmp). The current ADC can be configured to perform multiple current measurements
during each measurement phase (indicated by green and orange blocks in Figure 3.7 to Figure 3.9) while the
voltage/temperature ADC can be configured to perform multiple voltage measurements (orange blocks in Figure
3.7 to Figure 3.9). After performing the configured number of voltage measurements, the PMU changes the
configuration for the voltage/temperature ADC and performs a single measurement of the internal temperature.
Voltage and temperature are not measured in every loop if the ADCs are configured for measuring only current in
a specified number of initial loops. The user can configure register discCvtCntso that in the first discCvtCnt
loops, only current is measured before voltage and temperature are measured in the next loop.
Upon entering the LP/ULP state and between the measurements, both ADCs are powered down. The PMU
powers up the current ADC when triggered by the ADC trigger timer. The voltage/temperature ADC is only
powered up after discCvtCnt current-only measurements have been performed. Possible wake-up sources in
this setup are all interrupts except the LIN short and LIN TXD timeout interrupts.
Important: If no interrupt is enabled, the system cannot wake up.
To go to the LP or ULP state and perform measurements of discrete current, voltage, and internal temperature,
the following tasks must be done:
•
Enable at least one of the following interrupts:
o
o
o
Set irqEna[0] to 1 to enable the watchdog interrupt to wake up the system.
Set irqEna[1] to 1 to enable the sleep timer to wake up the system.
Set irqEna[4]to 1 to enable LIN wake-up detector and to enable the system to wake up due to
a LIN wakeup frame.
o
Enable any ADC interrupt.
•
•
•
•
Configure the sleep timer compare value (register sleepTCmp) if needed.
Configure the ADC trigger timer compare value (register sleepTAdcCmp) as needed.
Set pdStateto 0 or 1 to configure the LP state or to 2 to configure the ULP state.
Set pdMeas to 2 to configure the system to perform discrete current, voltage, and internal temperature
measurements.
•
Set discCvtCntas needed. This register defines the number of current-only measurement loops before
performing measurement of all three parameters.
•
•
Set lpEnaLp, ulpEnaLpand pwrRefbufOcLpas needed.
Write A9HEX to register gotoPdand then drive the CSN line high.
When an enabled interrupt occurs, the system wakes up and the settings from register pwrCfgFp are restored.
When all blocks have stabilized, the MCU clock is re-enabled and if coming out of the ULP state, the MCU reset is
released.
© 2016 Integrated Device Technology, Inc.
55
January 29, 2016
ZSSC1956 Datasheet
Important: If any measurement is active while an enabled interrupt occurs (e.g., the sleep timer expires) the
measurement is interrupted and the system returns to the FP the state.
Note: If register discCvtCnt is set to 0, voltage and temperature are measured in each loop (the default
setting).
Figure 3.7 LP/ULP State Performing Current, Voltage, and Temperature Measurements (discCvtCnt==2)
I
gotoPd
Command
ADC
Trigger
Time
Wakeup
Due to
Sleep
Timer
Interrupt
t
FP
LP / ULP
FP
Current measurement only
Measurement of current, voltage and temperature
Figure 3.8 LP/ULP State Performing Current, Voltage, and Temperature Measurements (discCvtCnt==5)
I
gotoPd
Command
Wakeup due
to Voltage,
Temperature,
or Current
ADC
Trigger
Time
ADC Interrupt
t
FP
LP / ULP
FP
Current measurement only
Measurement of current, voltage and temperature
© 2016 Integrated Device Technology, Inc.
56
January 29, 2016
ZSSC1956 Datasheet
Figure 3.9 LP/ULP State Performing Current, Voltage, and Temperature Measurements (discCvtCnt==1)
I
gotoPd
ADC
Trigger
Time
Command
Wakeup
Due to
Current
ADC
Interrupt
t
FP
LP / ULP
FP
Current measurement only
Measurement of current, voltage and temperature
3.7.2.4. Performing Discrete Measurements of Current, Voltage and External Temperature during LP/ULP
State
This setup is the same as the configuration described in the previous section, except that the external instead of
the internal temperature is measured. To use this option, pdMeasmust be set to 3.
3.7.2.5. Performing Continuous Measurements of Current during LP/ULP State
The system can be configured to perform continuous current measurements during the LP or ULP state. While
the current ADC is powered up during the entire power-down state, the voltage/temperature ADC is powered
down.
The current ADC is powered up on entering the LP/ULP state if it was not already powered up during the FP
state. The ADC trigger timer is not enabled as the measurement is continuous. Possible wake-up sources during
this scenario are the watchdog timer interrupt, the sleep timer interrupt, the LIN wakeup interrupt, or any of the
ADC interrupts related to current.
Important: If no interrupt is enabled, the system cannot wake up.
To go to the LP or ULP state and perform continuous current measurements, the following tasks must be done:
•
Enable at least one of the following interrupts:
o
o
o
Set irqEna[0]to 1 to enable the watchdog interrupt to wake up the system.
Set irqEna[1]to 1 to enable the sleep timer to wake up the system.
Set irqEna[4] to 1 to enable the LIN wake-up detector and to enable the system to wake up
due to a LIN wakeup frame.
o
Enable any ADC interrupt related to current.
•
•
•
•
•
Set up the sleep timer compare value (register sleepTCmp) if needed.
Set pdStateto 0 or 1 to configure LP state or to 2 to configure ULP state.
Set pdMeasto 4 to configure the system to perform continuous current measurements.
Set lpEnaLp, ulpEnaLpand pwrRefbufOcLpas needed.
Write A9HEX to register gotoPdand then drive the CSN line high.
© 2016 Integrated Device Technology, Inc.
57
January 29, 2016
ZSSC1956 Datasheet
When an enabled interrupt occurs, the system wakes up and the settings from register pwrCfgFp are restored.
When all blocks have stabilized, the MCU clock is re-enabled and if coming out of ULP state, the MCU reset is
released.
Important: If any measurement is active while an enabled interrupt occurs (e.g., the sleep timer expires), the
measurement is interrupted and the system returns to FP state.
Figure 3.10 LP/ULP State Performing Continuous Current-Only Measurements
Note: The sleep timer interrupt or an ADC interrupt related to current is used as the wake-up source in this
example, but it could also be the watchdog timer interrupt or the LIN wakeup interrupt.
I
gotoPd
Command
Wakeup Due to
Sleep Timer or
Current measurement only
Current ADC
Interrupt
t
FP
LP / ULP
FP
3.7.2.6. Performing Continuous Measurements of Current and Voltage during LP/ULP State
The system can be configured to perform continuous current and voltage measurements during the LP or ULP
state. Both ADCs are powered up during the entire power-down state.
The ADCs are powered up on entering the LP/ULP state if they were not already powered up during the FP state.
The ADC trigger timer is not enabled as the measurement is continuous. Possible wake-up sources during this
scenario are the watchdog timer interrupt, the sleep timer interrupt, the LIN wakeup interrupt, or any of the ADC
interrupts related to current or voltage.
Important: If no interrupt is enabled, the system cannot wake up.
© 2016 Integrated Device Technology, Inc.
58
January 29, 2016
ZSSC1956 Datasheet
To go to the LP or ULP state and perform continuous current and voltage measurements, the following tasks must
be done:
•
Enable at least one of the following interrupts:
o
o
o
Set irqEna[0]to 1 to enable the watchdog interrupt to wake up the system.
Set irqEna[1]to 1 to enable the sleep timer to wake up the system.
Set irqEna[4] to 1 to enable the LIN wake-up detector and to enable the system to wake up
due to a LIN wakeup frame.
o
Enable any ADC interrupt related to current.
•
•
•
•
•
Set up the sleep timer compare value (register sleepTCmp) if needed.
Set pdStateto 0 or 1 to configure the LP state or to 2 to configure the ULP state.
Set pdMeasto 5 to configure the system to perform continuous current and voltage measurements.
Set lpEnaLp, ulpEnaLpand pwrRefbufOcLpas needed.
Write A9HEX to register gotoPdand then drive the CSN line high.
When an enabled interrupt occurs, the system wakes up and the settings from register pwrCfgFp are restored.
When all blocks have stabilized, the MCU clock is re-enabled and if coming out of ULP state, the MCU reset is
released.
Important: If any measurement is active while an enabled interrupt occurs (e.g., the sleep timer expires), the
measurement is interrupted and the system returns to the FP state.
Figure 3.11 Performing Continuous Current and Voltage Measurements during LP/ULP State
Note: The sleep timer interrupt or an ADC interrupt related to voltage or current is used as the wake-up source in
this example, but it could also be the watchdog timer interrupt or the LIN wakeup interrupt.
I
gotoPd
Wakeup Due
Command
to Sleep Timer,
Voltage ADC,
or Current ADC
Measurement of current and voltage
Interrupt
t
FP
LP / ULP
FP
3.7.2.7. Performing Continuous Measurements of Current and Internal Temperature during LP/ULP State
This setup is the same as the configuration described in the previous section, except that the internal temperature
instead of the voltage is measured. To use this option, pdMeas must be set to 6. Possible wake-up sources
during this scenario are the watchdog timer interrupt, the sleep timer interrupt, the LIN wakeup interrupt, or any of
the ADC interrupts related to current or temperature.
© 2016 Integrated Device Technology, Inc.
59
January 29, 2016
ZSSC1956 Datasheet
3.7.2.8. Performing Continuous Measurements of Current and External Temperature during
LP/ULP State
This setup is the same as the configuration described in the previous section, except that the external
temperature instead of the internal temperature is measured. To use this option, pdMeas must be set to 7.
Possible wake-up sources during this scenario are the watchdog timer interrupt, the sleep timer interrupt, the LIN
wakeup interrupt, or any of the ADC interrupts related to current or temperature.
3.7.3.
OFF State
The OFF state is the power-down state with the lowest current consumption and no ADC measurements are
possible. It is intended for long periods of inactivity; e.g., when a vehicle is shipped around the world. During this
state, all oscillators and clocks are turned off, the MCU is not powered, and most of the analog blocks are
powered down. Only the digital core and the RX part of the LIN PHY remain powered. The system can only wake
up via the detection of a LIN wakeup frame. To go to the OFF state, the following tasks must be done:
•
Set irqEna[4]to 1 to enable the LIN wake-up detector and to enable the system to wake up due to a
LIN wakeup frame.
•
•
Set pdStateto 3 to configure the OFF state as the power-down state to be entered.
Write A9HEX to register gotoPdand then drive the CSN line high.
When the LIN RXD line goes low during the OFF state, the low-power oscillator is re-enabled and the digital logic
checks if the LIN RXD line is low for more than 150µs. If this is true, the complete system returns to FP state and
the MCU is powered up, reset, and clocked again. If the LIN RXD line was low for less than 150µs, the low-power
oscillator is powered down again and the system remains in the OFF state.
Important: If the LIN wakeup interrupt is not enabled, the system only can only wake up by a power-on reset.
3.7.4.
Registers for Power Configuration and the Discreet Current Measurement Count
3.7.4.1. Register “pwrCfgFp” – Power Configuration Register for the FP State
Table 3.18 Register pwrCfgFp
Name
pwrAdcI
pwrAdcV
Address
Bits
Default
Access
Description
[0]
[1]
0BIN
0BIN
RW
RW
When set to 1, the ADC for current is powered.
When set to 1, the voltage/temperature ADC is powered.
Reserved
lpEnaFp
[2]
[3]
0BIN
0BIN
RW
RW
Reserved; always write as 0.
When set to 1, the bias current of the analog blocks is
reduced to 10% in the FP state.
Note: if ulpEnaFpis also set to 1, the bias current of
the analog blocks is reduced to 15%.
When set to 1, the bias current of the analog blocks is
reduced to 5% in the FP state.
53HEX
ulpEnaFp
[4]
0BIN
RW
Note: if lpEnaFpis also set to 1, the bias current of the
analog blocks is reduced to 15%.
pdRefbufOcFp
Unused
[5]
0BIN
RW
RO
When set to 1, the offset cancellation of the reference
buffer is powered down.
Unused; always write as 0.
[7:6]
00BIN
© 2016 Integrated Device Technology, Inc.
60
January 29, 2016
ZSSC1956 Datasheet
3.7.4.2. Register “pwrCfgLp” – Power Configuration Register for Power-Down States
Table 3.19 Register pwrCfgLp
Name
pdState
Address
Bits
Default
Access
Description
Select the power-down state to be entered:
[1:0]
00BIN
RW
0 or 1
LP state
2
3
ULP state
OFF state
pdMeas
[4:2]
000BIN
RW
Type of measurements to be performed during the LP or
ULP state:
0
1
2
No measurements
Discrete measurements of current
Discrete measurements of current,
voltage, and internal temperature
Discrete measurements of current,
voltage, and external temperature
Continuous measurements of current
Continuous measurements of current
and voltage
3
4
5
64HEX
6
7
Continuous measurements of current
and internal temperature
Continuous measurements of current
and external temperature
lpEnaLp
[5]
[6]
[7]
1BIN
0BIN
0BIN
RW
RW
RW
When set to 1, the bias current of the analog blocks is
reduced to 10% in the LP/ULP state.
Note: if ulpEnaLpis also set to 1, the bias current of
the analog blocks is reduced to 15%.
When set to 1, the bias current of the analog blocks is
reduced to 5% in the LP/ULP state.
ulpEnaLp
Note: if lpEnaLpis also set to 1, the bias current of the
analog blocks is reduced to 15%.
When set to 1, the offset cancellation of the reference
buffer is powered in LP/ULP state while performing
measurements.
pwrRefbufOcLp
© 2016 Integrated Device Technology, Inc.
61
January 29, 2016
ZSSC1956 Datasheet
3.7.4.3. Register “gotoPd” – Enter Power-Down State
Table 3.20 Register gotoPd
Name
gotoPd
Address
Bits
Default
Access
Description
65HEX
[7:0]
00HEX
WO
Writing A9HEX to this register triggers the PMU to enter
the configured power-down state when the CSN line is
driven high.
3.7.4.4. Register “discCvtCnt” – Configuration Register for Discrete Measurements
Table 3.21 Register discCvtCnt
Name
Address
Bits
Default
Access
Description
discCvtCnt
5FHEX
[7:0]
00HEX
RW
Defines the number of "current only" measurements
before performing one measurement of current, voltage,
and temperature when pdMeasis 2 or 3.
3.8. SBC ADC Unit
The measurement subsystem incorporates two independent and synchronized high-resolution ADCs for
monitoring two channels. The conversion scheme is based on the sigma-delta modulation (SDM) principle. One
channel (ADC-I) is exclusively used for current measurement and includes a pre-amplifier with offset cancellation
circuitry. The second channel (ADC-V/T) can be programmed to measure either voltage or temperature (internal
or external).
The raw conversion data can be post-processed by calibration data to achieve a minimum offset and gain error
(gain and offset correction). The conversion results are stored in the register file from where they can be read via
the SPI digital communication interface. A completed conversion is flagged by a “data ready” signal that can be
used as an interrupt source for the MCU. A detailed functional block diagram of the analog circuitry is shown in
Figure 3.13.
© 2016 Integrated Device Technology, Inc.
62
January 29, 2016
ZSSC1956 Datasheet
Figure 3.12 Functional Block Diagram of the Analog Measurement Subsystem
cSel
VDDA
cSel
VSSA
fINT / fDEC
fiSC
fiSC
IM
sinc4
Digital
Filter
INP
IPZ1
MPX1
PGA-2
SG-Modulator-1
INN
VSSA
PA-C
PGA-1
IPZ2
VREF 1.2V
MPX2
VCM
VSSA
pd_vbat
VREFLP 1.2V
fSDM
VREF 1.2V
VCM
VBAT
VDDA
pd_inamp
VSSA
SC-Clock
Generator
VBATP
VBATN
fINT / fDEC
RREF
MPX3
fiSC
IPZ3
IPZ4
NTH
NTL
sinc4
Digital
Filter
RNTC
SG-Modulator-2
CVDA
pdExtTemp
VPTAT
On-Chip
Temperature
Sensor
Analog-2-Digital Conversion
PA-T
vtSel
VSSA
VCM=VDDA/2
PA-C = Preamplifier Current; PA-T = Preamplifier Temperature; MPX = Multiplexer; PGA = Programmable Gain Amplifier
The purpose of this analog architecture is to achieve a maximum level of diagnostic capability and flexibility as
well as best accuracy.
The digital ADC unit consists of a data processing unit and control logic. The control logic generates the clocks
and control signals for the analog SD-ADCs as well as control signals for the data processing part of the ADC
unit.
© 2016 Integrated Device Technology, Inc.
63
January 29, 2016
ZSSC1956 Datasheet
3.8.1.
ADC Clocks
Two clocks are generated in the digital part of the ADC unit and are driven to the analog part. The SMD clock is
used for both SD-ADCs. The chop clock is used for the chopping operation within the SD-ADCs. The base for
both clocks is the multiplexed clock muxClk, which is a 4MHz clock in FP state and a 125kHz clock in LP/ULP
state.
3.8.1.1. ADC Clocks in FP State
In the FP state, the SDM clock is generated from the 4MHz clock by dividing it by two times the value prog-
rammed into the field sdmClkDivFp in register sdmClkCfgFp (see Table 3.24):
fHP
fSDM
=
fHP = 4MHz
(4)
2* sdmClkDivFp
Important: When sdmClkDivFpis set to 0, the frequency of SDM clock is 2MHz.
The chop clock is generated from the SDM clock by further dividing it by 2, 4, 8, or 16 depending on the setting of
the sdmChopClkDivfield in register adcGomd (see Table 3.55):
fCHOP = fSDM ∗2-(sdmClkChopDiv+1)
(5)
Although the clock bases used to generate the SDM clock and the chop clock have a frequency of 4MHz, the
position of the clock edges used for the clock generation can be shifted relative to the 4MHz clock used for the
digital logic to obtain optimal noise behavior for the analog part. The 4MHz clock used to generate the SDM clock
(CLKSDMBASE; see Figure 3.13 through Figure 3.16) is delayed relative to the 4MHz clock used for the digital logic
(CLKMUXCLK) by one to four 20MHz clock cycles (CLKHPOSC) depending on the settings of the field sdmPos in
register sdmClkCfgFp (see Table 3.24). The 4MHz clock used to generate the chop clock (CLKCHOPBASE) is
delayed relative to the 4MHz clock used for the digital logic (CLKSDMBASE) by zero to four 20MHz clock cycles
depending on the settings of field sdmPos2and field sdmPosin register sdmClkCfgFp. The delay in the number
of 20MHz clock cycles of the chop clock to the SDM clock can be calculated using the following formula:
delay = (sdmPos2 - sdmPos)mod5
(6)
Important: The delay programmed into field sdmPos2 is related to CLKMUXCLK, not to CLKSDMBASE. Table 3.22
shows the value that must be programmed into field sdmPos2 depending on the field sdmPos and the desired
delay.
© 2016 Integrated Device Technology, Inc.
64
January 29, 2016
ZSSC1956 Datasheet
Table 3.22 Value for sdmPos2Depending on sdmPosand Desired Clock Delay from SDM to Chop Clocks
sdmPos
0
0
1
2
3
4
1
1
2
3
4
0
2
2
3
4
0
1
3
3
4
0
1
2
0
1
2
3
4
Figure 3.13 FP ADC Clocking Scheme for sdmPos= sdmPos2= 2; sdmClkDivFp= 1; sdmChopClkDiv=0
CLKHPOSC
CNT
4 0 1 2 3 4 0 1 2 3 4 0 1 2 3 4 0 1 2 3 4 0 1 2 3 4 0 1 2
CLKMUXCLK
CLKSDMBASE
CLKCHOPBASE
SDM clock
CHOP clock
Figure 3.14 FP ADC Clocking for sdmPos= 1 and sdmPos2= 4; sdmClkDivFp= 1; sdmChopClkDiv=0
CLKHPOSC
CNT
4
0
1
2
3
4
0
1
2
3
4
0
1
2
3
4
0
1
2
3
4
0
1
2
3
4
0
1
2
CLKMUXCLK
CLKSDMBASE
CLKCHOPBASE
SDM clock
CHOP clock
© 2016 Integrated Device Technology, Inc.
65
January 29, 2016
ZSSC1956 Datasheet
Figure 3.15 FP ADC Clocking for sdmPos= 3 and sdmPos2= 0; sdmClkDivFp= 1; sdmChopClkDiv= 0
CLKHPOSC
CNT
4
0 1 2 3 4 0 1 2 3 4 0 1 2 3 4 0 1 2 3 4 0 1 2 3 4 0 1 2
CLKMUXCLK
CLKSDMBASE
CLKCHOPBASE
SDM clock
CHOP clock
Figure 3.16 FP ADC Clocking for sdmPos= 0 and sdmPos2= 3; sdmClkDivFp= 1; sdmChopClkDiv= 0
CLKHPOSC
CNT
4 0 1 2 3 4 0 1 2 3 4 0 1 2 3 4 0 1 2 3 4 0 1 2 3 4 0 1 2
CLKMUXCLK
CLKSDMBASE
CLKCHOPBASE
SDM clock
CHOP clock
3.8.1.2. ADC Clocks in the LP/ULP State
In the LP or ULP state, the SDM clock is generated from the 125kHz clock (CLKLPOSC) by dividing it by two times
the value programmed into register field sdmClkDivLp(see Table 3.23):
fLP
fSDM
=
; fLP = 125kHz
(7)
2 * sdmClkDivLp
Important: When sdmClkDivLpis set to 0, the frequency of SDM clock is 62.5kHz.
© 2016 Integrated Device Technology, Inc.
66
January 29, 2016
ZSSC1956 Datasheet
The chop clock is generated from the SDM clock by further dividing it by 2, 4, 8, or 16 depending on the setting of
the field sdmChopClkDivin register adcGomd (see Table 3.55):
fCHOP = fSDM ∗2-(sdmChopClkDiv+1)
(8)
Both the SMD and chop clocks are generated from the same 125kHz clock that is used for the digital logic.
Shifting of the clocks used to generate the SDM and chop clock is not possible and not needed as the analog
clocks are generated on the falling clock edge where the digital logic is already stable and will not influence the
analog part.
Figure 3.17 LP/ULP ADC Clocking Scheme; sdmClkDivFp= 5; sdmChopClkDiv= 0
CLKLPOSC
SDM clock
CHOP clock
3.8.1.3. Register “sdmClkCfgLp” – Configuration Register for the SDM Clocks in the LP/ULP State
Table 3.23 Register sdmClkCfgLp
Name
Address
Bits
Default
Access
Description
sdmClkDivLp[7:0]
sdmClkDivLp[9:8]
B0HEX
[7:0]
[1:0]
18HEX
00BIN
RW
RW
Clock divider value for the SDM clock in the LP
and ULP states related to the 125kHz base clock.
With sdmClkDivLp= 0, the divider value is 2.
Unused; always write as 0.
B1HEX
Unused
[7:2] 00 0000BIN
RO
3.8.1.4. Register “sdmClkCfgFp” – Configuration Register for the SDM Clocks in the FP State
Table 3.24 Register sdmClkCfgFp
Name
Address
Bits
Default
Access
Description
sdmClkDivFp[7:0]
sdmClkDivFp[9:8]
B2HEX
[7:0]
[1:0]
08HEX
00BIN
RW
RW
Clock divider value for the SDM clock in the FP
state; related to the base clock. If 0, then the
SDM clock is 2MHz.
Unused
sdmPos2
[2]
[5:3]
0BIN
010BIN
RO
RW
Unused; always write as 0.
Position of the chop clock relative to the
CLKMUXCLK clock.
B3HEX
sdmPos
[7:6]
10BIN
RW
Position of the SDM clock relative to the base
clock.
© 2016 Integrated Device Technology, Inc.
67
January 29, 2016
ZSSC1956 Datasheet
3.8.2.
ADC Data Path
The incoming 2nd and 3rd order bit streams from the analog part of the SD-ADCs are first captured and then driven
through a 3rd order noise shaping filter as illustrated in Figure 3.18. The digital conversion is accomplished by a
4th-order low-pass filter (sinc4 decimation filter). The bit stream capturing and the noise shaping filter cannot be
directly changed by the user (no configuration registers), but the selected oversampling rate (register field osr)
affects the sinc4 decimation filter (one output value per N input values).
Figure 3.18 Functional Block Diagram of the Digital ADC Data Path
{000, BIST bitstream}
4
4
4
sinc
Decimation
SDM 1
SDM 2
Filter
Noise
Bitstream
Capture
Cancellation
Post Filter
Data Post
Correction
Result Register
A simple post filter (moving average filter) is placed behind the sinc4 decimation filter. The user can select the
averaging function (no averaging, 2-stage averaging, or 3-stage averaging) via the avgFiltCfg bit field in the
adcSampregister (see Table 3.56) when chopping is disabled. When chopping is enabled, the 2-stage averaging
is used independently of the filter configuration.
The function of the 2-stage averaging filter is
x (t) + x (t -1)
in
in
x
(t) =
(9)
out
2
The function of the 3-stage averaging filter is
x (t) + 2* x (t -1) + x (t - 2)
in
in
in
x
(t) =
(10)
out
4
© 2016 Integrated Device Technology, Inc.
68
January 29, 2016
ZSSC1956 Datasheet
3.8.2.1. Data Post-Correction Block
The data post-correction block performs the offset and gain correction of the post-filtered conversion data as well
as the over-range and the overflow detection.
Figure 3.19 Data Post Correction
Post-Filter
Channel 1
x
x
+
Post-Filter
Channel 2
First, an over-range check is performed on the incoming data. Values that are outside the interval [-0.75; 0.75) are
always mapped to the corresponding interval boundary. This is done for better results as the ADC accuracy
decreases for large input values. The user can enable a “set interrupt” strobe for each of the two channels by
setting the adcAcmpregister bits COvrEnaand VTOvrEnato 1 (see Table 3.54).
Note: The “set interrupt” strobes go to the interrupt controller. They have a different meaning than the
corresponding “interrupt enable” bits (interrupt bits [15:14]) in the irqEna register. The “set interrupt” bits are
used to select whether the interrupt status bits will be set or not; the “interrupt enable” bits select whether the
interrupt status bits will drive the interrupt line or not.
After the over-range check, a programmable offset, interpreted as a number in range [-1.0; 1.0), is added to the
data. Three registers allow setting different offsets for current, voltage, and temperature: adcCoff, adcVoff, and
adcToff (see Table 3.25, Table 3.27, and Table 3.29 respectively). The offset correction is followed by two
multiplication stages. In the first multiplication stage, individual gain factors for current (adcCgan), voltage
(adcVgan), or temperature (adcTgan), interpreted as numbers in the range [0.0; 2.0), are multiplied by the offset
corrected data (see Table 3.26, Table 3.28, and Table 3.30 respectively). The second multiplication stage is used
to shift the significant data into the most significant bits of the result register. The data is multiplied by 1, 2, 4, or 8,
which can be individually selected for current, voltage, and temperature via the curPoCoGain, voltPoCoGain,
and tempPoCoGainfields in the adcPoCoGain register (see Table 3.31).
© 2016 Integrated Device Technology, Inc.
69
January 29, 2016
ZSSC1956 Datasheet
Figure 3.20 Data Representation through Data Post Correction including Over-Range and Overflow Levels
Note: the yellow area represents the usable data space to avoid overflow when the post correction gain is 2.
Input to Data
Post-Correction
Gain and Offset
Correction
Post-Correction
Overflow
1
2.4V
FFFFFFHEX
E00000HEX
7FFFFFHEX
600000HEX
7FFFFFHEX
600000HEX
Over-Range
3/4 1.8V
1/2 1.2V
C00000HEX
400000HEX
400000HEX
800000HEX
000000HEX
000000HEX
0
0.0V
poCoGain = 2
400000HEX
200000HEX
C00000HEX
A00000HEX
C00000HEX
A00000HEX
-1/2 -1.2V
-3/4 -1.8V
-1 -2.4V
Over-Range
000000HEX
800000HEX
800000HEX
Overflow
Unsigned
Signed
Signed
An overflow check is performed on the output of the second multiplication stage as the result could be out of the
representable range of [-1.0; 1.0). The user can also enable a “set interrupt” strobe for each of the two channels
by setting the adcAcmpregister bits CovrEnaand VTOvrEnato 1 (same bits as for the over-range check).
Note: Although the same “set interrupt strobe enable” bits are used for over-range and overflow, independent
interrupt status bits exist that can be individually enabled or disabled for overflow (interrupt bits [13:12]).
Figure 3.21 illustrates the common enable CovrEnafor the interrupt strobes for current over-range and overflow.
The function of VTOvrEnaas the common enable for the interrupt strobes for voltage/temperature over-range and
overflow conditions is similar.
© 2016 Integrated Device Technology, Inc.
70
January 29, 2016
ZSSC1956 Datasheet
Figure 3.21 Common Enable for the “set overrange” and “set overflow” Interrupt Strobes for Current
irqStat[12]
current overflow detected
COvrEna
(current overflow)
set interrupt
set interrupt
&
&
irqStat[14]
(current overrange)
current overrange detected
3.8.2.2. Register “adcCoff” – Offset Correction Value for Current Channel
Table 3.25 Register adcCoff
Name
adcCoff[7:0]
adcCoff[15:8]
adcCoff[23:16]
Address
Bits
Default
Access
Description
33HEX
34HEX
35HEX
[7:0]
[7:0]
[7:0]
00HEX
00HEX
00HEX
RW
RW
RW
Offset value for current value in 2’s complement
representation; interpreted as a number in the range of
[-1.0; 1.0), programmable offset range = +/- 2 VREF
VREF= full-scale range ADC.
,
Note: The initial value is loaded from OTP after reset.
3.8.2.3. Register “adcCgan” – Gain Correction Value for Current Channel
Table 3.26 Register adcCgan
Name
Address
Bits
Default
Access
Description
adcCgan[7:0]
adcCgan[15:8]
adcCgan[23:16]
30HEX
31HEX
32HEX
[7:0]
[7:0]
[7:0]
00HEX
00HEX
80HEX
RW
RW
RW
Gain value for current value; interpreted as a number in
the range [0.0; 2.0).
Note: The initial value is loaded from OTP after reset.
3.8.2.4. Register “adcVoff” – Offset Correction Value for Voltage Channel
Table 3.27 Register adcVoff
Name
adcVoff[7:0]
adcVoff[15:8]
adcVoff[23:16]
Address
Bits
Default
Access
Description
39HEX
3AHEX
3BHEX
[7:0]
[7:0]
[7:0]
00HEX
00HEX
00HEX
RW
RW
RW
Offset value for voltage value in 2’s complement
representation; interpreted as a number in the range of
[-1.0; 1.0), programmable offset range = +/- 2 VREF
VREF = full-scale range ADC.
,
Note: The initial value is loaded from OTP after reset.
© 2016 Integrated Device Technology, Inc.
71
January 29, 2016
ZSSC1956 Datasheet
3.8.2.5. Register “adcVgan” – Gain Correction Value for Voltage Channel
Table 3.28 Register adcVgan
Name
Address
Bits
Default
Access
Description
adcVgan[7:0]
adcVgan[15:8]
adcVgan[23:16]
36HEX
37HEX
38HEX
[7:0]
[7:0]
[7:0]
00HEX
00HEX
80HEX
RW
RW
RW
Gain value for voltage value; interpreted as a number
in the range [0.0; 2.0).
Note: The initial value is loaded from OTP after reset.
3.8.2.6. Register “adcToff” – Offset Correction Value for Temperature Channel
Table 3.29 Register adcToff
Name
adcToff[7:0]
adcToff[15:8]
Address
Bits
Default
Access
Description
3EHEX
3FHEX
[7:0]
[7:0]
00HEX
00HEX
RW
RW
Offset value for temperature value; interpreted as a
number in the range [-1.0; 1.0)
Note: The initial value is loaded from OTP after reset.
3.8.2.7. Register “adcTgan” – Gain Correction Value for Temperature Channel
Table 3.30 Register adcTgan
Name
Address
Bits
Default
Access
Description
adcTgan[7:0]
adcTgan[15:8]
3CHEX
3DHEX
[7:0]
[7:0]
00HEX
80HEX
RW
RW
Gain value for temperature value; interpreted as a
number in the range [0.0; 2.0)
Note: The initial value is loaded from OTP after reset.
3.8.2.8. Register “adcPoCoGain” – Post Correction Gain Configuration
Table 3.31 Register adcPoCoGain
Name
Address
Bits
Default
Access
Description
curPoCoGain
[1:0]
00BIN
RW
Post correction gain for the current channel:
0
1
2
3
Gain factor is 1
Gain factor is 2
Gain factor is 4
Gain factor is 8
voltPoCoGain
[3:2]
[5:4]
00BIN
RW
Post correction gain for the voltage channel:
0
1
2
3
Gain factor is 1
Gain factor is 2
Gain factor is 4
Gain factor is 8
57HEX
tempPoCoGain
00BIN
RW
Post correction gain for the temperature channel:
0
1
2
Gain factor is 1
Gain factor is 2
Gain factor is 4
© 2016 Integrated Device Technology, Inc.
72
January 29, 2016
ZSSC1956 Datasheet
Name
Address
Bits
Default
Access
Description
Gain factor is 8
3
Unused
[7:6]
00BIN
RO
Unused; always write as 0.
3.8.3.
ADC Operating Modes and Related Registers
3.8.3.1. Single Measurement Results
Each value coming from the data post correction block is the result of a single measurement. These values are
signed and stored in the corresponding result registers adcCdat, adcVdat, adcTdat, or adcRdat. The
following formulas can be used to calculate the battery current and the battery voltage from the result register
values:
adcCdat ∗ 2 ∗ VREF
IBAT
=
(11)
23
∗
∗ ∗
GANA GPOCO
RSHUNT
2
adcVdat ∗ 24 ∗ 2 ∗ VREF
VBAT
=
(12)
223 GPOCO
∗
Where
IBAT
Battery current
VBAT
Battery voltage
GANA
Analog gain in current path (pgaIfc pga1 pga2; see Table 3.36)
Digital gain in post-correction stage (second multiplication; see Table 3.31)
Shunt resistance
GPOCO
RSHUNT
VREF
Reference voltage
adcCdat
adcVdat
Register value for current
Register value for voltage
3.8.3.2. Register “adcCdat” – Single Current Measurement Value
Table 3.32 Register adcCdat
Name
Address
Bits
Default
Access
Description
adcCdat[7:0]
adcCdat[15:8]
adcCdat[23:16]
02HEX
03HEX
04HEX
[7:0]
[7:0]
[7:0]
00HEX
00HEX
00HEX
RO
RO
RO
Conversion result of a single current measurement
(signed value)
© 2016 Integrated Device Technology, Inc.
73
January 29, 2016
ZSSC1956 Datasheet
3.8.3.3. Register “adcVdat” – Single Voltage Measurement Value
Table 3.33 Register adcVdat
Name
Address
Bits
Default
Access
Description
adcVdat[7:0]
adcVdat[15:8]
adcVdat[23:16]
05HEX
06HEX
07HEX
[7:0]
[7:0]
[7:0]
00HEX
00HEX
00HEX
RO
RO
RO
Conversion result of a single voltage measurement
(signed value)
3.8.3.4. Registers “adcTdat” and “adcRdat” – Single Temperature Measurement Values
Table 3.34 Register adcTdat
Name
Address
Bits
Default
Access
Description
adcTdat[7:0]
adcTdat[15:8]
0AHEX
0BHEX
[7:0]
[7:0]
00HEX
00HEX
RO
RO
Conversion result of a single temperature value (signed
value; inverted); this value is either the internally
measured temperature or the NTC value of an external
temperature measurement.
Important: This value is sign-inverted.
Table 3.35 Register adcRdat
Name
Address
Bits
Default
Access
Description
adcRdat[7:0]
adcRdat[15:8]
08HEX
09HEX
[7:0]
[7:0]
00HEX
00HEX
RO
RO
ADC result register of a single temperature measure-
ment by reading a voltage across the reference resistor
(external temperature measurement only).
3.8.3.5. Register “adcGain” – Analog Gain Configuration in the Current Path
Table 3.36 Register adcGain
Name
Address
Bits
Default
Access
Description
pgaIfc
pga1
[1:0]
00BIN
RW
Sets the gain of the IFC in the analog current path:
0
1
2
3
Gain factor is 1
Gain factor is 2
Gain factor is 4
Gain factor is 8
[3:2]
00BIN
RW
RW
Sets the gain of the PGA1 in the analog current path:
0
1
2
3
Gain factor is 1
Gain factor is 2
Gain factor is 4
Gain factor is 8
52HEX
pga2
[4]
0BIN
Sets the gain of the PGA2 in the analog current path:
0
1
Gain factor is 4
Gain factor is 8
Unused
[7:5]
000BIN
RO
Unused; always write as 0.
© 2016 Integrated Device Technology, Inc.
74
January 29, 2016
ZSSC1956 Datasheet
3.8.3.6. Result Counter Functionality and Conversion Ready Strobes
Three status bits are available in the interrupt status (irqStat[7:5]) that signal that the conversion of current,
voltage, or temperature has completed. The “set interrupt” strobe is generated for each completed temperature
measurement. For the voltage and current measurements, the user can independently select whether the
corresponding “set interrupt” strobe will be generated after each single measurement (SRCS – single result count
sequence) or after N measurements (MRCS – multi-result count sequence).
The register adcCrcl configures the number of current measurements before the current conversion ready
strobe is generated; the maximum number is 65535. Setting this register to 0 disables the result count
functionality which means that SRCS is configured. The present result counter value can always be read from the
register adcCrcv. The result counter is reset when startAdcCis set (rising edge) in FP state (see Table 3.58)
or at start of the first measurement in LP/ULP state. It is set to 1 at the end of the first measurement after the limit
defined in adcCrclhas been reached.
The register adcVrcl configures the number of measurements before the voltage conversion ready strobe is
generated, the maximum number is 15. Setting this register to 0 disables the result count functionality, which
means that SRCS is configured. The present result counter value can always be read from the register adcVrcv.
The result counter is reset when startAdcVis set (rising edge) in the FP state (see Table 3.58) or at the start of
the first measurement in the LP/ULP state. It is set to 1 at the end of the first measurement after the limit defined
in adcVrclwas reached.
Note: Setting register adcCrclor adcVrclto 1 leads to SRCS in the corresponding channel.
3.8.3.7. Register “adcCrcl” – Current Result Count Limit
Table 3.37 Register adcCrcl
Name
adcCrcl[7:0]
adcCrcl[15:8]
Address
Bits
Default
Access
Description
40HEX
41HEX
[7:0]
[7:0]
00HEX
00HEX
RW
RW
Number of current measurements before the current
conversion ready strobe is generated.
Note: Setting this bit to 0 disables this functionality,
and the strobe is generated after each current
measurement.
3.8.3.8. Register “adcCrcv” – Current Result Count Value
Table 3.38 Register adcCrcv
Name
Address
Bits
Default
Access
Description
adcCrcv[7:0]
adcCrcv[15:8]
1BHEX
1CHEX
[7:0]
[7:0]
00HEX
00HEX
RO
RO
Present value of the current result counter.
© 2016 Integrated Device Technology, Inc.
75
January 29, 2016
ZSSC1956 Datasheet
3.8.3.9. Register “adcVrcl” – Voltage Result Count Limit
Table 3.39 Register adcVrcl
Name
Address
Bits
Default
Access
Description
adcVrcl
[3:0]
0000BIN
RW
Number of voltage measurements before the voltage
conversion ready strobe is generated.
Note: Setting this bit to 0 disables this functionality,
and the strobe is generated after each voltage
measurement.
45HEX
Unused
[7:4]
0000BIN
RO
Unused; always write as 0.
3.8.3.10. Register “adcVrcv” – Voltage Result Count Value
Table 3.40 Register adcVrcv
Name
adcVrcv
Unused
Address
Bits
Default
Access
Description
[3:0] 0000BIN
[7:4] 0000BIN
RO
RO
Present value of the voltage result counter.
Unused; always write as 0.
1EHEX
3.8.3.11. Current Threshold Comparator Functionality
The current threshold comparator functionality is used to monitor the current level and to generate an interrupt
(irqStat[8]) if the absolute current value exceeds a programmable limit for a configurable number of
conversion results. This functionality is enabled when the field ctcvModein register adcAcmpis set to a non-zero
value. If enabled, this function is always triggered when a new current value is measured. The absolute value of
the most significant 17 bits of the measured current value is compared to the expanded programmable threshold
register adcCrth (see Table 3.41):
abs
(
adcCdat
[
23 : 7
]
)
≥
{
0,adcCrth
}
(13)
When the current threshold comparator functionality is enabled, the current threshold counter is used to count the
number of conversions where the absolute current value is above the threshold. If the absolute current value is
greater than or equal to the programmed threshold (above formula is true), the internal current threshold counter
is incremented (until it reaches its maximum value FFHEX). Otherwise the counter is either decremented (if
ctcvMode field in register adcAcmp is set to 1) or reset (if ctcvMode is set to 2), or it remains unchanged (if
ctcvModeis set to 3). The present value of the current threshold counter can be read from the register adcCtcv
(see Table 3.43).
Note: When bit field ctcvMode is set to 00BIN, the current threshold comparator functionality is disabled and
register adcCrtvis always 0.
Note: When ctcvModeis set to 01BIN, the current threshold counter is not decremented when the counter is 0.
After each comparison of the absolute current value versus the current threshold level and after the current
threshold counter has been updated, the internal current threshold counter is compared to the current threshold
counter limit (register adcCtcl;see Table 3.42). Whenever the current threshold counter is greater than or equal
to the programmable limit, a “set interrupt” strobe is generated.
© 2016 Integrated Device Technology, Inc.
76
January 29, 2016
ZSSC1956 Datasheet
Note: When the current threshold counter has reached its limit and it is configured to keep its value if the limit is
not reached, a “set interrupt” strobe is generated for each new measurement even if the new value is below
threshold.
The current threshold counter is reset to 0 for the following conditions:
•
•
•
•
If ctcvModeis set to 2 and the absolute current value is below the programmed threshold adcCrth
On assertion of startAdcI(rising edge) in the FP state
At the start of the first conversion in the LP or ULP state
Each time the result counter is reset (if the result counter is enabled) and the current threshold counter
reset mode bit (bit ctcvRstModein register adcAcmp) is set to 1
3.8.3.12. Register “adcCrth” – Absolute Current Threshold
Table 3.41 Register adcCrth
Name
adcCrth[7:0]
adcCrth[15:8]
Address
Bits
Default
Access
Description
42HEX
43HEX
[7:0]
[7:0]
00HEX
00HEX
RW
RW
Absolute current threshold (unsigned value).
When using current comparator threshold functionality,
the absolute current value is compared to {0, adcCrth}.
3.8.3.13. Register “adcCtcl” – Current Threshold Counter Limit
Table 3.42 Register adcCtcl
Name
Address
Bits
Default
Access
Description
adcCtcl
44HEX
[7:0]
00HEX
RW
Current threshold counter limit.
This register defines the number of current
measurements that must be greater than or equal to
the threshold “adcCrth” before the interrupt is set.
3.8.3.14. Register “adcCtcv” – Current Threshold Counter Value
Table 3.43 Register adcCtcv
Name
adcCtcv
Address
Bits
Default
Access
Description
1DHEX
[7:0]
00HEX
RO
Present current threshold counter value.
© 2016 Integrated Device Technology, Inc.
77
January 29, 2016
ZSSC1956 Datasheet
3.8.3.15. Current Accumulator Functionality
The current accumulator functionality is used to sum up all current conversion results. The present accumulator
value can be read from the register adcCaccu (signed value; see Table 3.45). Positive conversion results
increment the accumulator register; negative conversion results decrement it. The accumulator register saturates
at its minimum and maximum value.
The current accumulator is reset to 0 under these conditions:
•
•
•
On assertion of startAdcI(rising edge) in the FP state
At start of the first conversion in the LP or ULP state
Each time the result counter is reset (if the result counter is enabled) and the current accumulator reset
mode bit (bit accuRstModein register adcAcmp) is set to 1
Note: The current accumulator functionality can be used to calculate the mean value of the current.
The current accumulator is also compared to a programmable signed accumulator threshold value (register
adcCaccTh). This comparison can be used to generate a “set interrupt” strobe for irqStat[11], but to enable
the generation of the “set interrupt” strobe, bit CaccuThEna in register adcAcmp must be set to 1. The “set
interrupt” strobe is always generated on update of the accumulator register when
•
•
•
adcCaccThis greater than 0 and adcCaccuis greater than adcCaccTh
adcCaccThis lower than 0 and adcCaccuis lower than adcCaccTh
adcCaccThis equal to 0 and adcCaccuis not equal to 0
3.8.3.16. Register “adcCaccTh” – Current Accumulator Threshold Value
Table 3.44 Register adcCaccTh
Name
Address
Bits
Default
Access
Description
adcCaccTh[7:0]
adcCaccTh[15:8]
adcCaccTh[23:16]
adcCaccTh[31:24]
48HEX
49HEX
4AHEX
4BHEX
[7:0]
[7:0]
[7:0]
[7:0]
00HEX
00HEX
00HEX
00HEX
RW
RW
RW
RW
Signed threshold value for current accumulator mode.
3.8.3.17. Register “adcCaccu” – Current Accumulator Value
Table 3.45 Register adcCaccu
Name
Address
Bits
Default
Access
Description
adcCaccu[7:0]
0CHEX
0DHEX
0EHEX
0FHEX
[7:0]
[7:0]
[7:0]
[7:0]
00HEX
00HEX
00HEX
00HEX
RO
RO
RO
RO
Present current accumulator value.
adcCaccu[15:8]
adcCaccu[23:16]
adcCaccu[31:24]
© 2016 Integrated Device Technology, Inc.
78
January 29, 2016
ZSSC1956 Datasheet
3.8.3.18. Voltage Threshold Comparator and Voltage Accumulator Functionality
The ZSSC1956 also provides a threshold comparator as well as an accumulator comparator for the battery
voltage channel but with reduced functionality.
When the VthSelbit in register adcAcmpis set to 0, the absolute value of the most significant 17 bits of a single
voltage measurement (register adcVdat) is compared to the programmable voltage threshold (register adcVTh).
In this case, register adcVTh is interpreted as an unsigned value. There is also no counter functionality. When-
ever the absolute voltage value is below the programmed threshold, a “set interrupt” strobe for irqStat[9] is
generated when the strobe generation is enabled (field VthWuEnain register adcAcmpis set to 1).
abs
(
adcVdat
[
23 : 7
]
)
<
{
0,adcVTh
}
(14)
When bit VthSel in register adcAcmp is set to 1, the voltage accumulator functionality is enabled. The voltage
result counter functionality must also be enabled (register adcVrcl> 0). The voltage accumulator functionality is
used to sum up all voltage conversion results. In contrast to the current channel, only the upper 20 bits of the
voltage conversion results are accumulated. The present accumulator value can be read from the register
adcVaccu (signed value; see Table 3.47). Positive conversion results increment the accumulator register;
negative conversion results decrement it. The accumulator register saturates at its minimum and maximum value.
The voltage accumulator is reset to 0 under these conditions:
•
•
•
On assertion of startAdcV(rising edge) in the FP state
At start of the first conversion in the LP or ULP state
Each time the result counter is reset (if the result counter is enabled)
Note: The voltage accumulator functionality can be used to calculate the mean value of the voltage.
After the last accumulation within an MRCS, the upper 16 bits of the voltage accumulator are compared to the
voltage threshold adcVTh, which is interpreted as a signed value in this case. This comparison can be used to
generate a “set interrupt” strobe for irqStat[9], but to enable the generation of the “set interrupt” strobe, bit
VthWuEnain register adcAcmpmust be set to 1. The “set interrupt” strobe is generated when
•
•
•
adcVThis greater than 0 and adcVaccuis less than or equal to adcVTh
adcVThis lower than 0 and adcVaccuis greater than or equal to adcVTh
adcVThis equal to 0 and adcVaccuis equal to 0
Important: The threshold adcVTh is either interpreted as an unsigned or signed value depending on the
operation mode (VthSel).
Note: the voltage comparators compare only on the MSBs of the conversion result, so it might be beneficial to
use the post correction gain functionality to shift left the results to increase the accuracy of the comparison.
© 2016 Integrated Device Technology, Inc.
79
January 29, 2016
ZSSC1956 Datasheet
3.8.3.19. Register “adcVTh” – Voltage Threshold Value
Table 3.46 Register adcVTh
Name
adcVTh[7:0]
adcVTh[15:8]
Address
Bits
Default
Access
Description
46HEX
47HEX
[7:0]
[7:0]
00HEX
00HEX
RW
RW
Voltage threshold.
If VthSel == 0, then adcVThis interpreted as an
unsigned value and it is compared to the absolute
value of a single voltage conversion.
If VthSel== 1, then adcVThis interpreted as a signed
value and it is compared to the accumulated voltage
conversion results at the end of an MRCS.
3.8.3.20. Register “adcVaccu” – Voltage Accumulator Value
Table 3.47 Register adcVaccu
Name
Address
Bits
Default
Access
Description
adcVaccu[7:0]
adcVaccu[15:8]
adcVaccu[23:16]
10HEX
11HEX
12HEX
[7:0]
[7:0]
[7:0]
00HEX
00HEX
00HEX
RO
RO
RO
Present voltage accumulator value.
3.8.3.21. Minimum and Maximum Values of Current and Voltage
For current and voltage measurements, the minimum and maximum values are determined on the upper 16 bits
of the corresponding conversion results. These values can be read from registers adcCmax, adcCmin,
adcVmax, and adcVmin. These registers are reset in the same manner as the corresponding accumulator
registers. These values are only provided for statistical reasons and can be used to judge the accumulated
current or voltage values when used for mean value calculation.
Note: As the minimum and maximum values are only determined on the MSBs of the corresponding conversion
results, it might be beneficial to use the post correction gain functionality to shift left the results to increase the
accuracy of the comparison.
© 2016 Integrated Device Technology, Inc.
80
January 29, 2016
ZSSC1956 Datasheet
3.8.3.22. Register “adcCmax” – Maximum Current Value
Table 3.48 Register adcCmax
Name
Address
Bits
Default
Access
Description
adcCmax[7:0]
adcCmax[15:8]
13HEX
14HEX
[7:0]
[7:0]
00HEX
80HEX
RO
RO
Upper 16 bits of the maximum measured current value
(signed value).
3.8.3.23. Register “adcCmin” – Minimum Current Value
Table 3.49 Register adcCmin
Name
Address
Bits
Default
Access
Description
adcCmin[7:0]
adcCmin[15:8]
15HEX
16HEX
[7:0]
[7:0]
FFHEX
7FHEX
RO
RO
Upper 16 bits of the minimum measured current value
(signed value).
3.8.3.24. Register “adcVmax” – Maximum Voltage Value
Table 3.50 Register adcVmax
Name
Address
Bits
Default
Access
Description
adcVmax[7:0]
adcVmax[15:8]
17HEX
18HEX
[7:0]
[7:0]
00HEX
80HEX
RO
RO
Upper 16 bits of the maximum measured voltage value
(signed value).
3.8.3.25. Register “adcVmin” – Minimum Voltage Value
Table 3.51 Register adcVmin
Name
Address
Bits
Default
Access
Description
adcVmin[7:0]
adcVmin[15:8]
19HEX
1AHEX
[7:0]
[7:0]
FFHEX
7FHEX
RO
RO
Upper 16 bits of the minimum measured voltage value
(signed value).
© 2016 Integrated Device Technology, Inc.
81
January 29, 2016
ZSSC1956 Datasheet
3.8.3.26. Temperature Limits
The user can define an upper (register adcTmax) and a lower (register adcTmin) limit for the external and inter-
nal temperature measurement. On each update of register adcTdat(see Table 3.34), the upper 8 bits are com-
pared to the signed limit values. This can be used to generate a “set interrupt” strobe for irqStat[10] if the
value for adcTdatis outside the interval [adcTmin; adcTmax] and the TwuEnabit in register adcAcmphas been
set to 1.
Note: The minimum and maximum values are only compared to the MSBs of the conversion result, so it might be
beneficial to use the post correction gain functionality to shift left the results to increase the accuracy of the
comparison.
Important: Because the value stored in register adcTdat is inverted, the value given in register adcTmax is
actually the value for the lower temperature and the value given in register adcTminis actually the value for the
higher temperature.
3.8.3.27. Register “adcTmax” – Upper Boundary for Temperature Interval
Table 3.52 Register adcTmax
Name
adcTmax
Address
Bits
Default
Access
Description
4CHEX
[7:0]
00HEX
RW
Upper boundary for the temperature interval compared
to the upper bits of adcTdat.
3.8.3.28. Register “adcTmin” – Lower Boundary for Temperature Interval
Table 3.53 Register adcTmin
Name
adcTmin
Address
Bits
Default
Access
Description
4DHEX
[7:0]
00HEX
RW
Lower boundary for the temperature interval compared
to the upper bits of adcTdat
© 2016 Integrated Device Technology, Inc.
82
January 29, 2016
ZSSC1956 Datasheet
3.8.3.29. Miscellaneous ADC Registers
The registers defined in the next three sections provide settings that enable interrupts or control various functions
related to the ADCs.
3.8.3.30. Register “adcAcmp” – ADC Function Enable Register
Table 3.54 Register adcAcmp
Name
anaGndSw
Address
Bits
Default
Access
Description
[0]
0BIN
RW
If set to 1, the signal pdExtTemp (see Figure 3.12),
which is normally controlled by the PMU, is forced to 1.
In this case, the transistor shown in Figure 3.12 is not
conducting.
ctcvMode
[2:1]
00BIN
RW
Current threshold comparator mode:
00 The Current Threshold Comparator Mode
is disabled.
01 adcCtcv is decremented when the
absolute current value is below the
threshold and incremented otherwise.
10 adcCtcv is reset when the absolute
current value is below the threshold and
incremented otherwise.
11 adcCtcvretains its value when the
absolute current value is below the
threshold and incremented otherwise.
4EHEX
CaccuThEna
CovrEna
[3]
[4]
0BIN
1BIN
RW
RW
If set to 1, enables the strobe to interrupt the controller
when the current accumulator exceeds its threshold.
If set to 1, enables the strobes to interrupt the controller
when an over-range or overflow has been detected in
the current channel.
VTOvrEna
[5]
1BIN
RW
If set to 1, enables the strobes to interrupt the controller
when an over-range or overflow has been detected in
the voltage/temperature channel.
ctcvRstMode
accuRstMode
VthWuEna
[6]
[7]
[0]
0BIN
0BIN
0BIN
RW
RW
RW
If set to 1, then adcCtcvis reset when the current
result counter is reset (adcCrcv).
If set to 1, then adcCaccuis reset when the current
result counter is reset (adcCrcv).
If set to 1, enables the strobe to interrupt the controller
for the voltage threshold comparator and voltage
accumulator functionality.
VthSel
[1]
0BIN
RW
If set to 0, the absolute value of the single voltage
conversion result is compared to the threshold
adcVTh.
If set to 1, the accumulated results of all voltage
conversions within an MRCS are compared to the
threshold adcVTh.
4FHEX
TwuEna
Unused
[2]
0BIN
RW
RO
If set to 1, enables the strobe to interrupt the controller
for checking the temperature limits.
Unused; always write as 0.
[7:3]
00000BIN
© 2016 Integrated Device Technology, Inc.
83
January 29, 2016
ZSSC1956 Datasheet
3.8.3.31. Register “adcGomd” – Reference Voltage and SDM Configuration
Table 3.55 Register adcGomd
Name
Address
Bits
Default
Access
Description
vrefSel
[1:0]
00BIN
RW
Selection of the voltage reference:
00BIN vbgh (high precision bandgap)
01BIN vbgl (low power bandgap)
10BIN vcm (common mode voltage)
11BIN External reference voltage
sdmChopClkDiv
sdmSetup
[3:2]
[7:4]
00BIN
RW
RW
Divider value for the chop clock related to the SDM
clock. See equation (5) in section 3.8.1.1 for the FP
state and equation (8) in section 3.8.1.2 for the
LP/ULP state.
Configuration of the initial setup procedure:
0000BIN Execute 4 SDM clock cycles
0001BIN Execute 8 SDM clock cycles
…
50HEX
0001BIN
0111BIN Execute 512 SDM clock cycles
1000BIN Execute 1024 SDM clock cycles
to
1111BIN
3.8.3.32. Register “adcSamp” – Oversampling and Filter Configuration
Table 3.56 Register adcSamp
Name
Address
Bits
Default
Access
Description
osr
[1:0]
00BIN
RW
Oversampling rate:
00BIN
01BIN
10BIN
11BIN
0
1
2
3
256x oversampling
128x oversampling
64x oversampling
32x oversampling
Unused
avgFiltCfg
[2]
[4:3]
0BIN
00BIN
RO
RW
Unused; always write as 0.
Configuration of post filter (averaging filter) :
00BIN
No averaging
01BIN
10BIN 2-stage averaging filter
11BIN 3-stage averaging filter
51HEX
chopPause
[5]
0BIN
RW
Length of pause in chopping mode:
0
1
8 SDM clock cycles
16 SDM clock cycles
chopShiftPhaseEn
a
[6]
[7]
0BIN
RW
RO
0: Chopping clock is at positive phase of modulator clock
1: Chopping clock is shifted to negative phase of
modulator clock
Unused
0BIN
Unused; always write as 0.
© 2016 Integrated Device Technology, Inc.
84
January 29, 2016
ZSSC1956 Datasheet
3.8.4.
ADC Control and Conversion Timing
In the FP state, the ADC unit is running with the 4 MHz clock derived from the HP oscillator. Its operation is fully
controlled by the MCU via register settings. In the LP or ULP state, the ADC unit is running with the 125 kHz clock
from the LP oscillator. While basic configurations for the ADC unit are taken from the register file, its operation is
fully controlled by the PMU.
3.8.4.1. ADC Operation in the FP State
Before any of the ADCs can be used in the FP state, they must be powered up by setting the pwrAdcIbit for the
current ADC and/or the pwrAdcVbit for the voltage/temperature ADC in the pwrCfgFpregister to 1 (see Table
3.18). These bits can be kept set to 1 when entering one of the power-down states as the PMU takes over the
control of the power signals.
The user can select which kind of operation will be performed by the ADCs. For this, the user can control the input
multiplexers shown in Figure 3.12 by setting the field adcModein the adcCtrlregister appropriately (see Table
3.58). The following settings are possible:
Table 3.57 adcModeSettings
adcMode
Current ADC Configuration
Voltage / Temperature ADC Configuration
Current
INP/INN
Current
INP/INN
Current
INP/INN
Voltage
0
Divided VBAT/VSSA
External temperature
VDDA/NTH and NTH/NTL
Internal temperature
VPTAT/VREF
1
2
3
4
5
6
7
Offset Calibration Mode; shortened inputs
VCM/VCM
VCM/VCM
Gain Calibration Mode at maximum (positive) input
VREF / VSSA *
VREF/VSSA
Gain Calibration Mode at minimum (negative) input
VSSA / VREF *
1 mV internal test voltage
1 mV/VSSA
VSSA / VREF
Voltage
Divided VBAT/VSSA
Test Mode; each multiplexer is individually controlled by the following:
cSelfield in adcChanregister vtSelfield in adcChanregister
* Note: The two Gain Calibration Modes cause an ADC over-range error in the current ADC as the minimum gain
of PGA2 is 4. Therefore these modes are not usable for the current ADC.
After setting the desired mode of operation, the user must start the conversion by setting the startAdcC bit in
the adcCtrl register (see Table 3.58) for the current channel and/or the startAdcV bit for the
voltage/temperature channel to 1. After an initial setup phase, measurement results are stored in the
corresponding result registers. By controlling the startAdc bits, the user is able to generate an individual
conversion sequence (ADC operation stops after one conversion sequence has finished) or continuous
conversion (ADC operation continues after one conversion sequence has finished).
© 2016 Integrated Device Technology, Inc.
85
January 29, 2016
ZSSC1956 Datasheet
A conversion sequence is defined as a series of several measurements. The number of measurements to be
performed is controlled by the result counter functionality, so it is possible to have multiple measurements per
conversion sequence (MRCS) or just a single measurement (SRCS). At the end of one conversion sequence, the
“set interrupt” strobe for the corresponding conversion interrupt ready status bit (irqStat[7:5]) is generated.
Although this strobe is only generated after the last measurement within an MRCS, each measurement in the
MRCS is used for accumulation and min/max determination.
Note: The MRCS functionality is only available for current and voltage measurements, not for temperature
measurements.
To perform an individual conversion sequence for SRCS or MRCS, the user must generate a strobe signal on the
corresponding startAdcbit by setting the startAdcbit to 1 (rising edge) first and then to 0 (falling edge). The
rising edge of startAdc signals the ADC to start the conversion. On this start signal, the corresponding
adcActiveflag is set to 1, which can be read from bits 4 and/or 5 in the SSW. When the conversion sequence
has finished, the corresponding ready signal is generated. At that time, the internal logic evaluates the status of
the startAdc bit again. If it was cleared already as required for an individual conversion sequence, the ADC
stops its operation and clears the adcActiveflag. This behavior is shown in Figure 3.22 and Figure 3.23.
Figure 3.22 Individual SRCS
startAdc
adcActive
ready
result
a
Setup Time and Single
Measurement
Note that the ADC stops since startAdcis low at the end of the conversion sequence for the individual SRCS.
Figure 3.23 Individual MRCS (Example for Result Counter of 3)
startAdc
adcActive
ready
result
a
b
c
Setup Time and Single
Measurement
Single Measurement
Note that the ADC stops since startAdcis low at the end of the conversion sequence for an individual MRCS.
Important: The ready strobe shown in Figure 3.22 and Figure 3.23 is used to set the interrupt status bit, but the
interrupt status bit remains set until it is cleared by software.
© 2016 Integrated Device Technology, Inc.
86
January 29, 2016
ZSSC1956 Datasheet
To perform a continuous conversion sequence for SRCS or MRCS, the user must set the corresponding
startAdc bit to 1 (rising edge). The rising edge of startAdc signals the ADC to start the conversion. On this
start signal, the corresponding adcActiveflag is set to 1, which can be read from bits 4 and 5 in the SSW. When
one conversion sequence has finished, the corresponding ready signal is generated. At that time, the internal
logic evaluates the status of the startAdc bit again. As the startAdc bit is still 1, the ADC continues its
operation but without the need for the setup time. This behavior is shown in Figure 3.24 and Figure 3.25.
Figure 3.24 Continuous SRCS
startAdc
adcActive
ready
result
a
b
c
d
Setup Time and Single
Measurement
Single Measurement
Note that the ADC continues since startAdc is high at the end of the conversion sequence for a continuous
SRCS.
Figure 3.25 Continuous MRCS (Example for Result Counter of 3)
startAdc
adcActive
ready
result
a
b
c
d
e
f
g
Setup Time and Single
Measurement
Single Measurement
Note that the ADC continues since startAdc is high at the end of the conversion sequence for a continuous
MRCS.
When a continuous conversion sequence is performed that will be stopped after the present active conversion
sequence has completed, the user only needs to clear the startAdcbit of the channel that will be stopped. Then
the user can either wait for the next interrupt, which will be set by the last ready strobe, or check the
corresponding adcActivebit in the SSW.
© 2016 Integrated Device Technology, Inc.
87
January 29, 2016
ZSSC1956 Datasheet
Figure 3.26 Stopping Continuous SRCS
startAdc
adcActive
ready
result
d
e
f
g
h
i
j
Single Measurement
Note that the ADC stops since startAdcis low at the end of the conversion sequence for a continuous SRCS.
When a conversion sequence is performed that will be interrupted (stopped immediately), the user must clear the
startAdc bit of the channel that will be stopped (when set) and must set the stopAdc bit in the adcCtrl
register to 1. In the ADC unit, the stopAdcbit is only evaluated when the startAdcbit of a channel is low and
the corresponding adcActivebit is high.
Figure 3.27 Stopping Continuous MRCS (Example for Result Counter of 3)
startAdc
adcActive
ready
result
b
c
d
e
f
g
h
i
Single Measurement
Note that the ADC stops since startAdcis low at the end of the conversion sequence for a continuous MRCS;
otherwise the stopAdc bit is ignored. Therefore there is only one stopAdc bit that is used for both channels.
This allows the user to stop both channels by clearing both startAdc bits when setting the stopAdc bit or to
stop only one channel by keeping one startAdcbit high.
© 2016 Integrated Device Technology, Inc.
88
January 29, 2016
ZSSC1956 Datasheet
The signal behavior for interrupting a channel is shown in Figure 3.28 and Figure 3.29.
Figure 3.28 Interrupting a Continuous SRCS
startAdc
stopAdc
adcActive
ready
result
d
e
f
g
h
i
Single Measurement
Note that the ADC immediately stops since startAdcis low and stopAdc is high.
Figure 3.29 Interrupting a Continuous MRCS (Example for Result Counter of 3)
startAdc
stopAdc
adcActive
ready
result
b
c
d
e
f
g
Single Measurement
Note that the ADC immediately stops since startAdcis low and stopAdcis high.
Important: The stopAdcbit is only evaluated when startAdcbit is low.
Note: The interrupt sequence shown in Figure 3.28 and Figure 3.29 is also performed by the PMU on transition
from the FP state to any power-down state as well as on transition from any power-down state to the FP state.
This allows the user to keep the startAdc bits set on transition to any power-down state. After wake-up, the
ADCs continue the operation they performed before going to power-down.
Most of the register settings that influence both ADC channels (e.g., oversampling rate) can only be changed
when both ADC channels are inactive. As explained above, this is not true for the stopAdc bit. The adcMode
field can also be changed while any ADC channel is active. This is useful for continuing with current
measurements in the first ADC channel while changing the second ADC channel from voltage to temperature
measurements (as an example). On the rising edge of its startAdcbit, each ADC channel stores internally the
mode it is configured for and keeps this setting until the next rising edge of its startAdcbit.
© 2016 Integrated Device Technology, Inc.
89
January 29, 2016
ZSSC1956 Datasheet
When one channel is reconfigured while the other one is active, this channel does not start immediately after
being re-enabled but synchronizes to the active channel so that the results are generated at the same time. This
is shown in Figure 3.30.
Figure 3.30 Signal Behavior of adcMode
adcMode (Reg)
2
0
0
startAdcC
adcMode(Adc1)
adcActive1
ready1
SetupTime
+ 1 Meas
result1
1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2
startAdcV
adcMode(Adc2)
adcActive2
ready2
0
2
Sync + Setup
Time
+ 1 Meas
Setup Time
+ 1 Meas
result2
1 2 3 4 5
0 1 2 3 4 5 6 7 8 9 0
© 2016 Integrated Device Technology, Inc.
90
January 29, 2016
ZSSC1956 Datasheet
3.8.4.2. Register “adcCtrl” – ADC Control Register
Table 3.58 Register adcCtrl
Name
startAdcC
Address
Bits
Default
Access
Description
[0]
0BIN
RW
Start signal for the current ADC; used in the FP state,
ignored in other states.
startAdcV
stopAdc
[1]
[2]
0BIN
0BIN
RW
RW
RW
Start signal for the voltage ADC; used in the FP state,
ignored in other states.
Stop signal for both ADCs; used in the FP state,
ignored in other states.
ADC multiplexer configuration; used in the FP state,
ignored in other states; for settings 0, 1, 2, and 6, the
first value is applied to the current ADC, the second to
the voltage ADC.
adcMode
[5:3]
000BIN
0
1
2
3
4
5
6
7
Measure current and voltage
Measure current and external temperature
Measure current and internal temperature
Offset calibration
Gain calibration at maximum (positive) input
Gain calibration at minimum (negative) input
Internal test voltage and voltage
Test Mode (control multiplexer via the
adcChanregister’s cSeland vtSel
fields)
56HEX
chopEna
Unused
[6]
[7]
0BIN
0BIN
RW
RO
If set to 1, Chopping Mode is enabled.
Unused; always write as 0.
3.8.4.3. ADC Operation in LP / ULP State
During the LP or ULP state, the ADCs are fully controlled by the PMU depending on the settings of register
pwrCfgLp (see Table 3.19). The PMU overrides the settings of the startAdc bits, the stopAdc bit, and
adcMode field. The settings of pwrAdcI and pwrAdcV are also ignored until the system wakes up. While no
further settings are required for the continuous measurement set-ups, the user can independently configure how
many current and/or voltage measurements happen within a single measurement window. For current (the green
and orange boxes In Figure 3.6 to Figure 3.9), the number of current measurements in each window is configured
by the setting of adcCrcl. For voltage (the orange boxes in Figure 3.7 through Figure 3.9), the number of voltage
measurements in each window is configured by the setting of adcVrcl. There is always only one temperature
measurement.
Important: If an interrupt wakes up the system before the end of a measurement window, the conversion
sequence is interrupted and less than the configured number of measurements will have been completed. This
can be checked by the registers adcCrcvand adcVrcv.
© 2016 Integrated Device Technology, Inc.
91
January 29, 2016
ZSSC1956 Datasheet
3.8.4.4. ADC Conversion Timing
The complete conversion process is controlled by an internal state machine that guarantees that only valid
measurement results are used. The base for all ADC timings is the SDM clock, which is generated from the 4MHz
clock in FP state or from the 125kHz clock in LP and ULP state. After the ADC measurement has been started
(rising edge of startAdc), the state machine always introduces a configurable number of SDM clock cycles (field
sdmSetup in register adcGomd) to allow the analog part of the SDM to settle. After this delay, the incoming bit
streams are used to fill the sinc4 decimation filter. This lasts 4 times the sample rate, which is configured by the
oversampling rate (the osrfield in register adcSamp). Then the first valid result value comes from the decimation
filter.
Figure 3.31 Timing for Current, Voltage, and Internal Temperature Measurements without Chopping for
Different Configurations of the Average Filter
sdmSetup
startAdc
Sample Rate tS
Time to Fill Filter: 4 * tS
Conversion
Result (no avg)
M(tN)
M(tN+1
)
M(tN+2
M(tN+1
M(tN)
)
M(tN+3
M(tN+2
M(tN+1
)
)
)
M(tN+4
M(tN+3
M(tN+2
)
)
)
M(tN+5
M(tN+4
M(tN+3
)
)
)
ready (no avg)
Time to Fill Filter: 5 * tS
Conversion
Result (2x avg)
M(tN)
)
ready (2x avg)
Time to Fill Filter: 6 * tS
Conversion
Result (3x avg)
ready (3x avg)
M = measurement; t = time
For current, voltage, or internal temperature measurement without chopping, when only one input source must be
measured, this is the first valid value. The time when the first valid result is present also depends on the
configuration of the average filter (the avgFiltCfg field in register adcSamp). If no averaging is used, the first
valid value is also the first valid result stored in adcCdat, adcVdat, or adcTdat. For the 2-stage or 3-stage
average filter, respectively, two or three valid values are needed to calculate a valid result. This adds an additional
delay, respectively, of 1 or 2 times the sample rate.
© 2016 Integrated Device Technology, Inc.
92
January 29, 2016
ZSSC1956 Datasheet
For external temperature measurement without chopping, two input sources must be measured: the voltage drop
over the reference resistor (the result is stored in register adcRdat) and the voltage drop over the NTC resistor
(result stored in register adcTdat). The sdmSetup time is only introduced at the beginning of the conversion
sequence (the rising edge of startAdc). Each single measurement of one of the two values needs 4 times the
sample rate when averaging is disabled, or respectively, 5 or 6 times the sample rate when using the 2-stage or
3-stage average filter. This also means that a complete pair of values used to calculate one external temperature
value needs 8 (10 or 12 for averaging) times the sample rate because for each value, the pipeline of the sinc4
decimation filter must be filled first.
Figure 3.32 Timing for External Temperature Measurements without Chopping when No Average
Filter is Enabled
sdmSetup
startAdc
ref_not_ntc
conversion
result (no avg)
adcTdat
MNTC(tN)
MNTC(tN+1
)
MNTC(tN+2)
adcRdat
MREF(tN)
MREF(tN+1
)
MREF(tN+2)
ready (no avg)
M = measurement; t = time
Note that using an average filter will lead, respectively, to 5 and 6 conversion results during each high and low
phase of ref_not_ntc.
The timings shown in the previous two figures are without chopping, which means that the differential input signal
is always applied in the same manner to the analog SDM-ADC. Although this kind of measurement is fast (one
result value after each sample time), it has the drawback that it also converts any offset present in the analog
blocks. This would lead to less accurate measurement results. To overcome this, chopping can be enabled (bit
chopEna in register adcCtrl). When chopping is enabled, the differential input signal is directly applied to the
analog SDM-ADC the first time and inverted the second time. Taking this into account in the digital part removes
the offset applied by the ADC itself:
(
+ offset) + (-1)∗(-
+ offset)
Vin
Vin
data =
=
(15)
Vin
2
© 2016 Integrated Device Technology, Inc.
93
January 29, 2016
ZSSC1956 Datasheet
For current, voltage, or internal temperature measurement with Chopping Mode enabled (chopEnaset to 1), this
leads to a timing similar to the external temperature measurement without chopping and averaging since two
values are measured: the normal input and the inverted input. Each single measurement of one of the two values
needs 4 times the sample rate as no averaging of the single measurement is performed. Instead, the average
filter is automatically configured as a 2-stage average filter to calculate the formula above.
The second difference is that a small pause (chopping pause) is introduced each time the chop control signal
changes to allow the analog blocks to settle due to the input change. This is possible since the chopEna bit
influences both ADC paths. The length of the chop pause is either 8 or 16 SDM clock cycles, which can be
configured using the chopPausebit in register adcSamp.
Figure 3.33 Timing for Current, Voltage, and Internal Temperature Measurements using Chopping –
Example Showing Current (adcCdat)
sdmSetup
startAdc
chopPause
chop ctrl
Conversion
Result (chop)
M+
M-
M+
M-
M+
M-
M
0.5
CHP(tN) =
M
-0.5
CHP(tN+1) =
M
0.5
CHP(tN+2) =
MCHP(tN+3) =
-0.5
(M--M+)
adcCdat
(M+-M-)
(M--M+)
(M+-M-)
ready (chop)
M = measurement; t = time
For external temperature measurement using chopping, two different input sources must be measured twice, non-
inverted and inverted, which leads to four values to be measured to get a result. To keep both ADC paths aligned,
the chopPauseis introduced for each measured value.
© 2016 Integrated Device Technology, Inc.
94
January 29, 2016
ZSSC1956 Datasheet
Figure 3.34 Timing for External Temperature Measurements using Chopping
sdmSetup
startAdc
ref_not_ntc
chop ctrl
chopPause
Conversion
Result (chop)
M+
M-NTC
M+
M-REF
M+
M-NTC
M+
REF
M-REF
NTC
REF
NTC
adcTdat
0.5
(M+NTC(tN) - M-NTC(tN))
0.5
(M+NTC(tN+1) - M-NTC(tN+1))
adcRdat
0.5
(M+REF(tN) - M-REF(tN))
ready (chop)
M = measurement; t = time
Important: The timings only show the principle. Additional small delays such as pipeline delays are not included.
3.8.5. Diagnostic Features
3.8.5.1. ADC Analog Multiplexer Control for Diagnosis and Test
In the FP state, the three multiplexers shown in Figure 3.12 can be directly controlled via register adcChan when
the adcModefield in register adcCtrl is set to 7 (see Table 3.58). For other settings of adcMode, the settings of
register adcChan are ignored and both multiplexers for input selection are controlled either by the adcMode
field in FP state or by the PMU in LP or ULP state.
The vtSel field in register adcChan is used to select the input sources of the voltage/temperature ADC. The
cSel field in register adcChan is used to select the input sources of the current ADC. See Table 3.59.
Note: The reference voltage (non-inverted as well as inverted) cannot be measured by the current ADC as the
minimum gain of PGA2 is 4, which causes an ADC overrange error.
For some settings of adcMode, cSel and vtSel, the reference voltage is applied to the ADCs. The user can
select the source of the reference voltage by field vrefSel in register adcGomd (see section 3.8.3.31). As can
be seen from in Figure 3.12, the user can connect internal current sources to the input wires of INP and INN as
well as to the input wires of NTH and NTL. To enable the different current sources for the four input wires, the
corresponding enable bit in register currentSrcEna must be set to 1 (see Table 3.62).
Important Warning: Do not enable both current sources on the same input at once.
Important: The current sources can be enabled independent of the adcMode.
© 2016 Integrated Device Technology, Inc.
95
January 29, 2016
ZSSC1956 Datasheet
3.8.5.2. Register “adcChan” – Analog Multiplexer Configuration
Table 3.59 Register adcChan
Name
Address
Bits
Default
Access
Description
When adcMode == 7, this field selects the differential
vtSel
D0HEX
[2:0]
000BIN
RW
sources for the voltage/temperature ADC:
vtSel inp
inn
000BIN VDDA
001BIN NTL
NTH
NTH
010BIN VPTAT
011BIN VBATP
100BIN VBGH (i.e., VREF
VBGH (i.e., VREF
VBATN
VSSA
)
)
101BIN VBGL (i.e., VREFLP
110BIN VCM
)
VSSA
VCM
111BIN High impedance
High impedance
When adcMode== 7, this field selects the differential
cSel
[5:3]
000BIN
RW
sources for the current ADC:
000BIN INP
INN
001BIN INP
INN
010BIN INP
INN
011BIN INP
INN
100BIN 1 mV
101BIN Unused
110BIN Unused
111BIN VCM
VSSA
VCM
Unused
Unused
[6]
[7]
0BIN
0BIN
RW
RW
Unused; always write as 0
Unused; always write as 0.
3.8.6.
Digital Test Features
3.8.6.1. Built-in Self-Test (BIST)
The digital ADC BIST feature allows the user to test the digital logic of the ADC data path. The BIST feature is
enabled by setting the bistEna bit in the adcDiag register to 1 (see Table 3.61). When the BIST feature is
enabled, the same programmable bit stream is applied to both inputs of the decimation filter instead of the outputs
from the noise cancellation filters. The ADCs must also be set into operation as during normal operation.
The bit stream to be applied to the decimation filter is programmed to the lower 30 bits of register adcCaccTh.
These 30 bits function as a shift-rotate register as shown in Figure 3.35, and the output of the lowest bit is used
as the bit stream for the BIST.
Important: When register adcCaccTh is used for the BIST, the current accumulator threshold functionality
cannot be used.
© 2016 Integrated Device Technology, Inc.
96
January 29, 2016
ZSSC1956 Datasheet
Figure 3.35 Using Register adcCaccThfor the Digital ADC BIST
Bitstream
for BIST
. . .
X
X
1
0
1
0
1
0
1
0
29
28
27
26
3
2
1
0
Table 3.60 shows four example bit streams as well as the expected output stored in the corresponding data
registers adcCdat, adcVdat, adcTdat, and/or adcRdat if enabled. In these examples, the offset correction
value (e.g., register adcCoff) is set to 0; the gain correction value (e.g., register adcCgan) is set to 1.0; and the
post correction gain factor (e.g., bit field curPoCoGainin register adcPoCoGain) is set to gain factor 1 (bit field
set to 00BIN) and then to gain factor 2 (bit field set to 01BIN).
Table 3.60 Example Results of BIST
Result Data
(xPoCoGain = Gain Factor 1;
Result Data
(xPoCoGain = Gain Factor 2;
1/0 Bit
Ratio
Bit Stream
Bit Field = 00BIN
)
Bit Field = 01BIN)
100000_100000_100000_100000_100000
800000HEX
(negative over-range)
7FFFFFHEX
(positive over-range)
1/6
5/6
2/5
3/5
AAAAAAHEX
(20820820HEX
111110_111110_111110_111110_111110
(3EFBEFBEHEX
10010_10010_10010_10010_10010_10010
(25294A52HEX
10110_10110_10110_10110_10110_10110
(2D6B5AD6HEX
)
555555HEX
E66666HEX
199999HEX
)
CCCCCCHEX
333332HEX
)
)
3.8.6.2. Decimation Filter Output Test
The decimation filter output test allows the user to observe the outputs of both decimation filters. This feature is
enabled by setting bit rawEnain register adcDiagto 1 (see Table 3.61). When this feature is enabled, the 32-bit
output value of the decimation filter for the current ADC is stored in registers adcCmax (MSBs; see Table 3.48)
and adcCmin(LSBs; see Table 3.49) and the 32 bit output value of the decimation filter for the voltage/tempera-
ture ADC is stored in registers adcVmax (MSBs; see Table 3.50) and adcVmin (LSBs; see Table 3.51). The
ADCs must also be set into operation as during normal operation.
Note: When this feature is enabled, all normal ADC operations described in the previous sections function as
described except the minimum and maximum functionality for the current and voltage values as the registers are
used for this test function.
Note: This feature can be combined with the digital ADC BIST feature.
© 2016 Integrated Device Technology, Inc.
97
January 29, 2016
ZSSC1956 Datasheet
3.8.6.3. ADC Interface Test
The ADC interface test allows the user to observe the incoming 2nd and 3rd order bit streams from both analog
parts of the SD-ADCs. This feature is enabled by setting bit adcIfTestEnain register adcDiagto 1. The digital
part of the ADC unit must be enabled as for normal operation as it generates the correct sample strobe for the
test logic. This function is only available in the FP state as it runs on the 20MHz clock from the high-precision
oscillator. All sampled values (4 bits) are shifted out of the STO pad. To enable the user to synchronize on the
sampled data, a 1 and a 0 are shifted out before each 4-bit value as shown in Table 3.37.
Figure 3.36 Bit Stream of ADC Interface Test at STO Pad
2nd
I
3rd I 2nd V 3rd V
Note: This feature can be combined with the digital ADC BIST feature as well as with the decimation filter output
test.
3.8.6.4. Register “adcDiag” – Enable Register for Test and Diagnosis Features
Table 3.61 Register adcDiag
Name
bistEna
rawEna
Address
Bits
Default
Access
Description
If set to 1, enables BIST.
If set to 1, enables the decimation filter output test (ADC
raw data test).
[0]
[1]
0BIN
0BIN
RW
RW
adcIfTestEna
Unused
[2]
[5:3]
0BIN
000BIN
RW
RW
If set to 1, enables the serial ADC test.
Unused; always write as 0.
D1HEX
stopClkChop
[6]
0BIN
RW
Disable signal for the chop clock generation in the digital
section.
clkChopEna
[7]
1BIN
RW
Enable signal for the chop clock used partially in the
analog section.
3.8.6.5. Register “currentSrcEna” – Enable Register for Current Source
Table 3.62 Register currentSrcEna
Name
Address
Bits
Default
Access
Description
inampInpSrcEna
Unused
inampInnSrcEna
Unused
[0]
[1]
[2]
[3]
0BIN
0BIN
0BIN
0BIN
RW
RW
RW
RW
Enable 50µA current source to INP
Unused; always write as 0
Enable 50µA current source to INN
Unused; always write as 0
psrcEnVbat
psinkEnVbat
nsrcEnVbat
nsinkEnVbat
[4]
[5]
[6]
[7]
0BIN
0BIN
0BIN
0BIN
RW
RW
RW
RW
Enable 50µA current source on NTH
Enable -50µA current source on NTH
Enable 50µA current source on NTL
Enable -50µA current source on NTL
D2HEX
© 2016 Integrated Device Technology, Inc.
98
January 29, 2016
ZSSC1956 Datasheet
3.9. SBC LIN Support Logic
The LIN support logic contains only two functions – most of the LIN communication is handled by the LIN PHY on
one side and the MCU on the other side (see section 4.7). The two functions are used to handle error conditions
(TXD timeout; LIN short) and protect (force to high level) the LIN TXD line to LIN PHY if any of these errors is
detected or when the system is not in full-power state. Figure 3.37 illustrates the error protection logic discussed
in the next sections.
Figure 3.37 Protection Logic of the LIN TXD Line
detLinShort
detTxdTimeout
O
R
FP state (PMU)
&
txdProtDis (register file)
TXD (IBS-MCU)
O
R
LIN-TXD
(LIN-PHY)
3.9.1.
LIN Wakeup Detection
A LIN master generates a LIN wakeup frame by driving a dominant value of 0 of at least 250μs on the LIN bus.
The standard requires that a LIN slave shall recognize a LIN wakeup when the LIN bus is low for more than
150μs.
There is a 6-bit counter running with the 125kHz LP clock implemented in the IBS-SBC to support the LIN wakeup
detection. When the function is disabled (irqEn[4] is set to 0), the counter is set to 20HEX and no interrupt can
occur. When the function is enabled (irqEn[4] is set to 1), the LIN RXD line is observed. When the LIN RXD
line is high, the counter is set to 00HEX. When the LIN RXD line becomes low, the counter is incremented in each
clock cycle until it reaches the value 20HEX where it stops incrementing. When the counter is equal to the
programmed wakeup delay (register linWuDelay; see Table 3.66), a set strobe for the corresponding interrupt is
generated, which causes the system to wake up.
The register linWuDelay has a default value of 14HEX. This setting guarantees that no low level less than 150μs
on the LIN RXD line causes a wakeup due to the inaccuracy of the LP oscillator.
© 2016 Integrated Device Technology, Inc.
99
January 29, 2016
ZSSC1956 Datasheet
3.9.2.
TXD Timeout Detection
The digital LIN controller in the MCU ensures that it does not completely block the LIN bus due to continuously
transmitting a dominant value of 0. As it is still possible that the TXD line from the MCU could be stuck at 0 due to
a software or hardware error in the MCU or a broken connection between the two chips, the LIN support logic
observes the TXD line in full-power (FP) state to detect if the TXD line is erroneously low. Because the digital LIN
controller of the MCU is built for baud rates down to 1kBaud, the maximum time that the digital LIN controller
(slave device!) is transmitting a low level is 9ms (start bit and 8 data bits). To overcome inaccuracies of the
internal clocks, the internal logic and untrimmed LIN nodes, the timeout value is 10.24ms. On detection of a TXD
timeout, an internal flag (detTxdTimeoutin Figure 3.37) is set to the high level, which forces the LIN TXD line to
1, and the corresponding interrupt status (irqStat[2]) is set. While the interrupt status bit is cleared on read
access to the interrupt status register, the internal flag remains high, also keeping LIN TXD at the high level. The
status of the internal flag is mirrored in SSW[2]. To clear this internal flag and to be able to transmit again via the
LIN bus, a value of 1 must be written to bit clrTxdTimeoutin register linCfg(see Table 3.63).
3.9.3.
LIN Short Detection
The LIN PHY contains a function to detect a short to VBAT on the LIN bus by sensing the current through the
open-drain output transistor in the LIN PHY. When the current is too high, the LIN PHY drives the SHORT signal
going to the digital block to the high level (see Figure 3.38). Under normal circumstances, the LIN PHY signals a
short only if a dominant value of 0 will be transmitted, but the bus remains at its recessive high level. However,
high current consumption is also possible due to EMC events. To increase the safety of the system and to avoid
misinterpretation, the incoming SHORT signal is gated and filtered.
First, the SHORT signal from the LIN PHY is driven through a configurable gating block in the digital block. The
gating block is configured using register linShortDelay(see Table 3.65). If register linShortDelayis set to
a value not equal to 0, the TXD line going to and the RXD line coming from the LIN PHY are observed. When the
TXD line becomes low while the RXD line remains high, the gating block waits for linShortDelaytimes 4MHz
clock cycles before opening the gate. The gate is closed when either TXD becomes high again or RXD becomes
low (see Figure 3.38). This feature is used to evaluate the SHORT signal only when a dominant value of 0 is
transmitted but the bus remains at its recessive high level as well as to eliminate the delay from the TXD line
through the LIN PHY back to the RXD line.
Figure 3.38 Waveform Showing the Gating Principle for Non-zero Values of linShortDelay
TXD
RXD
en gate
linShortDelay x 250ns
gated SHORT
When the register linShortDelayis set to 0, the gate for the SHORT signal is always open. This means that
the SHORT signal is always passed through the gating block even when the TXD line is high or the RXD line is
low.
© 2016 Integrated Device Technology, Inc.
100
January 29, 2016
ZSSC1956 Datasheet
The gated SHORT signal is applied to a configurable de-bouncing filter. This de-bouncing filter is configured using
register linShortFilter (see Table 3.64), and it observes the gated SHORT signal using the internal 4MHz
clock. When the gated SHORT signal is continuously high for (linShortFilter + 1) clock cycles, the LIN
short interrupt status bit (irqStat[3]) is set, enabling the software running on the MCU to respond to this
situation. The interrupt status bit is cleared on read access to the interrupt status register.
The software can also enable the hardware to protect the TXD line in case of a detected short condition. When
the shortProtEnabit in register linCfg(see Table 3.63) is set to 1 and a short condition is detected by the de-
bouncing filter, an internal flag (detLinShortin Figure 3.37) is set to the high level, which forces the LIN TXD
line high. The status of the internal flag is mirrored in SSW[3]. The internal flag remains high until it is explicitly
cleared by the software by writing a value of 1 to the clrLinShortbit in register linCfg.
3.9.4.
LIN Testing
The LIN TXD line protection features (TXD timeout, LIN short, low-power (LP) state) might restrict the possibility
of testing the LIN PHY. Therefore the protection can be disabled (see Figure 3.7) by setting the txdProtDisbit
in register linCfgto 1.
Important Warning: This must never be done during normal operation (the IC will not be damaged, but commun-
ication errors are not detected).
3.9.4.1. Register “linCfg” – LIN Configuration Register
Table 3.63 Register linCfg
Name
Address
Bits
Default
Access
Description
linFastEna
[0]
0BIN
RW
When set to 1, the slew rate control in the LIN PHY
transmitter is disabled allowing higher LIN data rates of up
to 125kBaud (non-standard feature).
txdProtDis
[1]
0BIN
RW
When set to 1, all protection features that force the LIN
TXD line to 1 are overwritten (for test purposes only).
shortProtEna
Unused
clrTxdTimeout
[2]
[3]
[4]
0BIN
0BIN
0BIN
RW
RO
RWS
If set to 1, enables the LIN short protection.
Unused; always write as 0.
Strobe register; write 1 to clear the detected TXD timeout
flag and to release the protection of the LIN TXD line.
B4HEX
clrLinShort
Unused
[5]
0BIN
RWS
RO
Strobe register; write 1 to clear the detected LIN SHORT
flag and to release the protection of the LIN TXD line.
Unused; always write as 0.
[7:6]
00BIN
© 2016 Integrated Device Technology, Inc.
101
January 29, 2016
ZSSC1956 Datasheet
3.9.4.2. Register “linShortFilter” –Configuration Register for the LIN Short De-bounce Filter
Table 3.64 Register linShortFilter
Name
Address
Bits
Default
Access
Description
linShortFilter
B5HEX
[7:0]
0FHEX
RW
Filter configuration for the LIN short detector.
This register defines the number of 4MHz clock cycles
(linShortFilter+ 1) where the gated LIN SHORT
signal in the LIN PHY must be high to detect a SHORT
condition on the LIN bus.
3.9.4.3. Register “linShortDelay” – Configuration Register LIN Short TX-RX Delay
Table 3.65 Register linShortDelay
Name
Address
Bits
Default
Access
Description
linShortDelay
B6HEX
[7:0]
4FHEX
RW
Delay configuration for gating the LIN SHORT signal.
This register defines the number of 4MHz clock cycles
where TXD is low and RXD is high before the gating
logic of the LIN SHORT signal from the LIN PHY is
removed. When RXD becomes low or TXD becomes
high, the gating logic is reactivated.
Note: when linShortDelayis set to 0, the TXD and
RXD levels are ignored and the LIN SHORT signal is
not gated.
3.9.4.4. Register “linWuDelay” – Configuration Register for LIN Wakeup Time
Table 3.66 Register linWuDelay
Name
linWuDelay
Address
Bits
Default
Access
Description
[4:0]
10100BIN
RW
LIN wakeup time.
This register defines the number of 125 kHz clock
cycles where LIN-RXD must be low before a LIN
wakeup conditions is detected.
B7HEX
Important Warning: Do not set to 0.
Unused
[7:5]
000BIN
RO
Unused; always write as 0
3.10. SBC OTP
There is a 32x8 bit OTP integrated in the SBC that contains the required trimming data as well as the traceability
information. The default (erased) state of the OTP cells is 0. Because some of the programmed trim bits are
critical for operation, such as the voltage trim bits, redundancy is implemented for the lower quarter of the OTP
memory. This part of the OTP contains only up to four bits of information that are programmed to bits [3:0] as well
as to bits [7:4]. During the download procedure, the correct content is determined by combining bit 0 and bit 4, bit
1 and bit 5, bit 2 and bit 6, and bit 3 and bit 7 via an OR gate.
© 2016 Integrated Device Technology, Inc.
102
January 29, 2016
ZSSC1956 Datasheet
Table 3.67 OTP Memory Map
OTP
SPI
Copy
to Reg.
Redun- Byte
dancy Order
Name
Size
Description
[0]: OTP content valid
Address Address
OTP_VALID
LIN_TRIM
00HEX
01HEX
02HEX
E0HEX
E1HEX
E2HEX
0
No
Yes
Yes
Yes
---
---
---
3:0
3:0
Yes
Yes
[3:0]: IBIAS_LIN_TRIM[3:0]
VDD_TRIM
[0]: VDDC trim bit
[1]: VDDP trim bit
[3:2]: vbgh_trim[1:0]
BG_TRIM
03HEX
04HEX
05HEX
E3HEX
E4HEX
E5HEX
3:0
3:0
3:0
Yes
Yes
Yes
Yes
Yes
Yes
---
[3:0]: vbgh_trim[5:2]
IREF_OSC_0
IREF_OSC_1
LSB
[3:0]: IREF_OSC_TC_TRIM[3:0]
MSB
LSB
[0]: IREF_OSC_TC_TRIM[4]
[2]: IBIAS_LIN_TRIM[4]
[3]: IREF_OSC_TRIM[0]
IREF_OSC_2
IREF_OSC_3
IREF_LP_OSC
ADCCGAN_0
ADCCGAN_1
ADCCGAN_2
ADCCOFF_0
ADCCOFF_1
ADCCOFF_2
ADCVGAN_0
ADCVGAN_1
ADCVGAN_2
ADCVOFF_0
ADCVOFF_1
ADCVOFF_2
ADCTGAN_0
ADCTGAN_1
06HEX
07HEX
08HEX
09HEX
0AHEX
0BHEX
0CHEX
0DHEX
0EHEX
0FHEX
10HEX
11HEX
12HEX
13HEX
14HEX
15HEX
16HEX
E6HEX
E7HEX
E8HEX
E9HEX
EAHEX
EBHEX
ECHEX
EDHEX
EEHEX
EFHEX
F0HEX
F1HEX
F2HEX
F3HEX
F4HEX
F5HEX
F6HEX
3:0
3:0
6:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
---
MSB
---
[3:0]: IREF_OSC_TRIM[4:1]
[3:0]: IREF_OSC_TRIM[8:5]
Trim value for the low-power oscillator
LSB
---
Gain for the current measurement
Offset for the current measurement
Gain for the voltage measurement
Offset for the voltage measurement
MSB
LSB
---
MSB
LSB
---
MSB
LSB
---
MSB
LSB
MSB
Gain for the temperature measurement
Offset for the temperature measurement
ADCTOFF_0
ADCTOFF_1
17HEX
18HEX
F7HEX
F8HEX
7:0
7:0
Yes
Yes
No
No
LSB
MSB
---
19HEX
1AHEX
F9HEX
FAHEX
---
7:0
No
No
No
No
---
LSB
Unused
LOT_ID_0
Lot ID number
LOT_ID_1
1BHEX
1CHEX
1DHEX
1EHEX
1FHEX
FBHEX
FCHEX
FDHEX
FEHEX
FFHEX
7:0
7:0
7:0
7:0
7:0
No
No
No
No
No
No
No
No
No
No
MSB
LSB
MSB
LSB
MSB
WAFER_NO_0
WAFER_NO_1
DIE_POS_0
DIE_POS_1
Wafer number
Die position
© 2016 Integrated Device Technology, Inc.
103
January 29, 2016
ZSSC1956 Datasheet
After reset of the SBC, the OTP download procedure is automatically triggered. First, the OTP content is checked
for validity (“bit 0 OR bit 4” must be equal to 1). If the content is not valid, the download procedure is stopped.
Otherwise, the information stored at OTP addresses 01HEX to 18HEX is copied into the corresponding registers.
The download procedure can also be started by the user by writing the value 1 into the otpDownload bit in
register cmdExe (see Table 3.7). Special care must be taken after starting the OTP download procedure as the
system must not go to the power-down state as long as the download procedure is active. The status of the
download procedure is signaled to the user via the SSW bit 0.
In addition to being read by triggering the OTP download procedure that copies the OTP content into the
corresponding registers, the raw contents of the OTP can be read by the user via the SPI interface at SPI
addresses E0HEX to FFHEX. This might be useful for checking the content of the OTP. For the lowest quarter of the
OTP, this is useful for checking that no bit has changed its value. The user might also choose to implement
redundancy for the other values by mirroring the contents into the flash memory on the MCU.
3.11. Miscellaneous Registers
3.11.1.1. Register “pullResEna” – Pull-down Resistor Control Register
Each of the eight internal nodes CSN, SCLK, MOSI, TXD, TRSTN, TCK, TMS, and DBGEN contains a
controllable internal pull-down resistor that is active by default. The pull-down resistors are present to prevent a
floating input pin if the bonding wire gets broken and to enable the system to detect such a broken wire.
Example: If the bonding wire at TXD is broken, the pull-down resistor would drive TXD low continuously and the
LIN TXD timeout detector will trigger and inform the MCU that an error is present.
Directly behind the input pads is a secondary protection stage because VDDP is disabled in some power-down
states. The three SPI inputs to the SBC, which are CSN, SCLK and MOSI, as well as the TXD input, are only
enabled in full-power (FP) state when the MCU is powered and clocked. The DBGEN input is enabled as long as
MCU_RSTN is high (in the FP or LP state) while the three test inputs to the SBC, which are TRSTN, TCK and
TMS, are only enabled when TEST is high.
Note: Because the TEST input pad also contains a pull-down resistor, disabling the pull-down resistors for the
three test input pins is always safe as long as TEST is low.
© 2016 Integrated Device Technology, Inc.
104
January 29, 2016
ZSSC1956 Datasheet
Table 3.68 Register pullResEna
Name
Address
Bits
Default
Access
Description
pullResEnaCsn
[0]
1BIN
RW
When set to 1, the pull-down resistor in the CSN pad is
connected to the pad.
pullResEnaSpiClk
pullResEnaMosi
pullResEnaTxd
pullResEnaTrstn
pullResEnaTck
pullResEnaTms
pullResEnaDbgen
[1]
[2]
[3]
[4]
[5]
[6]
[7]
1BIN
1BIN
1BIN
1BIN
1BIN
1BIN
1BIN
RW
RW
RW
RW
RW
RW
RW
When set to 1, the pull-down resistor in the SCLK pad
is connected to the pad.
When set to 1, the pull-down resistor in the MOSI pad
is connected to the pad.
When set to 1, the pull-down resistor in the TXD pad is
connected to the pad.
When set to 1, the pull-down resistor in the TRSTN pad
is connected to the pad.
When set to 1, the pull-down resistor in the TCK pad is
connected to the pad.
When set to 1, the pull-down resistor in the TMS pad is
connected to the pad.
When set to 1, the pull-down resistor in the DBGEN
pad is connected to the pad.
B8HEX
3.11.1.2. Register “versionCode” – Version Code of SBC
The version code of the SBC is 300HEX
.
Table 3.69 Register versionCode
Name
versionCode[7:0]
versionCode[11:8]
Unused
Address
Bits
Default
Access
RO
Description
[7:0]
[3:0]
[7:4]
Version code of the SBC.
BAHEX
00HEX
0011BIN
0000BIN
RO
BBHEX
Unused; always write as 0.
RO
© 2016 Integrated Device Technology, Inc.
105
January 29, 2016
ZSSC1956 Datasheet
3.11.1.3. Register “pwrTrim” – Trim Register for the Voltage Regulators and Bandgap
Table 3.70 Register pwrTrim
Name
vddcTrim
Address
Bits
Default
Access
Description
[0]
0BIN
RW
Trim register for VDDC regulator:
0
1
VDDC is trimmed to 1.2V
VDDC is trimmed to 1.8V
Note: This register is set by the OTP download
procedure when the OTP content is valid.
vddpTrim
vbghTrim
[1]
0BIN
RW
RW
Trim register for the VDDP regulator:
C0HEX
0
1
VDDP is trimmed to 2.5V
VDDP is trimmed to 3.3V
Note: This register is set by the OTP download
procedure when the OTP content is valid.
011111BIN
[7:2]
Trim register for the high-precision bandgap.
Note: This register is set by the OTP download
procedure when OTP content is valid.
Important Warning: Changing the settings of bits vddcTrimand vddpTrimcan cause damage to the MCU or
cause malfunction of the MCU.
3.11.1.4. Register “ibiasLinTrim” – Trim Register for the Bias Current of the LIN Block
Table 3.71 Register ibiasLinTrim
Name
ibiasLinTrim
Address
Bits
Default
Access
Description
[4:0]
10000BIN
RW
Trim register for the bias current of the LIN block:
0
1
Smallest value
Largest value
C3HEX
Note: This register is set by the OTP download
procedure when OTP contents are valid.
Unused
[7:5]
000BIN
RO
Unused; always write as 0.
© 2016 Integrated Device Technology, Inc.
106
January 29, 2016
ZSSC1956 Datasheet
3.12. Voltage Regulators
In addition to the battery voltage (VBAT), four additional voltage domains are implemented in the ZSSC1956: the
analog voltage VDDA, the digital voltage for low-power mode (VDDL) for the SBC and the RAM of the MCU, the
supply voltage (VDDP) for the I/Os of the SBC and the MCU, and the supply voltage (VDDC) for the core of the
MCU. The regulators are low-dropout regulators (LDO). The VDDL regulator, which is active in the low-power
states, has very low power consumption.
3.12.1. VDDE
The following blocks are connected directly to the VDDE power supply:
•
•
•
•
•
•
•
•
Low-power bandgap
High-precision bandgap
High-precision oscillator
POR
Regulator for VDDA
Regulator for VDDL
Regulator for VDDC
Regulator for VDDP
3.12.2. VDDA
The analog regulator provides a 2.5V output and can drive up to 10mA of load current. The output voltage is
continuously regulated with respect to the bandgap voltage (vbgh). A resistor chain generates the appropriate
voltage for the feedback comparison with the bandgap voltage so that the correct voltage is generated. This
internal regulated voltage serves as a supply voltage for the analog blocks. The analog regulator can be switched
off (e.g., in Sleep Mode).
The following blocks are connected directly to the VDDA analog power supply:
•
•
•
•
•
•
•
Level-Shifter
PGA
Divider
Temperature Measurement
SD-ADC Channel 1 (current)
SD-ADC Channel 2 (voltage and temperature)
All blocks necessary for data acquisition (current, voltage and temperature)
© 2016 Integrated Device Technology, Inc.
107
January 29, 2016
ZSSC1956 Datasheet
3.12.3. VDDL
The VDDL regulator provides the necessary supply voltage for the low-power domain and the digital core (1.8V,
typical). It is permanently connected to the external supply rail and is always switched on until there is enough
voltage on it. The load capabilities depend on the value of the supply voltage as follows:
Table 3.72 VDDL Regulator Load Capabilities
Supply Voltage VDDE
VDDE ≥ 3.5V
Load Current Capability
Load current ≤ 6mA
2.0V ≤ VDDE < 3.5V
1.65V ≤ VDDE < 2.0V
Load current ≤ 100µA (guaranteed nominal output voltage)
Load current ≤ 100µA (guaranteed output voltage above 1.6V)
The regulator supports an IDDQ Test Mode during which its output is fully isolated from the rest of the circuit.
Another supported mode is the Low-Power Mode during which the current consumption of the regulator is
reduced. Additional circuitry is added for over-voltage protection of the output.
The following blocks are connected directly to VDDL:
•
•
•
•
LIN 2.1
Power Management Unit (supply for flash memory/microcontroller)
Control Register for the ADCs
Watchdog
3.12.4. VDDP
The peripheral regulator provides 3.3V. The VDDP regulator can drive up to 30mA of load current and can be
switched off (e.g., in Sleep Mode).
The I/O blocks of the SBC and the MCU are connected directly to VDDP.
3.12.5. VDDC
The core regulator provides 1.8V. This regulator can drive up to 40mA of load current and can be switched off
(e.g., in Sleep Mode).
The MCU core block is connected directly to VDDC.
© 2016 Integrated Device Technology, Inc.
108
January 29, 2016
ZSSC1956 Datasheet
4
Functional Block Descriptions for the MCU
4.1. Introduction
The MCU contains an ARM® subsystem, memories (FLASH, RAM, and ROM), and several peripherals for
external communication as well as an interface to the SBC. A simplified block diagram is shown in section 2.3,
which illustrates the included blocks.
The ARM® subsystem is comprised of the following blocks:
•
•
Cortex™-M0* processor
Debug controller including
o
o
o
JTAG interface
4 hardware break-point comparators
2 hardware watch-point comparators
•
Interrupt controller (NVIC) providing the non-maskable interrupt (NMI) and 9 interrupt lines:
o
o
o
o
o
o
o
o
o
Interrupt line 0: flash controller interrupt
Interrupt line 1: external interrupt (from SBC)
Interrupt line 2: ahbLIN interrupt
Interrupt line 3: SPIB8 interrupt
Interrupt line 4: 32-bit timer interrupt
level-sensitive
level-sensitive
level-sensitive
level-sensitive
pulse
level-sensitive
level-sensitive
level-sensitive
level-sensitive
Interrupt line 5: GPIO interrupt
Interrupt line 6: SPI2 interrupt (from ZSYSTEM2)
Interrupt line 7: USART interrupt (from ZSYSTEM2)
Interrupt line 8: I²C™ interrupt (from ZSYSTEM2)
•
•
System timer (SysTick)
Fast single-cycle multiplier
For details about usage of the ARM® subsystem, see the IDT ARM® CortexTM M0 User Guide and refer to
technical documents available from ARM, Ltd.
4.2. Memory Structure
There are two different kinds of physical memory integrated in the MCU: a 96kB flash and an 8kB SRAM block.
The peripherals and the required ROM table are also mapped into the memory space. A default slave replies with
an error response when unused parts of the memory space are accessed. By default, the flash is mirrored to
address 0000 0000HEX. Software can change this and mirror the SRAM to address 0000 0000HEX instead by writing
to the memSwapfield in register SYS_MEMPORTCFG (see Table 4.6).
* ARM® is a registered trademark of ARM Limited. Cortex™ is a trademark of ARM Limited.
© 2016 Integrated Device Technology, Inc.
109
January 29, 2016
ZSSC1956 Datasheet
4.2.1.
Memory Map
Table 4.1 Address Map of MCU
Address
Description
Reserved
FFFF FFFFHEX
F000 1000HEX
F000 0FFFHEX
F000 0000HEX
EFFF FFFFHEX
E010 0000HEX
E00F FFFFHEX
E000 0000HEX
DFFF FFFFHEX
6000 0000HEX
5FFF FFFFHEX
4000 2400HEX
4000 23FFHEX
4000 2000HEX
4000 1FFFHEX
4000 1C00HEX
4000 1BFFHEX
4000 1800HEX
4000 17FFHEX
4000 1400HEX
4000 13FFHEX
4000 1000HEX
4000 0FFFHEX
4000 0C00HEX
4000 0BFFHEX
4000 0800HEX
4000 07FFHEX
4000 0400HEX
4000 03FFHEX
4000 0000HEX
3FFF FFFFHEX
2000 2000HEX
2000 1FFFHEX
2000 0000HEX
1FFF FFFFHEX
1001 8000HEX
1001 7FFFHEX
1000 0000HEX
0FFF FFFFHEX
0001 8000HEX
0001 7FFFHEX
0000 0000HEX
System ROM Table
Reserved
Private Peripheral Bus; see ARM® documentation for details
Reserved
Reserved
SPIB8
ZSYSTEM2 (SPI2, USART, I²C™†)
ahbLIN
GPIO
32-Bit Timer
Flash Info Page
Flash Controller
Reserved
System Management Unit
Reserved
SRAM
Reserved
Flash
Reserved
Depending on the memSwapbit, either flash memory (0) or SRAM (1) is mapped to
address 0000 0000HEX and higher.
† I²C™ is a trademark of NXP.
© 2016 Integrated Device Technology, Inc.
110
January 29, 2016
ZSSC1956 Datasheet
4.2.2.
Flash Memory
There is a 96kB flash memory integrated into the system to store the boot loader, the program code, and logging
data. As the flash memory has some dedicated timings for the control signals when erasing (part of) the flash and
when writing data to the flash, a flash controller is used for flash integration into the system to support all
mandatory operations (read, write, erase) to be performed on the different flash locations and to guarantee the
correct timings for write and erase operations. It is also checked whether the different operations are allowed to
be performed depending on the memory protection scheme.
The flash memory consists of two sections: the MAIN area and the INFO pages. Together these sections
comprise several pages of 512 bytes each. Each page has four rows, and each row contains 32 words. A flash
page is the smallest block that can be erased.
The INFO pages have a total size of 1kB while the size of the MAIN area is 96kB. Each word is protected by ECC
logic with a hamming distance of 4, which enables the system to correct a single-bit error and to detect two-bit
errors within a word. The correct ECC code bits are automatically appended on each write access to the flash.
When a single-bit error within a word is detected during a read access, it is automatically corrected.
The occurrence of bit errors is signaled via dedicated status bits in registers FC_STAT_DATA (see Table 4.18)
and FC_STAT_PROG (see Table 4.17) in the flash controller. The status bits distinguish between an erased flash
word (all1 flag), the detection and correction of a single-bit error (1Err flag), and the detection of more than one bit
error (2Err flag), which is uncorrectable.
The two status register sets are distinguished by the type of flash access:
•
FC_STAT_PROG status bits are used when errors occur during an instruction fetch.
o
An instruction fetch to an erased memory location (all1 flag set) or to a memory location with
more than one error (not correctable!) will assert an NMI as the program is corrupted.
The detection and correction of a single-bit error within a word is signaled via the normal interrupt
(ARM® interrupt line 0).
o
•
FC_STAT_DATA status bits are used when errors occur during a load operation.
o
Loads from an erased memory location as well as the detection (and correction) of errors within a
word are indicated via the normal interrupt (ARM® interrupt line 0).
4.2.2.1. MAIN Area
The MAIN area of the flash is physically located at address 1000 0000HEX and higher. It can also be mirrored to
address 0000 0000HEX by setting the memSwapbit in register SYS_MEMPORTCFG (see Table 4.6) to 0 (default
setting). The flash is split into three sections: BOOT, PROG, and LOG (see Figure 4.1). Each section comprises
multiple flash blocks of 512 bytes. The BOOT and PROG sections must contain at least one flash block. This
partition is only needed for writes when memory protection is active and also for some erase commands.
Note: The flash boundaries can always be extracted from the flash INFO pages or from register SYS_MEMINFO
(see Table 4.7). Note that the last nine address bits are not included in the read value as they are always 0. The
read value can be interpreted as a flash block number.
The MAIN area can be read with byte, half-word, and word size. It can always be read by the ARM® processor,
but reads via the JTAG interface are blocked when memory protection is active. The different sections have no
influence on read accesses.
© 2016 Integrated Device Technology, Inc.
111
January 29, 2016
ZSSC1956 Datasheet
Figure 4.1
Flash Memory Example: BOOT Section of 7 Flash Pages (3.5kB) and
PROG Section of 22 Flash Pages (11kB)
LOG
Programmed logStart Address:
1DHEX (03A00HEX shifted by 9 bits)
03A00HEX
PROG
Programmed progStart Address:
07HEX (00E00HEX shifted by 9 bits)
00E00HEX
00000HEX
BOOT
MAIN
0HEX
INFO
As writes must only occur to erased memory locations (all1 flag set when read), one of the four erase commands
affecting the MAIN area must be executed before writing to a non-erased memory location. The erase commands
are always started via the flash controller.
To prevent an intruder from erasing only a small amount of flash memory and writing a small program in its place
that could read out the other memory locations, there are some restrictions for the erase commands:
•
ERASE_MAIN command: This command erases the complete MAIN area. Therefore it can always be
executed no matter whether memory protection is active or not. It takes approximately 16.3ms. After the
execution of this command, writes to all three sections are permitted if memory protection is inactive or as
long as the corresponding allowProgand allowBootflags in register FC_STAT_CORE are set (see
Table 4.16).
•
ERASE_PROG command: This command erases the complete PROG section. Therefore it can always be
executed no matter whether memory protection is active or not. It is mandatory that the two boundaries are
setup correctly. As this command erases all flash pages within the PROG section one after the other, the
command execution time is long (approximately 16.3ms per flash page). After the execution of this
command, writes to the PROG section are permitted if memory protection is inactive or as long as the
allowProgflag in register FC_STAT_CORE is set.
•
ERASE_BOOT_PROG command: This command erases the complete BOOT and PROG sections.
Therefore it can always be executed no matter whether memory protection is active or not. It is mandatory
that the upper boundary (PROG to LOG) is setup correctly (see section 4.2.2.2). As this command erases
all flash pages within both sections one after the other, the command execution time is long (approximately
16.3ms per flash page). After the execution of this command, writes to all three sections are permitted if
memory protection is inactive or as long as the corresponding allowProgand allowBoot flags in
register FC_STAT_CORE are set.
© 2016 Integrated Device Technology, Inc.
112
January 29, 2016
ZSSC1956 Datasheet
•
ERASE_MAIN_PAGE: This command erases a single flash page within the MAIN area, which takes
approximately 16.3ms. While this command can always be executed for a flash page in the LOG section, it
is rejected for flash pages in the BOOT or PROG section when memory protection is active. It is mandatory
that the upper boundary (PROG to LOG) is setup correctly.
Note: As erase commands erase at least a complete flash page, the user must save the data that must be
retained from the flash page to be erased.
Note: The allow flags will be cleared by writing 1 to the clrAllowbit of register FC_STAT_CORE or by a reset.
The MAIN area can only be written with word size as the ECC code is word-based. Writing one word requires
approximately 72µs. There are two ways of writing into the MAIN area: direct write or executing the WRITE
command by the flash controller. Direct writes can always be performed by the ARM® processor or via the JTAG
interface when the memory protection is inactive. When memory protection is active, no direct write is possible via
the JTAG interface. In that case, the ARM® processor can only perform a direct write to the LOG section while
direct writes to the BOOT or PROG section are rejected if the corresponding allowProgand allowBootflags
in register FC_STAT_CORE are not set.
The WRITE command can always be executed by the ARM® processor or via the JTAG interface, but the
command is rejected if the write would be performed to the BOOT or PROG section when memory protection is
active and the corresponding allowProgand allowBootflags in register FC_STAT_CORE are not set.
4.2.2.2. INFO Pages
The INFO pages are mapped into the system address space ranging from 4000 0C00HEX to 4000 0FFFHEX. No
memory location in the INFO pages can be directly written.
The first page (lower half) contains traceability information as well as a copy of the OTP contents of the SBC. This
page is only readable and cannot be accessed indirectly by the flash controller (no write, no erase).
Table 4.2 Memory Content of the Lower INFO Page
INFO Page 0
Local Address
000HEX
004HEX
008HEX
00CHEX
010HEX to 07FHEX
080HEX to 09FHEX
0A0HEX to 1EFHEX
1F0HEX to 1FFHEX
Size
Contents
Lot-Wafer-ID
Lot-Wafer-ID
X&Y coordinate
X&Y coordinate
Empty
OTP content
Empty
Tester information
1 word
1 word
1 word
1 word
---
8 words
---
---
The second page (upper half) contains information about memory protection and the three boundaries required to
split the flash MAIN area into three sections and the RAM into two sections. The lower half of the second flash
page (address offset 200HEX to 2FFHEX) is always readable while the upper half of the second flash page (address
offset 300HEX to 3FFHEX) can only be read when memory protection is inactive. The different fields can only be
modified by different flash controller commands.
© 2016 Integrated Device Technology, Inc.
113
January 29, 2016
ZSSC1956 Datasheet
When address 20CHEX is set to 0000 0000HEX the key-based lock is active, and when address 208HEX is set to
0000 0000HEX, the permanent lock is active. A permanent lock has a higher priority than the key-based lock. The
addresses 200HEX to 208HEX are also interpreted as a counter for failed attempts to unlock the key-based lock.
Each time an unlock command fails, one of these values is set to 0HEX causing the permanent lock to be activated
after the third failure.
The word at address 210HEX contains the three boundaries. The lowest byte of this word contains the flash page
number of the first flash page of the PROG section. The second byte of this word contains the flash page number
of the first flash page of the LOG section while the highest two bytes of this word contain the RAM word address
(without the last two 0’s) where the accessible RAM space starts. The complete RAM is always accessible by the
ARM® processor no matter whether memory protection is active or not. The lower part of the RAM (below the
RAM word address) can only be accessed via the JTAG interface when memory protection is not active. Placing
critical elements such as the stack in the RAM part below this RAM word address is recommended to protect the
system against intrusion. The upper part of the RAM (starting with the RAM word address) is always accessible
via the JTAG interface and can be used for programming the flash using the WRITE command.
Table 4.3 Memory Content of the Upper INFO Page
INFO Page 1
Local Address
Size
Content
1 word
1 word
1 word
1 word
1 word
Count 0
Count 1
Count 2 / permanent lock
Key-based lock
Boundaries for flash and RAM
1 byte (progStart)
1 byte (logStart)
2 bytes (ramSplit)
Empty
200HEX
204HEX
208HEX
20CHEX
210HEX
---
1 word
214HEX to 2FFHEX
300HEX
Key length
N words Key (maximum 31 words)
--- Empty
304HEX to 3??HEX
3??HEX to 3FFHEX
Addresses 300HEX and following (maximum to 37FHEX) contain the key information for the key-based lock.
4.2.3. RAM Memory
There is 8kB of SRAM memory integrated into the system. The SRAM is physically located at addresses
2000 0000HEX and higher. It can be accessed (read and write) with byte, half-word, and word size. The SRAM can
also be mirrored to address 0000 0000HEX by setting the memSwapbit in the register SYS_MEMPORTCFG to 1
(see Table 4.6).
The complete RAM is always accessible by the ARM® processor, but there are restrictions for RAM access via the
JTAG interface. From the JTAG perspective, the RAM is split into two sections with a configurable boundary
(ramSplitaddress). The ramSplitaddress is word-aligned and stored in the flash (see Figure 4.2). The upper
section starting with address ramSplit can always be accessed via JTAG and can be used for flash
reprogramming or to remove the key-based memory protection. The lower section can only be accessed via
JTAG when no memory protection is active. The stack used by software will be placed into the lower section to
prevent an intruder from corrupting the stack.
© 2016 Integrated Device Technology, Inc.
114
January 29, 2016
ZSSC1956 Datasheet
Figure 4.2 Example for ramSplit Address
1FFFHEX
1FFCHEX
110FHEX
110BHEX
110CHEX
1108HEX
Programmed ramSplit Address:
443HEX (110CHEX shifted by 2 bits)
7HEX
3HEX
4HEX
0HEX
Note: Always place the software stack into the lower section of the RAM. The lower section ends one word
address before the address ramSplit.
Note: The ramSplit address can always be extracted from the flash INFO pages or from register
SYS_MEMINFO. Note that the last two address bits are not included in the read value as they are always 0.
4.2.4.
System ROM Table
The system ROM table is used to identify the system by an external debugger. The system ROM is mapped into
the system address space ranging from F000 0000HEX to F000_0FFFHEX. Bit 0 of local address 000HEX can be
used by an external debugger to determine whether the memory protection is active (bit is 0) or not as the
processor ROM table is not accessible.
Table 4.4 Memory Content of System ROM
Address
FFCHEX
FF8HEX
FF4HEX
Value
Description
component ID3 – preamble
component ID2 – preamble
component ID1 – component class
component ID1 – preamble
component ID0 – preamble
peripheral ID3 – revision number
peripheral ID2 – project number [3:0]
peripheral ID2 – JEDEC assigned ID fields
peripheral ID2 – JEP106 ID code [6:4]
peripheral ID1 – JEP106 ID code [3:0]
peripheral ID1 – variant
peripheral ID1 – project number [13:12]
peripheral ID0 – project number [11:4]
peripheral ID7 – reserved
0000 00B1HEX
0000 0005HEX
0000 0010HEX
[7:0]
[7:0]
[7:4]
[3:0]
[7:0]
[7:4]
[7:4]
[3]
[2:0]
[7:4]
[3:2]
[1:0]
[7:0]
[7:0]
[7:0]
[7:0]
[3:0]
[0]
FF0HEX
FECHEX
FE8HEX
0000 000DHEX
0000 0000HEX
0000 009FHEX
FE4HEX
0000 0071HEX
FE0HEX
FDCHEX
FD8HEX
FD4HEX
FD0HEX
FCCHEX
004HEX to FC8HEX
000HEX
0000 0071HEX
0000 0000HEX
0000 0000HEX
0000 0000HEX
0000 0000HEX
0000 0001HEX
0000 0000HEX
0F00 FF0XHEX
peripheral ID6 – reserved
peripheral ID5 – reserved
peripheral ID4 – JEP106 continuation code
memType – indicates that the system memory is accessible via the DAP
Reserved
[31:12] address offset of next ROM table relative to this ROM table
[11:2] reserved
[1]
[0]
32-bit format ROM table → 1
0: next ROM table is not present; true when memory protection is active
1: next ROM table is present; true when memory protection is not active
© 2016 Integrated Device Technology, Inc.
115
January 29, 2016
ZSSC1956 Datasheet
4.2.5.
Memory Protection
Memory protection can be activated via dedicated commands of the flash controller to protect the software stored
in the flash. Two different types of memory protection are implemented: a key-based lock and a permanent lock.
Both restrict the access possibilities in the same manner, but the key-based lock can be removed by an unlock
procedure re-allowing access to the memory again. The user has three attempts to unlock the flash when the key-
based lock is active; after the third failed attempt, the flash is locked permanently. It is also possible to unlock the
flash from both types of memory protection by erasing the complete PROG section and then erasing the upper
INFO page.
When memory protection is active:
• The lower section of RAM cannot be accessed via JTAG interface. The upper section starting at the
ramSplitaddress is still accessible via JTAG for reprogramming the flash after erasing it or to unlock the
key-based lock.
• The complete flash MAIN area cannot be accessed via JTAG interface.
• Direct writes by the ARM® processor to the BOOT and PROG sections are rejected when corresponding
allow flags are not set (by a previous erase command).
• All JTAG accesses to the PPB area (system address space from E000 0000HEX to EFFF FFFFHEX) except to
the DHCSR (Debug Halting Control and Status Register) at address E000 EDF0HEX) (refer to the IDT
ARM® Cortex™ M0 User Guide) are rejected.
• For JTAG writes to DHCSR, data bit 2 (STEP) is forced to 0 to avoid debug stepping.
• The flash controller commands that are allowed to be executed are restricted.
The type of memory protection as well as the number of failed unlock attempts can be read from register
SYS_MEMINFO in the system management unit (SMU), which is always the reference as there might be an
inconsistency between this register and the contents of the flash INFO page after successful execution of an
UNLOCK_CMD (see Table 4.9).
4.3. System Management Unit
The system management unit (SMU) generates all internal clocks and resets. It also provides some support for
the different power-down modes controlled by the SBC and contains some registers for system configuration.
4.3.1.
Resets
There are five different reset sources in the system:
•
•
•
External reset provided via the MCU_RSTN internal node generated by the SBC.
External JTAG reset provided via the TRSTN pin.
System reset request generated in the ARM® core by writing to register AIRCR (refer to the IDT ARM®
Cortex™ M0 User Guide). This register is always accessible by the ARM® processor itself, but it can only
be accessed via JTAG if the memory protection is not active.
•
•
JTAG reset request generated in the SMU by writing to register SYS_RSTSTAT (see Table 4.8) in the
SMU. This reset can always be generated via the JTAG interface. It cannot be generated by the ARM®
processor itself.
System lockup. This reset can only occur when the ARM® processor detects a lockup and has previously
enabled this reset source (disabled by default) by writing to register SYS_RSTSTAT.
The external reset via the MCU_RSTN pad resets all logic except the JTAG state machine, which is reset by the
external JTAG reset only.
© 2016 Integrated Device Technology, Inc.
116
January 29, 2016
ZSSC1956 Datasheet
A reset caused by one of the other three reset sources sets the ARM® core back into its default state except the
debug logic. It also resets all peripherals except the following registers in the SMU:
•
•
•
Register SYS_MEMINFO (see Table 4.7)
The memSwapbit of register SYS_MEMPORTCFG (see Table 4.6)
The four reset status bits within register SYS_RSTSTAT (see Table 4.8)
4.3.2.
Clocks
The system has two different clock sources:
•
•
Internal clock provided via the MCU_CLK pad generated by the SBC (typically 20MHz)
External JTAG clock provided via the TCK pin
The TCK clock is only used for the JTAG access point. The rest of the MCU is clocked by a divided clock derived
from MCU_CLK. By default, MCU_CLK is divided by 1, but a divide value of 2, 4, and 8 can be configured via the
bit field clkDivin register SYS_CLKCFG (see Table 4.5) causing the system to run at 10, 5, or 2.5 MHz respect-
ively. While most of the system is clocked during normal operating mode, the clock for ZSYSTEM2 is disabled by
default and must be enabled before any access to ZSYSTEM2 takes place. To enable the clock for ZSYSTEM2,
set the enSclk2bit to 1 in register SYS_CLKCFG (see Table 4.5).
Important: Do not access ZSYSTEM2 when its clock is disabled.
Figure 4.3 System Clocks
clkDiv
enSclk2
Clock for
ZSYSTEM2
&
ctrl
MCU_CLK
Clock for rest
of the system
Clock Divider
by 1 / 2 / 4 / 8
Important Warning: Special care must be taken if changing the clock divider as the operation of several parts of
the system depends on the clock frequency.
Do not change the clkDivvalue when any of these conditions exist:
•
Any flash command is executed by the flash controller. Otherwise the flash can be destroyed. Wait until
command execution has finished.
•
ahbLIN is active as the inactivity timer, and the Break Sync Detector depends on the clock frequency.
When ahbLIN is transmitting, wait until the transmission has completed. The ahbLIN can be placed into a
safe state for changing the clock divider value by changing these bits in the Z1_LINCFG register: write 0
to the enToCnt field and write 1 to the stopRx and disableRxfields (see Table 4.32).
•
Any operation relying on the 10ms reference of the SYST_CALIB register of the ARM® core is active (see
the IDT ARM® Cortex™ M0 User Guide). These operations must be stopped first.
© 2016 Integrated Device Technology, Inc.
117
January 29, 2016
ZSSC1956 Datasheet
•
•
The USART or I2C™ module in ZSYSTEM2 is enabled as their baud rates depend on the clock fre-
quency. These modules must be disabled first.
Any slave connected to the SPI in ZSYSTEM2 requires a constant SPI frequency. In this case, an active
SPI transfer must finish first. The SBC does not need a constant frequency on its SPI. Therefore the
SPIB8 must only be stopped when changing the clock divider value would cause a SPI frequency higher
than 5MHz.
4.3.3.
Power Modes
There are three power modes within the MCU: the Normal Mode equal to the MCU-ON state on the system level
(see section 2.4), the Sleep Mode equal to the MCU-SLP state on the system level, and the DeepSleep Mode. In
Normal Mode, the ARM® core and the peripherals are clocked and software is executed. This state is entered
after power-up or when the system wakes up. The other two modes are distinguished by an ARM® internal
register, the system control register (SCR), and its SLEEPDEEP bit, which is controlled by software. Both sleep
modes are entered by the WFI (wait for interrupt) instruction.
If the SLEEPDEEP bit is not set on executing of a WFI instruction, the Sleep Mode is entered. In Sleep Mode, the
clock for the ARM® core is stopped, but the peripherals remain clocked to be able to wake up the ARM® core if an
interrupt occurs and this interrupt is enabled. If an enabled interrupt occurs, the clock for the ARM® core is re-
enabled and the system continues in Normal Mode at the position where it was stopped.
Important Warning: Do not enter Sleep Mode after sending a “power-down” command to the SBC. When the
SBC enters one of its power-down states (LP, ULP or OFF), at least the MCU_CLK is stopped on SBC side. This
can cause peripherals to stop in an unsafe state, which can cause damage to the system. The Sleep Mode must
only be entered when the SBC remains in its FP state.
Note: When an interrupt source is disabled, it cannot wake up the system.
If the SLEEPDEEP bit is set on executing of a WFI instruction, the DeepSleep Mode is entered on the MCU.
When the WFI instruction is executed without sending a power-down command to the SBC in advance, the SBC
remains in its FP state. In this case, the MCU_CLK is only gated at the MCU input while the SBC continues its
generation. This combination of power states (SBC in FP state, MCU in DeepSleep Mode) is called the MCU-
DEEP state on the system level. In the MCU-DEEP state, the MCU can only wake up by an active SBC interrupt.
It is mandatory that a source in the SBC is enabled to generate the interrupt and that the SBC interrupt is enabled
in the MCU.
When the WFI instruction is executed after sending a power-down command to the SBC, the CSN line of the SPI
connecting to the SBC will be released safely by the WFI instruction. This release of CSN triggers the SBC to
enter the configured power-down state. The CSN line must not be directly released by software as the MCU might
be in an intermediate state when the MCU_CLK clock and/or power are switched off on the SBC side.
© 2016 Integrated Device Technology, Inc.
118
January 29, 2016
ZSSC1956 Datasheet
There are three wake-up scenarios from the MCU’s DeepSleep Mode after a power-down command has been
sent to the SBC:
1. When SBC enters its ULP or OFF state (same power-down state on the system level), it stops the
generation of the MCU_CLK clock and disables the power for the pads and MCU core (VDDP and
VDDC); however, the RAM remains powered (VDDL). To protect the RAM contents from being corrupted
during that time, the MCU input RAM_PROTN is driven low by the SBC, which places all RAM inputs into
a safe state. When the MCU wakes up, the SBC re-enables all power supplies and the MCU clock and
generates a reset via the MCU_RSTN pad. After the reset is released, the MCU starts again as after
power-up.
2. When the SBC enters its LP state, it only stops the generation of the clock MCU_CLK but the MCU
remains fully powered. When the MCU wakes up, the SBC re-enables the clock and asserts the interrupt
line IRQN. Because the MCU is not reset, it restarts where it was stopped or enters the interrupt service
routine. It is important that the ARM® core has enabled the SBC interrupt for correct wakeup as it has
stopped its internal clock when entering its DeepSleep Mode.
3. When the SBC receives a power-down command when it has already detected an interrupt, it does not
enter the desired power-down state. It stays in its FP state but asserts the interrupt line IRQN. It is
important that the MCU has enabled the SBC interrupt for the correct wakeup as it has stopped its
internal clock when entering its DeepSleep Mode.
Important Warning: Always enable the SBC interrupt in the NVIC before going to Sleep Mode or DeepSleep
Mode as the SBC rejects the power-down commands when it has an active interrupt. Otherwise the system can
hang up.
Important Warning: Do not enter DeepSleep Mode when any flash command is active. Otherwise the flash could
be destroyed.
Important: Stop the ahbLIN, USART and I2C™ to prevent incorrect behavior after wakeup from the LP state or
when the SBC rejects the power-down command due to an active interrupt.
4.3.4.
Pin Configuration
While all the pins from/to the SBC have a fixed behavior, the functionality of the GPIO pads can be changed by
software.
Recommendation: The MCU has 16 GPIOs, but only 5 of them are bonded: GPIO0, GPIO1, GPIO2, GPIO3,
GPIO4. Keeping the unbonded GPIO pads switched as inputs is recommended.
By default, all GPIO pads operate as pure GPIOs switched as inputs and configured with open-drain output driver
functionality. The GPIO pins require an external pull-up resistor if they will operate as open-drain outputs.
© 2016 Integrated Device Technology, Inc.
119
January 29, 2016
ZSSC1956 Datasheet
The following bit fields in register SYS_MEMPORTCFG (see Table 4.6) can be used to change the behavior and
functionality of the GPIO pads:
•
ppNod: This 16-bit register field is used to individually select the output driver behavior of each GPIO
pad. Each GPIO can be configured to operate as push-pull or open-drain (default). This configured output
driver behavior is also used when one of the peripheral modules of ZSYSTEM2 is mapped on the
corresponding GPIO pad with the following exceptions:
o
o
o
The SCL line of I2C™ always operates as open-drain independent of the ppNodsetting.
The SDA line of I2C™ always operates as open-drain independent of the ppNodsetting.
The RXD line of USART always operates as open-drain independent of the ppNodsetting.
•
spiCfg: This 2-bit register field is used to connect the SPI of ZSYSTEM2 to the GPIO pads.
o
The lower bit of this 2-bit register field is used to enable the connections between the GPIO pads
and the SPI of ZSYSTEM2. When enabled, the GPIO functionality is not available.
o
The upper bit is used to distinguish between two GPIO pad sets to which the SPI lines are
connected when the connections are enabled by the lower bit:
.
Mapping when the upper bit is 0:
•
•
•
•
CSN
MOSI
MISO
GPIO[0]
GPIO[1]
GPIO[2]
SCLK GPIO[3]
.
Mapping when upper bit is 1 (do not use this setting as these GPIO pads are not
bonded):
•
•
•
•
CSN
MOSI
MISO
GPIO[9]
GPIO[10]
GPIO[11]
SCLK GPIO[12]
o
The output behavior of the three SPI output lines (SCLK, CSN, MOSI) are determined by the
settings of the ppNodfield.
•
usartCfg: This 3-bit register field is used to connect the USART of ZSYSTEM2 to the GPIO pads.
o
The lowest bit of this 3-bit register field is used to enable the connections between the GPIO pads
and the USART of ZSYSTEM2. When enabled, the GPIO functionality is not available.
The upper two bits are used to select between four GPIO pad sets to which the USART pins are
connected when the connections are enabled by the lowest bit in usartCfg:
o
.
Mapping when the upper two bits are 00BIN (only the TXD line is usable as the GPIO[8]
pad is not bonded):
•
•
TXD
RXD
GPIO[4]
GPIO[8]
.
Mapping when the upper two bits are 01BIN
:
•
•
TXD
RXD
GPIO[2]
GPIO[3]
© 2016 Integrated Device Technology, Inc.
120
January 29, 2016
ZSSC1956 Datasheet
.
.
Mapping when the upper two bits are 10BIN (do not use this setting as these GPIO pads
are not bonded):
•
•
TXD
RXD
GPIO[6]
GPIO[7]
Mapping when the upper two bits are 11BIN (do not use this setting as these GPIO pads
are not bonded):
•
•
TXD
RXD
GPIO[9]
GPIO[10]
o
The output behavior of the TXD line is determined by the settings of the ppNod field. The RXD
line always operates as open-drain (ppNodsetting is overridden).
•
i2cCfg: This 3-bit register field is used to connect the I2C™ of ZSYSTEM2 to the GPIO pads.
o
The lowest bit of this 3-bit register field is used to enable the connections between the GPIO pads
and the I2C™ of ZSYSTEM2. When enabled, the GPIO functionality is not available.
o
The upper two bits are used to select between four GPIO pad sets to which the I2C™ lines are
connected when the connections are enabled by the lowest bit in i2cCfg:
.
Mapping when the upper two bits are 00BIN (do not use this setting as these GPIO pads
are not bonded):
•
•
SCL
SDA
GPIO[11]
GPIO[12]
.
.
Mapping when the upper two bits are 01BIN:
•
•
SCL
SDA
GPIO[0]
GPIO[1]
Mapping when the upper two bits are 10BIN (do not use this setting as the GPIO[5] pad is
not bonded):
•
•
SCL
SDA
GPIO[4]
GPIO[5]
.
Mapping when the upper two bits are 11BIN (do not use this setting as these GPIO pads
are not bonded):
•
•
SCL
SDA
GPIO[14]
GPIO[15]
o
Both I2C™ lines (SCL, SDA) always operate as open-drain (ppNodsetting is overridden).
•
linTest:This 1-bit register field is used to provide a direct connection between the GPIO pads and the
TXD and RXD pads connected to the SBC. This must be used for the LIN conformance test where direct
access to the LIN-PHY is needed.
o
o
TXD line is connected to GPIO[4] pin for direct control.
RXD line is connected to GPIO[2] pin for direct observation.
Note: GPIO functionality is only available when no other interface is mapped onto the specific GPIO pad.
© 2016 Integrated Device Technology, Inc.
121
January 29, 2016
ZSSC1956 Datasheet
Note: As can be seen from the description above, different interface modules can be mapped onto the same
GPIO pads. When more than one interface is mapped onto a GPIO pad, only one functionality is enabled with the
following priority (highest priority first):
•
•
•
•
•
linTest
I2C™
USART
SPI
GPIO
Note: For software debugging purposes when only an output for printing debug information is needed, the
USART variant 0 (TXD at GPIO[4]; RXD at GPIO[8]) can be used although GPIO[8] is not bonded.
Example: As can be seen from the above mapping, the MOSI line of the SPI within ZSYSTEM2 can be mapped
to pad GPIO[1] or to the unbonded pad GPIO[10]. For simplification, the other mapping possibilities are not
considered for this example. To enable the connection for the SPI, the spiCfg[0] bit in register
SYS_MEMPORTCFG must be set to 1; otherwise both GPIO pads would be driven by the corresponding
registers from the GPIO module. spiCfg[1] is used to select the GPIO pad where MOSI will be connected. The
other GPIO pad remains connected to the GPIO module.
Figure 4.4 Example for Mapping MOSI of the SPI in ZSYSTEM2 to the GPIO Pads
Bit spiCfg[0] enables any connection; bit spiCfg[1] selects the appropriate GPIO pad.
0
pad GPIO[1]
gpioOut[1]
1
&
spiCfg[0]
spi.mosi
&
spiCfg[1]
1
pad GPIO[10]
0
gpioOut[10]
© 2016 Integrated Device Technology, Inc.
122
January 29, 2016
ZSSC1956 Datasheet
4.3.5.
SMU Module Register Overview
4.3.5.1. Register “SYS_CLKCFG” – Clock Configuration
Table 4.5 Register SYS_CLKCFG– system address 4000 0000HEX
Name
clkDiv
Bits
Default
Access
Description
[1:0]
00BIN
RW
Clock divider value
0: incoming clock is divided by 1
1: incoming clock is divided by 2
2: incoming clock is divided by 4
3: incoming clock is divided by 8
Unused; always write as 0.
Unused
[6:2]
00000BIN
RO
enSclk2
Unused
[7]
[31:8]
0BIN
00 0000HEX
RW
RO
Enable bit for ZSYSTEM2 clock
Unused; always write as 0.
4.3.5.2. Register “SYS_MEMPORTCFG” – Memory and Port Configuration
Table 4.6 Register SYS_MEMPORTCFG– system address 4000 0004HEX
Name
ppNod
Bits
Default
Access
Description
[15:0]
0000HEX
RW
Output configuration bits.
These 16 bits select individually for each GPIO whether the pad
will work as an open-drain (set to 0) or as a push-pull (set to 1).
spiCfg
[17:16]
[20:18]
00BIN
Configuration bits for SPI in ZSYSTEM2.
RW
RW
[0]: enable connection between GPIOs and SPI
[1]: select 1 of 2 port sets to which SPI will be mapped.
Configuration bits for USART in ZSYSTEM2.
[0]: enable connection between GPIOs and USART
[2:1]: select 1 of 4 port sets to which USART will be mapped.
Important: The RXD line is always open-drain; settings from
ppNodare overridden.
usartCfg
000BIN
i2cCfg
[23:21]
000BIN
RW
Configuration bits for I²C™ in ZSYSTEM2.
[0]: enable connection between the GPIOs and I²C™
[2:1]: select 1 of 4 port sets to which I²C™ will be mapped.
Important: Both I²C™ lines are always open-drain; settings from
ppNodare overridden.
Unused
linTest
[29:24]
[30]
000000BIN
0BIN
RO
RW
Unused; always read as 0.
Configuration bit for LIN test.
When set, RXD and TXD line are directly connected to GPIO.
memSwap
[31]
0BIN
RW
Memory swap bit.
This bit selects whether the flash MAIN area (set to 0) or the
RAM (set to 1) is mirrored to system address 0000 0000HEX
.
© 2016 Integrated Device Technology, Inc.
123
January 29, 2016
ZSSC1956 Datasheet
4.3.5.3. Register “SYS_MEMINFO” – Memory Information
Table 4.7 Register SYS_MEMINFO– system address 4000 0008HEX
Name
progStart
Bits
Default
Access
Description
[7:0]
RO
This register represents the first page where the PROG (pro-
gram) section in the flash memory starts. This value is read from
the flash memory during the power-up phase and is updated by
some flash commands.
FFHEX
Important: To get the correct flash address offset, nine 0’s must
be appended.
logStart
ramSplit
[15:8]
RO
RO
This register represents the first page where the LOG section in
the flash memory starts. This value is read from the flash during
the power-up phase and is updated by some flash commands.
Important: to get the correct flash address offset, nine 0’s must
be appended.
This register represents the first RAM word that is accessible by
JTAG although the memory is locked. This value is read from the
flash during the power-up phase and is updated by some flash
commands.
FFHEX
[26:16]
111 1111
1111BIN
Important: to get the correct RAM address offset, two 0’s must
be appended.
Unused
protInfo
[27]
[31:28]
RO
RO
Unused; always read as 0.
0BIN
1111BIN
This register represents the memory protection scheme. This
value is read from flash during the power-up phase and is
updated by some flash commands.
[0]: key based lock
[1]: permanent lock
[3:2]: number of failed unlock attempts
4.3.5.4. Register “SYS_RSTSTAT” – Reset Status
Table 4.8 Register SYS_RSTSTAT– system address 4000 000CHEX
Name
Bits
Default
Access
Description
extRst
[0]
RC
This bit indicates if an external reset has occurred. It is cleared
when the register is read.
1BIN
sysRstReq
lockupRst
jtagRst
[1]
[2]
[3]
RC
RC
RC
This bit indicates if a reset forced by a system reset request has
occurred. It is cleared when the register is read.
This bit indicates if a reset was forced by a detected lockup when
this reset was enabled. It is cleared when the register is read.
This bit indicates if a reset forced by a JTAG reset request has
occurred. It is cleared when the register is read.
0BIN
0BIN
0BIN
Unused
[6:4]
[7]
RO
RO
Unused; always read as 0.
This bit indicates whether a lockup from the ARM® core is allowed
to reset the system (set to 1) or not (set to 0).
000BIN
0BIN
enLockup
setEnLockup
[7:0]
00HEX
WO
To enable the lockup reset, C9HEX must be written to bits 7:0. It can
be disabled by writing a different value. This field is reset by all
four reset sources (extRst, sysRstReq, lockupRst,
jtagRst).
© 2016 Integrated Device Technology, Inc.
124
January 29, 2016
ZSSC1956 Datasheet
Name
Unused
Bits
[15:8]
[23:16]
Default
00HEX
Access
RO
Description
Unused; always read as 0.
jtagRstReq
00HEX
WO
To generate a reset via the JTAG interface, 3AHEX must be written
to bits 23:16. These bits cannot be written by the ARM® core.
Unused; always read as 0.
Unused
[31:24]
00HEX
RO
4.4. Flash Controller
The flash controller handles all accesses to the different flash locations (INFO pages; MAIN area). It takes care of
the memory protection by rejecting illegal accesses; it provides different types of commands for modifying the
flash content; it guarantees all required timings for the different accesses; and it appends and checks the ECC
code for robustness of the flash content. It also contains a set of registers that are needed for command
execution, which reflect the status of the flash controller and the flash and that enable the different interrupt
sources to drive the interrupt line. The interrupt is active-high and is connected to ARM® interrupt 0. Additionally,
there are two non-maskable interrupt sources that are connected to the NMI of the ARM® core.
Read accesses: The flash MAIN area containing the BOOT, PROG, and LOG section can always be read by the
ARM® processor while it can only be read via JTAG when no memory protection (key-based or permanent lock) is
active (register SYS_MEMINFO[29:28] == 0) to prevent unauthorized reading of the program. The lower three
quarters of the flash INFO pages and all flash controller registers can always be read by the ARM® processor or
via JTAG. The upper quarter of the flash INFO pages containing the key for the key-based lock is only readable
when no memory protection is active. All read accesses can be performed with byte, half-word, and word size.
Direct write accesses: The INFO pages cannot be directly written, while the registers are always writable by the
ARM® processor and via JTAG. Writes to the registers can be performed with byte, half-word, and word size.
When no memory protection is active, the complete MAIN area can be written directly by the ARM® core or via
JTAG, but it is the responsibility of the user that only erased memory locations are written. When memory
protection is active, only writes to the LOG section performed by the ARM® processor are possible. All other
writes to the MAIN area (other section or via JTAG) are rejected. All writes to the MAIN area can only be
performed with word size.
Commands: Several commands are implemented for erase and write operations as well as to configure the
system (memory boundaries and protection). These commands can always be configured and started by the
ARM® processor or via JTAG, but under certain conditions their execution is rejected.
Read status information: There are two registers, FC_STAT_PROG (see Table 4.17) and FC_STAT_DATA
(see Table 4.18), for signaling that an error occurred when reading the flash (INFO pages or MAIN area) and for
indicating whether the error occurred during an instruction fetch by the ARM® processor (FC_STAT_PROG is
used) or during a load operation by the ARM® processor or via JTAG.
© 2016 Integrated Device Technology, Inc.
125
January 29, 2016
ZSSC1956 Datasheet
Three different types of error are signaled:
•
The occurrence of a single error within a word that was corrected by the ECC logic is signaled via flags
prog1Errin FC_STAT_PROG or data1Errin FC_STAT_DATA. Both flags are cleared on read access
to the corresponding register and can be enabled via register FC_IRQ_EN (see Table 4.15) to drive the
normal interrupt line.
•
When an empty memory location is read, the flags progAll1 in FC_STAT_PROG or dataAll1 in
FC_STAT_DATA is set. Both flags are cleared on read access to the corresponding register. While the
dataAll1 flag can be enabled via register FC_IRQ_EN to drive the normal interrupt line (this flag is
useful to determine an empty memory location for a write operation to flash), the progAll1generates a
non-maskable interrupt (NMI) as this situation is a severe problem for software execution.
The occurrence of more than one error within a word that is not correctable by the ECC logic is signaled
via flags prog2Err in FC_STAT_PROG or data2Err in FC_STAT_DATA. Both flags are cleared on
read access to the corresponding register. While the data2Err flag can be enabled via register
FC_IRQ_EN to drive the normal interrupt line, the prog2Errgenerates a non-maskable interrupt (NMI)
as this situation is a severe problem for software execution.
•
In addition to the error flags, the address of the error position is stored. When consecutive errors occur, the
address of the first error is kept until the status register is read. When different types of error occurred (only one of
the three flags is set at a time), it cannot be determined from the read status value to which type of error the
address belongs. It is also not visible when several errors of the same type occurred.
Command status information: The FC_STAT_CORE register (see Table 4.16) contains eight different status
flags about the command execution and the access rights to different memory locations when the protection is
active. Four of them are cleared on read access and can be enabled via register FC_IRQ_EN to drive the normal
interrupt line. The three “allow” flags are read-only. To clear them for reactivation of the memory protection, a 1
must be written to the bit clrAllow. If the “allow” flags are not cleared, it is possible to read out the software.
4.4.1.
Commands
All commands can be started by the ARM® processor or via the JTAG interface. Their execution is only restricted
by the activated memory protection stored within the SMU. The write sequence for setting up the command can
be in any order except that the write to register EXE_CMD (see Table 4.14) must be the last step.
© 2016 Integrated Device Technology, Inc.
126
January 29, 2016
ZSSC1956 Datasheet
4.4.1.1. Overview
Table 4.9 gives a list of all commands, including when they are allowed to be executed and which flags are
influenced internally and in the system management unit. Details are given in subsequent sections.
Table 4.9 List of Commands
Allowed to be
Executed
Command
Other Internal Actions
ERASE_MAIN_CMD (00HEX
)
Always
Always
Always
Flag allowKeyis set at the end of command execution.
Flag allowBootis set at the end of command execution.
Flag allowProgis set at the end of command execution.
Flag allowKeyis set at the end of command execution.
Flag allowBootis set at the end of command execution.
Flag allowProgis set at the end of command execution.
Flag allowKeyis set at the end of command execution.
Flag allowProgis set at the end of command execution.
ERASE_BOOT_PROG_CMD
(02HEX
)
ERASE_PROG_CMD (03HEX
)
ERASE_MAINPAGE_CMD
BOOT: No lock active ---
PROG: No lock active
LOG: Always
(04HEX
)
ERASE_KEY_CMD (06HEX
)
No lock active or
The protection bits (register SYS_MEMINFO[31:28]; see
Table 4.7) are cleared at the end of command execution.
allowKeyflag set
The three boundary bit fields in register SYS_MEMINFO in SMU
are set to FFFFFFFFHEX at the end of command execution.
FAIL:
UNLOCK_CMD (08HEX
)
Key-lock only
The fail counter (register SYS_MEMINFO[31:30]) in the SMU is
incremented at the end of command execution.
The permanent lock bit (SYS_MEMINFO[29]) in SMU is set at
the end of command execution upon the third failure.
SUCCESS:
Flag allowKeyis set at the end of command execution.
The key-based lock bit (SYS_MEMINFO[28]) in the SMU is
cleared at the end of command execution.
The register SYS_MEMINFO will be updated with the extracted
values from flash.
GETENV_CMD (09HEX
)
Always
WRITE_CMD (0AHEX
)
BOOT:
---
(also valid for direct write to MAIN
area)
No lock active or
allowBootflag set
PROG:
No lock active or
allowProg flag set
LOG:
Always
SET_KEY_CMD (0CHEX
SET_BOUNDARY_CMD (0DHEX
)
No lock active
No lock active
---
)
The three boundary bit fields in register SYS_MEMINFO in
SMU are updated at the end of command execution.
The permanent lock bit (SYS_MEMINFO[29]) in SMU is set at
the end of command execution.
The key-based lock bit (SYS_MEMINFO[28]) in SMU is set at
the end of command execution.
LOCK_PERM_CMD (0EHEX
)
No lock active
No lock active
LOCK_KEY_CMD (0FHEX
)
© 2016 Integrated Device Technology, Inc.
127
January 29, 2016
ZSSC1956 Datasheet
4.4.1.2. ERASE_MAIN_CMD – Erasing the Complete Main Area
This command erases the complete MAIN area of the flash. It can always be executed independently of the lock
state (no lock active / key-based lock active / permanent lock active). For command execution, the settings of
registers FC_RAM_ADDR and FC_FLASH_ADDR as well as the bit field wrSizeof register FC_CMD_SIZE have
no meaning. Only the ERASE_MAIN_CMD must be programmed into bit field cmd of register FC_CMD_SIZE
(see Table 4.13). Then the command execution must be started by writing 1 to bit field exeCmd of register
FC_EXE_CMD (see Table 4.14).
When the command is started, the bit coreActive(FC_STAT_CORE[4]) is set (see Table 4.16). As long as the
command is active, all direct accesses to the flash (read and write) as well as writes to all registers of the flash
controller are postponed. When software is running from RAM, the system is still able to run. Read accesses to
the registers of the flash controller are allowed while the command is active to check the status of the command
execution. When the command has finished, the coreActive bit (FC_STAT_CORE[4]) is cleared and the bit
cmdRdy (FC_STAT_CORE[0]) is set, which is cleared when read. The three flags allowKey, allowBootand
allowProg are also set as the BOOT and PROG sections are now empty. Therefore it is possible to remove the
unneeded memory protection by erasing the upper INFO page using ERASE_KEY_CMD and to write new
software into the BOOT and PROG sections.
Note: The execution time is approximately 16.3ms.
Note: This command can always be executed via JTAG interface. As the program that the ARM® core is
executing might be located in the flash, it is strongly recommended that the following sequence is used:
•
•
•
The ARM® core first halts the processor via the DHCSR register.
Then it erases and reprograms the flash.
Last, it performs a JTAG reset via the SYS_RSTSTAT register in the SMU (see Table 4.8).
Note: This command can always be executed by the ARM® core. To prevent the ARM® core from erasing its own
active program, it is strongly recommended that the software is run entirely from RAM memory.
4.4.1.3. ERASE_BOOT_PROG_CMD – Erasing BOOT and PROG section
This command erases the complete BOOT and PROG section of the flash MAIN area, but the content of the LOG
section remains in the flash. It can always be executed independent of the lock state (no lock active / key-based
lock active / permanent lock active). For command execution, the settings of registers FC_RAM_ADDR and
FC_FLASH_ADDR as well as the bit field wrSize of register FC_CMD_SIZE have no meaning. Only the
ERASE_BOOT_PROG_CMD must be programmed into bit field cmd of register FC_CMD_SIZE. Then the
command execution must be started by writing 1 to bit field exeCmdof register FC_EXE_CMD.
© 2016 Integrated Device Technology, Inc.
128
January 29, 2016
ZSSC1956 Datasheet
When the command is started, the bit coreActive (FC_STAT_CORE[4]) is set. As long as the command is
active, all direct accesses to the flash (read and write) as well as writes to all registers of the flash controller are
postponed. When software is running from RAM, the system is still able to run. Read accesses to the registers of
the flash controller are allowed while the command is active to check the status of the command execution. When
the command has finished, the bit coreActive (FC_STAT_CORE[4]) is cleared and the bit cmdRdy
(FC_STAT_CORE[0]) is set which is cleared when read. The three flags allowKey, allowBoot, and
allowProg are set as the BOOT and PROG sections are now empty. Therefore it is possible to remove the
unneeded memory protection by erasing the upper INFO page using ERASE_KEY_CMD and to write new
software into the BOOT and PROG sections.
Note: The execution time depends on the number of flash pages contained in the BOOT and PROG sections.
Each flash page to be erased takes approximately 16.3ms.
Note: This command can always be executed via JTAG interface. As the program that the ARM® core is
executing might be located in the flash, it is strongly recommended that the following sequence be used:
•
•
•
The ARM® core first halts the processor via the DHCSR register.
Then it erases and reprograms the flash.
Last, it performs a JTAG reset via SYS_RSTSTAT register in SMU.
Note: This command can always be executed by the ARM® core. To prevent the ARM® core from erasing its own
active program, it is strongly recommended that the software is run completely from RAM memory.
Note: Because this command erases all flash pages from the first page until the page in front of the flash page
logStart, this command must only be used when the boundaries have a meaningful setting (see Table 4.7).
4.4.1.4. ERASE_PROG_CMD – Erasing PROG section
This command erases the complete PROG section of the flash MAIN area, but the content of the BOOT and the
LOG sections remains in the flash memory. It can always be executed independently of the lock state (no lock
active / key-based lock active / permanent lock active). For command execution, the settings of registers
FC_RAM_ADDR and FC_FLASH_ADDR as well as the bit field wrSize of register FC_CMD_SIZE have no
meaning. Only the ERASE_PROG_CMD must be programmed into the bit field cmdof register FC_CMD_SIZE.
Then the command execution must be started by writing 1 to bit field exeCmd of register FC_EXE_CMD.
When the command is started, the coreActivebit (FC_STAT_CORE[4]) is set. As long as the command is
active, all direct accesses to the flash (read and write) as well as writes to all registers of the flash controller are
postponed. When software is running from RAM, the system is still able to run. Read accesses to the registers of
the flash controller are allowed while the command is active to check the status of the command execution. When
the command has finished, the bit coreActive (FC_STAT_CORE[4]) is cleared and the cmdRdy bit
(FC_STAT_CORE[0]) is set, which is cleared when read. The two flags allowKeyand allowProg are also
set as the PROG section is now empty. Therefore the unneeded memory protection can be removed by erasing
the upper INFO page using ERASE_KEY_CMD and writing new software into the PROG sections.
Note: The execution time depends on the number of flash pages contained in PROG section. Each flash page to
be erased takes approximately 16.3ms.
© 2016 Integrated Device Technology, Inc.
129
January 29, 2016
ZSSC1956 Datasheet
Note: This command can always be executed via JTAG interface. As the program that the ARM® core is
executing might be located in the flash, it is strongly recommended that the following sequence is used:
•
•
•
The ARM® core first halts the processor via the DHCSR register.
Then it erases and reprograms the flash.
Last, it performs a JTAG reset via the SYS_RSTSTAT register in SMU.
Note: This command can always be executed by the ARM® core. To prevent the ARM® core from erasing its own
active program, it is strongly recommended that the software is run entirely from RAM memory.
Important: As this command erases all flash pages from the flash page progStartthrough the page in front of
the flash page logStart, this command must only be used when the boundaries have a meaningful setting
(see Table 4.7).
4.4.1.5. ERASE_MAINPAGE_CMD – Erasing a Single Page in the MAIN Area
This command erases a single page within the flash MAIN area. Its execution depends on the memory protection
and to which section of the MAIN area (BOOT / PROG / LOG) the page to be erased belongs. When no lock is
active (SYS_MEMINFO[29:28] == 00BIN), the selected flash page will be erased independent of its location. If any
lock is active, the page will only be erased if it is located within the LOG section. Otherwise, the command is
rejected.
For command execution, the settings of register FC_RAM_ADDR, as well as the wrSize bit field of register
FC_CMD_SIZE, have no meaning. The register FC_FLASH_ADDR (see Table 4.12) is used to select the flash
page to be erased. The value to be programmed must be calculated by shifting the flash address pointing to any
location in the desired page two bits to the right. The ERASE_MAINPAGE_CMD must be programmed into the
cmdbit field of register FC_CMD_SIZE. Then the command execution must be started by writing 1 to the exeCmd
bit field of register FC_EXE_CMD.
When the command is started, the coreActive bit (FC_STAT_CORE[4]) is set. As long as the command is
active, all direct accesses to the flash (read and write) as well as writes to all registers of the flash controller are
postponed. When software is running from RAM, the system is still able to run. Read accesses to the registers of
the flash controller are allowed while the command is active to check the status of the command execution. When
the command has finished, the coreActive bit (FC_STAT_CORE[4]) is cleared and the cmdRdy bit
(FC_STAT_CORE[0]) is set, which is cleared when read. If the command execution was rejected because a page
within BOOT or PROG section was selected while the memory protection is active, the invalidArea bit
(FC_STAT_CORE[2]) is also set.
Note: The execution time is approximately 16.3ms if the command is not rejected.
Warning: This command is intended for erasing a page in the LOG section. Special care must be taken for
erasing a page within the BOOT or PROG section as software might become inconsistent.
Note: Because this command distinguishes between the LOG section on one side and the BOOT and PROG
section on the other if memory protection is active using the setting of logStart, this command must only be
used if the boundaries have a meaningful setting in this case.
© 2016 Integrated Device Technology, Inc.
130
January 29, 2016
ZSSC1956 Datasheet
4.4.1.6. ERASE_KEY_CMD – Erasing the Upper INFO Page
This command erases the upper INFO page, which contains the lock information, the memory boundaries, and
the key to be used for the key-based lock. It is only executed when no lock is active (SYS_MEMINFO[29:28] ==
00BIN) or when the allowKey flag (FC_STAT_CORE[5]) is set. Otherwise, the command is rejected. For
command execution, the settings of registers FC_RAM_ADDR and FC_FLASH_ADDR, as well as the wrSize
bit field of register FC_CMD_SIZE, have no meaning. Only the ERASE_KEY_CMD must be programmed into the
cmd bit field of register FC_CMD_SIZE. After that, the command execution must be started by writing 1 to the
exeCmdbit field of register FC_EXE_CMD.
When the command is started, the coreActivebit (FC_STAT_CORE[4]) is set. As long as the command is
active, all direct accesses to the flash (read and write), as well as writes to all registers of the flash controller, are
postponed. When software is running from RAM, the system is still able to run. Read accesses to the registers of
the flash controller are allowed while the command is active to check the status of the command execution. When
the command has finished, the coreActive bit (FC_STAT_CORE[4]) is cleared and the cmdRdy bit
(FC_STAT_CORE[0]) is set, which is cleared when read. If the command execution was rejected because the
allowKeyflag was not set but the memory protection is active, the invalidCmdbit (FC_STAT_CORE[1]) is
also set. If the command was not rejected, all three boundary fields within register SYS_MEMINFO (bits [26:0]) in
the SMU are set to all 1s and the protInfobit field is set to all 0s at end of the command execution.
Note: The execution time is approximately 16.3ms if the command is not rejected.
Note: The register SYS_MEMINFO is updated at the end of the successful execution of this command.
Important: In addition to the lock and the key information, the boundaries are erased. Therefore the user must
reprogram the boundaries afterward using the SET_BOUNDARY_CMD (see section 4.4.1.8). Boundaries can be
read and stored before command execution from register SYS_MEMINFO.
© 2016 Integrated Device Technology, Inc.
131
January 29, 2016
ZSSC1956 Datasheet
4.4.1.7. WRITE_CMD – Writing 1 to 32 Words from RAM to Flash
This command copies up to 32 words from RAM into the flash MAIN area. Its execution depends on the memory
protection state, the destination section of the flash, and the “allow” flags set in register FC_STAT_CORE (see
Table 4.16).
•
•
•
If the write will be performed to the BOOT section, the command is only executed when no lock is active
or when the allowBootflag is set. Otherwise the command is rejected.
If the write will be performed to the PROG section, the command is only executed when no lock is active
or when the “allowProg” flag is set. Otherwise the command is rejected.
If the write will be performed to the LOG section, the command is always executed.
First, the data to be stored into the flash must be written into the RAM. The data must be placed word-aligned into
the RAM with consecutive words to consecutive addresses. The register FC_RAM_ADDR must be written with
the RAM address where the word containing the first word was stored (see Table 4.11). The value to be pro-
grammed must be calculated by shifting the RAM address pointing to that location by two bits to the right. Regis-
ter FC_FLASH_ADDR must be written with the flash address where the first word will be stored (see Table 4.12).
The value to be programmed must be calculated by shifting the flash address pointing to that location by two bits
to the right. Special care must be taken when more than one byte will be written. While there is no restriction on
how the block of words is placed into the RAM (no block alignment), the WRITE_CMD only operates on a single
flash row (one flash page consists of four flash rows; one row consists of 32 words). When a row boundary is
reached during execution of a write command while there is still data to be written present, the flash address
wraps to the beginning of the row.
The register FC_CMD_SIZE must be programmed with the WRITE_CMD to the cmdbit field and the number of
bytes to be written to the wrSizebit field. For wrSizeequal to 00001BIN, one word is written; for “wrSize”
equal to 00010BIN, two words are written, and so on. A value of 00000BIN, is interpreted as 32 words, which means
that a complete row must be programmed. After all registers are set appropriately, the command execution must
be started by writing 1 to the exeCmdbit field of register FC_EXE_CMD.
When the command is started, the coreActivebit (FC_STAT_CORE[4]) is set. As long as the command is
active, all direct accesses to the flash (read and write), as well as writes to all registers of the flash controller, are
postponed. When software is running from RAM, the system is still able to run. Read accesses to the registers of
the flash controller are allowed while the command is active to check the status of the command execution. When
the command has finished, the coreActive bit (FC_STAT_CORE[4]) is cleared and the cmdRdy bit
(FC_STAT_CORE[0]) is set, which is cleared when read. If the command execution was rejected because
the memory protection is active and the corresponding “allow” flag is not set, the invalidArea bit
(FC_STAT_CORE[2]) is also set.
Note: The execution time is approximately (22 + 50 * N)µs where N is the number of words to be programmed.
Note: The value to be programmed into register FC_RAM_ADDR does not contain the last two digits (always 0).
For this, the RAM address must be shifted right by two bits (value = (RAM address >> 2).
Note: The value to be programmed into register FC_FLASH_ADDR does not contain the last two digits (always
0). For this, the flash address must be shifted right by two bits (value = (flash address >> 2).
Note: This command does not erase the locations to be written. Therefore software must ensure that the
locations are empty.
© 2016 Integrated Device Technology, Inc.
132
January 29, 2016
ZSSC1956 Datasheet
Note: This command writes only within a single flash row. The address wraps at the end of a flash row back to
the beginning of the row and does not continue in the next row.
Figure 4.5 Block Writes Examples: from RAM to Flash with/without Wrapping at the Flash Row Boundary
RAM
FLASH
857HEX
word 32
854HEX
537FHEX
word 9
537CHEX
535BHEX
5357HEX
word 0
5358HEX
5354HEX
803HEX
7FFHEX
word 10
word 9
800HEX
7FCHEX
word 32
7DBHEX
word 0
7D8HEX
5303HEX
word 10
5300HEX
Programmed addrRam Value:
1F6HEX (7D8HEX >> 2)
Programmed addrFlash Value:
14D6HEX (5358HEX >> 2)
537FHEX
word 32
537CHEX
532BHEX
5327HEX
word 10
word 9
5328HEX
5324HEX
5303HEX
word 0
5300HEX
Programmed addrFlash Value:
14C0HEX (5300HEX >> 2)
4.4.1.8. SET_BOUNDARY_CMD – Setting the Three Boundaries
This command stores the required memory boundaries (progStart, logStart, ramSplit) from RAM into
upper INFO page at address 210HEX. It is only executed when no lock is active (SYS_MEMINFO[29:28] == 00BIN).
Otherwise, the command is rejected. For command execution, the settings of register FC_FLASH_ADDR, as well
as the bit field wrSize of register FC_CMD_SIZE have no meaning. First, one word containing the three
boundaries must be written into the RAM (word aligned) in the same format as they are stored into the flash or as
they are stored in register SYS_MEMINFO:
•
•
•
•
word bits [7:0] = flashAddr[16:9];
word bits [15:8] = flashAddr[16:9];
word bits [26:16] = ramAddr[12:2];
word bits [31:27] are “don’t care”
(progStart; number of first flash page of PROG section)
(logStart; number of first flash page for LOG section)
(ramSplit; first accessible word when any lock is active)
© 2016 Integrated Device Technology, Inc.
133
January 29, 2016
ZSSC1956 Datasheet
The register FC_RAM_ADDR must be written with the RAM address where the word containing the three
boundaries was stored (see Table 4.11). The value to be programmed must be calculated by shifting the RAM
address pointing to that location by two bits to the right. The SET_BOUNDARY_CMD must be programmed into
the cmdbit field of register FC_CMD_SIZE (see Table 4.13). After that, the command execution must be started
by writing 1 to the exeCmdbit field of register FC_EXE_CMD.
When the command is started, the coreActivebit (FC_STAT_CORE[4]) is set. As long as the command is
active, all direct accesses to the flash (read and write), as well as writes to all registers of the flash controller, are
postponed. When software is running from RAM, the system is still able to run. Read accesses to the registers of
the flash controller are allowed while the command is active to check the status of the command execution. When
the command has finished, the coreActive bit (FC_STAT_CORE[4]) is cleared and the cmdRdy bit
(FC_STAT_CORE[0]) is set, which is cleared when read. If the command execution was rejected because the
memory protection is active, the invalidCmd bit (FC_STAT_CORE[1]) is also set. If the command was not
rejected, all three boundary fields within register SYS_MEMINFO in SMU are set to the programmed values at
end of the command execution.
Note: The execution time is approximately 72µs when the command is not rejected.
Note: The value to be programmed into register FC_RAM_ADDR does not contain the last two digits (always 0).
For this, the RAM address must be shifted right by two bits (value = (RAM address >> 2).
Note: This command does not erase the upper INFO page. Therefore software must ensure that the location
where the boundaries are stored is empty. If the location already contains boundary information, the
ERASE_KEY_CMD must be executed in advance.
4.4.1.9. SET_KEY_CMD – Storing the Key for the Key-Based Lock
This command stores the key required for the key-based lock from RAM into the upper INFO page at address
300HEX and following. It is only executed when no lock is active (SYS_MEMINFO[29:28] == 00BIN). Otherwise, the
command is rejected. For command execution, the settings of register FC_FLASH_ADDR, as well as the
wrSizebit field of register FC_CMD_SIZE, have no meaning. First, the key must be stored into the RAM using
the format shown in Table 4.10. The key has a selectable length of 1 to 32 bytes. The key length is contained in
the first key word. For a key length of 1, the key consists of key word 0 only; for a key length of 2, the key consists
of key word 0 and key word 1, and so on. A key length of 0 is interpreted as 32, which means that N is 31.
Table 4.10 Key Format
Address Offset
Bits 31:5
Bits 4:0
Key length
0
Key word 0
1
Key word 1
…
…
N (N<= 31)
Key word N
The register FC_RAM_ADDR must be written with the RAM address where the key word 0, which contains the
key length, was stored. The value to be programmed must be calculated by shifting the RAM address pointing to
that location by two bits to the right. The SET_KEY_CMD must be programmed into the cmdbit field of register
FC_CMD_SIZE. Next, the command execution must be started by writing 1 to the exeCmdbit field of register
FC_EXE_CMD.
© 2016 Integrated Device Technology, Inc.
134
January 29, 2016
ZSSC1956 Datasheet
When the command is started, the coreActivebit (FC_STAT_CORE[4]) is set. As long as the command is
active, all direct accesses to the flash (read and write) as well as writes to all registers of the flash controller are
postponed. When software is running from RAM, the system is still able to run. Read accesses to the registers of
the flash controller are allowed while the command is active to check the status of the command execution. When
the command has finished, the coreActive bit (FC_STAT_CORE[4]) is cleared and the bit cmdRdy
(FC_STAT_CORE[0]) is set, which is cleared when read. If the command execution was rejected because the
memory protection is active, the invalidCmdbit (FC_STAT_CORE[1]) is also set.
Note: Storing the key does not activate the key-based lock. For activation, the LOCK_KEY_CMD must be
executed (see section 4.4.1.11).
Note: After the key is stored but before the lock is activated, it is possible to read the key from the upper INFO
page. This might be needed to check that the programming was correct.
Note: The execution time depends on the number of key words. Approximately 72µs is needed for each key word
to be stored.
Note: The value to be programmed into register FC_RAM_ADDR does not contain the last two digits (always 0).
For this, the RAM address must be shifted right by two bits (value = (RAM address >> 2).
Note: This command does not erase the upper INFO page. Therefore software must ensure that the locations
where the key words are stored are empty. If the locations already contain a key, the ERASE_KEY_CMD must be
executed in advance.
4.4.1.10. LOCK_PERM_CMD – Activation of Permanent Lock
This command stores the value 0000 0000HEX at address 208HEX in the upper INFO page, which activates the
permanent lock. It is only executed when no lock is active (SYS_MEMINFO[29:28] == 00BIN). Otherwise, the
command is rejected. For command execution, the settings of registers FC_RAM_ADDR and FC_FLASH_ADDR
as well as the wrSizebit field of register FC_CMD_SIZE have no meaning. Only the LOCK_PERM_CMD must
be programmed into the cmd bit field of register FC_CMD_SIZE. After that, the command execution must be
started by writing 1 to the exeCmdbit field of register FC_EXE_CMD.
When the command is started, the coreActivebit (FC_STAT_CORE[4]) is set. As long as the command is
active, all direct accesses to the flash (read and write), as well as writes to all registers of the flash controller, are
postponed. When software is running from RAM, the system is still able to run. Read accesses to the registers of
the flash controller are allowed while the command is active to check the status of the command execution. When
the command has finished, the coreActive bit (FC_STAT_CORE[4]) is cleared and the cmdRdy bit
(FC_STAT_CORE[0]) is set, which is cleared when read. If the command execution was rejected because the
memory protection is active, the invalidCmd bit (FC_STAT_CORE[1]) is also set. If the command was not
rejected, the permanent lock bit (SYS_MEMINFO[29]) in the SMU is set to 1 at end of the command execution.
Note: The execution time is approximately 72µs if the command is not rejected.
Note: Make sure that the boundaries have been stored before execution of this command as they cannot be
programmed afterward.
Note: This lock can only be removed by first executing an appropriate erase command (ERASE_MAIN_CMD,
ERASE_BOOT_PROG_CMD, ERASE_PROG_CMD), which guarantees that the program section is empty, and
then executing the ERASE_KEY_CMD (see section 4.4.1.6).
© 2016 Integrated Device Technology, Inc.
135
January 29, 2016
ZSSC1956 Datasheet
Note: Reprogramming is possible by first executing an appropriate erase command (ERASE_MAIN_CMD,
ERASE_BOOT_PROG_CMD, ERASE_PROG_CMD) to get a temporary access due to set “allow” flags and then
performing the correct amount of WRITE_CMD commands. After a reset is applied or the “allow” flags are
cleared, the permanent lock is reactivated.
4.4.1.11. LOCK_KEY_CMD – Activation of Key-based Lock
This command stores the value 0000 0000HEX at address 20CHEX within the upper INFO page, which activates the
key-based lock. It is only executed when no lock is active (SYS_MEMINFO[29:28] == 00BIN). Otherwise, the
command is rejected. For command execution, the settings of registers FC_RAM_ADDR and FC_FLASH_ADDR
as well as the wrSizebit field of register FC_CMD_SIZE have no meaning. Only the LOCK_KEY_CMD must be
programmed into the cmdbit field of register FC_CMD_SIZE. After that, the command execution must be started
by writing 1 to the exeCmdbit field of register FC_EXE_CMD.
When the command is started, the coreActivebit (FC_STAT_CORE[4]) is set. As long as the command is
active, all direct accesses to the flash (read and write), as well as writes to all registers of the flash controller, are
postponed. When software is running from RAM, the system is still able to run. Read accesses to the registers of
the flash controller are allowed while the command is active to check the status of the command execution. When
the command has finished, the coreActive bit (FC_STAT_CORE[4]) is cleared and the cmdRdy bit
(FC_STAT_CORE[0]) is set, which is cleared when read. If the command execution was rejected because the
memory protection is active, the invalidCmd bit (FC_STAT_CORE[1]) is also set. If the command was not
rejected, the key-based lock bit (SYS_MEMINFO[28]) in the SMU is set to 1 at the end of the command
execution.
Note: The execution time is approximately 72µs if the command is not rejected.
Important: Ensure that the boundaries and the key have been stored before execution of this command as they
cannot be programmed afterward.
Note: This lock can be removed by first executing an appropriate erase command (ERASE_MAIN_CMD,
ERASE_BOOT_PROG_CMD, ERASE_PROG_CMD), which guarantees that the program section is empty, and
then executing the ERASE_KEY_CMD (see section 4.4.1.6). It can also be removed by successful execution of
the UNLOCK command (section 4.4.1.12). This is used to get access to the software as no erase is performed.
Note: Reprogramming is possible by first executing an appropriate erase command (ERASE_MAIN_CMD,
ERASE_BOOT_PROG_CMD, ERASE_PROG_CMD) to get a temporary access to set “allow” flags and then
performing the required WRITE_CMD commands. After a reset is applied or the “allow” flags are cleared, the key-
based lock is reactivated.
© 2016 Integrated Device Technology, Inc.
136
January 29, 2016
ZSSC1956 Datasheet
4.4.1.12. UNLOCK_CMD – Deactivation of the Key-Based Lock
This command is used to temporarily deactivate the key-based lock to get access to the BOOT and PROG
section. It is only executed when the key-based lock is active (SYS_MEMINFO[29:28] == 01BIN). Otherwise, the
command is rejected. For command execution, the settings of register FC_FLASH_ADDR, as well as the
wrSizebit field of register FC_CMD_SIZE, have no meaning. First, the key must be stored in the RAM in the
same manner as for programming the key using the format shown in Table 4.10. The register FC_RAM_ADDR
must be written with the RAM address where the key word 0 was stored. The value to be programmed must be
calculated by shifting the RAM address pointing to that location by two bits to the right. The UNLOCK_CMD must
be programmed into the cmdbit field of register FC_CMD_SIZE. Next, the command execution must be started
by writing 1 to the exeCmdbit field of register FC_EXE_CMD.
When the command is started, the coreActivebit (FC_STAT_CORE[4]) is set. As long as the command is
active, all direct accesses to the flash (read and write) as well as writes to all registers of the flash controller are
postponed. When the software is running from RAM, the system is still able to run. Read accesses to the registers
of the flash controller are allowed while the command is active to check the status of the command execution.
When the command has finished, the coreActive bit (FC_STAT_CORE[4]) is cleared and the cmdRdy bit
(FC_STAT_CORE[0]) is set, which is cleared when read. If the command execution was rejected because no lock
or the permanent lock is active, the bit invalidCmd(FC_STAT_CORE[1]) is also set. If the unlock procedure
failed due to a wrong key, the unlockFail bit (FC_STAT_CORE[3]) is set, the failure counter
(SYS_MEMINFO[31:30]) is incremented, and, if it was the third failure, the permanent lock is activated
(SYS_MEMINFO[29] set to 1). If the unlock procedure was successful, the key-based lock is deactivated
(SYS_MEMINFO[28] set to 0).
Important: Although the protection is removed in register SYS_MEMINFO, the protection remains in the upper
flash INFO page causing a temporary inconsistency between the register settings and the flash content. To
permanently remove the lock after the successful execution, an ERASE_KEY_CMD must be executed afterward
(see section 4.4.1.6). Otherwise the key-based lock will be reactivated after a reset is applied or a GETENV_CMD
is executed.
4.4.1.13. GETENV_CMD – Restoring Memory Protection
This command restores the memory protection and boundary information from the upper flash INFO page into the
register SYS_MEMINFO in the SMU. Although it can always be executed independent of the lock state, it is only
required to be performed after the successful execution of the UNLOCK_CMD when the lock will be reactivated.
For command execution, the settings of registers FC_RAM_ADDR and FC_FLASH_ADDR, as well as the
wrSizebit field of register FC_CMD_SIZE, have no meaning. Only the GETENV_CMD must be programmed
into the cmdbit field of register FC_CMD_SIZE. Next, the command execution must be started by writing 1 to the
exeCmdbit field of register FC_EXE_CMD.
When the command is started, the coreActivebit (FC_STAT_CORE[4]) is set. As long as the command is
active, all direct accesses to the flash (read and write), as well as writes to all registers of the flash controller, are
postponed. When software is running from RAM, the system is still able to run. Read accesses to the registers of
the flash controller are allowed while the command is active to check the status of the command execution. When
the command has finished, the coreActive bit (FC_STAT_CORE[4]) is cleared and the cmdRdy bit
(FC_STAT_CORE[0]) is set, which is cleared when read.
© 2016 Integrated Device Technology, Inc.
137
January 29, 2016
ZSSC1956 Datasheet
4.4.2.
Register Overview for Flash Controller
4.4.2.1. Register “FC_RAM_ADDR” – RAM Address for Command Execution
Table 4.11 Register FC_RAM_ADDR– system address 4000 0800HEX
Name
addrRam
Bits
Default
Access
Description
[10:0]
RW
RAM word address where data to be written into flash is located
(first address); hardware increments this address when more than
one word is to be written.
Commands requiring this register:
SET_KEY_CMD
SET_BOUNDARY_CMD
WRITE_CMD
0000 0000HEX
UNLOCK_CMD
Note: The last two address digits of the RAM are not included as
they are always 0. For programming, the RAM address must be
shifted right by two bits.
Unused
[31:11]
RO
Unused; always write as 0.
4.4.2.2. Register “FC_FLASH_ADDR” – FLASH Address for Command Execution
Table 4.12 Register FC_FLASH_ADDR– system address 4000 0804HEX
Name
flashAddr
Bits
Default
Access
Description
[14:0]
RW
Flash word address (first address) where data will be written; also
used as the pointer to the page to be erased.
Commands requiring this register:
WRITE_CMD
ERASE_MAINPAGE_CMD
0000 0000HEX
Note: The last two address digits of the flash are not included as
they are always 0. For programming, the flash address must be
shifted right by two bits.
Unused
[31:15]
RO
Unused; always write as 0.
© 2016 Integrated Device Technology, Inc.
138
January 29, 2016
ZSSC1956 Datasheet
4.4.2.3. Register “FC_CMD_SIZE” – Command Setup and Write Size Configuration
Table 4.13 Register FC_CMD_SIZE– system address 4000 0808HEX
Name
Bits
Default
Access
Description
cmd
[3:0]
RW
Command to be executed by the flash controller.
Valid commands:
0HEX: ERASE_MAIN_CMD
2HEX: ERASE_BOOT_PROG_CMD
3HEX: ERASE_PROG_CMD
4HEX: ERASE_MAINPAGE_CMD
6HEX: ERASE_KEY_CMD
8HEX: UNLOCK_CMD
9HEX: GETENV_CMD
AHEX: WRITE_CMD
CHEX: SET_KEY_CMD
0000 0000HEX
DHEX: SET_BOUNDARY_CMD
EHEX: LOCK_PERM_CMD
FHEX: LOCK_KEY_CMD
Unused
wrSize
[7:4]
[12:8]
RO
RW
Unused; always write as 0.
Number of words to be written to the flash; 0 is interpreted as 32.
Note: Writing is always performed within a row. 1 row contains 32
words. While the RAM address is always incremented, the flash
address wraps at the row boundary to the beginning of the row. It
is in the responsibility of the user to take care of this.
Unused
[31:13]
RO
Unused; always write as 0.
4.4.2.4. Register “FC_EXE_CMD” – Start Command Execution
Table 4.14 Register FC_EXE_CMD– system address 4000 080CHEX
Name
exeCmd
Bits
Default
Access
Description
[0]
RW
Writing 1 to this bit starts the execution of the configured
command; always read as 0.
0000 0000HEX
Unused
[31:1]
RO
Unused; always write as 0.
© 2016 Integrated Device Technology, Inc.
139
January 29, 2016
ZSSC1956 Datasheet
4.4.2.5. Register “FC_IRQ_EN” – Interrupt Enables
Table 4.15 Register FC_IRQ_EN– system address 4000 0810HEX
Name
Bits
Default
Access
Description
enIrq0
enIrq1
enIrq2
enIrq3
enIrq4
enIrq5
enIrq6
enIrq7
[0]
0BIN
RW
When set to 1, the status signal cmdRdyis allowed to drive the
interrupt line.
When set to 1, the status signal invalidCmdis allowed to drive
the interrupt line.
When set to 1, the status signal invalidAreais allowed to
drive the interrupt line.
When set to 1, the status signal unlockFail is allowed to drive
the interrupt line.
When set to 1, the status signal dataAll1is allowed to drive the
interrupt line.
When set to 1, the status signal data1Err is allowed to drive
the interrupt line.
When set to 1, the status signal data2Err is allowed to drive
the interrupt line.
When set to 1, the status signal prog1Err is allowed to drive
the interrupt line.
[1]
[2]
0BIN
0BIN
RW
RW
RW
RW
RW
RW
RW
RO
[3]
0BIN
[4]
0BIN
[5]
0BIN
[6]
0BIN
[7]
0BIN
00 0000HEX
Unused
[31:8]
Unused; always write as 0.
4.4.2.6. Register “FC_STAT_CORE” – FLASH Controller Core Status
Table 4.16 Register FC_STAT_CORE– system address 4000 0814HEX
Name
cmdRdy
Bits
Default
Access
Description
[0]
RC
This bit is set when a command execution has finished; it is
cleared when this register is read.
invalidCmd
invalidArea
[1]
[2]
RC
RC
This bit is set when an invalid command was executed; it is
cleared when this register is read.
This bit is set when a command is executed targeting a protected
area; e.g., performing ERASE_MAINPAGE_CMD to program
space when the flash is locked. It is cleared when this register is
read.
unlockFail
coreActive
allowKey
allowBoot
allowProg
[3]
[4]
[5]
[6]
[7]
RC
RO
RO
RO
RO
This bit is set when the UNLOCK_CMD fails; it is cleared when this
register is read.
This bit reflects the status of the core state machine; when set, the
core is active.
When set but flash is locked, the ERASE_KEY_CMD is allowed to
be performed.
When set but flash is locked, the WRITE_CMD is allowed to be
performed on the boot space.
0000 0000HEX
When set but flash is locked, the WRITE_CMD is allowed to be
performed on the program space.
clrAllow
Unused
[8]
[31:9]
W1C
RO
Writing 1 to this bit clears all 3 allow flags.
Unused; always write as 0.
© 2016 Integrated Device Technology, Inc.
140
January 29, 2016
ZSSC1956 Datasheet
4.4.2.7. Register “FC_STAT_PROG” – FLASH Controller Instruction Fetch Status
Table 4.17 Register FC_STAT_PROG– system address 4000 0818HEX
Name
addrProg
Bits
Default
Access
Description
[17:0]
RO
This register contains the address of the instruction fetch error that
caused the first of the three flags below to be set; the highest bit is
used to distinguish between MAIN (0) and INFO (1) area.
Unused; always read as 0.
This bit is set when an instruction fetch occurs to an erased
memory address; it is cleared when this register is read.
This bit is set when a correctable error occurs during an instruction
fetch; it is cleared when this register is read.
Unused
progAll1
[28:18]
[29]
RO
RC
0000 0000HEX
prog1Err
prog2Err
[30]
[31]
RC
RC
This bit is set when an uncorrectable error occurs during an
instruction fetch; it is cleared when this register is read.
4.4.2.8. Register “FC_STAT_DATA” – FLASH Controller Data Load Status
Table 4.18 Register FC_STAT_DATA– system address 4000 081CHEX
Name
addrData
Bits
Default
Access
Description
[17:0]
RO
This register contains the address of the read error that caused the
first of the three flags below to be set; the highest bit is used to
distinguish between MAIN (0) and INFO (1) area.
Unused; always read as 0.
This bit is set when a read is performed to an erased memory
address; it is cleared when this register is read.
This bit is set when a correctable error occurs during a read; it is
cleared when this register is read.
Unused
dataAll1
[28:18]
[29]
RO
RC
0000 0000HEX
data1Err
data2Err
[30]
[31]
RC
RC
This bit is set when an uncorrectable error occurs during a read; it
is cleared when this register is read.
4.5. GPIO
There are 16 GPIO pads (GPIO00 to GPIO15) implemented in the MCU, but only the lower five (GPIO00 –
GPIO04) are bonded out of the package. The unbonded GPIO pads contain a pull-up resistor in their pad and
must never be used (must be kept in their default state as input). The bonded GPIO pads contain pull-down
resistors.
Note: Do not use unbonded GPIO pads. Keep them in their reset state where they are configured as inputs.
Each GPIO pad can be individually configured to operate as an input or output. When configured as an output,
the value driven out of the GPIO pad can be directly written or controlled via a set-clear register. Additionally,
each GPIO can be enabled to be used as a trigger source for the 32-bit timer or it can be used as an interrupt
source with a selectable edge.
Note: Each register in the GPIO module can be accessed on byte, half-word and word size.
© 2016 Integrated Device Technology, Inc.
141
January 29, 2016
ZSSC1956 Datasheet
4.5.1.
Normal Functionality
When a GPIO pad should be used as a simple input or output, registers GPIO_DIR, GPIO_IN, GPIO_OUT and
GPIO_SETCLR are needed. Register GPIO_DIR is used to select the direction of the GPIO pad (see Table 4.19).
By default, the GPIO pad is configured as an input pad. The synchronized value from that pad can be read by
reading register GPIO_IN (see Table 4.20). The values from those GPIO pads that are configured as outputs or
which have other functionality will be ignored.
The value driven out of a GPIO pad that is configured as an output can be set by writing to register GPIO_OUT
(see Table 4.21). The initial value can already be written before switching the direction from input to output.
Instead of writing all output values in each access, it is also possible to set and clear dedicated output values by
using the register GPIO_SETCLR (see Table 4.22). This functionality avoids needing to read and modify the
GPIO_OUT register when only some bits need to be changed.
Note: In addition to the internal configuration, the settings of register SYS_MEMPORTCFG (see Table 4.6) in the
SMU module must be taken into account. This register is used to configure the output type (push-pull or open-
drain (default)) and to map sub-modules of the ZSYSTEM2 module onto GPIO pads. When the latter is true,
normal GPIO functionality is not available.
4.5.2.
Trigger Functionality
Each GPIO pad can be used as an external trigger source for the 32-bit timer (see section 4.6). To enable the
trigger functionality, the GPIO pad must be configured as an input and the trigger functionality must be enabled
via register GPIO_TRIGEN (see Table 4.26). It is possible to enable several GPIO pads as external trigger
sources; however it is not recommended because power consumption slightly increases when trigger functionality
is enabled.
Note: It is not sufficient to enable a GPIO pad as a trigger source. The 32-bit timer must also be configured
appropriately, and the desired GPIO trigger source must be selected via register T32_TRIGSEL (see Table 4.29)
within the 32-bit timer.
4.5.3.
Interrupt Functionality
Each GPIO pad can be used as an external, edge-sensitive interrupt source. To enable the interrupt functionality,
the GPIO pad must be configured as an input and the interrupt functionality must be enabled via register
GPIO_IRQEN. Additionally, it is selectable via register GPIO_IRQEDGE whether a rising or a falling edge on the
GPIO pad activates the interrupt (see Table 4.25).
All GPIO pads enabled as external interrupt sources drive one single interrupt line connected to ARM® interrupt 5.
The user can determine which GPIO pad caused the interrupt by reading register GPIO_IRQSTAT. All interrupt
status bits are cleared when reading register GPIO_IRQSTAT (see Table 4.23).
Note: As the synchronization flip-flops are only continuously clocked when the trigger or interrupt functionality is
enabled for the corresponding GPIO pad, it might be possible that an unwanted interrupt occurs when enabling
the interrupt functionality. To avoid this, the following sequence must be guaranteed by software:
•
•
•
Enable the GPIO trigger functionality and select the desired interrupt edge to be used.
Enable the GPIO interrupt functionality at least three cycles after enabling as a trigger.
Disable the GPIO trigger functionality (when not needed in parallel).
© 2016 Integrated Device Technology, Inc.
142
January 29, 2016
ZSSC1956 Datasheet
4.5.4.
Register Overview of GPIO Module
4.5.4.1. Register “GPIO_DIR” – GPIO Direction
Table 4.19 Register GPIO_DIR– system address 4000 1400HEX
Name
gpioDir
Bits
Default
Access
Description
[15:0]
0000HEX
RW
Direction of each GPIO.
1: GPIO pad is switched as an output
0: GPIO pad is switched as an input
Unused
[31:16]
0000HEX
RO
Unused; always write as 0.
4.5.4.2. Register “GPIO_IN” – GPIO Input Value
Table 4.20 Register GPIO_IN– system address 4000 1404HEX
Name
Bits
Default
Access
Description
gpioIn
Unused
[15:0]
[31:16]
0000HEX
0000HEX
RO
RO
Synchronized input value.
Unused; always write as 0.
4.5.4.3. Register “GPIO_OUT” – GPIO Output Value
Table 4.21 Register GPIO_OUT– system address 4000 1408HEX
Name
gpioOut
Unused
Bits
Default
Access
Description
[15:0]
[31:16]
0000HEX
0000HEX
RW
RO
Value to be driven out of each GPIO; can be selected individually.
Unused; always write as 0.
4.5.4.4. Register “GPIO_SETCLR” – Set and Clear for GPIO Output Value
Table 4.22 Register GPIO_SETCLR– system address 4000 140CHEX
Name
Bits
Default
Access
Description
15 : 0
[15:0]
0000HEX
WO
There is one set bit per GPIO; the value driven out of the GPIO is
set to 1 when 1 is written to the corresponding bit (lower priority
than clear); always read as 0.
31 : 16
[31:16]
0000HEX
WO
There is one set bit per GPIO; the value driven out of the GPIO is
set to 0 when 1 is written to the corresponding bit (higher priority
than set); always read as 0.
© 2016 Integrated Device Technology, Inc.
143
January 29, 2016
ZSSC1956 Datasheet
4.5.4.5. Register “GPIO_IRQSTAT” – Interrupt Status
Table 4.23 Register GPIO_IRQSTAT– system address 4000 1410HEX
Name
irqStat
Bits
Default
Access
Description
[15:0]
0000HEX
RC
This register reflects the interrupt status of each GPIO that is
enabled as an interrupt.
Unused
[31:16]
0000HEX
RO
Unused; always write as 0.
4.5.4.6. Register “GPIO_IRQEN” – Interrupt Enable
Table 4.24 Register GPIO_IRQEN– system address 4000 1414HEX
Name
Bits
Default
Access
Description
irqEn
[15:0]
0000HEX
RW
When set to 1, the corresponding interrupt is allowed to drive the
interrupt line when the appropriate edge occurs.
Unused; always write as 0.
Unused
[31:16] 0000HEX
RO
4.5.4.7. Register “GPIO_IRQEDGE” – Edge Selection for Interrupt
Table 4.25 Register GPIO_IRQEDGE– system address 4000 1418HEX
Name
irqEdge
Bits
Default
Access
Description
[15:0]
0000HEX
RW
0: a rising edge on the corresponding GPIO triggers the IRQN line
1: a falling edge on the corresponding GPIO triggers the IRQN line
Unused; always write as 0.
Unused
[31:16] 0000HEX
RO
4.5.4.8. Register “GPIO_TRIGEN” – Trigger Enable
Table 4.26 Register GPIO_TRIGEN– system address 4000 141CHEX
Name
Bits
Default
Access
Description
trigEn
Unused
[15:0]
[31:16] 0000HEX
0000HEX
RW
RO
When set to 1, the corresponding GPIO drives its trigger line.
Unused; always write as 0.
© 2016 Integrated Device Technology, Inc.
144
January 29, 2016
ZSSC1956 Datasheet
4.6. 32-Bit Timer
The timer provides event counting on the rising clock edge with a 32-bit resolution. It is capable of counting clock
events in Timer Mode and counting events from a selectable external trigger signal in Counter Mode. The external
trigger can be configured to operate on the rising or falling edges as well as on the low or high level. Additionally,
it can be selected whether the timer/counter stops when it overflows or continues its operation.
The timer has an interrupt line that is active-high and set high for a single clock cycle whenever the counter
overflows. The interrupt line is connected to ARM® interrupt 4.
Note: The counter is incremented when enabled.
4.6.1.
Timer Mode
In Timer Mode (bit modeTC in register T32_CTRL == 0), the counter register is incremented in each clock cycle
(see Table 4.28). When the counter reaches FFFF FFFFHEX, the reload value is copied into the counter register
and both the overflow bit and the interrupt line are set high for one clock cycle. When Reload Mode is enabled
(modeSR== 0), the counter continues counting. Otherwise the counter stops. The two other control bits (modeLE
and modePN) have no meaning in this mode.
4.6.2.
Counter Mode
In Counter Mode (bit modeTCin register T32_CTRL== 0), the counter register is incremented in each clock cycle
when the trigger is active. When the counter has a value of FFFF FFFFHEX and the trigger is active, the reload
value is copied into the counter register and both the overflow bit and the interrupt line are set high for one clock
cycle. When Reload Mode is enabled (modeSR == 0), the counter continues counting. Otherwise the counter
stops. The two control bits modeLEand modePNare used to configure the trigger as shown in Table 4.27.
Table 4.27 Configuration of Trigger Behavior
modeLE
modePN
Behavior
0
0
The trigger is active when the trigger input is low but was high in the previous clock cycle
(sensitive on falling edge).
0
1
The trigger is active when the trigger input is high but was low in the previous clock cycle
(sensitive on rising edge).
1
1
0
1
The trigger is active when the trigger input is low (sensitive on low level).
The trigger is active when the trigger input is high (sensitive on high level).
© 2016 Integrated Device Technology, Inc.
145
January 29, 2016
ZSSC1956 Datasheet
4.6.3.
Timer Module Register Overview
4.6.3.1. Register “T32_CTRL” – Timer Control
Table 4.28 Register T32_CTRL– system address 4000 1000HEX
Name
Bits
Default
Access
Description
en
[0]
RW
Enable bit for timer; this bit is cleared by hardware when an
overflow occurs and the module is operating in Single-Shot Mode.
Select between the timer and counter modes:
modeTC
[1]
RW
0: Timer Mode
1: Counter Mode
modeSR
[2]
RW
Select between the reload and single-shot modes.
0: Reload Mode; at overflow, the reload value is copied into the
counter register and the counter continues
1: Single-Shot Mode; at overflow, the reload value is copied into
the counter register and the counter stops
modeLE
modePN
[3]
[4]
RW
RW
Select between level or edge sensitive trigger; Counter Mode only.
0000 0000HEX
0: Trigger is edge-sensitive
1: Trigger is level-sensitive
Selects between the rising or falling edge active trigger
(modeLE == 1) or high or low level (modeLE == 0); Counter Mode
only.
0: Trigger on the falling edge / low level
1: Trigger on the rising edge / high level
Overflow flag (strobe); set for a single cycle when the counter
overflows; this bit also drives the interrupt line.
Unused; always write as 0.
overflow
Unused
[5]
RO
RO
[31:6]
4.6.3.2. Register “T32_TRIGSEL” – Trigger Selection
Table 4.29 Register T32_TRIGSEL– system address 4000 1004HEX
Name
Bits
Default
Access
Description
Select signal for the trigger source.
trigSel
[4:0]
RW
00000BIN: No trigger source
00001BIN: GPIO00 is used as trigger source
00010BIN: GPIO01 is used as trigger source
…
0000 0000HEX
10000BIN: GPIO15 is used as trigger source
10001BIN to 11111BIN: no trigger source
Unused; always write as all 0s.
Unused
[31:5]
RO
© 2016 Integrated Device Technology, Inc.
146
January 29, 2016
ZSSC1956 Datasheet
4.6.3.3. Register “T32_CNT” – Timer Value
Table 4.30 Register T32_CNT– system address 4000 1008HEX
Name
counter
Bits
Default
Access
Description
0000 0000HEX
[31:0]
RW
Timer value; this register can be written directly whether or not the
timer is enabled. It is set to the reload value when reload value is
written.
4.6.3.4. Register “T32_REL” – Timer Reload Value
Table 4.31 Register T32_REL– system address 4000 100CHEX
Name
reloadVal
Bits
Default
Access
Description
0000 0000HEX
[31:0]
RW
Timer reload value; when the timer (counter) overflows, the reload
value is copied into the counter register. In Reload Mode, the timer
continues; when Reload Mode is not enabled, the timer stops.
© 2016 Integrated Device Technology, Inc.
147
January 29, 2016
ZSSC1956 Datasheet
4.7. LIN Communication Control Logic (ahbLIN)
Although the LIN PHY is integrated in the SBC (see section 3.9), LIN communication is controlled by the ahbLIN
block (the “LIN UART” block in Figure 2.2) on the MCU side (ahb stands for the Advanced High-performance Bus
widely used on ARM® microcontrollers). The ahbLIN has access to the TXD and RXD lines going to the LIN PHY
on the SBC.
The ahbLIN module is the communication control logic that performs the serial communication interface (SCI)
according the LIN Protocol Specification (Revision 2.2, SAE J2602). The type of the interface is LIN slave.
The LIN communication logic has a modular structure of different independent transceiver processes. The
processes are driven by the synchronized serial data stream linRxD and linTxD and are controlled by the LIN ahb
controller module.
Figure 4.6 ahbLIN Block Diagram
© 2016 Integrated Device Technology, Inc.
148
January 29, 2016
ZSSC1956 Datasheet
Key Features:
Support of the LIN Specification 2.2
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Support of SAE J2602
Autobauding; i.e., synchronization using the first received LIN frame
Programmable baud rate between 1kBit/s and 20kBit/s
Programmable LIN bus idle time
Programmable LIN wake up time
LIN frame header length supervision
Validation of protected frame identifiers (parity check)
Bit sample majority (7/16, 8/16, 9/16)
Rx monitoring
Rx polarity switch
Tx bit boundary cancel
Tx polarity switch
Unambiguous break field detection to support correct error response reporting
Suppression of active LIN frame reception (invalid identifier >> wait for next LIN frame)
AMBA 3 AHB-Lite host controller interface
4.7.1.
Functional Description
The "Sync" module synchronizes the incoming serial bit-stream by the ASIC clock. To avoid malfunction due to
spikes on the data stream, glitch suppression is implemented by checking for a minimum pulse width of three
clock cycles.
The basic data receiver of the serial communication interface is the "UART" module with a byte-filled receiver,
triggered by the first falling edge of the start bit and terminated after eight consecutive data bits with the stop bit
data value "1.” The oversampling rate of each data bit is 16, and the bit data is determined by the bit-sample
majority decision of samples 7/16, 8/16 and 9/16.
The "UART" transmitter when triggered by the software allows sending byte fields with the corresponding
programmed baud rate. For LIN protocol requirements, the receiver monitoring function is implemented to check
the consistency of the bidirectional LIN physical line.
The Break Sync detector is used to identify the beginning of a new LIN frame, and it checks the "Sync” byte field
for consistency with the programmed baud rate. The durations of the Break field low phase and Break field
delimiter are measured and can be monitored by the software. Additional software-defined thresholds are used for
successful frame synchronization. The LIN header inter-byte space between the "Sync" byte field and the
Protected Identifier field is measured to evaluate the maximum LIN frame header length.
The "Autobauding" module determines the baud rate on the basis of the first received Break field and Sync field. It
ensures that the first received frame is synchronized and valid for LIN communication. The duration of the Break
field low phase and Break field delimiter is measured and can be monitored by the software. To support a
complete Break Sync field pattern validation, the Sync field’s bit 7 data value and the stop bit data value are
verified.
© 2016 Integrated Device Technology, Inc.
149
January 29, 2016
ZSSC1956 Datasheet
The "IdleWakeUp" module supports the LIN Protocol Specification 2.2, chapters 2.6.2 WAKE UP and 2.6.3 GO
TO SLEEP. The threshold for the dominant pulse length after a recessive-to-dominant change for the WAKE UP
scenario is defined by a programmable parameter. The inactivity time length for the GO TO SLEEP scenario is
defined by a programmable threshold parameter. This allows significant flexibility for low pulse length and
inactivity time definitions.
4.7.2.
Overview of Registers for LIN ahb Controller
4.7.2.1. Register “LIN_CFG” – Configuration
Table 4.32 Register LIN_CFG – system address 4000 1800HEX
Name
Bits
Default
Access
Description
UART receive process
0BIN: disable
rx_enable
[0]
RW
1BIN: enable
UART transmit process
0BIN: disable
1BIN: enable
Break Sync Detection control
0BIN: disable
1BIN: enable
Autobauding process control
0BIN: disable
1BIN: enable
Idle monitor control
tx_enable
break_sync
autobauding
idle
[1]
[2]
[3]
[4]
RW
RW
RW
RW
0BIN: disable
1BIN: enable
00000000HEX
Evaluated autobaudrate is applied to Break Sync and
UART process
0BIN: apply ctrl_baudratedefined by software
(LIN_BAUDRATEregister)
1BIN: apply auto_baudrate(LIN_BAUDRATE
register)
apply-autobaudrate
[5]
RW
Receiver monitoring at active transmitting
0BIN: transmitted signal is validated at TBIT/2
1BIN: transmitted serial signal is validated by
receiver process
UART receive process
0BIN: off
rx_monitoring
wakeup
[6]
[7]
RW
RW
1BIN: wakeup monitor active
© 2016 Integrated Device Technology, Inc.
150
January 29, 2016
ZSSC1956 Datasheet
Name
Bits
Default
Access
Description
Strobe Bit: Wait for new Break field reception
0BIN: no action
break_trigger
[8]
W
1BIN: suppress UART receiver flags until new
Break Sync field reception
Rxdat0 mode
0BIN: off
1BIN: if 11 consecutive bits = ‘0’ >> suppress rx
status flags assertion
1BIN: if 10 consecutive bits = ‘0’ >> extend rx
status flag assertion at 10.5 TBIT
1BIN: if fewer than 10 consecutive bit =’0’ >> rx
status flag assertion at 9.5 TBIT
rxdat0_mode
[9]
RW
Receiver start bit data verification:
0BIN: start bit data not checked
1BIN: start bit data checked (sampling point
defined by rx_bit_sample_majority
bit [12] below)
rx_start_bit_verification
tx_bit_boundary
[10]
[11]
[12]
RW
RW
RW
Cancel transmission (linTxD = recessive 1BIN) at bit
boundary if framing error or data error detected
0BIN: off
1BIN: active
Receiver sampling mode
0BIN: sampling time point = TBIT/2
1BIN: sampling time points = 7/16 and 8/16 and
9/16 TBIT
rx_bit_sample_majority
Bit samples majority determines the bit data.
LIN bus idle detector sampling mode
0BIN: continuous monitoring of rx_sync line
1BIN: sampling points = 216 clock period (1.6µs,
3.2µs, 6.4µs, 12.8µs); the majority of 3
consecutive samples determines the bit
data.
idle_bit_sample_majority
[13]
RW
LIN wakeup detector sampling mode
0BIN: continuous monitoring of rx_sync line
1BIN: sampling points = 216 clock periods (1.6µs,
3.2µs, 6.4µs, 12.8µs); the majority of 3 con-
secutive samples determines the bit data.
Break Sync detector sampling mode
0BIN: sampling time point TBIT/2
wakeup_bit_sample_majority
[14]
[15]
RW
RW
break_sync_bit_sample_majority
1BIN: sampling time points: 7/16 & 8/16 & 9/16 TBIT
Bit samples majority determines the bit data.
© 2016 Integrated Device Technology, Inc.
151
January 29, 2016
ZSSC1956 Datasheet
Name
Bits
Default
Access
Description
Break low phase length threshold for autobauding
process
0000BIN: 11 TBIT
0001BIN: 11 + 11/128 TBIT
0010BIN: 11 + 11/64 TBIT
0011BIN: 11 + 11/32 TBIT
0100BIN: 11 + 11/16 TBIT
autobauding_threshold
[19:16]
RW
1001BIN: 11 – 11/128 TBIT
1010BIN: 11 – 11/64 TBIT
1011BIN: 11 – 11/32 TBIT
1100BIN: 11 – 11/16 TBIT
Others: 11 TBIT
Test strobe register to trigger receive sequence; read
as 0BIN
rx_start
rx_inverse
tx_start
[20]
[21]
[22]
[23]
W
RW
W
0BIN: off
1BIN: trigger receive sequencer
Test register for inverse of linRxD bit value
0BIN: off
1BIN: linRxD bit value inverted
Test strobe register to trigger transmit sequencer; read
as 0BIN
0BIN: off
1BIN: trigger transmit sequencer
Test register for inversion of linTxD bit value
0BIN: off
tx_inverse
RW
1BIN: linTxD bit value inverted
Test register for start and stop bit value for byte field
transmission
0BIN: start_bit = 0BIN and stop_bit = 1BIN
1BIN: start_bit = bit [8] in LIN_TXDATAregister
and
tx_start_stop
[24]
RW
stop_bit = bit [9] in LIN_TXDATAregister
Test register for basic UART mode
0BIN: Rx and Tx are locked
unlock
[25]
RW
RO
1BIN: Rx and Tx are unlocked
Unused
[31:26]
Unused; read as 0.
© 2016 Integrated Device Technology, Inc.
152
January 29, 2016
ZSSC1956 Datasheet
4.7.2.2. Register “LIN_RXDATA” – RX data
Table 4.33 Register LIN_RXDATA – system address 4000 1804HEX
Name
Bits
[0:7]
[8]
Default
00HEX
0BIN
Access
Description
rx_data
RO
RO
Received byte field data value.
Received byte field start bit data.
rx_start_bit
rx_stop_bit
RO
RO
[9]
0BIN
Received byte field stop bit data.
linRxD bit data synchronized by clock.
rx_sync
Unused
[10]
0BIN
Note: can be changed after reset (sampling of serial input stream
after reset).
[31:11]
RO
Unused; read as 0.
4.7.2.3. Register “LIN_TXDATA” – TX data
Table 4.34 Register LIN_TXDATA – system address 4000 1808HEX
Name
Bits
Default
Access
Description
tx_data
[7:0]
00HEX
W
Transmit byte field value (write only, read as 0).
Transmit byte field start bit data (write only, read as 0).
Only applicable if unlock = 1BIN and transfer size is word or
halfword.
tx_start_bit
[8]
0BIN
W
Transmit byte field stop bit value (write only, read as 0).
Only applicable if unlock = 1BIN and transfer size is word or
halfword
tx_stop_bit
Unused
[9]
0BIN
W
[31:10]
RO
Unused; read as 0.
4.7.2.4. Register “LIN_HEADERLEN” – LIN header length
Table 4.35 Register LIN_HEADERLEN – system address 4000 180CHEX
Name
Bits
Default
Access
Description
Measured length of Break field low phase (TBIT/16)
0000BIN: 0/16 TBIT
0001BIN: 1/16 TBIT
…
T_BRKFLD_16
[3:0]
0000BIN
RO
1111BIN: 15/16 TBIT
Measured length of Break field low phase (TBIT
)
0000BIN: 0 TBIT
0001BIN: 1 TBIT
….
T_BRKFLD
Unused
[8:4]
0000BIN
RO
RO
1111BIN: 31 TBIT
[15:9]
Unused; always read as 0.
© 2016 Integrated Device Technology, Inc.
153
January 29, 2016
ZSSC1956 Datasheet
Name
Bits
Default
Access
Description
Measured length of Break field delimiter (TBIT/16)
0000BIN: 0/16 TBIT
0001BIN: 1/16 TBIT
…
T_BRKDEL_16
[19:16]
0000BIN
RO
1111BIN: 15/16 TBIT
Measured length of Break field low phase (TBIT
)
0000BIN: 0 TBIT
0001BIN: 1 TBIT
….
T_BRKDEL
[23:20]
0000BIN
RO
1111BIN: 31 TBIT
When set to 1, the corresponding status bit is allowed to drive the
IRQ output.
When set to 1, the corresponding status bit is allowed to drive the
IRQ output.
When set to 1, the corresponding status bit is allowed to drive the
IRQ output.
When set to 1, the corresponding status bit is allowed to drive the
IRQ output.
rxOverflow_LIN_irq
wrCollision_LIN_irq
txOff_irq
[4]
[5]
[6]
0BIN
0BIN
0BIN
0BIN
RW
RW
RW
inactive_irq
Unused
[7]
RW
RO
[31:8]
Unused; read as 0.
4.7.2.5. Register “LIN_BAUDRATE” – LIN baud rate
Table 4.36 Register LIN_BAUDRATE– system address 4000 1810HEX
Name
Bits
Default
Access
Description
Controller defined baudrate
ctrl_baudrate
[14:0]
03E8HEX
RO
ctrl_baudrate = Tbit / PI ASIC clock period (50ns)
Example: 03E8HEX = 50µs / 50ns
Unused
auto_baudrate
Unused
[15]
[30:16]
[31]
RO
RW
RO
Unused; always write as 0.
Evaluated baudrate from autobauding process
Tbit = auto_baudrate x PI ASIC clock period (50ns)
0000HEX
Unused; read as 0
© 2016 Integrated Device Technology, Inc.
154
January 29, 2016
ZSSC1956 Datasheet
4.7.2.6. Register “LIN_BRKLOW” – LIN Break field low phase
Table 4.37 Register LIN_BRKLOW– system address 4000 1814HEX
Name
Bits
Default
Access
Description
Minimum threshold of Break field low phase (TBIT/16)
0000Bin: 0/16 TBIT
brk_low_min_threshold/16
[3:0]
0000BIN
RW
0001Bin: 1/16 TBIT
…
1111Bin: 15/16 TBIT
Minimum threshold of Break field low phase (TBIT
00000Bin: 0 TBIT
)
brk_low_min_threshold
Unused
[8:4]
[15:9]
[19:16]
01011BIN
RW
RO
RW
00001Bin: 1 TBIT
…
11111Bin: 31 TBIT
Unused; always write as 0.
Maximum threshold of Break field low phase (TBIT/16)
0000Bin: 0/16 TBIT
brk_low_max_threshold/16
1010BIN
0001Bin: 1/16 TBIT
…
1111Bin: 15/16 TBIT
Maximum threshold of Break field low phase (TBIT
00000Bin: 0 TBIT
)
brk_low_max_threshold
Unused
[24:20]
[31:25]
1010BIN
RW
RO
00001Bin: 1 TBIT
…
11111Bin: 31 TBIT
Unused; read as 0.
© 2016 Integrated Device Technology, Inc.
155
January 29, 2016
ZSSC1956 Datasheet
4.7.2.7. Register “LIN_HINTERBRKDEL” – LIN interbyte and Break field delimiter
Table 4.38 Register LIN_HINTERBRKDEL – system address 4000 1818HEX
Name
Bits
Default
Access
Description
Minimum threshold of Break field delimiter
(TBIT/16)
0000Bin: 0/16 TBIT
0001Bin: 1/16 TBIT
brk_delimiter_min_threshold/16
[3:0]
1010BIN
RW
…
1111Bin: 15/16 TBIT
Minimum threshold of Break field delimiter (TBIT
0000Bin: 0 TBIT
)
brk_delimiter_min_threshold
[7:4]
0000BIN
RW
RW
0001Bin: 1 TBIT
…
1111Bin: 15 TBIT
Maximum threshold of Break field delimiter
(TBIT/16)
0000Bin: 0/16 TBIT
brk_delimiter_max_threshold/16
[11:8]
0000BIN
0001Bin: 1/16 TBIT
…
1111Bin: 15/16 TBIT
Maximum threshold of Break field delimiter
(TBIT
)
0000Bin: 0 TBIT
0001Bin: 1 TBIT
…
brk_delimiter_max_threshold
h_interbyte_max_threshold/16
[15:12]
[19:16]
1110BIN
0000BIN
1110BIN
RW
RW
1111Bin: 15 TBIT
Maximum threshold of header inter-byte space
(TBIT/16)
0000Bin: 0/16 TBIT
0001Bin: 1/16 TBIT
…
1111Bin: 15/16 TBIT
Maximum threshold of header inter-byte space
(TBIT
)
0000Bin: 0 TBIT
0001Bin: 1 TBIT
…
h_interbyte_max_threshold
Unused
[23:20]
[31:24]
RW
RO
1111Bin: 15 TBIT
Unused; read as 0
© 2016 Integrated Device Technology, Inc.
156
January 29, 2016
ZSSC1956 Datasheet
4.7.2.8. Register “LIN_WAKEUPIDLE” – LIN wakeup threshold and LIN idle
Table 4.39 Register LIN_WAKEUPIDLE – system address 4000 181CHEX
Name
Bits
Default
Access
Description
LIN bus idle threshold (bit [4] in the LIN_CFGregister = 1BIN
)
Exceeding bus idle threshold >> bit [5] in the LIN_STAT
register = 1BIN; see Table 4.42
bus_idle_th
[15:0]
4C4CHEX
RW
bus_idle_th= Tbusidle / (212 x 50ns)
Example: 212 x dec(4C4CHEX) x 50ns = 4s = Tbusidle
(See the LIN Protocol Specification Rev. 2.2 for the definition of
Tbusidle.)
LIN wakeup threshold (bit [7] in the LIN_CFGregister = 1BIN
)
Exceeding wakeup threshold >> bit [6] in the LIN_STAT
register = 1BIN
wakeup_th
[31:16]
05DCHEX
RW
wakeup_th= Twakeup / (2 x 50ns)
See the LIN Protocol Specification Rev. 2.2 for the definition of
Twakeup
)
4.7.2.9. Register “LIN_IREN” – Interrupt enable
Table 4.40 Register LIN_IREN – system address 4000 1820HEX
Name
Bits
Reset
Access
Description
Receive byte field complete interrupt enable
0BIN: bit [0] in the LIN_STATregister is disabled from
driving interrupt request signal linIrq
0BIN
rx_byte_field_complete_en
[0]
RW
1BIN: bit [0] in the LIN_STATregister drives interrupt
request linIrq
Transmit byte field complete interrupt enable
0BIN: bit [1] in the LIN_STATregister is disabled from
driving interrupt request signal linIrq
[1]
[2]
[3]
0BIN
0BIN
0BIN
RW
RW
RW
tx_byte_field_complete_en
brksync_complete_en
1BIN: bit [1] in the LIN_STATregister drives interrupt
request signal linIrq
Break Sync complete interrupt enable
0BIN: bit [2] in the LIN_STATregister is disabled from
driving interrupt request signal linIrq
1BIN: bit [2] in the LIN_STATregister drives interrupt
request signal linIrq
Autobauding Sync complete interrupt enable
0BIN: bit [3] in the LIN_STATregister is disabled from
driving interrupt request signal linIrq.
auto_sync_complete_en
1BIN: bit [3] in the LIN_STATregister drives interrupt
request signal linIrq
© 2016 Integrated Device Technology, Inc.
157
January 29, 2016
ZSSC1956 Datasheet
Name
Bits
Reset
Access
Description
Autobauding complete interrupt enable
0BIN: bit [4] in the LIN_STATregister is disabled from
[4]
RW
autobauding_complete_en
0BIN
driving interrupt request signal linIrq
1BIN: bit [4] in the LIN_STATregister drives interrupt
request signal linIrq
Bus idle interrupt enable
0BIN: bit [5] in the LIN_STATregister is disabled from
driving interrupt request signal linIrq
1BIN: bit [5] in the LIN_STATregister drives interrupt
request signal linIrq
[5]
[6]
0BIN
0BIN
0BIN
0BIN
0BIN
0BIN
0BIN
0BIN
0BIN
RW
RW
RW
RW
RW
RW
RW
RW
RW
bus_idle_en
wake_up_en
Wake up interrupt enable
0BIN: bit [6] in the LIN_STATregister is disabled from
driving interrupt request signal linIrq
1BIN: bit [6] in the LIN_STATregister drives interrupt
request signal linIrq
PID field parity error interrupt enable
0BIN: bit [7] in the LIN_STATregister is disabled from
driving interrupt request signal linIrq
1BIN: bit [7] in the LIN_STATregister drives interrupt
request signal linIrq
Break field interrupt enable
[7]
parity_error_en
brkfld_error_en
brkdel_error_en
brksync_error_en
h_interbyte_error_en
rx_overrun_en
0BIN: bit [8] in the LIN_STATregister is disabled from
driving interrupt request signal linIrq
1BIN: bit [8] in the LIN_STATregister drives interrupt
request signal linIrq
[8]
Break delimiter interrupt enable
0BIN: bit [9] in the LIN_STATregister is disabled from
driving interrupt request signal linIrq
1BIN: bit [9] in the LIN_STATregister drives interrupt
request signal linIrq
Break Sync field interrupt enable
0BIN: bit [10] in the LIN_STATregister is disabled from
driving interrupt request signal linIrq
1BIN: bit [10] in the LIN_STATregister drives interrupt
request signal linIrq
[9]
[10]
[11]
[12]
[13]
Header interbyte space interrupt enable
0BIN: bit [11] in the LIN_STATregister is disabled from
driving interrupt request signal linIrq
1BIN: bit [11] in the LIN_STATregister drives interrupt
request signal linIrq
Receive buffer overrun interrupt enable
0BIN: bit [12] in the LIN_STATregister is disabled from
driving interrupt request signal linIrq
1BIN: bit [12] in the LIN_STATregister drives interrupt
request signal linIrq
Receive framing error interrupt enable
0BIN: bit [13] in the LIN_STATregister is disabled from
driving interrupt request signal linIrq
rx_framing_error_en
1BIN: bit [13] in the LIN_STATregister drives interrupt
request signal linIrq
© 2016 Integrated Device Technology, Inc.
158
January 29, 2016
ZSSC1956 Datasheet
Name
Bits
Reset
Access
Description
Receive data error interrupt enable
0BIN: bit [14] in the LIN_STATregister is disabled from
[14]
0BIN
RW
rx_data_error_en
driving interrupt request signal linIrq
1BIN: bit [14] in the LIN_STATregister drives interrupt
request signal linIrq
Transmit buffer overrun interrupt enable
0BIN: bit [15] in the LIN_STATregister is disabled from
driving interrupt request signal linIrq
[15]
[16]
0BIN
0BIN
0BIN
RW
RW
tx_overrun_en
1BIN: bit [15] in the LIN_STATregister drives interrupt
request signal linIrq
Transmit framing error interrupt enable
0BIN: bit [16] in the LIN_STATregister is disabled from
driving interrupt request signal linIrq
1BIN: bit [16] in the LIN_STATregister drives interrupt
request signal linIrq
Transmit data error interrupt enable
0BIN: bit [17] in the LIN_STATregister is disabled from
driving interrupt request signal linIrq
tx_framing_error_en
[17]
RW
RO
tx_data_error_en
Unused
1BIN: bit [17] in the LIN_STATregister drives interrupt
request signal linIrq
[31:18]
Unused; read as 0.
4.7.2.10. Register “LIN_CLI” – Interrupt clear
Table 4.41 Register LIN_CLI – system address 4000 1824HEX
Name
Bits
Reset
Access Description
Receive byte field complete
BIN: no action
0BIN
rx_byte_field_complete_cl
[0]
W
W
W
W
W
W
0
1BIN: reset bit [0] in the LIN_STATregister
Transmit byte field complete
0BIN: no action
1BIN: reset bit [1] in the LIN_STATregister
[1]
[2]
[3]
[4]
[5]
0BIN
0BIN
0BIN
0BIN
0BIN
tx_byte_field_complete_cl
brksync_complete_cl
Break Sync complete
0
BIN: no action
1BIN: reset bit [2] in the LIN_STATregister
Autobauding Break Sync complete
0BIN: no action
1BIN: reset bit [3] in the LIN_STATregister
auto_break_sync_complete_cl
autobauding_complete_cl
bus_idle_cl
Autobauding complete
0
BIN: no action
1BIN: reset bit [4] in the LIN_STATregister
Bus idle
0BIN: no action
1BIN: reset bit [5] in the LIN_STATregister
© 2016 Integrated Device Technology, Inc.
159
January 29, 2016
ZSSC1956 Datasheet
Name
Bits
Reset
Access Description
Wake up
[6]
0BIN
wake_up_cl
W
W
W
W
W
W
W
W
W
W
W
0BIN: no action
1BIN: reset bit [6] in the LIN_STATregister
PID field parity error
0BIN: no action
1BIN: reset bit [7] in the LIN_STATregister
[7]
[8]
0BIN
0BIN
0BIN
0BIN
0BIN
0BIN
0BIN
0BIN
0BIN
0BIN
0BIN
parity_error_cl
brkfld_error_cl
Break field
0
BIN: no action
1BIN: reset bit [8] in the LIN_STATregister
Break delimiter
0BIN: no action
1BIN: reset bit [9] in the LIN_STATregister
[9]
brkdel_error_cl
Break Sync field
0BIN: no action
1BIN: reset bit [10] in the LIN_STATregister
[10]
[11]
[12]
[13]
[14]
[15]
[16]
brksync_error_cl
h_interbyte_error_cl
rx_overrun_cl
Header interbyte space
0
BIN: no action
1BIN: reset bit [11] in the LIN_STATregister
Receive buffer overrun
0
BIN: no action
1BIN: reset bit [12] in the LIN_STATregister
Receive framing error
0BIN: no action
1BIN: reset bit [13] in the LIN_STATregister
rx_framing_error_cl
rx_data_error_cl
tx_overrun_cl
Receive data error
0
BIN: no action
1BIN: reset bit [14] in the LIN_STATregister
Transmit buffer overrun
0BIN: no action
1BIN: reset bit [15] in the LIN_STATregister
Transmit framing error
0BIN: no action
1BIN: reset bit [16] in the LIN_STATregister
tx_framing_error_cl
Transmit data error
0BIN: no action
1BIN: reset bit [17] in the LIN_STATregister
tx_data_error_cl
Unused
[17]
W
[31:18]
----
Unused
© 2016 Integrated Device Technology, Inc.
160
January 29, 2016
ZSSC1956 Datasheet
4.7.2.11. Register “LIN_STAT” – Status
Table 4.42 Register LIN_STAT – system address 4000 1828HEX
Name
Bits
Reset
Typ
Description
Receive byte field complete interrupt request
0BIN
rx_byte_field_complete
[0]
RO
0
BIN: idle
1BIN: interrupt request
Transmit byte field complete interrupt request
BIN: idle
[1]
[2]
0BIN
0BIN
0BIN
0BIN
0BIN
0BIN
0BIN
0BIN
0BIN
0BIN
0BIN
0BIN
0BIN
tx_byte_field_complete
brksync_complete
auto_sync_complete
autobauding_complete
bus_idle
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
0
1BIN: interrupt request
Break Sync complete interrupt request
0BIN: idle
1BIN: interrupt request
Autobauding Sync complete interrupt request
0
1BIN: interrupt request
Autobauding complete interrupt request
0BIN: idle
1BIN: interrupt request
Bus idle interrupt request
[3]
BIN: idle
[4]
[5]
0
BIN: idle
1BIN: interrupt request
Wake up interrupt request
0BIN: idle
1BIN: interrupt request
PID field parity error interrupt request
[6]
wake_up
[7]
parity_error
0BIN: idle
1BIN: interrupt request
Break field interrupt request
0BIN: idle
1BIN: interrupt request
Break delimiter interrupt request
0BIN: idle
1BIN: interrupt request
Break Sync field interrupt request
0BIN: idle
1BIN: interrupt request
Header interbyte space interrupt request
0
1BIN: interrupt request
Receive buffer overrun interrupt request
0BIN: idle
1BIN: interrupt request
Receive framing error interrupt request
0BIN: idle
[8]
brkfld_error
[9]
brkdel_error
[10]
[11]
[12]
[13]
brksync_field_error
h_interbyte_error
rx_overrun
BIN: idle
rx_framing_error
1BIN: interrupt request
© 2016 Integrated Device Technology, Inc.
161
January 29, 2016
ZSSC1956 Datasheet
Name
Bits
Reset
Typ
Description
Receive data error interrupt request
0BIN: idle
[14]
0BIN
rx_data_error
RO
1BIN: interrupt request
Transmit buffer overrun interrupt request
[15]
[16]
0BIN
0BIN
0BIN
tx_overrun
RO
RO
0BIN: idle
1BIN: interrupt request
Transmit framing error interrupt request
0BIN: idle
1BIN: interrupt request
Transmit data error interrupt request
0BIN: idle
tx_framing_error
tx_data_error
Unused
[17]
RO
RO
1BIN: interrupt request
[31:18]
Unused; read as 0
© 2016 Integrated Device Technology, Inc.
162
January 29, 2016
ZSSC1956 Datasheet
4.8. SPIB8
4.8.1.
Introduction
The SPIB8 module provides a four-wire SPI master module. The three lines SPI_CLK, MOSI and MISO are fully
controlled by hardware while the SSN line must be controlled by software to guarantee the required setup and
hold times. In addition to the AHB-Lite bus interface, this SPI module has an active-high interrupt line and an
additional input to disable the module. This additional input is needed as the rising edge of SSN will execute the
command sent to the SBC. To avoid any problems when the power or system clock is disabled, this input will be
triggered by the PMU and goes to deep sleep (i.e., any power-down mode on the SBC; see section 4.3.3).
Figure 4.7 SPIB8 Block Diagram
AHBlite Bus Interface
SpiCfg
SpiStat
SpiClkCfg
Write SpiData
SpiData
TxBuffer (8 byte)
SPI_CLK
SSN
RxBit
ShiftReg
RxBuffer (8 byte)
SPI CONTROL LOGIC
MOSI
TxBit
MISO
IRQ
Read SpiData
© 2016 Integrated Device Technology, Inc.
163
January 29, 2016
ZSSC1956 Datasheet
4.8.2.
SPI Signal Description
4.8.2.1. SPI Clock (SPI_CLK)
The SPI clock is used to synchronize the data transfer between the master and the selected slave. The SPI clock
is an output of this master and an input to the connected slave (SBC). This module generates the clock if it is
enabled and if data is present to be sent. Otherwise the clock line is kept at the configured polarity level.
4.8.2.2. SPI Slave Select (SSN)
The low-active SPI slave select signal is directly driven by bit [14] of the SPICFG_B8 register (see Table 4.43).
This means that this line is completely under software control. Software must ensure that the required setup and
hold times as well as the required protocol for the SBC are in the defined range.
4.8.2.3. SPI Master Out Slave In (MOSI)
The MOSI pin is used to transfer data from the master to the (selected) slave. Data on this pin is always trans-
ferred with the most significant bit (MSB) first.
4.8.2.4. SPI Master In Slave Out (MISO)
The MISO pin is used to transfer data from the slave to the master. Data on this pin is always expected with the
most significant bit (MSB) first. It can be selected by software if the MISO line is sampled at the middle (default) or
the end of a transmitted bit. The latter case is added to relax the timing when a fast SPI clock is selected.
4.8.3.
Functional Description
The SPIB8 master initiates all transfers on the SPI bus. To start a transfer, the module must be enabled (set the
SpiEnbit [15] in the SPICFG_B8register to 1BIN; see Table 4.43), the slave must be activated (set SSN to 0), and
the required clock behavior must be configured via the CDIV_B8, CPHA_B8 and CPOL_B8 bits in the
SPICLKCFG_B8register; see Table 4.44). The required interrupt sources must also be enabled. Note that the TX
buffer is empty at the beginning.
When the required setup time for the SSN line has expired, place at least the first byte to be transmitted into the
TX buffer. This also clears the TxNotFull flag bit [2] in the SPISTAT_B8 register. In the next system clock
cycle, this byte is transferred into the shift register, the clock line is driven appropriately, and the TxNotFullflag
(when only one byte was written into the TX buffer) and the busy flag (bit [7] in the SPISTAT_B8 register) are
set. The first byte is shifted out of the MOSI line and the SPI clock is generated as configured.
© 2016 Integrated Device Technology, Inc.
164
January 29, 2016
ZSSC1956 Datasheet
Simultaneously the MISO line is sampled and shifted in. Normally, the MISO line is sampled in the middle of a
transmitted bit (blue lines in Figure 4.8). Although the MOSI line changes its value at the same time as the SPI
clock, there is a delay regarding the MISO line as first the clock must be driven out of the chip into the connected
slave and then the data must be driven back from the connected slave. To relax the timing, especially for fast SPI
clocks, the SamplePosbit [13] in the SPICLKCFG_B8register can be configured so that the RX data is sampled
at the end of a transmitted bit (red lines in Figure 4.8). If the complete byte is shifted in and the RX buffer is not
full, the byte is stored into the RX buffer at the byte boundary and the RxNotEmpty flag (bit [1] in the
SPISTAT_B8register) is set, signaling the end of the byte transfer. In the case that the RX buffer is already full
and no byte is read from RX buffer in the same cycle, the byte currently received is rejected (lost) and the RxOf
flag bit [0] in the SPICFG_B8register is set.
Because the SPI module operates in a full-duplex mode, a dummy byte must be placed into TX buffer if only a
byte has to be read from the slave.
Figure 4.8 SPI Bus and Status Flags for a Single Byte Transfer
byte boundary
SCLK (POL == 0; PHA == 0)
SCLK (POL == 1; PHA == 0)
SCLK (POL == 0; PHA == 1)
SCLK (POL == 1; PHA == 1)
MOSI
MSB
LSB
MISO
MSB
LSB
busy
TxNotFull
RxNotEmpty
When the user writes a new byte into TX buffer before the end of the byte transfer, the transfer for the new byte
starts immediately after the actual transfer. This means that the busy flag stays active at the end of the first
transmitted byte.
As it can be possible that the software disables the SPI while a transfer is in progress (not recommended), bytes
could be present inside the TX and/or RX buffer indicated by the values NoTxFreeor NoRxBytes(bits [23:20] or
bits [19:16] respectively in register SPISTAT_B8). These bytes can be removed from the buffers by writing a 1 to
the ClrTxBufbit [31] or ClrRxBufferbit [30] respectively in the SPISTAT_B8register.
© 2016 Integrated Device Technology, Inc.
165
January 29, 2016
ZSSC1956 Datasheet
As noted above, the user can configure the SPI clock frequency via the CDIV bit field. The SPI clock frequency is
calculated using the following equation:
SPI clock frequency = system clock frequency / (2 * (CDIV + 1))
4.8.4.
Interrupts and Status Flags
There are eight status flags in this module; seven of them can be enabled to drive the interrupt line. Four of them
correspond to the status of the TX or RX buffer: RxNotEmpty, TxNotFull, RxLvl, and TxLvl. They are
cleared when data is written to or read from the corresponding buffer. The other three flags that can drive the
interrupt line are signaling error conditions: RxOf, WrColl, and RdErr. These three flags are cleared by read
access to the status register. The last status bit, Busy, is a read-only signal which reflects the status of the
module and is fully controlled by hardware. The other flags are controlled by hardware and by software.
•
RxOf:
This overflow bit is set by hardware when it is unable to store a received byte into RX
buffer (RX buffer is already full). It is cleared by software read access to the status
register. To avoid losing information, the set condition has higher priority than the clear
condition. This bit is not set when a byte in the RX buffer is read in the same system clock
cycle when the received byte will be stored.
•
•
•
RxNotEmpty: This bit is set by hardware when a received byte is stored into the RX buffer and cleared
when all bytes are read by the software. To avoid losing any information, the set condition
has higher priority than the clear condition. This situation occurs when the byte in the RX
buffer is read in the same system clock cycle when the next received byte will be stored.
TxNotFull:
This flag is active on default. It is cleared when software writes 8 bytes to the TX buffer
and is set by hardware when it moves one byte into the shift register. As it might be
possible that both actions happen in the same system clock cycle, the clear condition has
the higher priority.
WrColl:
This write collision flag is set when the software writes more bytes to TX buffer than free
places exist. When one byte is moved into the shift register in the same system clock
cycle, its place is also interpreted as free. The bytes software wants to write are
completely rejected to avoid loss of data. It is cleared by software read access to the
status register.
•
•
RdErr:
RxLvl:
This read error flag is set when software tries to read more bytes than are present in the
RX buffer. It is cleared by software read access to the status register.
This bit is set by hardware when the number of bytes present in the RX buffer (the
NoRxBytesbit field [19:16] in the SPISTAT_B8register) reaches the level defined by the
RxTrigLvlbit field[19:16] in the SPICFG_B8register. It is cleared by hardware when the
number of bytes present in the RX buffer drops below the defined level due to
reconfiguration of the level, RX buffer read accesses, or clearing it via ClrRxBuf bit in
the SPISTAT_B8register.
•
•
TxLvl:
Busy:
This bit is set by hardware when the number of free byte locations in the TX buffer (the
NoTxFree bit field in the SPISTAT_B8 register) reaches the level defined by the
txTrigLvl [23:20] bit field in the SPICFG_B8 register. It is cleared by hardware when
the number of free byte locations in the TX buffer drops below the defined level due to
reconfiguration of the level or TX buffer write accesses.
This bit reflects the status of the SPI module.
© 2016 Integrated Device Technology, Inc.
166
January 29, 2016
ZSSC1956 Datasheet
4.8.5.
Overview of Registers for SPIB8
4.8.5.1. Register “SPICFG_B8” – SPIB8 configuration
Table 4.43 Register SPICFG_B8 – system address 4000_2000HEX; local address is 00HEX
Name
Bits
Reset
Type
Description
When set to 1, the corresponding status bit is allowed to drive the IRQ
output.
[0]
RxOf_en
0BIN
RW
When set to 1, the corresponding status bit is allowed to drive the IRQ
output.
When set to 1, the corresponding status bit is allowed to drive the IRQ
output.
When set to 1, the corresponding status bit is allowed to drive the IRQ
output.
When set to 1, the corresponding status bit is allowed to drive the IRQ
output.
When set to 1, the corresponding status bit is allowed to drive the IRQ
output.
When set to 1, the corresponding status bit is allowed to drive the IRQ
output.
RxNotEmpty_en
TxNotFull_en
WrColl_en
[1]
[2]
[3]
[4]
[5]
0BIN
0BIN
0BIN
0BIN
0BIN
0BIN
RW
RW
RW
RW
RW
RdErr_en
RxLvl_en
TxLvl_en
unused
[6]
RW
RO
[12:7]
Unused; always read as 0.
Selects whether data on MISO is sampled at the sampling edge (set
to 0) or at shift edge (set to 1).
Note: Change this bit only when module is disabled (SpiEn== 0; see
below) or when no transfer is in progress.
SamplePos
[13]
0BIN
RW
SSN
[14]
[15]
1BIN
0BIN
RW
RW
This bit directly controls the SSN line.
Enable for SPI module.
SpiEn
Defines the number of bytes that must be present in the RX FIFO
buffer to activate the RxLvl interrupt
Defines the number of empty locations (bytes) that must be present in
TX FIFO buffer to activate the TxLvl interrupt.
RxTrigLvl
[19:16]
0100BIN
0100BIN
RW
TxTrigLvl
Unused
[23:20]
[31:24]
RW
RO
Unused; always read as 0.
© 2016 Integrated Device Technology, Inc.
167
January 29, 2016
ZSSC1956 Datasheet
4.8.5.2. Register “SPICLKCFG_B8” – SPIB8 clock configuration
Table 4.44 Register SPICLKCFG_B8 – system address 4000_2004HEX; local address is 08HEX
Name
Bits
Reset
Access Description
Clock polarity; the content of this bit directly reflects the idle state of the
clock.
CPOL_B8
[0]
1BIN
RW
Note: change this bit only when module is disabled (spien == 0)
Clock phase; data is centered to the first (set to 0) or to the second (set to 1)
clock edge.
CPHA_B8
[1]
1BIN
RW
Note: change this bit only when module is disabled (spien == 0).
Clock divider value; spi clock period is 2*(CDIV+1) times the system clock.
Note: change this bit only when module is disabled (spien == 0) or when no
transfer is in progress.
CDIV_B8
Unused
[7:2]
00001BIN
RW
RO
[31:8]
Unused; read as 0.
4.8.5.3. Register “SPISTAT_B8” – SPIB8 status
Table 4.45 Register SPISTAT_B8 – system address 4000_2008HEX; local address is 04HEX
Name
Bits
Reset Access Description
Signals that an Rx overflow has occurred.
Note: This bit is cleared when its status is read.
Note: The received byte causing the overflow is rejected; the previous
received bit is kept in the RxBuffer.
[0]
RxOf
0BIN
RC
This bit reflects the status of the RxBuffer. It is set when a new byte is trans-
fered into the empty RxBuffer. It is cleared when SPIDATA is completely read
(see Table 4.46).
This bit reflects the status of the TxBuffer. It is set when at least one byte can
be placed into the TxBuffer. It is cleared when no byte can be placed into the
TxBuffer.
This bit is set when SPIDATA is written while the TxBuffer is already full.
Note: This bit is cleared when its status is read.
Note: The bytes to be written causing this error are rejected.
This bit is set when SPIDATA is read with more bytes than present in the
RxBuffer.
RxNotEmpty
TxNotFull
WrColl
[1]
[2]
[3]
[4]
0BIN
1BIN
0BIN
0BIN
RO
RO
RC
RC
RdErr
Note: This bit is cleared when its status is read.
This bit is fully controlled by hardware. It is set when NoRxBytes(see bits
[19:16] below) has reached the level configured by the RxTrigLvlbit field
[19:16] in the SPICFG_B8 register. It is cleared when the RxBuffer is cleared
or when enough bytes are read from the RxBuffer so that NoRxBytesdrops
below RxTrigLvl.
This bit is fully controlled by hardware. It is set when NoTxFree(see bits
[23:20] below) has reached the level configured by the TxTrigLvlbit field
[23:20] in the SPICFG_B8 register. It is cleared when the TxBuffer is cleared
or when enough bytes are written to the TxBuffer so that NoTxFreedrops
below TxTrigLvl.
RxLvl
TxLvl
[5]
[6]
0BIN
RO
RO
1BIN
Busy
[7]
0BIN
RO
RO
RO
This bit reflects the status of the SPI module.
Unused; read as 0.
Unused
[15:8]
NoRxBytes
[19:16] 0000BIN
Number of bytes present in the RxBuffer.
© 2016 Integrated Device Technology, Inc.
168
January 29, 2016
ZSSC1956 Datasheet
Name
NoTxFree
Unused
Bits
Reset Access Description
[23:20] 1000BIN
[29:24]
RO
RO
Number of free locations (bytes) present in the TxBuffer.
Unused; read as 0.
Writing a 1 to this bit clears the RxBuffer (strobe register).
Note: Write only when spi is disabled; always read as 0.
Writing a 1 to this bit clears the TxBuffer (strobe register)
Note: Write only when spi is disabled; always read as 0.
ClrRxBuf
ClrTxBuf
[30]
[31]
0BIN
0BIN
WO
WO
4.8.5.4. Registers “SPIDATA*_B8” – SPIB8 data
Table 4.46 Accessing the FIFO Buffers – system address 4000_XXXXHEX
Name
Address
XXXX Write Access
All 4 bytes from data bus
Read Access
4 bytes are taken from the RxBuffer and placed
onto the data bus with the first byte out as the LSB.
Note: Only word access is possible.
are placed into the
TxBuffer with lowest byte
first
SPIDATA4B_B8
0CHEX
200C
2010
Unsigned read: 1 byte is taken from the RxBuffer
and placed onto the data bus (LSB). The upper 3
bytes on the data bus are set to 0.
Note: Word, halfword, and byte accesses are
possible.
Signed read: 1 byte is taken from the RxBuffer.
This byte is sign extended to form the word sent on
the data bus.
Note: Word, halfword, and byte accesses are
possible.
Unsigned read: 2 bytes are taken from the
RxBuffer and combined into a 16-bit value with the
first byte out as LSB. The upper 2 bytes on data
bus are set to 0.
SPIDATA1BU_B8
SPIDATA1BS_B8
10HEX
Lowest byte from data
bus is placed into the
TxBuffer
14HEX
2014
2018
SPIDATA2BU_B8
SPIDATA2BS_B8
18HEX
Note: Only word and halfword accesses are
possible.
Lowest 2 bytes from data
bus are placed into the
TxBuffer with lowest byte Signed read: 2 bytes are taken from the RxBuffer
first
and combined into a 16-bit value with first byte out
as LSB. This value is sign extended to form the
word sent on the data bus.
1CHEX
201C
Note: Only word and halfword accesses are
possible.
Unsigned read: 3 bytes are taken from the
RxBuffer and combined into a 24-bit value with the
first byte out as the LSB. The highest byte on the
data bus is set to 0.
SPIDATA3BU_B8
SPIDATA3BS_B8
20HEX
2020
2024
Lowest 3 bytes from data
bus are placed into the
Note: Only word accesses are possible.
TxBuffer with lowest byte Signed read: 3 bytes are taken from the RxBuffer
first
and combined into a 24-bit value with first byte out
as the LSB. This value is sign extended to form the
word sent on the data bus.
24HEX
Note: Only word accesses are possible.
© 2016 Integrated Device Technology, Inc.
169
January 29, 2016
ZSSC1956 Datasheet
4.9. SPI in ZSYSTEM2
The two SPIs contained in the ZSSC1956 are identical four-wire master interfaces: the SPIB8 is used for
communication with the SBC and the other SPI block contained in ZSYSTEM2 can be mapped onto the GPIO
pads for external communication. The SPI for external communication is described here. The three lines SCLK,
MOSI, and MISO are fully controlled by hardware while the CSN line must be controlled by software.
By default, SCLK is high (CPOL == 1; see Table 4.49). However, it can be changed as needed for the SPI
mapped onto the GPIO pads. The SPI clock frequency is configurable by software with a maximum frequency of
half of the system clock frequency.
By default, the MISO line is sampled on the second edge of SCLK. However, it can be changed as needed for the
SPI mapped onto the GPIO pads as all four possible SPI modes are implemented.
Important: Before the SPI in ZSYSTEM2 can be used, the clock of ZSYSTEM2 must be enabled via register
SYS_CLKCFG (see Table 4.5). After enabling the clock for the ZSYSTEM2, the SPI lines must be mapped onto
appropriate GPIO pads (see section 4.3.4).
4.9.1.
Data Transfers
The SPI master initiates all transfers on the SPI bus. To start a transfer, the module must be enabled (set bit
SpiEnin the SPI configuration register to 1; see Table 4.47), the required clock behavior must be configured (set
CDIV, CPHA and CPOL as needed; see Table 4.49), and the slave must be activated (set CSN to 0 in the SPI
configuration register). Additionally, the required interrupt sources must be enabled.
Note: The TX buffer is empty at the beginning.
When the required setup time for the CSN line has expired (50ns), the first byte to be transmitted must be placed
into the TX buffer. This write access to the TX buffer also clears the TxEmpty_SPIflag. In the next system clock
cycle, this byte is transferred into the shift register, the clock line is driven appropriately, and the TxEmpty_SPI
and Busyflag are set to 1, which allows the user to place a second byte into the TX buffer. The first byte is shifted
out of the MOSI line, and the SPI clock is generated as configured.
Simultaneously, the MISO line is sampled and shifted in. Normally, the MISO line is sampled in the middle of a
transmitted bit (blue lines in Figure 4.9). While the MOSI line changes its value at the same time as the SPI clock,
there is a delay regarding the MISO line as first the clock must be driven out of the chip into the connected slave
and then the data must be driven back from the connected slave. To relax the timing, especially for fast SPI
clocks, the SamplePos bit in the SPI configuration register (see Table 4.47) can be set so that the RX data is
sampled at the end of a transmitted bit (red lines in Figure 4.9).
When the complete byte is shifted in and the RX buffer is empty, the byte is stored into the RX buffer at the byte
boundary and the RxFull_SPIflag is set to 1 in the SPI status register (see Table 4.50), signaling the end of the
byte transfer. If the RX buffer is already full and the byte in the RX buffer is not read in the same cycle, the byte
currently received is rejected (lost) and the RxOverflow_SPIflag is set to 1 in the SPI status register.
Note: As the SPI module operates in a full-duplex mode, a dummy byte must be placed into the TX buffer if a
byte must be read from the slave without any write to the slave.
When a new byte is written into the TX buffer before the end of an active byte transfer, the transfer of the new
byte starts immediately after the actual transfer. This means that the busy flag stays active at the end of the first
transmitted byte.
© 2016 Integrated Device Technology, Inc.
170
January 29, 2016
ZSSC1956 Datasheet
As it can be possible that the software disables the SPI while a transfer is in progress (not recommended), a byte
could be present in the TX buffer indicated by a low value of the TxEmpty_SPI flag in the SPI status register.
This byte can be removed from the TX buffer by writing a 1 to the ClrTxBuf bit of the SPI status register (see
Table 4.50); otherwise it would be transmitted when SPI is enabled again.
As mentioned above, the user can configure the SPI clock frequency by the CDIVfield. The SPI clock frequency
is given by the following equation:
SPI clock frequency = system clock frequency / (2 (CDIV + 1))
*
Figure 4.9 SPI Bus and Status Flags for a Single Byte Transfer
byte boundary
SCLK (POL == 0; PHA == 0)
SCLK (POL == 1; PHA == 0)
SCLK (POL == 0; PHA == 1)
SCLK (POL == 1; PHA == 1)
MOSI
MSB
LSB
MISO
MSB
LSB
busy
txEmpty
rxFull
4.9.2.
Interrupts and Status Flags
There are five status flags for this SPI module (see Table 4.50); four of them can be enabled to drive the interrupt
line. Two of the flags correspond to the status of the TX or RX buffer. They are cleared when data is written to or
read from the corresponding buffer. The other two flags can drive the interrupt line are signaling error conditions.
These two flags are cleared by read access to the status register. The fifth status bit is a read only signal which
reflects the status of the module and is fully controlled by hardware. The other flags are controlled by hardware
and by software:
© 2016 Integrated Device Technology, Inc.
171
January 29, 2016
ZSSC1956 Datasheet
• RxOverflow_SPI: This bit is set to 1 by hardware when it is not able to store a received byte into the RX
buffer (RX buffer is already full). It is cleared by software read access to the status
register. To prevent losing any information, the set condition has higher priority than the
clear condition. This bit is not set when the byte in the RX buffer is read in the same
system clock cycle when the next received byte will be stored.
• RxFull_SPI:
This bit is set to 1 by hardware when a received byte is stored in the RX buffer and
cleared when the byte is read by the software. To prevent losing any information, the set
condition has higher priority than the clear condition. This situation occurs when the byte
in the RX buffer is read in the same system clock cycle when the next received byte will
be stored.
• TxEmpty_SPI:
This flag is active on default (1). It is cleared when software writes a byte to the TX buffer
and is set to 1 by hardware when it moves this byte into the shift register. As it might be
possible that both actions happen in the same system clock cycle, the clear condition has
the higher priority.
• WrCollision_SPI: This flag is set when the software writes a byte into the TX buffer while the TX buffer is
not empty and its content is not moved into the shift register in the same system clock
cycle. The byte that the software attempted to write is rejected to avoid loss of data. It is
cleared by software read access to the status register.
4.9.3.
Example of SPI Transfer Handling
The following gives a short example of a transfer of six bytes on the SPI bus (SPI2 module):
•
•
Write the SPICLKCFG register (see Table 4.49) with the required CPOL, CPHAand CDIVvalue.
Write the SPICFG register with SpiEnset to 1 and CSNset to 0 and enable the RxFull_SPI_irqand
RxOverflow_SPI_irqinterrupts (see Table 4.47). Enabling interrupts can also happen before enabling
SPI.
•
•
Write the first TX byte to the TX buffer when the CSN setup time has expired.
Write the second TX byte to the TX buffer.
•
•
•
Wait for the RxFull_SPIinterrupt.
Read the first RX byte from the RX buffer.
Write the third TX byte to the TX buffer.
•
•
•
Wait for RxFull_SPIinterrupt.
Read the second RX byte from the RX buffer.
Write the fourth TX byte to the TX buffer.
•
•
•
Wait for the RxFull_SPIinterrupt.
Read the third RX byte from the RX buffer.
Write the fifth TX byte to the TX buffer.
•
•
•
Wait for the RxFull_SPIinterrupt.
Read the fourth RX byte from the RX buffer.
Write the sixth TX byte to the TX buffer.
© 2016 Integrated Device Technology, Inc.
172
January 29, 2016
ZSSC1956 Datasheet
•
•
Wait for the RxFull_SPIinterrupt.
Read the fifth RX byte from the RX buffer.
•
•
•
Wait for the RxFull_SPIinterrupt.
Read the sixth RX byte from the RX buffer.
Write the SPICFG register with CSNset to 1 (and SpiEn set to 0) when the CSN hold time has expired.
When the software is not able to read the RX byte before the next byte is received (RX overflow), the timing can
be relaxed by waiting for the first RxFull_SPIinterrupt before writing the second TX byte. Instead the second TX
byte can be written after this interrupt. This guarantees that no RX overflow can occur but introduces some delay
between two consecutive bytes as the module waits for the next byte transfer until data is present.
Note: A special case for releasing CSN is when a power-down command has been sent to SBC. As the SBC will
at least disable the clock for the MCU when CSN is released, disabling CSN by software can lead to unwanted
behavior. Therefore a hardware mechanism is implemented that disables SPI and releases CSN when a WFI
command with the SLEEPDEEP bit set to 1 is executed (see section 4.3.3).
© 2016 Integrated Device Technology, Inc.
173
January 29, 2016
ZSSC1956 Datasheet
4.9.4.
Register Overview of SPI2
The register description below is for the SPI2. The SPIB8 register description can be found in the SPIB8 section.
4.9.4.1. Register “Z2_SPICFG” – SPI Configuration
Table 4.47 Register Z2_SPICFG– system address 4000 1C00HEX
Name
Bits
Default
Access Description
When set to 1, the corresponding status bit is allowed to drive the
IRQ output.
When set to 1, the corresponding status bit is allowed to drive the
IRQ output.
When set to 1, the corresponding status bit is allowed to drive the
IRQ output.
RxOverflow_SPI_irq
[0]
0BIN
RW
RW
RW
RxFull_SPI_irq
[1]
[2]
0BIN
0BIN
TxEmpty_SPI_irq
When set to 1, the corresponding status bit is allowed to drive the
IRQ output.
Unused; always write as 0.
WrCollision_SPI_irq
Unused
[3]
[4]
0BIN
0BIN
RW
RO
This bit selects whether data on MISO is sampled at the sampling
edge (set to 0) or at the shift edge (set to 1).
Note: Change this bit only when the module is disabled
(SpiEn== 0) or when no transfer is in progress.
This bit directly controls the CSN line.
Enable for the SPI module.
SamplePos
[5]
0BIN
RW
CSN
SpiEn
[6]
[7]
1BIN
0BIN
RW
RW
Unused; read as 0
Unused
[31:8]
RO
4.9.4.2. Register “Z2_SPIDATA” – SPI Data Buffers
Table 4.48 Register Z2_SPIDATA– system address 4000 1C04HEX
Name
SpiData
Unused
Bits
Default
Access
Description
When writing a byte to this register, the value is stored in the TX
buffer. A write access to this register also clears the TxEmpty_SPI
flag in the status register.
When reading this register, the contents of the RX buffer is
returned. A read access to this register also clears the
RxFull_SPIflag in the status register.
[7:0]
00HEX
RW
Note: When writing to this register when the TX buffer is full, the
TX buffer keeps its content and the written byte is rejected. This is
signaled by the WrCollision_SPIflag in the status register.
Unused; read as 0
[31:8]
RO
© 2016 Integrated Device Technology, Inc.
174
January 29, 2016
ZSSC1956 Datasheet
4.9.4.3. Register “Z2_SPICLKCFG” – SPI Clock Configuration
Table 4.49 Register Z2_SPICLKCFG– system address 4000 1C08HEX
Name
Bits
Default
Access
Description
Clock polarity; the content of this bit directly reflects the idle state
of the SPI clock.
Note: Change this bit only when the module is disabled
(SpiEn== 0).
CPOL
[0]
1BIN
RW
Clock phase; data is centered to the first (set to 0) or to the
second (set to 1) clock edge.
Note: Change this bit only when the module is disabled
(SpiEn== 0).
CPHA
[1]
1BIN
RW
Clock divider value; SPI clock period is 2*(CDIV+1) times the
system clock.
Note: Change this bit only when the module is disabled
(SpiEn== 0) or when no transfer is in progress.
Unused; read as 0
CDIV
[7:2]
000001BIN
RW
RO
Unused
[31:8]
4.9.4.4. Register “ Z2_SPISTAT” – SPI Status
Table 4.50 Register Z2_SPISTAT– system address 4000 1C0CHEX
Name
Bits
Default
Access
Description
This bit signals that an Rx overflow occurred.
Note: This bit is cleared when status is read.
RxOverflow_SPI
[0]
0BIN
RC
Note: the received byte causing the overflow is rejected; the
previous received bit is kept in the RX buffer.
This bit reflects the status of the RX buffer. It is set when a new
byte is transferred into the RX buffer.
RxFull_SPI
TxEmpty_SPI
WrCollision_SPI
[1]
[2]
[3]
0BIN
1BIN
0BIN
RO
RO
RC
Note: This bit is cleared when SpiDatais read.
This bit reflects the status of the TX buffer. It is set when a byte is
transferred from the TX buffer into the shift register.
Note: This bit is cleared when SpiDatais written.
This bit is set when SpiDatais written while TX buffer is already
full.
Note: This bit is cleared when the status is read.
This bit reflects the status of the SPI module.
Unused; always write as 0.
Busy
Unused
[4]
[6:5]
0BIN
00BIN
RO
RO
Writing a 1 to this bit clears the TX buffer.
Note: Write only when SPI is disabled; always read as 0.
Unused; read as 0
ClrTxBuf
Unused
[7]
0BIN
WO
RO
[31:8]
© 2016 Integrated Device Technology, Inc.
175
January 29, 2016
ZSSC1956 Datasheet
4.10. I²C™ in ZSYSTEM2
The master-slave I²C™ module provides an interface to the I²C™ bus, which is compliant to the Philips I²C™ bus
specification. It supports all transfer modes (RX and TX; master and slave) and can be connected to busses
operating as a slave, single-master, or as one of many masters. It supports true multi-master operation including
collision detection and bus arbitration. The 10-bit addressing mode and the high-speed mode are not supported.
The maximum possible frequency on the bus is one sixteenth of the internal clock.
Each transfer on the I²C™ bus is controlled by interrupts when software interaction is needed. All registers of this
I²C™ module must only be accessed when the device is disabled or when an interrupt is active.
Important: Before the I²C™ in ZSYSTEM2 can be used, the clock of ZSYSTEM2 must be enabled via register
SYS_CLKCFG (see Table 4.5). After the clock for the ZSYSTEM2 is enabled, the I²C™ lines must be mapped
onto appropriate GPIO pads (see section 4.3.4).
The I²C™ module in ZSYSTEM2 has an active-high interrupt line connected to ARM® interrupt 8.
4.10.1. External Signal Lines
The I²C™ bus consists of two external signal lines, SCL and SDA, for communication between all devices con-
nected to the bus. As SCL is always driven by the master and SDA by various devices, both output drivers
operate as open-drain drivers independent of the corresponding bit in the ppNod bit field in the register
SYS_MEMPORTCFG.
The I²C™ clock is used to synchronize the data transfer between the devices. During each transfer, the clock is
generated by the master on the SCL line, but its low phase can be extended by each connected slave. In slave
mode, the device extends the low phase of the ninth bit (ACK) to enable the software to setup the next byte
transfer. The incoming clock is synchronized and filtered for resistance against short spikes on the clock line.
The I²C™ data line is always driven by the transmitter. For the first byte of a transfer, the transmitter is always the
master transferring the address and the direction of the next bytes. When a transmitter sends a 1 but detects a 0
on the bus, it immediately releases the bus. The incoming data line is synchronized and filtered for resistance
against short spikes on the data line.
4.10.2. The I²C™ Bus
Each transfer on the I2C™ bus is a read or write access by a master to a slave. All transfers are initiated by a
master generating a START condition on a bus followed by the address byte, which must be acknowledged by
the addressed slave. Depending on the access type (read; write), data bytes are sent over the bus by the
transmitter. Each byte sent on the bus must be 8 bits long followed by an acknowledge bit returned by the
receiver. The transfer is terminated by the master generating a STOP condition on the bus or by starting a new
transfer by generating a RESTART condition. All bytes are transferred MSB first.
Sequence when the master requests data from the slave:
•
•
•
Master generates a START condition when the bus is free.
Master sends the address byte; the slave sends the acknowledge bit in response.
Slave sends the data bytes; the master sends the acknowledge bit in response to each byte (last byte is
NACKed to signal to the slave to release the bus).
•
Master generates the STOP condition to release the bus or the RESTART condition to start a new
transfer.
© 2016 Integrated Device Technology, Inc.
176
January 29, 2016
ZSSC1956 Datasheet
Figure 4.10 Read Transfer Example
Start
Stop
...
...
...
SCL
A[6]
A[5]
A[0]
Rd
ACK D[7]
D[6]
D[0] NACK
MST
SDA
Master drives SDA line (MST)
Slave drives SDA line (SLV)
Sequence when the master sends data to the slave:
•
•
•
Master generates a START condition when the bus is free.
Master sends the address byte; the slave sends the acknowledge bit in response.
Master sends the data bytes; the slave sends the acknowledge bit in response to each byte
(master continues until NACK is received or no more data is to be sent).
Master generates the STOP condition to release the bus or the RESTART condition to start a new
transfer.
•
Figure 4.11 Write Transfer Example
Start
Stop
...
...
...
SCL
A[6]
A[5]
MST
A[0]
Wr
ACK D[7]
SLV
D[6]
MST
D[0]
ACK
SLV
SDA
MST
4.10.3. Bus Conflicts
Bus conflicts can occur when two devices drive the data line SDA at the same time. This can happen when two
master devices have generated a START condition at the same time, when two slave devices have the same
slave address, or when two slave devices are accessed for writing by the global call address. As the outputs are
open-drain drivers, a conflict can be detected by the device driving a 1 as this 1 is overridden by the device
driving a 0 on the bus. All these conflicts are handled in hardware.
Exceptions: The following possible conflicts (masters only) cannot be handled in hardware:
•
•
•
Data bit
Data bit
RESTART STOP
STOP
RESTART
The occurrence of these conflicts must be avoided by software protocols.
Note: The first two conflicts can be avoided if all masters access the same slave with the same amount of bytes.
However, different numbers of bytes can be used for different slaves.
Note: The third conflict can be avoided if all masters behave in the same manner, either generating a STOP or a
RESTART.
© 2016 Integrated Device Technology, Inc.
177
January 29, 2016
ZSSC1956 Datasheet
Note: Another solution for avoiding these conflicts can be that each master performs a write access without any
data to all the other masters to ensure that it is the only master on the bus.
When the ZSSC1956 IBS is accessed as slave, it automatically handles the following conflicts:
•
•
•
Conflict during transmission of the acknowledge bit following the address byte: this can only occur when
another device has the same slave address or the global call address is used and when this device is not
ready to be accessed and therefore is sending a NACK. It just releases the bus and ignores all actions on
the bus until it detects a RESTART, START, or STOP condition.
Conflict during transmission of the acknowledge bit following a data byte: this can only occur for a write
transfer when another device has the same slave address or the global call address is used and when
this device is not ready to receive more data and therefore is sending a NACK. It just releases the bus
and ignores all actions on the bus until it detects a RESTART, START, or STOP condition.
Conflict during transmission of a data byte: this can only occur for a read transfer when another device
has the same slave address and both have sent an ACK in response to the address byte. This conflict
occurs when this device is transmitting a 1 (recessive value) while the other slave is transmitting a 0
(dominant value). This device immediately releases the bus and generates an interrupt with status
S_I2cStConflict (see page 193).
4.10.4. Operating as Slave-Only
When the ZSSC1956 IBS is operating as a pure slave on the I2C™ bus without using the master functionality, the
registers Z2_I2CCLKRATE and Z2_I2CCLKRATE2 are not needed as the clock on the I2C™ bus is always
generated by the master device. The stopand startbits of register Z2_I2CCTRL(see Table 4.54) must always
be set to 0 as the START and STOP conditions are always generated by the master while the multi bit must be
set to 1 to avoid conflicts when enabling the module (see section 4.10.8).
For the ZSSC1956 IBS to be accessible via its own slave address, a non-zero slave address must be prog-
rammed into the addrbit field in the Z2_I2CADDRregister (see Table 4.53) and the ackand enI2C bits in the
Z2_I2CCTRLregister must be set to 1.
For the ZSSC1956 IBS to be accessible via the global call address (only write access allowed; read access is
rejected), the gcbit in the Z2_I2CADDRregister and the ackand enI2C bits must be set to 1. When the slave
module detects a START (or RESTART) condition on the bus, it enables its address checker.
4.10.4.1. Slave Receiver
After the slave detects its own slave address and a write command (see Figure 4.11) and after the slave returns
an ACK, an interrupt with the status S_I2cStRxWrAddr is generated (see page 188) and the module becomes the
slave receiver. It then expands the low phase of the SCL of the acknowledge bit until its interrupt is cleared. As
there is no required content in the data register, software only needs to set the ack bit in the Z2_I2CCTRL
register to the desired value and clear the interrupt (irq bit in the Z2_I2CCTRL register). The programmed
acknowledge bit will be used as the response to the following data byte to be written.
When the ack bit is set to 1, an ACK will be returned, indicating that the module is able to receive further data
bytes. The master can then send a data byte, which will be acknowledged, and the slave generates a new
interrupt after responding with ACK with the status S_I2cStRxWrData (see page 189). Additionally, the low phase
of the acknowledge bit on SCL is expanded until the interrupt is cleared. When the interrupt is active, software
must read the received data byte first before setting the ack bit to the desired value and clearing the interrupt
(irq bit).
© 2016 Integrated Device Technology, Inc.
178
January 29, 2016
ZSSC1956 Datasheet
When the ackbit is to set to 0, a NACK will be returned in response to the following data byte, indicating that the
module is not able to receive further data and is leaving the bus. After the NACK has been sent, an interrupt with
status S_I2cStRxWrDataN is generated (see page 190). Software must read the received data byte first and then
must set the ackbit to the desired value and clear the interrupt (irq bit). As the slave leaves the bus, it does not
expand the low phase of SCL, but if a new START condition is detected while the interrupt is still active, the low
phase of SCL following this START will be expanded so that the slave can setup the ackbit for the next incoming
address.
When the master generates a STOP or RESTART condition instead of sending a data byte, an interrupt with
status S_I2cStRxSlvEnd is generated immediately (see page 191). If a RESTART or a START follows the STOP,
the low phase of SCL following the RESTART/START will be expanded until the interrupt is cleared to be able to
setup the ackbit correctly as it might be possible that software has programmed a NACK for the next data byte
but wants to return an ACK when it detects its address.
When detecting the global call address and a write command and returning an ACK, the behavior is the same as
for being accessed via the slave’s own address. Only the status values are different: S_I2cStRxGcAddr instead of
S_I2cStRxWrAddr, S_I2cStRxGcData instead of S_I2cStRxWrData, and S_I2cStRxGcDataN instead of
S_I2cStRxWrDataN.
A conflict on the I2C™ bus can only be detected during a returned acknowledge bit when the slave is sending a
NACK. As the slave leaves the bus after transmitting the NACK, no specific actions are required and the conflict is
ignored.
Important: Always clear the interrupt flag to avoid this device blocking the bus.
4.10.4.2. Slave Transmitter
After the slave detects its own slave address and a read command (see Figure 4.10) and after the slave returns
an ACK, an interrupt with the status S_I2cStRxRdAddr is generated (see page 191) and the module becomes the
slave transmitter. It then expands the low phase of the acknowledge bit on SCL until its interrupt is cleared.
Additionally the bus is turned over to the slave for transmitting data. Software must program the data byte to be
transmitted into the register Z2_I2CDATA first (see Table 4.56) and then must set the ackbit in the Z2_I2CCTRL
register to the desired value and clear the interrupt (irq bit). The programmed acknowledge bit will be used to
signal to the hardware whether the programmed data byte is the last one (ackbit == 0) or if further data could be
sent (ackbit == 1).
When the received acknowledge bit is an NACK, the master signals that it does not want to read more data and
that it wishes to return the bus to the master. An interrupt with status S_I2cStSlvTxDataN is generated (see
page 192) and the slave leaves the bus. If a new RESTART/START occurs while the interrupt is still active, the
low phase of SCL following the RESTART/START will be expanded until the interrupt is cleared.
When the received acknowledge bit is an ACK but the ackbit is 0, indicating that the sent byte was the last byte,
an interrupt with status S_I2cStSlvTxDataL is generated (see page 193) and the slave leaves the bus. The next
bytes read by the master will be FFHEX as the slave stops driving the data line. If a new RESTART/START occurs
while the interrupt is still active, the low phase of SCL following the RESTART/START will be expanded until the
interrupt is cleared.
© 2016 Integrated Device Technology, Inc.
179
January 29, 2016
ZSSC1956 Datasheet
When the received acknowledge bit is an ACK and the ackbit is 1, an interrupt with status S_I2cStSlvTxData is
generated (see page 192). The next data byte to be transmitted must be programmed to register Z2_I2CDATA
first and then the ackbit must be set to the desired value and the interrupt must be cleared. To avoid the master
continuing to generate the clock, this slave extends the low phase of SCL following the ACK until the interrupt is
cleared.
A conflict on the bus can only be detected during transmission of a data byte when sending a logic 1 but detecting
a logic 0 on the bus, which means that two slaves have the same slave address. In this case, the slave immedi-
ately leaves the bus and generates an interrupt with status S_I2cStConflict at the negative clock edge of the
acknowledge bit.
4.10.5. Operating as Single Master
When the ZSSC1956 I2C™ module is operating as the only master on the I2C™ bus, all transfers on the bus are
started and stopped by this module. Additionally, this module generates the clock for all transfers on the I2C™ bus
on the SCL line. The clock can be configured via registers Z2_I2CCLKRATEand Z2_I2CCLKRATE2(see Table
4.51 and Table 4.52). However, each connected slave is allowed to extend the low phase of the clock, which
results in a reduced data rate.
As all transfers are started by this module, no slave address needs to be programmed to the addrbit field in the
Z2_I2CADDR register and the global call address does not need to be enabled via the gc bit. This module only
needs to be enabled by setting the enI2C bit in the Z2_I2CCTRLregister to 1 and setting its multi bit to 0 for a
faster bus access time (see section 4.10.8).
To start a transfer as a master, the start bit in the Z2_I2CCTRL register must be set to 1. When the START
condition has been generated on the bus and SCL is low, an interrupt is generated with status S_I2cStTxStart
(see page 185). When the interrupt is active, the data register must be written with the address of the slave to be
accessed and the command bit. Next the stop, start, and irq bits in the Z2_I2CCTRL register must be
cleared to continue the transfer. (The startand stopbits must be set to 0 as generating a RESTART or STOP
condition on the bus directly after the START is not allowed.) After transmitting the address and the command
and after the reception of the acknowledge bit, the next interrupt is generated. The status depends on the
transmitted command (read or write) and the received acknowledge bit (ACK or NACK).
4.10.5.1. Master Transmitter
When a write command was sent and a NACK was received, the interrupt status is S_I2cStTxWrAddrN (see
page 186). This means that the slave is not ready to receive data. Software then must generate a STOP on the
bus by setting the stop bit in the Z2_I2CCTRL register to 1 and clearing the interrupt or must generate a
RESTART on the bus by setting the start bit to 1 and clearing the interrupt. When both the stop and start
bits are set to 1, first a STOP condition will be generated on the I2C™ bus followed by a START condition. No
interrupt will occur for generating a STOP condition. For both RESTART and START, an interrupt with status
S_I2cStTxStart occurs.
© 2016 Integrated Device Technology, Inc.
180
January 29, 2016
ZSSC1956 Datasheet
When a write command has been sent and an ACK has been received, the interrupt status is S_I2cStTxWrAddr
(see page 185). This means that the slave is ready to receive data. Software now can send data, or it can
generate a STOP or RESTART condition. The behavior for sending a STOP or RESTART is as described above
when receiving a NACK. To send data, the byte to be transmitted must be programmed into the data register.
Next the stop, start, and irq bits in the Z2_I2CCTRL register must be cleared. Depending on the
acknowledge bit received as a response to the data byte, an interrupt with status S_I2cStMstTxData (ACK; see
page 186) or S_I2cStMstTxDataN (NACK; see page 186) is generated. For a received ACK, the same actions as
for the received ACK in response to the address byte can be performed. For a received NACK, the same actions
as for the received NACK in response to the address byte can be performed.
4.10.5.2. Master Receiver
When a read command has been sent and a NACK was received, the interrupt status is S_I2cStTxRdAddrN (see
page 187). This means that the slave is not ready to deliver data and the master remains the owner of the bus.
Software then must generate a STOP on the bus by setting the stop bit in the Z2_I2CCTRL register to 1 and
clearing the interrupt or must generate a RESTART on the bus by setting the start bit to 1 and clearing the
interrupt. When both the stopand startbits are set to 1, first a STOP condition will be generated followed by a
START condition. No interrupt will occur for generating a STOP condition. For both RESTART and START, an
interrupt with status S_I2cStTxStart occurs.
When a read command has been sent and an ACK has been received, the interrupt status is S_I2cStTxRdAddr
(see page 187). This means that the slave is ready to deliver data, and the I2C™ bus is turned over to the slave.
Software must keep the startand stopbits low as this module is not the owner of the data line. The ackbit in
the Z2_I2CCTRL register must be set to the appropriate value that will be sent in response to the subsequent
received data byte. A value of 0 (NACK will be sent) signals to the slave that the data byte is the last one to be
read and the slave must leave the bus so that the master can generate a STOP or a RESTART. A value of 1
(ACK will be sent) signals to the slave that additional bytes will be read afterward. The irq bit must also be
cleared to continue the transfer.
When a data byte has been received and an ACK has been returned, an interrupt with status S_I2cStMstRxData
occurs (see page 187) and the slave retains the ownership of the data line. Software must first read the received
byte and then must set the acknowledge bit to the desired value and to clear the interrupt bit.
When a data byte has been received and an NACK has been returned, an interrupt with status
S_I2cStMstRxDataN occurs (see page 188). The bus is returned to the master. Software must read the received
data byte and then must generate a STOP or RESTART by setting the appropriate bits and must clear the
interrupt.
4.10.6. Operating as Master on a Multi-Master Bus
When the ZSSC1956 I2C™ module is operating as one of many masters on the I2C™ bus, the transfers on the
I2C™ bus can be started by this or by another module. When this module is the master, it generates the clock for
its master transfers on the SCL line using registers Z2_I2CCLKRATEand Z2_I2CCLKRATE2while it will use the
clock provided by another master if accessed as slave. When two masters drive the clock line at the same time
before any contention has occurred, the high phase is determined by the fastest master on the bus while the low
phase is determined by the slower one. However, each connected slave is allowed to extend the low phase of the
clock, which results in a reduced data rate.
© 2016 Integrated Device Technology, Inc.
181
January 29, 2016
ZSSC1956 Datasheet
To be accessible via its own slave address, a non-zero slave address must be programmed into the addrbit field
in the Z2_I2CADDRregister and the ackbit and enI2C bits in the Z2_I2CCTRLregister must be set to 1. To be
able to be accessed via the global call address (only write access allowed, read access is rejected), the gcbit in
the Z2_I2CADDR register and the ack and enI2C bits must be set to 1. When the slave module detects a
START (or RESTART) condition on the bus, it enables its address checker. When this module is enabled by
writing 1 to the enI2C bit, then the multi bit must also be set to 1 as there might already be an active transfer
by another master. This is needed to avoid this module disturbing the traffic on the bus (see section 4.10.8).
The handling for transfers is almost the same as described in the previous sections. Only some additional status
interrupts can occur due to conflict situations. On a multi-master bus, it is possible that at least two masters
assume the bus is free and generate a START condition at the same moment.
If the master detects a conflict during the address and command byte, it immediately switches into slave mode to
check whether it will be accessed or not. In this situation, if it detects its own slave address and a read command
and then it returns an ACK (ackbit == 1), an interrupt with status S_I2cStRxRdAddrL (see page 192) instead of
status S_I2cStRxRdAddr is generated and the device becomes a slave transmitter. In this situation, if it detects its
own slave address and a write command and then it returns an ACK (ack bit == 1), an interrupt with status
S_I2cStRxWrAddrL (see page 188) instead of status S_I2cStRxWrAddr is generated and the device becomes a
slave receiver. In this situation, if it detects the global call address and a write command and then it returns an
ACK (ack bit == 1), an interrupt with status S_I2cStRxGcAddrL (see page 189) instead of status
S_I2cStRxGcAddr (see page 189) is generated and the device becomes a slave receiver. Otherwise (wrong
address, NACK returned), an interrupt with status S_I2cStConflict is generated and the device leaves the bus.
It is also possible that two masters could access the same slave with the same command. In this case, a conflict
might be detected during the transmission of a data byte or an acknowledge bit. In both cases, an interrupt with
status S_I2cStConflict is generated and the device leaves the bus.
4.10.7. Error Conditions
In addition to all the interrupts related to transmission and reception, two error interrupts are possible. If one of the
state machines in this module enters an undefined state (due to cosmic radiation), an interrupt with status
S_I2cStHWError (see page 194) is generated. To solve this situation, the module must be disabled as all state
machines are then set back to their default states.
If a START or STOP condition is detected on the bus during an active transfer as a master or a slave, this module
immediately leaves the bus and generates an interrupt with status S_I2cStBusError (see page 194). If this error
was caused by a START condition or if a START conditions follows afterward, the low phase of SCL following the
START will be expanded until the interrupt is cleared to be able to setup the device correctly for a new transfer.
Warning: Due to several error conditions, for example if a slave missed one clock cycle, other state transitions
are possible, and the bus might get stuck. When an unexpected state transition occurs, the module must be
disabled and re-enabled to clean up the bus. One possible situation is a conflict when operating as single master.
4.10.8. Bus States
There are four different states possible for the I2C™ bus. The bus can be busy, free, or stuck, or the state can be
unknown. The last state occurs when the device is just enabled. The determination of the bus state depends on
whether the device is the only master on the bus (multi bit in the Z2_I2CCTRLregister == 0) or not (multi bit
== 1).
© 2016 Integrated Device Technology, Inc.
182
January 29, 2016
ZSSC1956 Datasheet
4.10.8.1. Single Master
At enable, the I2C™ bus state is unknown as the module did not observe the bus when it was disabled. When this
device is configured to be the only master on the bus (multi bit in the Z2_I2CCTRLregister == 0), no START or
STOP condition can occur. Additionally SCL cannot change from high to low as this transition is only allowed for
masters, but a slave can only hold SCL low after it has detected a low clock line. This is needed to handle
interrupts and data before the transfer continues. Therefore three bus conditions are possible after enabling this
module:
•
•
SCL == 1 and SDA == 1: When both lines are undriven, the module assumes the bus to be free.
SCL == 1 and SDA == 0: This situation can only occur if a slave has missed a clock pulse or if the
master was disabled within a transfer. In this case, the module assumes the
bus to be stuck and generates clock pulses until both lines are undriven.
•
SCL == 0: This situation can only occur when the master was disabled within a transfer and the
accessed slave holds SCL low as it has not cleared its interrupt. This situation cannot be
directly cleared so the master must wait until the slave releases SCL. After that, one of the
two situations above is present which the master is able to handle.
Note: The module assumes the bus is free if both SCL and SDA are high. When the module detects a START
condition (generated by itself), it assumes the bus is busy.
Note: If the bus is stuck, the device generates clock pulses until both SDA and SCL are high. Then it assumes
the bus is free again. Therefore the multi bit must be set to 1 when operating as slave-only to avoid this module
assuming the bus to be stuck and generating clock pulses on the SCL line.
Note: The bus is only busy after the module has generated a START. Normally, the module generates a STOP to
release the bus at the end of its transfer. When this STOP does not occur on the bus because a slave drives SDA
low due to an error, the bus is stuck.
4.10.8.2. Multi Master
At enable, the bus state is unknown as the module did not observe the bus when it was disabled. In contrast to a
single master system, it cannot assume the bus to be free when both lines are undriven as this situation also
occurs during the transmission of a 1 when the clock is high. The following conditions are possible:
•
•
•
START detected: The module assumes the bus to be busy.
STOP detected:
The bus assumes the bus to be free.
Falling edge of SCL:
As only a master is allowed to change the level of SCL from 1 to 0, the module
assumes an active transfer and therefore the bus to be busy.
•
•
•
SCL == 1 and SDA == 1: When this condition is true for a specific time (timeout), the module assumes
the bus to be free. Before the timeout occurs, the bus state remains unknown.
SCL == 1 and SDA == 0: When this condition is true for a specific time (timeout), the module assumes
the bus to be stuck. Before the timeout occurs, the bus state remains unknown.
SCL == 0: This situation can occur because a transfer is active but also can occur due to the situation
described for single master. Therefore the master cannot determine the correct state and waits
until SCL becomes high again.
Note: The module assumes the bus is free if both SCL and SDA are high. When the module detects a START
condition, it assumes the bus is busy.
© 2016 Integrated Device Technology, Inc.
183
January 29, 2016
ZSSC1956 Datasheet
Note: If the bus is stuck, the device generates clock pulses until both SDA and SCL are high. Then it assumes
the bus is free again.
Note: The bus is busy after a detection of a START condition generated by any master. The following conditions
are possible for a change of the bus state:
•
•
STOP detected:
The bus assumes the bus to be free.
SCL == 1 and SDA == 1: When this condition is true for a specific time (timeout), the module assumes
the bus to be free.
•
•
SCL == 1 and SDA == 0: When this condition is true for a specific time (timeout), the module assumes
the bus to be stuck.
STOP sent but not detected on the bus: The module assumes the bus to be stuck.
4.10.9. Status Description
Status name and code:
S_I2cStIdle – 00HEX
•
Description: This is the only state where no interrupt is activated. This state is entered via reset if the
device is disabled or when this device is the master and a STOP condition is generated.
First action (access to Z2_I2CDATAregister):---
•
•
Second action (write to Z2_I2CCTRL register):
o
o
o
o
Stop:
Start: 0 or 1
Irq::
Ack:
0
0
0 or 1
•
Possible next status:
o
o
o
o
o
o
S_I2cStTxStart
S_I2cStRxRdAddr
S_I2cStRxGcAddr
S_I2cStRxWrAddr
S_I2cStBusError
S_I2cStIdle (disable)
Note: This state is entered without activating the interrupt line.
© 2016 Integrated Device Technology, Inc.
184
January 29, 2016
ZSSC1956 Datasheet
Status name and code:
S_I2cStTxStart – 01HEX (MASTER STATE)
•
Description: This state is entered after a START condition was generated on the bus. The interrupt is
entered after SCL is low. SCL stays low until the interrupt is cleared. The device has
allocated the bus as master and will continue generating the clock.
First action (access to Z2_I2CDATAregister):Program command (R/W; bit 0) and address (bits [7:1])
of slave to be accessed.
•
•
Second action (write to Z2_I2CCTRL register):
o
o
o
o
Stop:
Start: Clear
Irq::
Ack:
0
Clear
0 or 1
•
Possible next status:
o
o
o
o
o
o
o
o
o
o
S_I2cStTxWrAddr
S_I2cStTxWrAddrN
S_I2cStTxRdAddr
S_I2cStTxRdAddrN
S_I2cStRxRdAddrL
S_I2cStRxGcAddrL
S_I2cStRxWrAddrL
S_I2cStConflict
S_I2cStBusError
S_I2cStIdle (disable)
Note: Generating a STOP or RESTART condition directly after a START condition is not allowed.
Status name and code: S_I2cStTxWrAddr – 02HEX
(TX MASTER STATE)
•
•
•
Description: This state is entered after ACK is received as a response to a successful transmission of
the slave address and write command. The ACK response means that the slave is ready
to receive data.
First action (access to Z2_I2CDATAregister):Program data to be written to the slave only if data will
be transmitted but not when RESTART or STOP will be
generated.
Second action (write to Z2_I2CCTRL register):
o
o
o
o
Stop: 0 or 1
Start: 0 or 1
Irq::
Clear
0 or 1
Ack:
•
Possible next status:
o
o
o
o
o
o
S_I2cStMstTxData
S_I2cStMstTxDataN
S_I2cStTxStart
S_I2cStConflict
S_I2cStBusError
S_I2cStIdle (disable / STOP)
© 2016 Integrated Device Technology, Inc.
185
January 29, 2016
ZSSC1956 Datasheet
Status name and code:
S_I2cStTxWrAddrN – 03HEX
(TX MASTER STATE)
•
Description: This state is entered after NACK is received as a response to a successful transmission
of the slave address and write command. The NACK response means that the slave is
not ready to receive data or the address used is not assigned to any slave on the bus.
First action (access to Z2_I2CDATAregister):---
•
•
Second action (write to Z2_I2CCTRL register):
o
o
o
o
Stop: 0 or 1
Start: 0 or 1
Irq::
Clear
0 or 1
Ack:
•
Possible next status:
o
o
S_I2cStTxStart
S_I2cStIdle (disable / STOP)
Status name and code:
S_I2cStMstTxData – 04HEX
(TX MASTER STATE)
•
Description: This state is entered after ACK is received as the response to a successful transmission
of data. The ACK response means that the slave is ready to receive more data.
First action (access to Z2_I2CDATAregister):Program data to be written to the slave only if data will
be transmitted but not when RESTART or STOP will be
•
generated.
•
•
Second action (write to Z2_I2CCTRL register):
o
o
o
o
Stop: 0 or 1
Start: 0 or 1
Irq::
Clear
0 or 1
Ack:
Possible next status:
o
o
o
o
o
o
S_I2cStMstTxData
S_I2cStMstTxDataN
S_I2cStTxStart
S_I2cStConflict
S_I2cStBusError
S_I2cStIdle (disable / STOP)
Status name and code:
S_I2cStMstTxDataN – 05HEX
(TX MASTER STATE)
•
Description: This state is entered after NACK is received as a response to a successful transmission
of data. The NACK response means that the slave is not able to receive more data.
First action (access to Z2_I2CDATAregister):---
•
•
Second action (write to Z2_I2CCTRL register):
o
o
o
o
Stop: 0 or 1
Start: 0 or 1
Irq::
Clear
0 or 1
Ack:
•
Possible next status:
o
o
S_I2cStTxStart
S_I2cStIdle (disable / STOP)
© 2016 Integrated Device Technology, Inc.
186
January 29, 2016
ZSSC1956 Datasheet
Status name and code:
S_I2cStTxRdAddr – 06HEX
(RX MASTER STATE)
•
Description: This state is entered after ACK is received as a response to a successful transmission of
the slave address and read command. The ACK response means that the slave is ready
to transmit data bus turnaround, slave becomes the transmitter.
•
•
First action (access to Z2_I2CDATAregister):---
Second action (write to Z2_I2CCTRL register):
o
o
o
o
Stop:
Start:
Irq::
0
0
Clear
0 or 1
Ack:
•
Possible next status:
o
o
o
o
o
S_I2cStMstRxData
S_I2cStMstRxDataN
S_I2cStConflict
S_I2cStBusError
S_I2cStIdle (disable)
Status name and code:
S_I2cStTxRdAddrN – 07HEX
(RX MASTER STATE)
•
Description: This state is entered after NACK is received as a response to a successful transmission
of the slave address and read command. The NACK response means that the slave is
not ready to transmit data or the address used is not assigned to any slave on the bus
no bus turnaround, the master keeps the bus to generate the STOP or RESTART.
First action (access to Z2_I2CDATAregister):---
•
•
Second action (write to Z2_I2CCTRL register):
o
o
o
o
Stop: 0 or 1
Start: 0 or 1
Irq::
Clear
0 or 1
Ack:
•
Possible next status:
o
o
S_I2cStTxStart
S_I2cStIdle (disable / STOP)
Status name and code:
S_I2cStMstRxData – 08HEX
(RX MASTER STATE)
•
Description: This state is entered after ACK is transmitted as a response to a received data byte. The
ACK response means that the slave remains the transmitter and that the master waits for
the next data byte.
•
•
First action (access to Z2_I2CDATAregister):Read received data byte.
Second action (write to Z2_I2CCTRL register):
o
o
o
o
Stop:
Start:
Irq::
0
0
Clear
0 or 1
Ack:
•
Possible next status:
o
o
o
o
o
S_I2cStMstRxData
S_I2cStMstRxDataN
S_I2cStConflict
S_I2cStBusError
S_I2cStIdle (disable)
© 2016 Integrated Device Technology, Inc.
187
January 29, 2016
ZSSC1956 Datasheet
Status name and code:
S_I2cStMstRxDataN – 09HEX
(RX MASTER STATE)
•
Description: This state is entered after NACK is transmitted as a response to a received data byte.
The NACK response means that the slave releases the bus (bus turnaround) and that the
master becomes the transmitter for STOP or RESTART generation.
•
•
First action (access to Z2_I2CDATAregister):Read received data byte.
Second action (write to Z2_I2CCTRL register):
o
o
o
o
Stop: 0 or 1
Start: 0 or 1
Irq::
Clear
0 or 1
Ack:
•
Possible next status:
o
o
S_I2cStTxStart
S_I2cStIdle (disable / STOP)
Status name and code:
S_I2cStRxWrAddr – 0AHEX
(RX SLAVE STATE)
•
Description: This state is entered when the device’s own slave address and a write command were
received and ACK was returned while the device was idle.
•
•
First action (access to Z2_I2CDATAregister):---
Second action (write to Z2_I2CCTRL register):
o
o
o
o
Stop:
Start: 0 or 1
Irq::
Ack:
0
Clear
0 or 1
•
Possible next status:
o
o
o
o
o
S_I2cStRxSlvEnd
S_I2cStRxWrData
S_I2cStRxWrDataN
S_I2cStBusError
S_I2cStIdle (disable)
Status name and code:
S_I2cStRxWrAddrL – 0BHEX
(RX SLAVE STATE; multi-master only)
•
Description: This state is entered when the device’s own slave address and a write command were
received and ACK was returned while the device lost arbitration. This can happen after
an S_I2cStTxStart interrupt when another master also accessed the bus, winning
arbitration and accessing this device.
•
•
First action (access to Z2_I2CDATAregister):---
Second action (write to Z2_I2CCTRL register):
o
o
o
o
Stop:
Start: 0 or 1
Irq::
Ack:
0
Clear
0 or 1
•
Possible next status:
o
o
o
o
o
S_I2cStRxSlvEnd
S_I2cStRxWrData
S_I2cStRxWrDataN
S_I2cStBusError
S_I2cStIdle (disable)
© 2016 Integrated Device Technology, Inc.
188
January 29, 2016
ZSSC1956 Datasheet
Status name and code:
S_I2cStRxGcAddr – 0CHEX
(RX SLAVE STATE)
•
Description: This state is entered when the global call address and a write command were received
and ACK was returned while the device was idle.
•
•
First action (access to Z2_I2CDATAregister):---
Second action (write to Z2_I2CCTRL register):
o
o
o
o
Stop:
Start: 0 or 1
Irq::
Ack:
0
Clear
0 or 1
•
Possible next status:
o
o
o
o
o
S_I2cStRxSlvEnd
S_I2cStRxWrData
S_I2cStRxWrDataN
S_I2cStBusError
S_I2cStIdle (disable)
Status name and code:
S_I2cStRxGcAddrL – 0DHEX
(RX SLAVE STATE; multi-master only)
•
Description: This state is entered when the global call address and a write command were received
and ACK was returned while the device lost arbitration. This can happen after an
S_I2cStTxStart interrupt when another master also accessed the bus, winning arbitration
and accessing this device.
•
•
First action (access to Z2_I2CDATAregister):---
Second action (write to Z2_I2CCTRL register):
o
o
o
o
Stop:
Start: 0 or 1
Irq::
Ack:
0
Clear
0 or 1
•
Possible next status:
o
o
o
o
o
S_I2cStRxSlvEnd
S_I2cStRxWrData
S_I2cStRxWrDataN
S_I2cStBusError
S_I2cStIdle (disable)
Status name and code:
S_I2cStRxWrData – 0EHEX
(RX SLAVE STATE)
•
Description: This state is entered when the device was accessed via its slave address, data was
received, and ACK was returned.
•
•
First action (access to Z2_I2CDATAregister):Read received data byte.
Second action (write to Z2_I2CCTRL register):
o
o
o
o
Stop:
Start: 0 or 1
Irq::
Ack:
0
Clear
0 or 1
•
Possible next status:
o
o
o
o
o
S_I2cStRxSlvEnd
S_I2cStRxWrData
S_I2cStRxWrDataN
S_I2cStBusError
S_I2cStIdle (disable)
© 2016 Integrated Device Technology, Inc.
189
January 29, 2016
ZSSC1956 Datasheet
Status name and code:
S_I2cStRxWrDataN – 0FHEX
(RX SLAVE STATE)
•
Description: This state is entered when the device is accessed via its slave address, data was
received, and NACK was returned. The device leaves the active slave state.
First action (access to Z2_I2CDATAregister):Read received data byte.
•
•
Second action (write to Z2_I2CCTRL register):
o
o
o
o
Stop:
Start: 0 or 1
Irq::
Ack:
0
Clear
0 or 1
•
Possible next status:
o
o
o
o
o
o
S_I2cStTxStart
S_I2cStRxRdAddr
S_I2cStRxGcAddr
S_I2cStRxWrAddr
S_I2cStBusError
S_I2cStIdle (disable)
Status name and code:
S_I2cStRxGcData – 10HEX
(RX SLAVE STATE)
•
Description: This state is entered when the device was accessed via the global call address, data was
received, and ACK was returned.
•
•
First action (access to Z2_I2CDATAregister):Read received data byte.
Second action (write to Z2_I2CCTRL register):
o
o
o
o
Stop:
Start: 0 or 1
Irq::
Ack:
0
Clear
0 or 1
•
Possible next status:
o
o
o
o
o
S_I2cStRxSlvEnd
S_I2cStRxGcData
S_I2cStRxGcDataN
S_I2cStBusError
S_I2cStIdle (disable)
Status name and code:
S_I2cStRxGcDataN – 11HEX
(RX SLAVE STATE)
•
Description: This state is entered when the device is accessed via the global call address, data was
received, and NACK returned. The device leaves the active slave state.
•
•
First action (access to Z2_I2CDATAregister):Read received data byte.
Second action (write to Z2_I2CCTRL register):
o
o
o
o
Stop:
Start: 0 or 1
Irq::
Ack:
0
Clear
0 or 1
•
Possible next status:
o
o
o
o
o
o
S_I2cStTxStart
S_I2cStRxRdAddr
S_I2cStRxGcAddr
S_I2cStRxWrAddr
S_I2cStBusError
S_I2cStIdle (disable)
© 2016 Integrated Device Technology, Inc.
190
January 29, 2016
ZSSC1956 Datasheet
Status name and code:
S_I2cStRxSlvEnd – 12HEX
(RX SLAVE STATE)
•
Description: This state is entered when the device is operating as an active slave and a STOP or
RESTART condition is received.
•
•
First action (access to Z2_I2CDATAregister):---
Second action (write to Z2_I2CCTRL register):
o
o
o
o
Stop:
Start: 0 or 1
Irq::
Ack:
0
Clear
0 or 1
•
Possible next status:
o
o
o
o
o
o
S_I2cStTxStart
S_I2cStRxRdAddr
S_I2cStRxGcAddr
S_I2cStRxWrAddr
S_I2cStBusError
S_I2cStIdle (disable)
Status name and code:
S_I2cStRxRdAddr – 13HEX
(TX SLAVE STATE)
•
Description: This state is entered when the device’s own slave address and a read command were
received and ACK was returned while the device was idle.
•
•
First action (access to Z2_I2CDATAregister):Program data to be written to master.
Second action (write to Z2_I2CCTRL register):
o
o
o
o
Stop:
Start: 0 or 1
Irq::
Ack:
0
Clear
0 or 1
•
Possible next status:
o
o
o
o
o
o
S_I2cStSlvTxData
S_I2cStSlvTxDataN
S_I2cStSlvTxDataL
S_I2cStConflict
S_I2cStBusError
S_I2cStIdle (disable)
© 2016 Integrated Device Technology, Inc.
191
January 29, 2016
ZSSC1956 Datasheet
Status name and code:
S_I2cStRxRdAddrL – 14HEX
(TX SLAVE STATE; multi-master only)
•
Description: This state is entered when the device’s own slave address and a read command were
received and ACK was returned while the device lost arbitration. This can happen after
an S_I2cStTxStart interrupt when another master also accessed the bus, winning
arbitration and accessing this device.
•
•
First action (access to Z2_I2CDATAregister):Program data to be written to master.
Second action (write to Z2_I2CCTRL register):
o
o
o
o
Stop:
Start: 0 or 1
Irq::
Ack:
0
Clear
0 or 1
•
Possible next status:
o
o
o
o
o
o
S_I2cStSlvTxData
S_I2cStSlvTxDataN
S_I2cStSlvTxDataL
S_I2cStConflict
S_I2cStBusError
S_I2cStIdle (disable)
Status name and code:
S_I2cStSlvTxData – 15HEX
(TX SLAVE STATE)
•
Description: This state is entered when data was transmitted, ACK was returned by the master, and
there is still data to be transmitted (ackbit in the Z2_I2CCTRLregister == 1).
First action (access to Z2_I2CDATAregister):Program data to be written to master.
Second action (write to Z2_I2CCTRL register):
•
•
o
o
o
o
Stop:
Start: 0 or 1
Irq::
Ack:
0
Clear
0 or 1
•
Possible next status:
o
o
o
o
o
o
S_I2cStSlvTxData
S_I2cStSlvTxDataN
S_I2cStSlvTxDataL
S_I2cStConflict
S_I2cStBusError
S_I2cStIdle (disable)
Status name and code:
S_I2cStSlvTxDataN – 16HEX
(TX SLAVE STATE)
•
Description: This state is entered when data was transmitted and NACK was returned by the master.
The device leaves the active slave state.
•
•
First action (access to Z2_I2CDATAregister):---
Second action (write to Z2_I2CCTRL register):
o
o
o
o
Stop:
Start: 0 or 1
Irq::
Ack:
0
Clear
0 or 1
© 2016 Integrated Device Technology, Inc.
192
January 29, 2016
ZSSC1956 Datasheet
•
Possible next status:
o
o
o
o
o
o
S_I2cStTxStart
S_I2cStRxRdAddr
S_I2cStRxGcAddr
S_I2cStRxWrAddr
S_I2cStBusError
S_I2cStIdle (disable)
Status name and code:
S_I2cStSlvTxDataL – 17HEX
(TX SLAVE STATE)
•
Description: This state is entered when data was transmitted, ACK was returned by the master, but no
more data is available (ackbit in the Z2_I2CCTRLregister == 0). The device leaves the
active slave state.
•
•
First action (access to Z2_I2CDATAregister):---
Second action (write to Z2_I2CCTRL register):
o
o
o
o
Stop:
Start: 0 or 1
Irq::
Ack:
0
Clear
0 or 1
•
Possible next status:
o
o
o
o
o
o
S_I2cStTxStart
S_I2cStRxRdAddr
S_I2cStRxGcAddr
S_I2cStRxWrAddr
S_I2cStBusError
S_I2cStIdle (disable)
Status name and code:
S_I2cStConflict – 18HEX (MASTER / SLAVE STATE)
•
Description: This state is entered when the device is sending a logic 1 but receiving a logic 0. This can
happen when
•
•
•
•
sending the slave address or the read command as the master device
sending data as the master transmitter
sending NACK as the master receiver
sending data as the slave transmitter
•
•
First action (access to Z2_I2CDATAregister):---
Second action (write to Z2_I2CCTRL register):
o
o
o
o
Stop:
Start: 0 or 1
Irq::
Ack:
0
Clear
0 or 1
•
Possible next status:
o
o
o
o
o
o
S_I2cStTxStart
S_I2cStRxRdAddr
S_I2cStRxGcAddr
S_I2cStRxWrAddr
S_I2cStBusError
S_I2cStIdle (disable)
Note: When sending NACK as the slave receiver, it is not interpreted as a conflict. The bus is just left. (The
master might write to multiple slaves.)
© 2016 Integrated Device Technology, Inc.
193
January 29, 2016
ZSSC1956 Datasheet
Status name and code:
S_I2cStBusError – 19HEX
(MASTER / SLAVE STATE)
•
Description: This state is entered when device is active as the master or slave and a
RESTART/START or STOP condition is detected at a wrong position within a transfer.
When detecting an error, the device leaves the bus immediately.
•
•
First action (access to Z2_I2CDATAregister):---
Second action (write to Z2_I2CCTRL register):
o
o
o
o
Stop:
Start: 0 or 1
Irq::
Ack:
0
Clear
0 or 1
•
Possible next status:
o
o
o
o
o
o
S_I2cStTxStart
S_I2cStRxRdAddr
S_I2cStRxGcAddr
S_I2cStRxWrAddr
S_I2cStBusError
S_I2cStIdle (disable)
Status name and code:
S_I2cStHWError – 1FHEX
(MASTER / SLAVE STATE)
•
Description: This state is entered when one of the state machines goes to an undefined state (due to
cosmic radiation). This state is used for safety only. To leave this state and to setup the
module correctly, the module must be disabled and re-enabled again.
•
•
First action (access to Z2_I2CDATAregister):---
Second action (write to Z2_I2CCTRL register):
o
o
o
o
Stop:
Start:
Irq::
0
0
Clear
0
Ack:
•
Possible next status:
S_I2cStIdle (disable)
o
© 2016 Integrated Device Technology, Inc.
194
January 29, 2016
ZSSC1956 Datasheet
4.10.10. egister Overview for I²C™ Module
4.10.10.1.
Register “Z2_I2CCLKRATE” and “Z2_ I2CCLKRATE 2 – Baud Rate Configuration
Table 4.51 Register Z2_I2CCLKRATE– system address 4000 1C20HEX
Name
Bits
Default
Access
Description
crLsb
[7:0]
RW
Configuration of bit rate for master operation.
bit rate = clk / (2*[{crMsb, crLsb}+1])
FFHEX
Note: Do not program values less than 7.
Note: Do not change during active master transfer.
Unused
[31:8]
RO
Unused; always write as 0.
00 0000HEX
Table 4.52 Register Z2_I2CCLKRATE2– system address 4000 1C24HEX
Name
Bits
Default
Access
Description
crMsb
[5:0]
11 1111BIN
RW
Configuration of bit rate for master operation.
Bit rate = clk / (2*[{crMsb, crLsb}+1])
Note: Do not program values less than 7.
Note: Do not change during active master transfer.
Unused
[31:6]
0…0BIN
RO
Unused; always write as 0.
4.10.10.2.
Register “Z2_I2CADDR” – I²C™ Address
Table 4.53 Register Z2_I2CADDR– system address 4000 1C28HEX
Name
Bits
Default
Access
Description
General call address enable.
gc
[0]
0BIN
RW
A write access by another master using the general call address is
only accepted when this bit is set to 1.
Note: Read accesses using the general call address are not
allowed and ignored by hardware.
addr
[7:1]
0BIN
RW
RO
Own I2C™ slave address.
Used to recognize if another master tries to access this device.
Unused; always write as 0.
Unused
[31:8]
00 0000HEX
© 2016 Integrated Device Technology, Inc.
195
January 29, 2016
ZSSC1956 Datasheet
4.10.10.3.
Register “Z2_I2CCTRL” – I²C™ Control
Table 4.54 Register Z2_I2CCTRL– system address 4000 1C2CHEX
Name
Bits
Default
Access
Description
enI2C
multi
[0]
0BIN
RW
Enable bit for the I2C™ module; all state machines are reset at
disable.
Note: Do not disable the I2C™ module during an active master
transfer. Otherwise a slave could block the bus if it did not receive
enough clock pulses.
[1]
[2]
0BIN
RW
RW
This bit must be set in multi-master applications.
When set to 1, the timeout counter to detect a stuck bus and to
detect a free or busy bus state at enable of the I2C™ module is
enabled.
Note: Change only when module is disabled.
ack
0BIN
When set to 1, an ACK bit is generated in response to a detected
address match (slave access) as well as a response to a received
data byte (master and slave). It is also used to stop the transfer as
a slave transmitter (see status handling).
Note: When the ackbit is not set, no packet will be received;
when set, packets with matching addresses or global addresses
will be received if enabled.
irq
[3]
0BIN
RW
Interrupt bit.
This bit is set by hardware and must be cleared by software after
handling the interrupt.
All transactions must be interrupt-driven.
Stop bit for master mode.
stop
start
[4]
[5]
0BIN
RW
RW
This bit must be set by software to stop a master transfer and to
generate a STOP on the bus. It is cleared by hardware.
Start or restart bit for master mode.
0BIN
This bit must be set by software to generate a START or
RESTART condition on the bus.
This bit must be cleared by software after each interrupt.
Unused; always write as 0.
Unused
[31:6]
0…0BIN
RO
© 2016 Integrated Device Technology, Inc.
196
January 29, 2016
ZSSC1956 Datasheet
4.10.10.4.
Register “Z2_I2CSTAT” – I²C™ Status
Table 4.55 Register Z2_I2CSTAT– system address 4000 1C30HEX
Name
gc_stat
Bits
Default
Access
Description
This value reflects the last interrupt reason (see section 4.10.9):
[4:0]
00000BIN
RO
00HEX: S_I2cStIdle
01HEX: S_I2cStTxStart
02HEX: S_I2cStTxWrAddr
04HEX: S_I2cStMstTxData
06HEX: S_I2cStTxRdAddr
08HEX: S_I2cStMstRxData
0AHEX: S_I2cStRxWrAddr
0CHEX: S_I2cStRxGcAddr
0EHEX: S_I2cStRxWrData
10HEX: S_I2cStRxGcData
12HEX: S_I2cStRxSlvEnd
14HEX: S_I2cStRxRdAddrL
16HEX: S_I2cStSlvTxDataN
18HEX: S_I2cStConflict
03HEX: S_I2cStTxWrAddrN
05HEX: S_I2cStMstTxDataN
07HEX: S_I2cStTxRdAddrN
09HEX: S_I2cStMstRxDataN
0BHEX: S_I2cStRxWrAddrL
0DHEX: S_I2cStRxGcAddrL
0FHEX: S_I2cStRxWrDataN
11HEX: S_I2cStRxGcDataN
13HEX: S_I2cStRxRdAddr
15HEX: S_I2cStSlvTxData
17HEX: S_I2cStSlvTxDataL
19HEX: S_I2cStBusError
1FHEX: S_I2cStHWError
Unused; always write as 0.
Unused
[31:5]
0…0BIN
RO
4.10.10.5.
Register “Z2_I2CDATA” – I²C™ Data
Table 4.56 Register Z2_I2CDATA– system address 4000 1C34HEX
Name
gc_data
Bits
Default
Access
Description
[7:0]
00HEX
RW
Data register.
As there are no buffers for RX or TX, data is shifted through this
register.
Note: Write access is only allowed (and possible) when the I2C™
module is enabled and the interrupt is active; additional restrictions
occur due to the interrupt reason (status).
Note: Read access is only valid if the interrupt is active.
Unused
[31:8] 00 0000HEX
RO
Unused; always write as 0.
© 2016 Integrated Device Technology, Inc.
197
January 29, 2016
ZSSC1956 Datasheet
4.11. USART in ZSYSTEM2
The USART module provides four different operating modes. Two of them deliver synchronous operation with a
size of 8 bits, during which this module is the master (it generates the clock). These modes vary only in the
sampling position in the RX mode. The other two modes offer asynchronous operation: one with a size of 8 bits
and the other with a size of 9 bits. The last mode can also be used for multiprocessor communication.
The maximum possible baud rate on the bus is a fifth of the internal clock in synchronous mode or a fourth of the
internal clock in asynchronous mode.
The USART has an active-high interrupt line connected to ARM® interrupt 7.
Important: Before the USART can be used, the clock of ZSYSTEM2 must be enabled first via register
SYS_CLKCFG (see Table 4.5). After the clock for the ZSYSTEM2 is enabled, the USART pins must be mapped
onto appropriate GPIO pads (see section 4.3.4).
The USART module in ZSYSTEM2 has an active-high interrupt line connected to ARM® interrupt 7.
4.11.1. External Signal Lines
The USART bus consists of two external signal lines, TXD and RXD. The TXD line always operates as an output.
Therefore the behavior of its output driver (open-drain; push-pull) is selectable by setting the corresponding bit of
bit field ppNodof register SYS_MEMPORTCFG (see Table 4.6) to the desired value. In synchronous mode, the
TXD line is used to provide the clock for the connected slave. In asynchronous mode, the TXD line is used to
send data to the connected device. As the RXD line is used to send and receive data in synchronous mode, its
output driver always operates as an open-drain independent of the setting of the ppNod bit field. In asynchronous
mode, it is always used to receive data from the connected device.
4.11.2. Asynchronous Mode
When operating in asynchronous mode (Modebit field in register Z2_USARTCFG is set to 2 or 3; see Table 4.57),
the receive channel and the transmit channel are completely independent. When mode 2 is selected, 8 bits are
transferred between the START bit and the STOP bit. In mode 3, there are 9 bits transferred between the START
bit and the STOP bit. The USART module is enabled by the UsartEnbit in register Z2_USARTCFG. The mode
must not be changed when the module is enabled, but it can be selected in the same write access as the module
enable.
As the operation is asynchronous, the timing of the transfer must be defined identically on both sides (this device
and the connected device) before a transfer can take part. This can be done for this device by programming the
appropriate value to the baud rate registers (Z2_USARTCLK1 and Z2_USARTCLK2; see section 4.11.4.5). The
baud rate depends on the divided system clock (see section 4.3.2) and must only be changed when the module is
disabled. The value to be programmed is calculated using the following formula:
period = round(module clock / baud rate) – 1
The minimum value allowed to be programmed is 3.
While there is no dedicated enable for the TX channel (transmission is started by a write access to the TX buffer),
the receive channel has a dedicated enable bit (RxEn_USART bit in register Z2_USARTCFG). As the incoming
data cannot be influenced regarding arrival time, it is recommended that enabling or disabling the receive channel
only be performed when the module is disabled. The RX enable bit can be selected in the same write access as
the module enable.
© 2016 Integrated Device Technology, Inc.
198
January 29, 2016
ZSSC1956 Datasheet
When the module is disabled, all state machines as well as all status bits in the Z2_USARTSTAT register except
RxFull_USARTand RxBit8are set back to their default state (see Table 4.58). The RxFull_USARTstatus bit
is only cleared by read access to the RX buffer to prevent losing data at disable.
Figure 4.12 Data Format of Asynchronous Transfers
Mode 2 (8-bit asynchronous transfer)
(period+1) /
f(module)
START
D[0]
D[1]
D[2]
D[3]
D[4]
D[5]
D[6]
D[7]
STOP
RX sampling
Mode 3 (9-bit asynchronous transfer)
(period+1) /
f(module)
START
D[0]
D[1]
D[2]
D[3]
D[4]
D[5]
D[6]
D[7]
D[8]
STOP
RX sampling
4.11.2.1. USART Asynchronous Transmission
A transmission is started by writing the data to be transmitted into the TX buffer (write to Z2_USARTDATA; see
Table 4.59). As this register is only 8-bit wide, the ninth bit (MSB) in mode 3 must be written to TxBit8
(Z2_USARTCFG [7]) before writing the LSBs to the TX buffer. Writing to the TX buffer clears the status flag
TxBufEmpty in the status register Z2_USARTSTAT (see Table 4.58). When the transmitter is idle (bit
TxSrEmptyis 1), the START bit and the STOP bit are added to the TX data and all 10/11 bits are moved into the
TX shift register. The status flag TxBufEmpty is cleared, and the data is shifted out of the module. Both the
START bit and the STOP bit have a length of 1 bit. New data can be written into TxBit8and into the TX buffer
when the buffer is marked as empty (directly after the data transfer into the TX shift register).
When the data is shifted out and further data is present in the TX buffer, the next transfer follows immediately.
When no further data is present, the transmitter stops and the TxSrEmptyflag is set. When the software tries to
write to the TX buffer or to change TxBit8while the buffer is not empty (bit TxBufEmptyis 0), the write access
is rejected (old data is kept) and the write collision flag WrCollision_USARTis set to 1.
All three flags (TxSrEmpty, TxEmpty_USART, WrCollision_USART) are allowed to drive the interrupt line
when they are enabled for this via register Z2_USARTIRQEN (see Table 4.60). All three flags are set to their
default values when the module is disabled. The flag TxSrEmptyis also set and cleared by hardware only. The
flag TxEmpty_USART is set by data transfer into the shift register and cleared by write access to the TX buffer.
WrCollision_USART is only set by hardware and cleared on read access to the status register
Z2_USARTSTAT.
© 2016 Integrated Device Technology, Inc.
199
January 29, 2016
ZSSC1956 Datasheet
4.11.2.2. USART Asynchronous Reception
The module synchronizes to incoming data on the falling edge on the RXD line (START detection). After half a
period, it is checked whether the value on the RXD line is still 0. If this is not the case, the actual transfer is
stopped, the status flag StartErris set to 1 in register Z2_USARTSTAT (see Table 4.58) and the module waits
on the next falling edge on the RXD line. This error condition can occur due to a mismatch in the programmed
period in both devices, due to a spike on the RXD line that caused the erroneous synchronization or due to a
misaligned enable of the module. The last situation could be avoided by software if both devices send FFHEX as
data for an initial synchronization. In this case, only the START bit would drive the data line low. The flag
StartErris set by hardware and is cleared by read access to the status register Z2_USARTSTAT or when the
module is disabled. Further data reception is not blocked when this bit is set. When enabled via
Z2_USARTIRQEN (see Table 4.60), this flag is allowed to drive the interrupt line.
When operating in mode 2 and the Mpcebit (Z2_USARTCFG[4]) is 0, the received data byte is stored into the RX
buffer and the level of the received STOP bit is stored into RxBit8 (Z2_USARTSTAT[7]). The data is stored at
the sampling position of the STOP bit. If the Mpcebit is 1 instead, the received byte and STOP bit are only stored
when the STOP bit has a value of 1. Otherwise the data is rejected. The rejection is not signaled to the software.
When data is stored in the RX buffer, the RxFull_USARTflag is set. This flag is cleared by reading the data out
of the RX buffer. If the RX buffer is marked as full when new data is received, the new data is rejected and the
RxOverflow_USART status flag is set. As there is no overflow check for RxBit8, the status including RxBit8must
be read before the RX buffer.
The flag RxOverflow_USART is set by hardware and cleared by read access to the status register or when the
module is disabled. When enabled via register Z2_USARTIRQEN, this flag is allowed to drive the interrupt line.
Also the RxFull_USARTflag is set by hardware and is allowed to drive the interrupt line. This flag is cleared on
read access to the RX buffer, but it is not cleared when module is disabled to avoid loss of data.
When operating in mode 3, there will be 9 instead of 8 data bits received. The module behaves almost the same,
except that there is no check for the STOP bit level. Instead the level of the ninth data bit can be checked when
bit Mpceis set to 1. This can be used for multiprocessor communication.
In multiprocessor communication, all devices set their Mpcebit to 1. In this case, they only receive and store data
when the ninth data bit is 1. The ninth bit is used to distinguish between the address byte (ninth bit is 1) and data
bytes (ninth bit is 0). For a complete transfer, the first byte is sent with the ninth bit set to 1 where this byte is used
as the address byte. All devices will receive this byte and can do an address check in software. After the address
check is performed, the addressed device clears its Mpcebit to be able to receive the following data bytes and the
originator of the address sends data bytes with the ninth bit set to 0. All other devices that are not addressed,
keep their Mpcebit set to 1 to ignore all incoming data bytes. They continue receiving when the next address byte
arrives.
4.11.3. Synchronous Mode
When operating in synchronous mode (Modebit field in register Z2_USARTCFG is set to 0 or 1; see Table 4.57),
this module generates the clock on the TXD line whenever a transfer will take place. Each transfer consists of 8
bits without any START or STOP bit. The data is transferred via the RXD line. The USART module is enabled by
the UsartEnbit in register Z2_USARTCFG. The mode must not be changed when the module is enabled, but it
can be selected in the same write access as the module enable. The two modes differ only by the sampling
position.
© 2016 Integrated Device Technology, Inc.
200
January 29, 2016
ZSSC1956 Datasheet
The transfer speed must be programmed as in asynchronous mode with the following formula:
period = round(module clock / baud rate) – 1
The minimum value allowed to be programmed is 4.
The clock is generated by hardware. The falling edge is generated at approximately ¼ of the period and the rising
edge is generated at approximately ¾ of the period.
If the real period (programmed period + 1) is equal to
• 4 N
the high phase of the generated clock is equal to the low phase.
*
• 4 N+1
the high phase of the generated clock is one cycle longer than the low phase.
the high phase of the generated clock is equal to the low phase.
*
• 4 N+2
*
• 4 N+3
the high phase of the generated clock is one cycle shorter than the low phase.
*
As one line is used for the transfer clock, the direction of the transfer must be selected via the RX enable bit
(RxEn_USARTin register Z2_USARTCFG). As this module controls the transfer, the RX enable bit should only be
changed when no transfer is in progress. This can be checked via the TxSrEmptystatus flag.
For transmission, the data byte to be transmitted must be programmed into the TX buffer. The data byte is then
transferred into the TX shift register and shifted out of the module. The three status flags behave as in
asynchronous mode.
Because the RXD line is a bidirectional open-drain buffer, a receive transfer is started by writing FFHEX into the TX
buffer. This means that receiving is the same as transmitting FFHEX except that the RX enable bit (RxEn_USART)
is set. The status flags RxOverflow_USART and RxFull_USARTbehave as in asynchronous mode except that
they are set at the sampling position of the last bit of the received data byte.
In mode 0, the RXD line is sampled at the rising edge of the generated clock. As the transfer is synchronous, the
connected slave is assumed to send the data to the RX line on the falling edge. Therefore the device samples the
data half a period after it was generated. This time is further shortened due to the PCB delay of the clock, the
internal delay of the accessed device, and the PCB delay of the returned data. To address this timing issue, a
second mode (mode 1) is implemented where the data is sampled later at the end of the bit period.
Figure 4.13 Data Format of Synchronous Transfers
Mode 0 and Mode 1 differ only in sampling position
D[0]
D[1]
D[2]
D[3]
D[4]
D[5]
D[6]
D[7]
RX sampling in mode 0
RX sampling in mode 1
© 2016 Integrated Device Technology, Inc.
201
January 29, 2016
ZSSC1956 Datasheet
4.11.4. Register Overview of USART
4.11.4.1. Register “Z2_USARTCFG” – USART Configuration
Table 4.57 Register Z2_USARTCFG– system address 4000 1C40HEX
Name
UsartEn
RxEn_USART
Bits
Default
Access
Description
[0]
[1]
0BIN
0BIN
RW
RW
Enable for the USART.
Enable for the RX part of the USART.
Note: RxEn_USARTselects the direction in mode 0 and 1; change
only when no transfer is in progress.
Note: Change only when module is disabled in mode 2 or 3.
USART mode.
Mode
[3:2]
[4]
00BIN
RW
RW
0: 8 bit synchronous operation; RX sampling at rising edge
1: 8 bit synchronous operation; RX sampling at end of bit period
2: 8 bit asynchronous operation
3: 9 bit asynchronous operation
Note: Change only when module is disabled.
Mpce
0BIN
Multiprocessor communication enable; unused in modes 0 and 1.
In mode 2:
0: ignore level of STOP bit
1: receive only when STOP bit is 1
In mode 3:
0: ignore level of ninth bit
1: receive only when ninth bit is 1
Unused
TxBit8
[6:5]
[7]
00BIN
0BIN
RO
RW
Unused; always write as 0.
Ninth bit to be transmitted in mode 3; unused in other modes.
Note: If a write access to this register occurs when the TX buffer is
full and when operating in mode 3, this bit keeps its contents and
the written bit is rejected. This is signaled by the
WrCollision_USARTflag in the status register only if write
access would have changed this bit.
Unused
[31:8] 00 0000HEX
RO
Unused; always write as 0.
© 2016 Integrated Device Technology, Inc.
202
January 29, 2016
ZSSC1956 Datasheet
4.11.4.2. Register “Z2_USARTSTAT” – USART Status
Table 4.58 Register Z2_USARTSTAT– system address 4000 1C44HEX
Name
Bits
Default
Access
Description
RxOverflow_USART
[0]
0BIN
RC
This bit signals that an Rx overflow occurred.
Note: This bit is cleared when the status is read or when disabling
the module.
Note: The received byte causing the overflow is rejected; the
previous received bit is kept in the RX buffer.
RxFull_USART
TxBufEmpty
[1]
[2]
0BIN
RO
RO
This bit reflects the status of the RX buffer. It is set when a new
byte is transferred into the RX buffer.
Note: This bit is cleared when UsartDatais read.
This bit reflects the status of the TX buffer. It is set when a byte is
transferred from the TX buffer into the shift register. It is cleared
when writing data to TX buffer.
1BIN
Note: This bit is set when disabling the module.
This bit is set when UsartDatais written while TX buffer is
already full.
Note: This bit is cleared when the status is read or when disabling
the module.
This bit is set when an invalid START bit is detected in mode 2 or
3; the currently active RX transfer is stopped.
Note: This bit is cleared when the status is read or when disabling
the module.
This bit reflects the status of the TX shift register. It is cleared
when a byte is transferred from the TX buffer into the shift
register. It is set when data is transferred and no more data is
available in the TX buffer.
WrCollision_USART
StartErr
[3]
[4]
[5]
0BIN
0BIN
1BIN
RC
RC
RO
TxSrEmpty
Note: This bit is set when disabling the module.
RxActive_USART
[6]
[7]
0BIN
0BIN
RO
This bit reflects the status of the receiver in mode 2 and 3.
Note: This bit is cleared when disabling the module.
This bit reflects the value of the ninth received bit in mode 3 and
the value of the STOP bit in mode 2.
RxBit8
RO
RO
Unused
[31:8] 00 0000HEX
Unused; always write as 0.
© 2016 Integrated Device Technology, Inc.
203
January 29, 2016
ZSSC1956 Datasheet
4.11.4.3. Register “Z2_USARTDATA” – USART Data Buffers
Table 4.59 Register Z2_USARTDATA– system address 4000 1C48HEX
Name
UsartData
Bits
Default
Access
Description
[7:0]
FFHEX
RW
When writing a byte to this register, the value is stored in the TX
buffer. Additionally a write access to this register clears the
TxEmpty_USARTflag in the status register.
When reading this register, the content of the RX buffer is
returned. Additionally, a read access to this register clears the
RxFull_USARTflag in the status register.
Note: When writing to this register when TX buffer is full, the TX
buffer keeps its contents and the written byte is rejected. This is
signaled by the WrCollision_USARTflag in the status register.
Note: Write access is only possible when the module is enabled.
Unused
[31:8] 00 0000HEX
RO
Unused; always write as 0.
4.11.4.4. Register “Z2_USARTIRQEN” – Interrupt Enable
Table 4.60 Register Z2_USARTIRQEN– system address 4000 1C4CHEX
Name
Bits
Default
Access
Description
RxOverflow_USART_irq
[0]
0BIN
RW
When set to 1, the corresponding status bit is allowed to drive
the IRQ output.
RxFull_USART_irq
TxEmpty_USART_irq
WrCollision_USART_irq
StartErr_irq
[1]
[2]
0BIN
0BIN
RW
RW
RW
RW
RW
RO
When set to 1, the corresponding status bit is allowed to drive
the IRQ output.
When set to 1, the corresponding status bit is allowed to drive
the IRQ output.
When set to 1, the corresponding status bit is allowed to drive
the IRQ output.
When set to 1, the corresponding status bit is allowed to drive
the IRQ output.
[3]
0BIN
[4]
0BIN
TxSrEmpty_irq
[5]
0BIN
When set to 1, the corresponding status bit is allowed to drive
the IRQ output.
Unused; always write as 0.
Unused
[31:6]
0…0BIN
© 2016 Integrated Device Technology, Inc.
204
January 29, 2016
ZSSC1956 Datasheet
4.11.4.5. Register “Z2_USARTCLK1” and “Z2_USARTCLK2 – Baud Rate Configuration
Table 4.61 Register Z2_USARTCLK1– system address 4000 1C50HEX
Name
Bits
Default
Access
Description
crLsb
[7:0]
FFHEX
RW
Configuration of baud rate.
baud rate = clk / ({crMsb, crLsb}+1)
Note: Change only when module is disabled.
Note: Do not program values less than 4 for synchronous modes.
Note: Do not program values less than 3 for asynchronous modes.
Unused; always write as 0.
Unused
[31:8] 00 0000HEX
RO
Table 4.62 Register Z2_USARTCLK2– system address 4000 1C54HEX
Name
Bits
Default
Access
Description
111 1111BIN
crMsb
[6:0]
RW
Configuration of baud rate.
baud rate = clk / ({crMsb, crLsb}+1)
Note: Change only when module is disabled.
Note: Do not program values less than 4 for synchronous modes.
Note: Do not program values less than 3 for asynchronous modes.
Unused
[31:7]
0…0BIN
RO
Unused; always write as 0.
© 2016 Integrated Device Technology, Inc.
205
January 29, 2016
ZSSC1956 Datasheet
5
ESD / EMC
The ZSSC1956 is designed to maximize EM immunity and minimize emissions.
Functional status A: According to specifications; no LIN communication errors; memory content must not be
lost; no wake-up from Sleep Mode; no reset.
Functional status B: According to specifications; offset error extended to < 100mA; no LIN communication
errors; memory content must not be lost; no wake-up from Sleep Mode; no reset.
Functional status C: Measurement tolerance beyond specifications; LIN communication errors allowed;
memory content must not be lost; reset allowed.
During EM exposure, all functions perform as designed; after exposure, all functions return automatically to within
normal limits; memory functions always remain in functional status A.
5.1. Electrostatic Discharge
ESD protection according to AEC-Q100 Rev. G
No.
1.
Parameter
ESD, LIN on system level 1)
Condition
Min
±6
Max
Unit
kV
kV
kV
V
IEC 61000-4-2
IEC 61000-4-2
AEC Q 100-002
AEC Q 100-011
AEC Q 100-011
2.
ESD, BAT+ on system level
ESD, HBM, all pins
±6
3.
±2
4.
ESD, CDM, corner pins
±750
±500
5.
ESD, CDM, all other pins
With external protection Diode GSOT36
V
1)
5.2. Power System Ripple Factor
Component functionality meets these specifications.
UN = 13.5V
Voltage variation: sine-wave
Amplitude GV = ±2V
Frequency range: 50Hz ≤ F ≤ 25kHz (linear sweep width for 10 min.)
Ri of output stage ≤ 100mΩ
5.3. Conducted Susceptibility
DPI in accordance with IEC 62132-4:2006; CW and 80% amplitude modulated carrier frequency; modulation
frequency 1 kHz, peak conservation. In the range from 1 to 10 MHz, the step is 0.1 MHz; in the range from 10 to
1000 MHz, it is 1MHz.
The dwell time is longer than the response time of the component and is not less than 1s. The test is carried out
with power level 1 and power level 2. Functional status A required for both levels. For bus pin “LIN,” the actual
OEM hardware requirements are valid.
© 2016 Integrated Device Technology, Inc.
206
January 29, 2016
ZSSC1956 Datasheet
Table 5.1 Conducted Susceptibility
Group
Pin Description
Frequency Range
1 to <10MHz
Power Level 1
0.2W
Power Level 2
3.7W
1
Pin connected to vehicle wiring harness.
1 to 1000MHz
1 to 1000MHz
1.3W
3.7W
2
3
Pin not connect to vehicle wiring harness: all
pins not in group 3 and 4.
0.05W
0.1W
Pin not connected to vehicle wiring harness:
one external high impedance pin (e.g.,
reference).
1 to 1000MHz
0.01W
0.02W
5.4. Conducted Susceptibility on Power Supply Lines
Test in accordance with ISO 7637-2:2004; pulse amplitudes are under no load condition.
Table 5.2 Conducted Susceptibility on Power Supply Lines
Burst Cycle /
Pulse Repetition
Time
Pulse
Mode
Internal Resistance
Generator
Functional
Status Class
Voltage
Condition
1
-100V
+100V
10Ω
2Ω
5000 pulses
5000 pulses
1h
5s
C
A
A
A
A
2a
3a
3b
4
0.2s
-150V
50Ω
50Ω
0.02Ω
100ms
100ms
1 min
+100V
1h
-7V
5 pulses
5 pulses
td=400ms
5b
Us = 86.5V
Us* = 26.5V
1Ω
1 min
C
5.5. Conducted Susceptibility on Signal Lines
The tests are in accordance with ISO 7637-3:2004. The direct capacitor coupling (DCC) method is used with the
functional status A. The pulse amplitudes are under no load condition.
Table 5.3 Conducted Susceptibility on Signal Lines
Internal Resistance
Generator
Coupling
Capacitor
Burst Cycle / Pulse
Repetition Time
Pulse Mode
Voltage
Condition
Fast pulse a
Fast pulse b
-200V
+200V
50Ω
50Ω
100pF
100pF
10 min
10 min
100ms
100ms
© 2016 Integrated Device Technology, Inc.
207
January 29, 2016
ZSSC1956 Datasheet
5.6. Conducted Emission
The tests are in accordance with IEC 61967-4:2002. In the whole frequency range of 0.1 to 1000MHz, a peak
detector with a bandwidth of 9kHz (measuring receiver with step 5 kHz) or 10 kHz (spectrum analyzer) is used.
The measuring or sweep time is selected in such a way that a longer time will not result in a change of more than
1dB in the measured emission. For the 150Ω method for each pin, the pin-group must be defined. With the 1Ω
method, the RF current is measured.
Table 5.4 Conducted Emission
Group
Pin Description
Limit
Method
15 K 11 m O
1Ω
Pin connected to vehicle wiring harness:
Power supply
A1
A2
A3
H 10 k N
150Ω
150Ω
150Ω
Analog, static
H 10 k N
Digital, PWM
13 H 10 k N
Pin not connected to vehicle wiring harness:
Power supply
B1
B2
H 10 k M
H I M
150Ω
150Ω
150Ω
150Ω
150Ω
Analog, static, test pin, not connected
Pin group B connected to trace shorter than 1cm
Digital, PWM
B2short
B3
H g M
6 e M
B4
Oscillator
E I M
© 2016 Integrated Device Technology, Inc.
208
January 29, 2016
ZSSC1956 Datasheet
5.7. Application Circuit Example for EMC Conformance
The final application may require adaption of the external circuit for EMC compliance in the target system as
shown in Figure 5.1.
Depending on the application, the resistor Rlin is either a BLM21AG221SN1D ferrite bead or a 20Ω resistor as
shown in this application circuit example.
Figure 5.1 Example Application Circuit
Cddp
2.2µF
Cddp
Cddl
2.2µF
10nF
Rbat
BAT+
Rtest
1kΩ
Cbat
100nF
100Ω
Rlin
Dbat
GSOT36
lin
Clin
220pF
DLin
GSOT36
VBAT VPP VDDP VDDC TEST VSSPC VDDL LIN
Ddde
Rdde Cdde1
Cdde2
100nF
VDDE
VSSLIN
TESTH
TESTL
STO
1
BAS21 2.2Ω
10µF
VSSE
VSSA
INP
.
n.c
n.c
.
Cinp
10nF
Chassis
GND
Rinp
sto
tck
221Ω
Rshunt
100µΩ
Cin
100nF
ZSSC1956
Rinn
INN
TCK
BAT-
221Ω
Cinn
10nF
VSSA
VDDA
TMS
tms
TRSTN
VSSN
trstn
Cdda
470nF
Rref
75kΩ
NTH
NTL GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 TDO TDI
Rntc
Cntc
10kΩ
470pF
gpio0 gpio1 gpio2 gpio3 gpio4 tdo
tdi
© 2016 Integrated Device Technology, Inc.
209
January 29, 2016
ZSSC1956 Datasheet
6
Pin Configuration and Package
Table 6.1 IC Pins
PIN Signal
VDDE
Description
1
Power supply
2
VSSE
VSSA
INP
Power ground
3
Analog voltage ground
Positive input for current channel
Negative input for current channel
Analog voltage ground
Analog voltage supply
4
5
INN
6
VSSA
VDDA
NTH
7
8
Positive input for the temperature channel
Negative input for the temperature channel
General purpose I/O
General purpose I/O
General purpose I/O
General purpose I/O
General purpose I/O
JTAG output
9
NTL
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
TDO
TDI
JTAG input
VSSN
TRSTN
TMS
Digital voltage ground
JTAG input
JTAG input
TCK
JTAG input
STO
Test data output
TESTL
TESTH
VSSLIN
LIN
No connection
No connection
Ground for LIN
LIN input
VDDL
VSSPC
TEST
VDDC
VDDP
VPP
SBC core supply and MCU RAM supply
Ground for MCU (periphery and core blocks)
Test input
MCU core supply voltage
Supply voltage I/O
OTP programming voltage
Input for battery voltage monitor
VBAT
© 2016 Integrated Device Technology, Inc.
210
January 29, 2016
ZSSC1956 Datasheet
Figure 6.1 PQFN32 Package Drawing of the ZSSC1956
Minimum
Maximum
(mm)
Dimension
(mm)
A
A1
b
0.80
0.00
0.20
0.90
0.05
0.30
e
0.5 nominal
HD
HE
L
4.90
4.90
0.30
5.10
5.10
0.50
© 2016 Integrated Device Technology, Inc.
211
January 29, 2016
ZSSC1956 Datasheet
7
Ordering Information
Product Sales Code
ZSSC1956BA3R
ZSSC1956KIT V1.0
Description
Package
PQFN32 5x5 mm (reel)
ZSSC1956 battery sensing IC – temperature range -40°C to +125°C
ZSSC1956 Evaluation Kit: modular evaluation and development board for ZSSC1956, IC samples, and USB cable,
(software and documentation can be downloaded from the product page at www.IDT.com/ZSSC1956)
8
Related Documents
8.1. IDT Documents
Document
ZSSC1956 Feature Sheet
IDT ARM® Cortex™ M0 User Guide *
ZSSC1956 Evaluation Kit Operation
Manual *
Visit the ZSSC1956 product page (www.IDT.com/ZSSC1956) or contact your nearest sales office for the latest
version of these documents.
* Note: Documents marked with an asterisk (*) require a login account for access on the web.
8.2. Third-Party Related Documents
Document
LIN Specification Package Revision 2.2 (copyright LIN Consortium)
© 2016 Integrated Device Technology, Inc.
212
January 29, 2016
ZSSC1956 Datasheet
9
Glossary
Term
Description
ADC
AHB
BIST
DAP
DHCSR
EBS
ECC
FIFO
FSR
IBS
Analog-to-Digital Converter
Advanced High-performance Bus
Built-in Self-Test
Debug Access Port
Debug Halting Control and Status Register
Earliest Bit Sample
Error Correction Code
First In, First Out
Full Scale Range
Intelligent Battery Sensor IC
Joint Test Action Group
JTAG
LIN
Local Interconnect Network
Latest Bit Sample
LBS
LSB
Least Significant Bit or Byte Depending on Context
Microcontroller Unit
MCU
MPX
MRCS
MSB
NMI
Multiplexer
Multiple Results per Conversion Sequence
Most Significant Bit or Byte Depending on Context
Non-maskable Interrupt
NTC
NVIC
OTP
PA-C
PA-T
PGA
PMU
PID
Negative Temperature Coefficient
Nested Vectored Interrupt Controller
One Time Programmable Memory
Preamplifier for Current
Preamplifer for Temperature
Programmable Gain Amplifier
Power Management Unit
Protected Identifier
POR
PPB
Power-On-Reset
Private Peripheral Bus
© 2016 Integrated Device Technology, Inc.
213
January 29, 2016
ZSSC1956 Datasheet
Term
PTAT
RC
Description
Proportional to Absolute Temperature
Read Clear
RO
Read Only
RW
Readable and Writable
System Basis Chip
SBC
SCI
Serial Communication Interface
Sigma Delta Modulator
System Management Unit
System Packet Interface
Single Result per Conversion Sequence
Universal Asynchronous Receiver/Transmitter
Write 1 to Clear
SDM
SMU
SPI
SRCS
UART
W1C
WO
Write Only
© 2016 Integrated Device Technology, Inc.
214
January 29, 2016
ZSSC1956 Datasheet
10
Document Revision History
Revision
Date
May 18, 2014
August 29, 2014
Description
1.04
2.00
First release.
Ordering info updated from xxAA2R to xxBA3R.
Updated SPI1 Master (SPI1 to SPIB8); section 4.8.
Updated LIN (SW-LIN to AHB-LIN), section 4.7.
Parameter 1.2.3 and 1.2.4 updated/changed.
2.01
December 4, 2014
Renamed SW-LIN CTRL as ahbLIN; removed dotted box around ahbBLIN and
Master SPIB8 in Figure 2.4.
Changed section 4.7 title from “Software Controlled LIN Controller (ahbLIN)” to “LIN
Communication Control Logic (ahbLIN).”
Section SPIB8 was moved forward by one section (now 4.8).
All instances of SW-LIN were replaced by ahbLIN.
Update for contact information.
January 29, 2016
Changed to IDT branding.
Corporate Headquarters
Sales
Tech Support
www.IDT.com/go/support
6024 Silver Creek Valley Road
San Jose, CA 95138
www.IDT.com
1-800-345-7015 or 408-284-8200
Fax: 408-284-2775
www.IDT.com/go/sales
DISCLAIMER Integrated Device Technology, Inc. (IDT) reserves the right to modify the products and/or specifications described herein at any time, without notice, at IDT's sole discretion. Performance
specifications and operating parameters of the described products are determined in an independent state and are not guaranteed to perform the same way when installed in customer products. The
information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT's products for any particular purpose, an
implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property
rights of IDT or any third parties.
IDT's products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be
reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT.
Integrated Device Technology, IDT and the IDT logo are trademarks or registered trademarks of IDT and its subsidiaries in the United States and other countries. Other trademarks used herein are the
property of IDT or their respective third party owners. For datasheet type definitions and a glossary of common terms, visit www.idt.com/go/glossary. All contents of this document are copyright of Integrated
Device Technology, Inc. All rights reserved.
© 2016 Integrated Device Technology, Inc.
215
January 29, 2016
相关型号：
ZSSC1956BA3R
Intelligent Battery Sensor ICWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
IDT
ZSSC3008
Sensor Signal Conditioner with DiagnosticsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
ETC
ZSSC3008AA2R
Sensor Signal Conditioner with DiagnosticsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
ETC
ZSSC3008AA2T
Sensor Signal Conditioner with DiagnosticsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
ETC
ZSSC3015
Sensor Signal Conditioner with DiagnosticsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
IDT
ZSSC3015KIT
Sensor Signal Conditioner with DiagnosticsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
IDT
ZSSC3015NA1B
Sensor Signal Conditioner with DiagnosticsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
IDT
ZSSC3015NA1C
Sensor Signal Conditioner with DiagnosticsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
IDT
ZSSC3015NA2T
Sensor Signal Conditioner with DiagnosticsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
IDT
ZSSC3015NE1B
Sensor Signal Conditioner with DiagnosticsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
IDT
ZSSC3015NE1C
Sensor Signal Conditioner with DiagnosticsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
IDT
ZSSC3015NE1D
Sensor Signal Conditioner with DiagnosticsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
ETC
©2020 ICPDF网 联系我们和版权申明