1ED32XXMC12H [INFINEON]
EiceDRIVER⢠1ED32xxMC12H Two-level slew-rate control (2L-SRC);
| 型号： | 1ED32XXMC12H |
| 厂家： | 
Infineon |
| 描述： | EiceDRIVER⢠1ED32xxMC12H Two-level slew-rate control (2L-SRC) 驱动 |
| 文件： | 总22页 (文件大小：2853K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
™
EiceDRIVER 1ED32xxMC12H Two-level slew-rate
control (2L-SRC)
Single-channel 5.7kV (rms) isolated gate driver IC with 2L-SRC
Feature list
•
•
•
•
•
•
•
•
•
•
•
•
Single channel isolated gate driver
Two-level slew rate control
For use with 600 V/650 V/1200 V/1700 V/2300 V IGBTs, Si and SiC MOSFETs
Up to 18.0 A typical peak output current
40 V absolute maximum output supply voltage
High common-mode transient immunity CMTI > 200 kV/μs
Active output clamping
Active Miller Clamp options available
Galvanically isolated coreless transformer gate driver
3.3 V and 5 V input supply voltage
Suitable for operation at high ambient temperature and in fast switching applications
Certification: VDE 0884-11 with VIORM= 1767 V (peak) (pending) and UL 1577 with VISO = 5.7 kV (rms) for 1 min
Potential applications
•
•
•
•
AC and brushless DC motor drives
High voltage DC/DC converter and DC/AC inverter
UPS systems
Welding
PG-DSO-8-66
Product validation
Qualified for industrial applications according to the relevant tests of JEDEC47/20/22.
Device information
Product type
Typical output current and
configuration
Slew-rate control
Certification
Package
1ED3240MC12H 10 A, standard
1ED3241MC12H 18 A, standard
1ED3250MC12H 10 A, Miller clamp
1ED3251MC12H 18 A, Miller clamp
turn-on and turn-off VDE + UL
turn-on and turn-off VDE + UL
PG-DSO-8-66
PG-DSO-8-66
PG-DSO-8-66
PG-DSO-8-66
turn-on
turn-on
VDE + UL
VDE + UL
Description
The 1ED32xx family is a group of galvanically isolated single-channel driver ICs in a DSO-8 300 mil package. The
driver ICs provide typical peak output currents up to 18 A. The family implements two-level slew rate control
(2L-SRC). This feature allows for controlling two independent gate resistors, which enables the optimization of
both EMI and switching losses.
Datasheet
Please read the Important Notice and Warnings at the end of this document
v2.0
www.infineon.com
2021-04-09
™
EiceDRIVER 1ED32xxMC12H Two-level slew-rate control (2L-SRC)
Single-channel 5.7kV (rms) isolated gate driver IC with 2L-SRC
Description
The family comprises standard output configuration and active Miller clamp output configurations with the
same current rating to protect against parasitic turn-on. The input logic terminals operate safely with supply
voltages of 3.3 V and 5 V. All input structures have threshold levels for support of 3.3 V microcontrollers. The
driver IC family offers suitable output undervoltage lockout (UVLO) levels to operate various kinds of power
transistors. The wide range of the output side supply voltage up to 40 V can be configured arbitrarily for positive
and negative voltages as long as the absolute maximum of 40 V is not exceeded. All driver ICs have output
sections with active shutdown.
VCC2
OUT
OUTF
VEE2
VCC1
/INF
IN
Sel. Speed
PWM
GND1
VCC2
OUT
OUTFC
VEE2
VCC1
/INF
IN
Sel. Speed
PWM
GND1
Figure 1
Typical application for standard pinout (leꢀ) and CLAMP pinout (right)
Datasheet
2
v2.0
2021-04-09
™
EiceDRIVER 1ED32xxMC12H Two-level slew-rate control (2L-SRC)
Single-channel 5.7kV (rms) isolated gate driver IC with 2L-SRC
Table of contents
Table of contents
Feature list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Potential applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Product validation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Device information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Table of contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1
2
3
Block diagram reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Related products to 1ED32xxMC12H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
4
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
IC supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Input terminals IN and /INF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Output terminal OUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Output terminal OUTF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Output terminal OUTFC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Input-to-output control scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.1
4.2
4.3
4.4
4.5
4.6
5
5.1
5.2
5.3
5.3.1
5.3.2
5.3.3
5.3.4
5.3.5
Electrical characteristics and parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Operating parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Eletrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Logic input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Gate driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Active shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
6
Isolation ratings and characteristics (all pending) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Safety limiting values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Certified according to VDE 0884-11 for reinforced insulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Recognized under UL 1577 (File E311313, planned) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.1
6.2
6.3
7
8
Timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Disclaimer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Datasheet
3
v2.0
2021-04-09
™
EiceDRIVER 1ED32xxMC12H Two-level slew-rate control (2L-SRC)
Single-channel 5.7kV (rms) isolated gate driver IC with 2L-SRC
Block diagram reference
1
Block diagram reference
VCC1
/INF
UVLO
UVLO
Logic
VCC2
OUT
Input
Filter
Logic
TX
RX
Input
Filter
IN
OUTF
VEE2
GND1
VCC1
/INF
UVLO
Logic
UVLO
Logic
VCC2
OUT
Input
Filter
TX
RX
Input
Filter
IN
OUTFC
VEE2
GND1
Figure 2
Block diagram for standard variants (top) and for CLAMP variants (bottom)
2
Related products to 1ED32xxMC12H
Note:
Please consider the gate driver IC power dissipation and insulation requirements for the selected
power switch and operating condition.
Product group Product name
Description
Evaluation
boards
EVAL-1ED3241MC12H
Supporting 1ED3241MC12H and IKQ75N120CT2 for double pulse
tests
EVAL-1ED3251MC12H
IKQ75N120CS6
Supporting 1ED3251MC12H and IKQ75N120CT2 for double pulse
tests
TRENCHSTOP™
IGBT Discrete
High Speed 1200 V, 75 A IGBT with anti-parallel diode in TO247-3
Datasheet
4
v2.0
2021-04-09
™
EiceDRIVER 1ED32xxMC12H Two-level slew-rate control (2L-SRC)
Single-channel 5.7kV (rms) isolated gate driver IC with 2L-SRC
Pin configuration
Product group Product name
Description
IKQ75N120CT2
1200 V, 75 A IGBT discrete with anti-parallel diode in TO-247PLUS
package
IKW15N120BH6
IHW40N120R5
High Speed 1200 V, 15 A IGBT with anti-parallel diode in TO247
Reverse conducting 1200 V, 40 A IH IGBT with integrated diode in
TO247
CoolSiC™ SiC
MOSFET Discrete
IMBF170R650M1
IMBG120R045M1H
IMZ120R350M1H
IMZA65R027M1H
IMW65R107M1H
1700 V, 650 mΩ SiC MOSFET in TO263-7 package
1200 V, 45 mΩ SiC MOSFET in TO263-7 package
1200 V, 350 mΩ SiC MOSFET in TO247-4 package
650 V, 27 mΩ SiC MOSFET in TO247-4 package
650 V, 107 mΩ SiC MOSFET in TO247-3 package
EasyPACK™ 1B 1200 V / 45 mΩ sixpack module
EasyDUAL™ 2B 1200 V, 6 mΩ half-bridge module
CoolSiC™ SiC
MOSFET Module
FS45MR12W1M1_B11
FF6MR12W2M1_B11
F3L11MR12W2M1_B74 EasyPACK™ 2B 1200 V, 11 mΩ 3-Level module in Advanced NPC
(ANPC) topology
F4-23MR12W1M1_B11 EasyPACK™ 1B 1200 V, 23 mΩ fourpack module
TRENCHSTOP™
IGBT Modules
F4-200R17N3E4
FS150R17N3E4
FF650R17IE4
EconoPACK™ 3 1700 V, 200 A fourpack IGBT module
EconoPACK™ 3 1700 V, 150 A sixpack IGBT module
PrimePACK™ 3 1700 V, 650 A half-bridge dual IGBT module
PrimePACK™ 3 1700 V, 1000 A half-bridge dual IGBT module
PrimePACK™ 3+ 1700 V, 1200 A dual IGBT module
PrimePACK™ 3+ 1700 V, 1500 A dual IGBT module
PrimePACK™ 3 1700 V, 1500 A dual IGBT module
PrimePACK™ 3+ 1700 V, 1800 A dual IGBT module
FF1000R17IE4
FF1200R17IP5
FF1500R17IP5
FF1500R17IP5R
FF1800R17IP5
FP10R12W1T7_B11
EasyPIM™ 1B 1200 V, 10 A three phase input rectifier PIM IGBT
module
FS100R12W2T7_B11
FP150R12KT4_B11
FS200R12KT4R_B11
EasyPACK™ 2B 1200 V, 100 A sixpack IGBT module
EconoPIM™ 3 1200V three-phase PIM IGBT module
EconoPACK™ 3 1200 V, 200 A sixpack IGBT module
3
Pin configuration
Pin configuration
Table 1
Pin configuration
Pin No. Name
Function
1
2
VCC1
/INF
Positive logic supply
Driver input (active low) for operation OUTF or OUTFC
Datasheet
5
v2.0
2021-04-09
™
EiceDRIVER 1ED32xxMC12H Two-level slew-rate control (2L-SRC)
Single-channel 5.7kV (rms) isolated gate driver IC with 2L-SRC
Pin configuration
Table 1
Pin configuration (continued)
Pin No. Name
Function
3
4
5
6
7
8
IN
PWM driver input (active high)
Logic ground
GND1
VEE2
Power ground
OUTF / OUTFC
OUT
Additional driver output
Regular driver output
VCC2
Positive power supply output side
1
2
3
4
VCC1
/INF
VCC2
OUT
8
7
6
5
IN
OUTF
VEE2
GND1
Figure 3
Pinout standard configuration (top view)
1
2
3
4
VCC1
/INF
VCC2
OUT
8
7
6
5
IN
OUTFC
VEE2
GND1
Figure 4
Pinout clamp configuration (top view)
Pin description
•
VCC1: Logic input supply voltage with wide operating range from 3.3 V up to 15 V. This terminal is referenced
to GND1
•
•
GND1: Ground connection of input circuit. This is the reference point for the input side.
/INF: Inverted control signal for controlling the operation of output OUTF or OUTFC respectively. An internal
filter provides robustness against noise at terminal /INF. An internal weak pull-down resistor favors a low
level. This terminal is referenced to GND1
•
•
IN: Direct control signal for driver output. An internal filter provides robustness against noise at terminal IN.
An internal weak pull-down resistor favors off-state. This terminal is referenced to GND1
VCC2: Positive power supply pin of output driving circuit. A proper blocking capacitor has to be placed close
to this supply pin. This terminal is referenced to VEE2.
Datasheet
6
v2.0
2021-04-09
™
EiceDRIVER 1ED32xxMC12H Two-level slew-rate control (2L-SRC)
Single-channel 5.7kV (rms) isolated gate driver IC with 2L-SRC
Functional description
•
•
VEE2: Reference ground of the output driving circuit. In case of a bipolar supply (positive and negative
voltage referred to IGBT emitter) this pin is connected to the negative supply voltage.
OUT: This driver output terminal follows the signal at terminal IN to turn on or off the external power
transistor. During on-state the driving output is switched to VCC2. This output will be actively pulled down
to VEE2 in case of an UVLO event on either the input side or the output side. The active shutdown keeps the
output voltage at a low level in case that the output side supply voltage collapses.
•
•
OUTF: This output follows terminal OUT according to the signal at terminal /INF.
OUTFC: This output follows terminal OUT according to the signal at terminal /INF for turn-on only.
4
Functional description
The 1ED32xxMC12H are general purpose gate drivers incorporating two-level slew-rate control functionality
(2L-SRC). Based on one additional input control signal /INF, these drivers enable on-the-fly gate resistor
changes.
The integrated galvanic isolation between control input logic and driving output stage grants additional
safety. Its input voltage supply range supports the direct connection of various signal sources like DSPs and
microcontrollers.
4.1
IC supply
The driver can operate over a wide supply-voltage range at both input side and output side. Both sides have
an undervoltage lockout (UVLO) function which suppresses incoming control signals and prevents insufficient
supply or gate voltages. The outputs are pulled down in cases of under-voltage lockout on either side.
The input-side power supply at terminal VCC1 can range from typically 3.3 V up to 15 V. This allows a high safety
margin with respect to voltage spikes on the supply voltage when supplying with 3.3 V or 5 V. A minimum of
VUVLOH1 is required to start-up the input side of the driver IC.
Datasheet
7
v2.0
2021-04-09
™
EiceDRIVER 1ED32xxMC12H Two-level slew-rate control (2L-SRC)
Single-channel 5.7kV (rms) isolated gate driver IC with 2L-SRC
Functional description
IN
/INF
VUVLOH1
VUVLOH1
VUVLOL1
VUVLOL1
VCC1
VCC2
OUT
VOUTFC
OUTF/
OUTFC
t1
t2
t3
t4
IN
/INF
VCC1
VUVLOH2
VUVLOH2
VUVLOL2
VUVLOL2
VCC2
OUT
OUTF/OUTFC
t1
t2 t3
t4
t5 t6
Figure 5
UVLO behavior regarding VVCC1 (top) and VVCC2 (bottom) aꢀer start up
The output side supports negative gate voltage operation, which helps to avoid a parasitic turn-on during
off-state. The negative rail is connected to terminal VEE2 in this case. A minimum voltage of VUVLOH2 at terminal
VCC2 is required for a safe start-up of the IC on the output side. The device is equipped with an undervoltage
lockout for input and output independently to ensure correct switching of power transistors . Operation starts
only, if both VVCC1 and VVCC2 have increased above the respective levels VUVLOH1 and VUVLOH2
.
The input signals at terminals IN and /INF are ignored until VVCC1 reaches the power-up voltage VUVLOH1. Terminal
OUT is activated according to the instantaneous state of terminal IN. Terminal OUTF or OUTFC are activated aꢀer
a UVLO condition for turn-on according to the default state at terminal /INF, which is LOW aꢀer start up. A new
edge at terminal /INF is required to establish the initial user setting aꢀer a UVLO event. A new edge at terminal
IN is required to replace the /INF default setting on the output side. If the power supply voltage VVCC1 of the
input chip drops below VUVLOL1 a turn-off signal is sent to the output chip before power-down. Both outputs OUT
and OUTF shut down according to the last transmitted status at terminals IN and /INF.
The input signals at terminals IN and /INF are ignored until VVCC2 reaches the power-up voltage VUVLOH2
.
Terminal OUT is activated according to the instantaneous state of terminal IN. Terminal OUTF or OUTFC are
activated aꢀer a UVLO condition of VVCC2 for turn-on according to the default state at terminal /INF, which is
LOW aꢀer start up. A new edge at terminal /INF is required to establish the initial user setting aꢀer a UVLO
event. A new edge at terminal IN is required to replace the /INF default setting on the output side. If the power
supply voltage VVCC2 of the output side drops below VUVLOL2, output OUT pulls down independent of the last
transmitted status at terminals IN and /INF. Output OUTF or OUTFC pull down in addition when the their voltage
is below VCLAMPL
.
Datasheet
8
v2.0
2021-04-09
™
EiceDRIVER 1ED32xxMC12H Two-level slew-rate control (2L-SRC)
Single-channel 5.7kV (rms) isolated gate driver IC with 2L-SRC
Functional description
UVLO events on the output side other than a full IC start-up result in a recovery of the output terminals OUTF
and OUTFC according to the input-to-output control scheme.
Note:
The supply voltage VVCC2 and related protection functions is always referred to as VEE2. There is no
differentiation between unipolar or bipolar supply.
A capacitor that is placed in close proximity to the supply terminals VCC1 and GND1 on the input side, and VCC2
and VEE2 on the output side, avoids eventual triggering of under-voltage lockout events.
The IC is safe with any start-up sequence regarding its supply voltages VVCC1 and VVCC2. However, it is good
practice to have the input side supply voltage to start up first, followed by the output side supply.
4.2
Input terminals IN and /INF
The input terminals IN and /INF determine the behavior of the two output terminals OUT and OUTF(C). While
a PWM signal is connected to the IN terminal, thus determining the switching behavior of OUT and OUTF(C),
the /INF terminal controls if only OUT or both OUT and OUTF(C) follow the input terminal IN. Since both output
terminals OUT and OUTF(C) are connected to gate resistors, /INF determines whether a single or both gate
resistors are connected to an IGBT's gate.
Both input terminals contain a pull-down resistor to bias the IC into a safe mode in case the connection to
the system control is interrupted. The non-inverting Schmitt trigger receives the input control signal and has
CMOS-compatible trigger thresholds with minimum VIN,L for LOW level and maximum VIN,H for HIGH level. The
input signal at terminal IN follows a positive logic, while the signal at terminal /INF follows an active-low logic.
There is a short-pulse suppression filter aꢀer the Schmitt trigger with a filter time TINFLT. All pulses that
are below TINFLT,min will be suppressed, and pulses that are longer than TINFLT,max will pass the filter and be
transmitted to the output side. External RC-filters with time constants of more than 10 ns, for example 1 nF and
10 Ω, have to be used to further support the integrated short pulse suppression function to filter input noise.
IN
/INF
TINFLT,min
TINFLT,max
TINFLT,max
TINFLT,max
OUT
OUTF
TP1 > TINFLT,max
TP2 < TINFLT,min
TP3 < TINFLT,min
TP4 > TINFLT,max
OUTFC
Figure 6
Timing of input signals with respect of the input filter
All changes at terminal /INF are acknowledged, if they occur earlier than or simultaneously with a change at
terminal IN. Aꢀer a signal edge is applied at terminal IN, the signal at terminal /INF has to be kept for at least
T/INF,hold for its status to be transmitted to the output side.
4.3
Output terminal OUT
The output terminal OUT changes its status according to the status of the input signal at terminal IN. A high
signal at terminal IN determines a high signal at terminal OUT. A low signal determines a low signal.
The driver IC's output section at terminal OUT provides a rail-to-rail output. This feature allows the tight control
of gate voltage during on-state and short circuit to be maintained as long as the driver’s supply is stable. The
switching behavior of the power transistor is mainly controlled by the gate resistor, due to the low internal
voltage drop of the IC. In turn, the low voltage drop reduces the power to be dissipated by the driver.
The active shutdown feature of terminal OUT ensures a safe off-state of the power transistor in case the output
side is not connected to the power supply or an undervoltage lockout is in effect. The transistor's gate is
clamped at terminal OUT to VEE2.
Datasheet
9
v2.0
2021-04-09
™
EiceDRIVER 1ED32xxMC12H Two-level slew-rate control (2L-SRC)
Single-channel 5.7kV (rms) isolated gate driver IC with 2L-SRC
Functional description
4.4
Output terminal OUTF
Terminal OUTF is the second output of those gate driver ICs, which have the standard output configuration.
OUTF changes its status according to the status of the input signals /INF and IN. It turns the power transistor on
and off in combination with the terminal OUT, so that depending on the status at terminal /INF, a higher gate
current is available, and the switching speed can be modified on the fly. Terminal OUTF is also set to clamping
mode, if it is not activated for active gate operation. The clamping mode is activated when the gate voltage
of the power transistor is below VCLAMPL during off-state or above VVCC2-VCLAMPH during on-state. The clamping
mode during on-state helps to achieve better short circuit clamping. The on-state clamping is activated aꢀer
turn-on, as soon as the filter time of tdCLAMPH is elapsed. A clamping filter time tdCLAMPL for off-state improves the
robustness of the IC's Miller clamp function.
The driver IC's output section at terminal OUTF provides a rail-to-rail output. This feature allows the tight
control of gate voltage during on-state and short circuit to be maintained as long as the driver’s supply is stable.
The switching behavior of the power transistor is mainly controlled by the gate resistor, due to the low internal
voltage drop of the IC. In turn, the low voltage drop reduces the power to be dissipated by the driver.
Terminal OUTF features the active shutdown function. This ensures a safe off-state of the power transistor in
case the output side is not connected to the power supply, or the power supply of the output side collapses
faster than the UVLO can react. The transistor's gate is clamped at terminal OUTF to VEE2.
The driving capability of terminal OUTF is the same as for terminal OUT. OUTF and OUT can be operated in low
resistive connection (i.e. direct paralleling) only if the voltage V/INF at terminal /INF is at the corresponding level
at any time.
4.5
Output terminal OUTFC
Terminal OUTFC is the second output of those gate driver ICs having the Miller clamp function, i.e. the two-level
slew-rate control in for turn-on only. OUTFC changes its status according to the status of the input signal /INF
and IN. It turns on the power transistor in combination with terminal OUT, so that depending on the status at
terminal /INF, a higher gate current is available and the switching speed can be modified for each PWM edge.
Terminal OUTFC is not activated during the turn-off transient.
Terminal OUTFC is set to clamping mode also if it is not activated for active gate turn-on or turn-off . The
clamping mode is activated when the gate voltage of the power transistor is below VCLAMPL during off-state or
above VVCC2-VCLAMPH during on-state. The clamping mode during on-state helps to achieve better short circuit
clamping. The on-state clamping is activated aꢀer turn-on, as soon as the filter time of tdCLAMPH is elapsed. A
clamping filter time tdCLAMPL for off-state improves the robustness of the IC's Miller clamp function.
The clamping capability of the output OUTFC during off-state of the power transistor is identical to turn-off
current capability terminal OUT.
The driver IC's output section at terminal OUTFC provides a rail-to-rail output. This feature allows the tight
control of gate voltage during on-state and short circuit to be maintained as long as the driver’s supply is stable.
The switching behavior of the power transistor is mainly controlled by the gate resistor, due to the low internal
voltage drop of the IC. In turn, the low voltage drop reduces the power to be dissipated by the driver.
Terminal OUTFC features the active shutdown function. This ensures a safe off-state of the power transistor in
case the output side is not connected to the power supply, or the power supply of the output side collapses
faster than the UVLO can react. The transistor's gate is clamped at terminal OUTFC to VEE2.
The driving capability of terminal OUTFC is the same as for terminal OUT. OUTFC and OUT can be operated in
low resistive connection (i.e. direct paralleling) only if the voltage V/INF at terminal /INF is at the corresponding
level at any time.
Datasheet
10
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™
EiceDRIVER 1ED32xxMC12H Two-level slew-rate control (2L-SRC)
Single-channel 5.7kV (rms) isolated gate driver IC with 2L-SRC
Functional description
4.6
Input-to-output control scheme
The two-level slew rate control IC family can activate the additional output OUTF or OUTFC depending on the
input signals at the terminals IN and /INF. The relationship between input signals and output signals is defined
in the table below.
Table 2
State
Input-to-output control scheme
IN
/INF
OUT
OUTF
OUTFC
(1ED3240MC12H,
1ED3241MC12H)
(1ED3250MC12H,
1ED3251MC12H)
1
0
0
0
0*
0*
2
0 → 1
0
0 → 1
0 → 1
0*
0 → 1
0*
3
0
0 → 1
0
4
1
0
1
1*
1*
5
1 → 0
0
1 → 0
1 → HiZ
1*
1 → HiZ
1*
6
1
0 → 1
1
7
0
1
0
0*
0*
8
0
1 → 0
0
0*
0*
9
0 → 1
1
0 → 1
0 → HiZ
1*
0 → HiZ
1*
10
1
1
1
11
1
1 → 0
1
1*
1*
12
1 → 0
1
X
X
1 → 0
1 → 0
last /INF
HiZ
1 → HiZ
last /INF
HiZ
Input UVLO↓
Output UVLO↓
X
X
0
0
*) Output is activated when the voltage at terminal OUTF or OUTFC is higher thanVVCC2 - VCLAMPH during on-state,
or lower than VCLAMPL during off-state.
The control scheme of the gate driver IC family inherently avoids the activation of the two outputs OUT or
OUTF / OUTFC in active opposite status. Both outputs OUTF and OUTFC can have the states 1, 0 and high
impedance (HiZ) according to the table above. The status of terminal /INF can be changed pulse-by-pulse with a
short delay with respect to a potential change of status at terminal IN according to the timing diagrams below.
Datasheet
11
v2.0
2021-04-09
™
EiceDRIVER 1ED32xxMC12H Two-level slew-rate control (2L-SRC)
Single-channel 5.7kV (rms) isolated gate driver IC with 2L-SRC
Electrical characteristics and parameters
IN
/INF
OUT
VclampH
VclampH
tdclampL tdclampH
VclampH
tdclampH
OUTF
VclampL
tdclampH
tdclampL
OUTF
status
Hi
Z
Hi
Z
Hi
Z
Hi
Z
Hi
Z
OFF
Clamp-ON
OFF
ON
Clamp-OFF
Clamp-ON
Clamp-OFF
Clamp-ON
OFF
IN
/INF
OUT
VclampH
VclampH
VclampH
VclampL
OUTFC
tdclampH
tdclampL
tdclampL
tdclampH
tdclampL tdclampH
tdclampL
OUTFC
status
Hi
Z
Hi
Z
Hi
Hi
Z
Hi
Z
Hi
Z
Hi
OFF
Clamp-ON
Clamp-OFF
ON
Clamp-OFF
Clamp-ON
Clamp-OFF
Clamp-ON
Clamp-OFF
Z
Z
Figure 7
Timing diagram of input and output signals for standard version (top) and clamp
version (bottom)
5
Electrical characteristics and parameters
5.1
Absolute maximum ratings
Absolute maximum ratings are defined as ratings, that can lead to the destruction of the integrated circuit, if
exceeded. Unless otherwise noted all parameters refer to terminal GND1.
Table 3
Absolute maximum ratings
Parameter
Symbol
Values
Max.
2300
Unit Note or test
condition
Min.
Input to output offset voltage
VOFFSET
V
VVEE2,max-VVEE2,min
with VVEE2,max ≥ VGND1
1)2)
≥ VVEE2,min
Power supply input side
VVCC1
-0.3
15
V
1
For functional isolation only
See also: Insulation characteristics
2
Datasheet
12
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™
EiceDRIVER 1ED32xxMC12H Two-level slew-rate control (2L-SRC)
Single-channel 5.7kV (rms) isolated gate driver IC with 2L-SRC
Electrical characteristics and parameters
Table 3
Absolute maximum ratings (continued)
Symbol
Parameter
Values
Unit Note or test
condition
Min.
VVCC1,dyn -0.3
Max.
Power supply input side
17
15
17
40
V
V
V
V
t < 1 µs3)
Logic input voltages (IN, /INF)
Dynamic logic input voltages (IN, /INF)
Power supply output side
VIN
-0.3
VIN,dyn
VVCC2
-0.3
-0.3
t < 1 µs3)
with respect to VEE2
with respect to VEE2
Gate driver output (OUT, OUTF, OUTFC)
Junction temperature
VOUT
VVEE2 - 0.3 VVCC2 +0.3 V
TJ
-40
150
150
100
625
104
104
4
°C
Storage temperature
Tstg
-55
°C
Power dissipation (input side)
Power dissipation (output side)
Thermal resistance (input side)
Thermal resistance (output side)
ESD capability
PD,IN
-
-
-
-
-
-
mW
mW
K/W
K/W
kV
TA = 85 °C, 1s0p 4)
TA = 85 °C, 1s0p 5)
TA = 85 °C, 1s0p
PD,OUT
RTHJA,IN
RTHJA,OUT
VESD,HBM
ESD,CDM
TA = 85 °C, 1s0p
6)
7)
TC 1000
Figure 8
Reference layout for thermal data (1s0p, 2 x 50 mm² cooling area, Copper thickness 35
μm)
This PCB layout represents the reference layout used for the thermal characterization of the 300 mil package.
5.2
Operating parameters
The IC operates as described in the functional description within the operating parameters. Unless otherwise
noted all parameters refer to GND1.
Table 4
Operating parameters
Parameter
Symbol
Values
Unit Note or test
condition
Min.
Max.
Power supply output side
Power supply input side
VVCC2
VVCC1
10
3
35
15
V
V
3
Parameter is not subject of production test - verified by design/ characterization
IC output-side power dissipation is derated linearly with 9.62 mW/°C above 139,6 °C
IC output-side power dissipation is derated linearly with 9.62 mW/°C above 85 °C
According to ANSI/ESDA/JEDEC-JS-001-2017
4
5
6
7
According to ANSI/ESDA/JEDEC-JS-002-2014, TC = test condition in Volt
Datasheet
13
v2.0
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™
EiceDRIVER 1ED32xxMC12H Two-level slew-rate control (2L-SRC)
Single-channel 5.7kV (rms) isolated gate driver IC with 2L-SRC
Electrical characteristics and parameters
Table 4
Operating parameters (continued)
Symbol
Parameter
Values
Max.
Unit Note or test
condition
Min.
-0.3
Logic input voltages (IN, /INF)
Ambient temperature
VIN
5.5
125
6.8
200
V
TA
-40
°C
Thermal coefficient, junction-top
Common mode transient immunity (CMTI)
ΨTH,JT
|CMTI|
-
-
K/W
TA = tbd °C
kV/µs VOFFSET,test = 1500 V
5.3
Eletrical characteristics
The electrical characteristics include the spread of values in supply voltages, load and junction temperatures
given below. Typical values represent the median values at VVCC1 = 5 V, VVCC2 = 15 V, and TA = 25°C. Unless
otherwise noted all voltages are given with respect to their respective reference GND1 or VEE2.
5.3.1
Power supply
Table 5
Power supply
Parameter
Symbol
Values
Typ.
Unit Note or test
condition
Min.
Max.
3.1
UVLO threshold input side (on)
UVLO threshold input side (off)
UVLO hysteresis input side
VUVLOH1
VUVLOL1
VHYS1
-
2.85
V
2.5
2.65
0.2
11.8
10.8
-
-
V
0.1
-
V
UVLO threshold output side (on) VUVLOH2
UVLO threshold output side (off) VUVLOL2
-
12.5
-
V
10.4
V
UVLO hysteresis output side
Quiescent current input side
Quiescent current output side
Start up time8)
VHYS2
IQ1
0.8
-
V
-
-
-
1.2
1.9
7.4
1.4
2.3
20
mA
mA
µs
IQ2
tSTART
5.3.2
Logic input
Table 6
Logic input
Parameter
Symbol
Values
Typ.
1.2
Unit Note or test
condition
Min.
Max.
IN, /INF low-input threshold
voltage
VIN,L
VIN,H
1
-
-
V
V
V
IN, /INF high-input threshold
voltage
2.1
2.3
IN, /INF low/high hysteresis
IN, /INF input current
VIN,HYS
IIN
0.7
-
-
-
100
µA
VIN = VVCC1
8
Parameter is not subject of production test - verified by design/ characterization
Datasheet
14
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™
EiceDRIVER 1ED32xxMC12H Two-level slew-rate control (2L-SRC)
Single-channel 5.7kV (rms) isolated gate driver IC with 2L-SRC
Electrical characteristics and parameters
Table 6
Logic input (continued)
Symbol
Parameter
Values
Typ.
Unit Note or test
condition
Min.
Max.
IN, /INF pull-down resistor
/INF hold time9)
RIN,PD
-
75
-
-
kΩ
ns
t/INF,hold
50
-
5.3.3
Gate driver
Table 7
Gate driver
Parameter
Symbol
Values
Typ.
Unit
Note or test
condition
Min.
Max.
High-level output peak
current (OUT, OUTF, OUTFC,
1ED32x0MC12H)10)
IOH
-
5
-
A
Output on
Low-level output peak current
IOL
-
-
5
-
A
Output off
(OUT, OUTF, 1ED3240MC12H)10)
High-level output resistance
(OUT, OUTF, OUTFC,
1ED32x0MC12H)
ROH,1
0.92
0.73
9
1.47
1.1
-
Ω
Output on, IOH = 0.1
A
Low-level output resistance
(OUT, OUTF, OUTFC,
1ED32x0MC12H)
ROL,1
-
-
Ω
A
Output off, IOL = 0.1 A
Output on
High-level output peak
current (OUT, OUTF, OUTFC,
1ED32x1MC12H)10)
IOH
Low-level output peak current
IOL
-
-
9
-
A
Output off
(OUT, OUTF, 1ED3241MC12H)10)
High-level output resistance
(OUT, OUTF, OUTFC,
1ED32x1MC12H)
ROH,2
0.51
0.81
Ω
Output on, IOH = 0.1
A
Low-level output resistance
(OUT, OUTF, OUTFC,
1ED32x1MC12H)
ROL,2
-
0.42
0.63
Ω
Output off, IOL = 0.1 A
High-level output voltage (OUT, ΔVOH
OUTF, OUTFC)
-
-
-
-
-
0.1
0.1
-
V
V
A
V
Output on, VVCC2
VOH; IOH = 20 mA
-
Low-level output voltage (OUT, ΔVOL
OUTF, OUTFC)
-
Output off, VVCC2
VOH; IOH = 20 mA
-
Low-level clamp peak current
ICLAMPL
2.1
-
VOL = 2 V
(OUTF, OUTFC) 10)
Short-circuit clamp voltage
between OUT / OUTF / OUTFC
and VCC210)
VCLP
1.3
Output on, IOH
=
500 mA, t < 10 µs
9
Parameter is not subject of production test - verified by design/ characterization
Parameter is not subject of production test - verified by design/ characterization
10
Datasheet
15
v2.0
2021-04-09
™
EiceDRIVER 1ED32xxMC12H Two-level slew-rate control (2L-SRC)
Single-channel 5.7kV (rms) isolated gate driver IC with 2L-SRC
Electrical characteristics and parameters
Table 7
Gate driver (continued)
Symbol
Parameter
Values
Typ.
Unit
Note or test
condition
Min.
Max.
Active Miller clamp threshold
VCLAMPL
-
2
1
-
2.5
V
VOL-VVEE2, V/INF = 0
VVCC2-VOH, V/INF = 1
voltage OFF (OUTF, OUTFC)
Clamping ON threshold voltage VCLAMPH
(OUTF, OUTFC)
0.5
-
V
Active Miller clamp delay time
tdCLAMPL
-
-
80
-
ns
ns
VOL ≤ VVEE2+VCLAMPL
V/INF = 1
,
(OUTF, OUTFC)10)
Clamping ON delay time (IGBT
tdCLAMPH
890
VOH ≥ VVCC2-VCLAMPH
V/INF = 1
,
variants, OUTF, OUTFC)10)
5.3.4
Dynamic characteristics
The load capacitance is 100 pF if not otherwise noted.
Table 8
Dynamic characteristics
Symbol
Parameter
Values
Typ.
Unit Note or test
condition
Min.
Max.
Input-to-output propagation
delay ON
tPDON
tPDOFF
tPDISTO
tINFLT
-
-
-
110
110
5
ns
ns
ns
IN turn-on threshold
to 10% output on
Input-to-output propagation
delay OFF
-
IN turn-off threshold
to 90% output off
Input-to-output propagation
delay distortion (tPDOFF - tPDON
-10
0
)
Input-pulse suppression time
30
-
-
40
-
ns
ns
Input-to-output propagation
delay mismatch OUT vs. OUTF/
OUTFC11)
tPDOUT-
OUTF
<1
Input-to-output, part to part
propagation delay variation
tPD,P2P
tPD,T
-
-
-
15
12
ns
ns
Input-to-output propagation
delay variation due to
temperature
-5
Rise time
Fall time
Rise time
Fall time
tRISE
tFALL
tRISE
tFALL
-
-
-
-
1.6
1.5
9
15
15
30
30
ns
ns
ns
ns
CLOAD = 100 pF
CLOAD = 100 pF
CLOAD = 1 nF
CLOAD = 1 nF
8.5
10
Parameter is not subject of production test - verified by design/ characterization
Parameter is not subject of production test - verified by design/ characterization
11
Datasheet
16
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™
EiceDRIVER 1ED32xxMC12H Two-level slew-rate control (2L-SRC)
Single-channel 5.7kV (rms) isolated gate driver IC with 2L-SRC
Isolation ratings and characteristics (all pending)
5.3.5
Active shutdown
Table 9
Active shutdown
Symbol
Parameter
Values
Typ.
Unit Note or test
condition
Min.
Max.
2.0
Active shutdown voltage
VACTSD,L
-
1.5
V
IO = 10 mA; VVCC2
open
6
Isolation ratings and characteristics (all pending)
6.1
Safety limiting values
This coupler is suitable for rated insulation only within the given safety ratings. Compliance with the safety
ratings shall be ensured by means of suitable protective circuits.
Table 10
Safety limiting values
Description
Symbol
TS
Characteristic
Unit
°C
Maximum ambient safety temperature
150
Maximum input-side power dissipation at TA = 25°C12)
Maximum output-side power dissipationat TA = 25°C13)
PSI
100
mW
mW
PSO
1100
6.2
Certified according to VDE 0884-11 for reinforced insulation
This coupler is suitable for safe electrical insulation only within the safety ratings. Compliance with the safety
ratings shall be ensured by means of suitable protective circuits.
Table 11
Reinforced insulation ratings according to VDE 0884-11
Description
Symbol
Characteristic
Unit
Installation classification per EN 60664-1, Table 1
for rated mains voltage ≤ 150 V (rms)
for rated mains voltage ≤ 300 V (rms)
for rated mains voltage ≤ 600 V (rms)
for rated mains voltage ≤1000 V (rms)
–
I-IV
I-IV
I-III
I-II
Climatic classification
40/125/21
–
Pollution degree (EN 60664-1)
Minimum external clearance
Minimum external creepage
Minimum comparative tracking index
2
–
CLR
CPG
CTI
>8
>8
400
mm
mm
–
12
IC input-side power dissipation is derated linearly at 9.62 mW/°C above 139.6 °C
IC output-side power dissipation is derated linearly at 7.35 mW/°C above 25 °C
13
Datasheet
17
v2.0
2021-04-09
™
EiceDRIVER 1ED32xxMC12H Two-level slew-rate control (2L-SRC)
Single-channel 5.7kV (rms) isolated gate driver IC with 2L-SRC
Timing diagrams
Table 11
Reinforced insulation ratings according to VDE 0884-11 (continued)
Description
Symbol
VIORM
Characteristic
1767
Unit
Maximum repetitive insulation voltage
Highest allowable overvoltage
V (peak)
V (peak)
V (peak)
VIOTM
8000
Maximum surge insulation voltage
VIOSM
6875
Surge insulation test voltage VTEST = VIOSM × 1.6
Apparent charge, method a
Vpd(ini),a = VIOTM, Vpd(m) = 1.6 × VIORM, tini = 1 min
qc
qc
<5
<5
pC
pC
Apparent charge, method b
Vpd(ini),b = 1.2 × VIOTM, Vpd(m) = 1.875 × VIORM, tini,b = 1 s
Insulation resistance at TA, max
Insulation resistance at TS
Insulation capacitance
RIO
RIO
CIO
> 1011
> 109
1.66
Ω
Ω
pF
6.3
Recognized under UL 1577 (File E311313, planned)
Table 12
Recognized under UL 1577
Description
Symbol
VISO
Characteristic
5700
Unit
Insulation withstand voltage/1 min
Insulation test voltage/1 s
V (rms)
V (rms)
VISO, TEST
6840
7
Timing diagrams
/INF-level for active operation of
/INF
IN
OUTF or OUTFC
50%
50%
tPDON
tPDOFF
OUT
OUTF
50%
50%
OUTFC
Figure 9
Propagation delay
Datasheet
18
v2.0
2021-04-09
™
EiceDRIVER 1ED32xxMC12H Two-level slew-rate control (2L-SRC)
Single-channel 5.7kV (rms) isolated gate driver IC with 2L-SRC
Timing diagrams
/INF-level for active operation of
/INF
OUTF or OUTFC
IN
50%
50%
OUT
50%
tPDOUT-OUTF
50%
50%
50%
OUTF
OUTFC
Figure 10
OUT - OUTF/OUTFC propagation delay mismatch
/INF
/INF-level for active operation of
OUTF or OUTFC
IN
80%
80%
OUT
Tf
Tr
OUTF
20%
20%
80%
Tr
OUTFC
20%
Figure 11
Rise and fall time
Datasheet
19
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2021-04-09
™
EiceDRIVER 1ED32xxMC12H Two-level slew-rate control (2L-SRC)
Single-channel 5.7kV (rms) isolated gate driver IC with 2L-SRC
Timing diagrams
IN
/INF
tH < t/INF,hold
tL > t/INF,hold tH > t/INF,hold
tL < t/INF,hold
OUT
VclampH
OUTF
VclampL
VclampH
OUTFC
VclampL
t1
t3
t4
t2
Figure 12
/INF hold time
Datasheet
20
v2.0
2021-04-09
™
EiceDRIVER 1ED32xxMC12H Two-level slew-rate control (2L-SRC)
Single-channel 5.7kV (rms) isolated gate driver IC with 2L-SRC
Package dimensions
8
Package dimensions
1)
1)
6.4
7.5
0.81±0.4
Seating plane
Coplanarity
10.3
2)
1.27
0.4±0.08
8
5
Pin1 Marking
1
4
1) Does not include plastic or metal protrusion of 0.15 max. per side
2) Dambar protrusion shall be maximum 0.1mm total in excess of lead width
All dimensions are in units mm
The drawing is in compliance with ISO 128-30, Projection Method 1 [
]
Figure 13
PG-DSO-8-66 (Plastic (green) dual small outline package)
Revision history
Document
version
Date of
release
Description of changes
2.0
9.4.2021
initial release
•
Datasheet
21
v2.0
2021-04-09
Trademarks
All referenced product or service names and trademarks are the property of their respective owners.
Edition 2021-04-09
Published by
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