1ED3431MU12MXUMA1 [INFINEON]
EiceDRIVER⢠1ED34x1Mc12M Enhanced;
| 型号： | 1ED3431MU12MXUMA1 |
| 厂家： | 
Infineon |
| 描述： | EiceDRIVER⢠1ED34x1Mc12M Enhanced 驱动 |
| 文件： | 总45页 (文件大小：814K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
1ED34x1Mc12M (1ED-X3 Analog)
EiceDRIVER™ 1ED34x1Mc12M Enhanced
Datasheet
Single-channel 5.7 kV (rms) isolated gate driver IC with adjustable DESAT and
soꢀ-off
Features
•
•
•
•
•
•
650 V, 1200 V, 1700 V, 2300 V IGBTs, SiC, and Si MOSFETs
40 V absolute maximum output supply voltage
±3 A, ±6 A, and ±9 A typical sinking and sourcing peak output current
Separate source and sink outputs for hard switching and with active Miller clamp/clamp driver
Adjustment pins for parameter configuration from input side
Precise VCEsat detection (DESAT) with fault output and adjustable filter time and leading edge blanking time
with resistor at ADJB pin
•
•
•
•
•
•
•
Adjustable IGBT soꢀ turn-off aꢀer desaturation detection with resistor at ADJA pin
Operation at high ambient temperature up to 125 °C with over-temperature shut down at 160 °C (±10 °C)
Tight IC-to-IC propagation delay matching (tPDD,max = 30 ns)
Undervoltage lockout protection with hysteresis for input and output side with active shut-down
High common-mode transient immunity CMTI = 200 kV/µs
Small space-saving DSO-16 fine-pitch package with large creepage distance (>8 mm)
Safety certification
-
-
UL 1577 recognized (File E311313) with VISO,test = 6840 V (rms) for 1 s, VISO = 5700 V (rms) for 60 s
IEC 60747-17/VDE 0884-11 approval (pending) with VIORM = 1767 V (peak, reinforced)
•
Evaluation board available EVAL-1ED3491MX12M
Potential applications
•
•
•
•
•
•
•
•
Industrial motor drives - compact, standard, premium, servo drives
Solar inverters
UPS systems
Welding
Commercial and agricultural vehicles (CAV)
Commercial air-conditioning (CAC)
High-voltage isolated DC-DC converters
Isolated switch mode power supplies (SMPS)
PG-DSO-16
Product validation
Qualified for industrial applications according to the relevant tests of JEDEC47/20/22.
Datasheet
Please read the Important Notice and Warnings at the end of this document
v2.1
www.infineon.com/gdisolated
2021-02-15
EiceDRIVER™ 1ED34x1Mc12M Enhanced
Datasheet
Device information
Device information
Product type
Output current CLAMP type1) Isolation class Marking
OPN
1ED3431MC12M
1ED3461MC12M
1ED3491MC12M
1ED3431MU12M
1ED3461MU12M
1ED3491MU12M
3 A (typ)
6 A (typ)
9 A (typ)
3 A (typ)
6 A (typ)
9 A (typ)
CLAMP
reinforced
reinforced
reinforced
UL 1577
3431MC12 1ED3431MC12MXUMA1
3461MC12 1ED3461MC12MXUMA1
3491MC12 1ED3491MC12MXUMA1
3431MU12 1ED3431MU12MXUMA1
3461MU12 1ED3461MU12MXUMA1
3491MU12 1ED3491MU12MXUMA1
CLAMPDRV
CLAMPDRV
CLAMP
CLAMPDRV
CLAMPDRV
UL 1577
UL 1577
1) Please refer to Chapter 4.5.4.1 for circuit connection to avoid damage to the gate driver IC
Description
The 1ED34x1Mc12M family (X3 Analog) consists of galvanically isolated single channel gate driver ICs in a small
PG-DSO-16 package with a large creepage and clearance of 8 mm. The gate driver ICs provide a typical peak
output current of 3 A, 6 A, and 9 A.
Adjustable control and protection functions are included to simplify the design of highly reliable systems. All
parameter adjustments are done from the input side, including adjustable DESAT filter time, leading edge
blanking time, and soꢀ-off current level with only two resistors..
All logic I/O pins are supply voltage dependent 3.3 V or 5 V CMOS compatible and can be directly connected to a
microcontroller.
The data transfer across the galvanic isolation is realized by the integrated coreless transformer technology.
VCC1
VCC2H
IN,H
DESAT,H
RDYC, FLT_N
EiceDRIVERTM
DESAT SoftOff
ON,H
ADJ,H
OFF.H
CLAMP,H
GND2,H
CPU
GND1
VCC1
VEE2,H
VCC2,L
IN,L
DESAT,L
RDYC, FLT_N
EiceDRIVERTM
DESAT SoftOff
ON,L
ADJ,L
OFF,L
CLAMP,L
GND2,L
GND1
VEE2,L
Figure 1
Typical application
Datasheet
2
v2.1
2021-02-15
EiceDRIVER™ 1ED34x1Mc12M Enhanced
Datasheet
Table of contents
Table of contents
Table of contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1
2
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Related products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3
3.1
3.2
Pin configuration and functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Pin functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
4
4.1
4.2
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Start-up and fault clearing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Input side undervoltage lockout, VCC1 UVLO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Output side under-voltage lockout, VCC2 UVLO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Input side logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
IN non-inverting driver input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
RDYC ready status output, fault-off and fault clear input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
RDYC fault-off input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
RDYC fault clear input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
FLT_N status output and fault-off input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
FLT_N fault-off input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Desaturation protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
DESAT behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
DESAT filter and leading edge blanking time adjustment with ADJB . . . . . . . . . . . . . . . . . . . . . . . . 19
Gate driver output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Turn-on behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Turn-off and fault turn-off behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Hard switching turn-off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Soꢀ turn-off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Soꢀ-off current source adjustment with ADJA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Active shut-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Active Miller clamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
CLAMP output types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Switch-off timeout until forced switch-off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Short circuit clamping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4.2.1
4.2.2
4.3
4.3.1
4.3.2
4.3.2.1
4.3.2.2
4.3.3
4.3.3.1
4.4
4.4.1
4.4.2
4.5
4.5.1
4.5.2
4.5.2.1
4.5.2.2
4.5.2.2.1
4.5.3
4.5.4
4.5.4.1
4.5.5
4.6
5
Electrical parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Thermal parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Operating parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Voltage supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
5.1
5.2
5.3
5.4
5.4.1
Datasheet
3
v2.1
2021-02-15
EiceDRIVER™ 1ED34x1Mc12M Enhanced
Datasheet
Table of contents
5.4.2
5.4.3
5.4.4
5.4.5
5.4.6
5.4.7
5.4.8
5.4.9
Logic input and output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Analog input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Gate driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Active Miller clamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Desaturation protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Soꢀ-off current source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Over-temperature protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
6
6.1
6.2
Insulation characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Certified according to VDE 0884-11 reinforced insulation (pending) . . . . . . . . . . . . . . . . . . . . . . . . . .41
Recognized under UL 1577 (File E311313) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
7
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
8
8.1
8.2
Application notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
Reference layout for thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
Printed circuit board guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Disclaimer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Datasheet
4
v2.1
2021-02-15
EiceDRIVER™ 1ED34x1Mc12M Enhanced
Datasheet
1 Block diagram
1
Block diagram
VCC1
VCC2
2
7
UVLO1
UVLO2
14
10
opt.
CLAMP
CLAMPDRV
CLAMP control
and detection
IN
PWM logic TX
RX
VEE2
VCC2
1
1
FLT_N
6
5
ON
Output control
with hard-
12
11
switching and
SoftOff
OFF
RDYC
VEE2
VCC2
1
LOGIC
TRX
TRX
LOGIC
ADJB
ADJA
4
3
DESAT
GND2
13
15
DESAT control
and detection
2
VEE2
1
1
8
9
16
GND1
GND1
VEE2
VEE2
Figure 2
Block diagram
Datasheet
5
v2.1
2021-02-15
EiceDRIVER™ 1ED34x1Mc12M Enhanced
Datasheet
2 Related products
2
Related products
Note:
Please consider the gate driver IC power dissipation and insulation requirements for the selected
power switch and operating condition.
Product group Product name
Description
TRENCHSTOP™
IGBT Discrete
IKQ75N120CS6
IKW15N120BH6
IHW40N120R5
High Speed 1200 V, 75 A IGBT with anti-parallel diode in TO247-3
High Speed 1200 V, 15 A IGBT with anti-parallel diode in TO247
Reverse conducting 1200 V, 40 A IH IGBT with integrated diode in
TO247
CoolSiC™ SiC
IMBF170R650M1
IMW120R045M1
1700 V, 650 mΩ SiC MOSFET in TO263-7 package
1200 V, 45 mΩ SiC MOSFET in TO247-3 package
1200 V, 350 mΩ SiC MOSFET in TO247-4 package
650 V, 27 mΩ SiC MOSFET in TO247-4 package
650 V, 107 mΩ SiC MOSFET in TO247-3 package
EasyPACK™ 1B 1200 V / 45 mΩ sixpack module
EasyDUAL™ 2B 1200 V, 6 mΩ half-bridge module
MOSFET Discrete
IMZ120R350M1H
IMZA65R027M1H
IMW65R107M1H
FS45MR12W1M1_B11
FF6MR12W2M1_B11
CoolSiC™ SiC
MOSFET Module
F3L11MR12W2M1_B74 EasyPACK™ 2B 1200 V, 11 mΩ 3-Level module in Advanced NPC
(ANPC) topology
F4-23MR12W1M1_B11 EasyPACK™ 1B 1200 V, 23 mΩ fourpack module
TRENCHSTOP™
IGBT Modules
F4-200R17N3E4
FS150R17N3E4
FF650R17IE4
EconoPACK™ 3 1700 V, 200 A fourpack IGBT module
EconoPACK™ 3 1700 V, 150 A sixpack IGBT module
PrimePACK™ 3 1700 V, 650 A half-bridge dual IGBT module
PrimePACK™ 3 1700 V, 1000 A half-bridge dual IGBT module
PrimePACK™ 3+ 1700 V, 1200 A dual IGBT module
PrimePACK™ 3+ 1700 V, 1500 A dual IGBT module
PrimePACK™ 3 1700 V, 1500 A dual IGBT module
PrimePACK™ 3+ 1700 V, 1800 A dual IGBT module
FF1000R17IE4
FF1200R17IP5
FF1500R17IP5
FF1500R17IP5R
FF1800R17IP5
FP10R12W1T7_B11
EasyPIM™ 1B 1200 V, 10 A three phase input rectifier PIM IGBT
module
FS100R12W2T7_B11
FP150R12KT4_B11
FS200R12KT4R_B11
EasyPACK™ 2B 1200 V, 100 A sixpack IGBT module
EconoPIM™ 3 1200V three-phase PIM IGBT module
EconoPACK™ 3 1200 V, 200 A sixpack IGBT module
Datasheet
6
v2.1
2021-02-15
EiceDRIVER™ 1ED34x1Mc12M Enhanced
Datasheet
3 Pin configuration and functionality
3
Pin configuration and functionality
The pin assignment at the gate driver IC generally differentiates between the input side and the output side.
Table 1
General pin assignment
Designation
Pins
1 to 8
9 to 16
input side, input logic signal side, or low voltage side
output side, driver power side, or high voltage side
For simplicity reasons the driver is described as an IGBT driver. For use with MOSFETs and other power switches
simply replace any mentioning of collector and emitter with their corresponding pin names.
3.1
Pin configuration
Table 2
Pin configuration table abbreviations
Description
Abbreviation
Pin type
PWR
I/O
Power supply and gate current output pins
Digital input and output pin
Digital input pin
I
GND
AI
Ground reference pin
Analog input pin
Buffer type
OD
Open drain output
CMOS
PP
CMOS compatible input threshold levels
Push/pull output buffer
special
Pull device
PD
Special output/input function, see individual description
Pull-down resistor
Current source
CS
Table 3
Pin configuration
Pin Pin name Pin type Buffer type Pull
Function
no.
device
1
GND1
VCC1
ADJA
ADJB
RDYC
GND
PWR
AI
–
–
Ground input side
2
–
–
Positive power supply input side
Parameter adjust set A
Parameter adjust set B
3
special
special
OD, CMOS
CS
CS
–
4
AI
5
I/O
Combined ready output, high active and fault clear
input and soꢀ-off input, low active
6
7
FLT_N
IN
I/O
I
OD, CMOS
CMOS
–
Fault output, low active and soꢀ- off input, low active
PD, 40 kΩ Non inverted driver input
Datasheet
7
v2.1
2021-02-15
EiceDRIVER™ 1ED34x1Mc12M Enhanced
Datasheet
3 Pin configuration and functionality
Table 3
Pin configuration (continued)
Pin Pin name Pin type Buffer type Pull
Function
no.
device
8
GND1
VEE2
GND
GND
PWR
–
–
–
–
Ground input side
9
–
Negative power supply output side
10
CLAMP
OD
Active Miller clamping, open drain to VEE2
(1ED3431M only)
10
CLAMPDRV PWR
PP
–
Active miller clamping, clamp driver for external
MOSFET (1ED3461M, 1ED3491M)
11
12
13
14
15
16
OFF
PWR, AI
OD
–
–
Driver sink output
ON
PWR, AI
AI
OD
Driver source output
DESAT
VCC2
GND2
VEE2
special
CS, 500 µA Enhanced desaturation protection
PWR
AI
–
–
–
–
–
–
Positive power supply output side
Signal ground output side
GND
Negative power supply output side
GND1
VCC1
ADJA
ADJB
RDYC
FLT_N
IN
VEE2
GND2
VCC2
DESAT
ON
1
16
15
14
13
12
11
10
9
2
3
4
5
6
7
8
OFF
CLAMP
VEE2
GND1
Figure 3
PG-DSO-16 (top view) with CLAMP
GND1
VCC1
ADJA
ADJB
RDYC
FLT_N
IN
VEE2
GND2
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VCC2
DESAT
ON
OFF
CLAMPDRV
VEE2
GND1
Figure 4
PG-DSO-16 (top view) with CLAMPDRV
Datasheet
8
v2.1
2021-02-15
EiceDRIVER™ 1ED34x1Mc12M Enhanced
Datasheet
3 Pin configuration and functionality
3.2
Pin functionality
GND1
Reference ground of the input side. Connect direct to input signal ground.
VCC1
Positive power supply terminal of the input side, connect to 5 V or 3.3 V for proper operation. Place a decoupling
capacitor close to this pin and GND1.
ADJA and ADJB parameter adjust input for set A or B
The pins ADJA and ADJB are used to adjust two sets of independent parameters of output functions.
Connect a resistor between 1.33 kΩ and 28.0 kΩ to GND1 to adjust each parameter. All valid resistor values
belong to the E96-series with 1% tolerance.
Connecting ADJA to GND1 uses a default value for soꢀ switch-off. Connecting it to VCC1 is disabling the gate
driver IC.
Connecting ADJB to GND1 is disabling the gate driver IC. Connecting it to VCC1 is setting the function to
minimum values.
RDYC ready status output, fault-off input and fault-clear input
Open-drain output reports the correct operation of the device, ready output is high active. Fault-clear input and
fault-off input clears a gate driver fault or switch the gate driver output to off with fault-off function, input is low
active. Connect to a microcontroller with 5 V or 3.3 V I/O with an external pull-up resistor to VCC1. A typical value
for this resistor is 2.2 kΩ. The RDCY signal is referenced to GND1.
FLT_N fault output and fault-off input
Open-drain output reports the failures related to operating of the inverter system to the microcontroller, fault
output is active low. Fault-off input switch the gate driver output to off with fault-off function, input is low
active. Connect to a microcontroller with 5 V or 3.3 V I/O with an external pull-up resistor to VCC1. A typical value
for this resistor is 2.2 kΩ. The FLT_N signal is referenced to GND1.
IN non inverting gate driver input
IN input controls the output of the gate driver IC, the IGBT is turned on if IN is set to high. Connect to a PWM
output of the microcontroller with 5 V or 3.3 V IO. An internal pull-down resistor ensures IGBT off-state if not
connected. A minimum pulse width of typical 103 ns is defined to make the gate driver IC robust against glitches
at IN.
VEE2
Negative power supply terminal of the output side. Connect to a voltage of 0 V to -25 V referenced to GND2 for
proper operation. Place a decoupling capacitor close to the following pins:
•
•
VCC2 and VEE2
GND2 and VEE2
If no negative supply voltage is used, all VEE2 pins have to be connected to GND2.
CLAMP Miller clamp output, CLAMPDRV Miller clamp pre-driver output
CLAMP: High-current clamp output to hold the gate voltage low during collector-emitter-voltage rise. Connect
directly to the gate of the IGBT.
CLAMPDRV: Clamp pre-driver output for the use of an external clamp switch. Connect directly to the gate of a
n-channel MOSFET.
Datasheet
9
v2.1
2021-02-15
EiceDRIVER™ 1ED34x1Mc12M Enhanced
Datasheet
3 Pin configuration and functionality
OFF driver output
High-current driver sink output to discharge the gate of the external IGBT.The gate driver IC also sinks the
Soꢀ-off current at this pin. Connect to the gate of the IGBT via a chosen turn-off gate resistor.
ON driver output
High-current driver source output to charge the gate of the external IGBT and turn it on and sense input for the
CLAMP function. Connect to the gate of the IGBT via a chosen turn-on gate resistor.
DESAT enhanced desaturation detection input
Desaturation detection input to monitor the IGBT collector-emitter voltage (VCE) to detect desaturation caused
by short circuit events. Connect to the collector of the driven IGBT via a series connection of a protection
resistor and a high-voltage diode. The DESAT signal is referenced to GND2.
VCC2
Positive power supply terminal of the output side. Connect to sufficient supply voltage referenced to GND2 for
proper operation. Place a decoupling capacitor close to the following pins:
•
•
VCC2 and VEE2
VCC2 and GND2
GND2 reference ground
Reference ground of the output side. Connect to common voltage of a bipolar supply and the emitter of the
IGBT. Place a decoupling capacitor close to the following pins:
•
•
VCC2 and GND2
GND2 and VEE2
Datasheet
10
v2.1
2021-02-15
EiceDRIVER™ 1ED34x1Mc12M Enhanced
Datasheet
4 Functional description
4
Functional description
The 1ED34x1Mc12M family (X3 Analog) consists of galvanically isolated single channel gate driver ICs with
adjustable feature parametrization by two simple resistors. All adjustments can be done from the low voltage
input side.
To start-up the gate driver IC for normal operation both input and output sides of the gate driver IC need to be
powered.
The 1ED34x1Mc12M family (X3 Analog) is designed to support various supply configurations on the input and
output side. On the output side unipolar and bipolar supply is possible.
The output stage is realized as rail-to-rail. There the gate driver voltage follows the supply voltage without an
additional voltage drop. In addition it provides an easy clamping of the gate voltage during short circuit of an
external IGBT.
The RDYC status output reports correct operation of the gate driver IC like sufficient voltage supply. The FLT_N
status output reports failures in the application like desaturation detection.
To ensure safe operation the gate driver IC is equipped with an input and output side under-voltage lockout
circuit. The UVLO levels are optimized for IGBTs.
The desaturation detection circuit protects the external IGBT from destruction at a short circuit. The gate driver
IC reacts on a DESAT fault by turning off the IGBT with the adjustable soꢀ-off method.
The soꢀ turn-off function is used to switch-off the external IGBT in overcurrent conditions in a soꢀ-controlled
manner to protect the IGBT against collector emitter over-voltages.
An active Miller clamp function protects the IGBT from parasitic turn-on in fast switching applications.
4.1
Start-up and fault clearing
For normal operation both input and output sides of the gate driver IC need to be powered. A low level at the
FLT_N pin always indicates a fault condition. In this case the IC starts internal mechanisms for fault clearing.
Input side start-up
1.
2.
3.
4.
5.
6.
Voltage at VCC1 reaches the input UVLO threshold: input side of gate driver IC starts operating
FLT_N follows input supply voltage
Records resistor programmable function from ADJA and ADJB
Waits until output side is powered
Initiates internal start-up: Transfers configured values to output side
Performs internal self-test
The start-up delay takes approx. 200 µs and is part of the complete start-up time tSTART1
.
Output side start-up
1.
2.
3.
4.
5.
Voltage at VCC2 reaches the output UVLO threshold: output side of gate driver IC starts operating
Activates OFF gate driver output: connected gate stays discharged
Waits until input side is powered
Initiates internal start-up: Receives configured values from input side
Performs internal self-test
The start-up delay takes approx. 200 µs and is part of the complete start-up time tSTART2
.
The gate driver IC releases RDYC to high to signal a successful start-up and its readiness to operate. The gate
driver IC will follow the status of the IN signal.
Clearing a fault with RDYC to low cycle
1.
2.
Set IN to low
Set RDYC to low for a duration longer than the fault clear time tCLRMIN
Datasheet
11
v2.1
2021-02-15
EiceDRIVER™ 1ED34x1Mc12M Enhanced
Datasheet
4 Functional description
3.
Release RDYC to high
a.
b.
If the source of the fault is no longer present, FLT_N is released to high
If another fault source is active, FLT_N stays low and the cycle needs to be repeated
4.
Continue PWM operation
4.2
Supply
The 1ED34x1Mc12M family (X3 Analog) is designed to support various supply configurations. The input side can
be used with a 3.3 V or 5 V supply.
The output side requires either an unipolar supply (VEE2 = GND2) or a bipolar supply.
•
•
Individual supply voltages between VCC2 and GND2 or GND2 and VEE2 shall not exceed 25 V.
The total supply voltage between VCC2 and VEE2 shall not exceed 35 V.
To ensure safe operation of the gate driver IC, it is equipped with an input and output side undervoltage lockout
circuit.
Unipolar supply
In unipolar supply configuration the gate driver IC is typically supplied with a positive voltage of 15 V at VCC2.
GND2 and VEE2 are connected together and this common potential is connected to the IGBT emitter.
+3V3
+15V
VCC1
VCC2
100n
1µ
1k
DESAT
ON
SGND
GND1
1R
1R
IN
IN
OFF
RDYC
FLT_N
RDYC
FLT_N
ADJA
ADJB
CLAMP
GND2
VEE2
Figure 5
Application example with unipolar supply (1ED3431M)
Bipolar supply
For bipolar supply the gate driver IC is typically supplied with a positive voltage of 15 V at VCC2 and a negative
voltage of -8 V or -15 V at VEE2 relative to GND2.
Between VCC2 and VEE2 the maximum potential difference is 35 V.
+3V3
+15V
VCC1
GND1
VCC2
100n
1µ
1k
DESAT
ON
SGND
1R
1R
IN
IN
OFF
RDYC
FLT_N
RDYC
FLT_N
ADJA
ADJB
CLAMP
GND2
1µ
-8V
VEE2
Figure 6
Application example with bipolar supply (1ED3431M)
Negative supply prevents a parasitic turn-on due to the additional voltage margin to the gate turn-on threshold.
Datasheet
12
v2.1
2021-02-15
EiceDRIVER™ 1ED34x1Mc12M Enhanced
Datasheet
4 Functional description
VEE2 over GND2 supply connection check
The gate driver IC has a built-in connection check for VEE2. A loss of VEE2 connection will be detected and
signaled via RDYC.
4.2.1
Input side undervoltage lockout, VCC1 UVLO
To ensure correct operation of the input side and safe operation of the application the gate driver IC is equipped
with an input supply undervoltage lockout for VCC1.
UVLO behavior during start-up:
1.
2.
The voltage at the supply terminal VCC1 reaches the VUVLO1H threshold
The gate driver IC reads the ADJA and ADJB resistor values and transfers the configuration to the output
side
3.
The IC releases the RDYC output to high and is ready to operate.
The start-up delay takes approx. 200 µs and is part of the complete start-up time tSTART1
.
UVLO behavior during shut-down:
•
If the supply voltage VVCC1 of the input side drops below VUVLO1L the RDYC signal is switched to low and the
output will be switched off.
The fault signal FLT_N follows the input supply voltage.
IN
VUVLO1H
VUVLO1L
VCC1
VCC2
tPDRDYC
tSTART1
ON+OFF
RDYC
tUV1LRDYC
tPDRDYC
FLT_N
Figure 7
UVLO VCC1 behavior
4.2.2
Output side under-voltage lockout, VCC2 UVLO
To ensure correct operation of the output side and safe operation of the IGBT in the application, the gate driver
IC is equipped with an output supply undervoltage lockout for VCC2 versus GND2.
UVLO behavior during start-up:
•
If the voltage at the supply terminal VCC2 reaches the VUVLO2H threshold the RDYC output is released to high
and the gate driver IC is ready to operate.
The start-up delay takes approx. 200 µs and is part of the complete start-up time tSTART2
.
UVLO behavior during shut-down:
•
If the supply voltage VVCC2 of the output side drops below VUVLO2L the RDYC signal is switched to low and the
output will be switched off.
Datasheet
13
v2.1
2021-02-15
EiceDRIVER™ 1ED34x1Mc12M Enhanced
Datasheet
4 Functional description
IN
VCC1
VUVLO2H
VUVLO2L
VCC2
ON+OFF
tPDRDYC
tUV2LOFF
RDYC
tSTART2
tUV2LRDYC
FLT_N
Figure 8
UVLO VCC2 behavior
Any VUVLO2L event will lead to a fault-off and a RDYC low level. Depending of the level of the voltage drop, the
gate driver IC either stays in a not ready state and waits for the supply voltage to recover, or it will fully reset the
gate driver IC. Both variants differ in the necessary delay of RDYC release aꢀer the supply voltage has recovered.
Aꢀer a reset, the gate driver IC needs to fully restart until it becomes ready again.
Datasheet
14
v2.1
2021-02-15
EiceDRIVER™ 1ED34x1Mc12M Enhanced
Datasheet
4 Functional description
4.3
Input side logic
The input threshold levels are always CMOS compliant. The threshold levels are 30% of VCC1 for low level and
70% of VCC1 for high level.
The 1ED34x1Mc12M family (X3 Analog) has three input pins (IN, ADJA, ADJB) and two I/O pins (RDYC, FLT_N) at
the input side.
4.3.1
IN non-inverting driver input
The input pin has a positive logic. To turn on the associated IGBT apply a logic high signal at the IN pin. A
minimum pulse width of typical 103 ns is defined to make the IC robust against glitches at IN.
4.3.2
RDYC ready status output, fault-off and fault clear input
The RDYC pin is a logic input and open drain output and has three different functions:
•
•
•
RDYC as ready status output of all ready sources
RDYC as fault-off input
RDYC as fault clear input
In a typical application the RDYC pins of all gate driver ICs in the inverter are connected together and form a
single wire RDYC signal.
An external pull-up resistor is required to ensure RDYC status output during operation.
Ready sources
•
•
•
•
•
the input side is properly supplied, VCC1 supply above UVLO1 threshold
the output side is properly supplied with a positive voltage, VCC2 supply above UVLO2 threshold
no VEE2 over GND2 failure
Internal signal transmission is operating nominal
the ON pin monitoring of the gate driver is below VEE2 + 2 V, IGBT has to be off at start-up
4.3.2.1
RDYC fault-off input
Pulling RDYC to low disables the operation of the gate driver IC. The gate driver IC ignores IN signals as long as
the RDYC pin stays low and the IC uses its fault-off function to switch-off the IGBT.
The defined minimum pulse width makes the IC robust against glitches at RDYC. The gate driver ignores pulses
with a shorter duration.
IN
RDYC ext.
tSSIO
RDYC
<tRDYCMIN
>tRDYCMIN
<tRDYCMIN
>tRDYCMIN
tPDRDYC
tSSIO
VEE2 + 2V
ON+OFF
Figure 9
RDYC short pulse behavior of external manipulation of the RDYC pin
Aꢀer an external RDYC low signal the IC is actively pulling RDYC to low until the voltage at ON pin falls below the
VEE2+2 V threshold.
The RDYC fault-off input is active low.
Datasheet
15
v2.1
2021-02-15
EiceDRIVER™ 1ED34x1Mc12M Enhanced
Datasheet
4 Functional description
4.3.2.2
RDYC fault clear input
Setting RDYC to low for longer than the fault clear time tCLRMIN will reset the stored fault signal at pin FLT_N with
the rising edge of RDYC. Additionally the following conditions have to be met as well:
•
•
•
PWM IN pin level needs to be low,
voltage at ON pin has dropped below the VEE2+2 V threshold, and
triggering fault condition is no longer present.
The typical fault clear time tCLRMIN is 1.0 µs.
IN
FLT event
FLT_N
tDESATFLT
tDESATFLT
VEE2 + 2V
ON+OFF
tSSIO
tSSIO
RDYC
>tCLRMIN
>tCLRMIN
Figure 10
RDYC fault clear timing
VIH
RDYC
FLT_N
Figure 11
RDYC fault clear rising edge to FLT_N
4.3.3
FLT_N status output and fault-off input
The FLT_N pin is a logic input and open drain output and has two different functions:
•
•
FLT_N as fault-status output for fault sources
FLT_N as fault-off input
In a typical application the FLT_N pins of all gate driver ICs in the inverter are connected together and form a
single wire FLT_N signal.
An external pull-up-resistor is required to ensure FLT_N status output during operation.
Fault sources
The following fault sources can trigger a FLT_N pin to low and initiate a fault turn-off:
•
•
desaturation detection of IGBT
gate driver over temperature protection
4.3.3.1
FLT_N fault-off input
Pulling FLT_N to low disables the operation of the gate driver IC. The gate driver IC ignores IN signals as long as
the FLT_N pin stays low and the IC uses its fault-off function to switch-off the IGBT.
The defined minimum pulse width makes the gate driver IC robust against glitches at FLT_N.
Aꢀer a low at the FLT_N pin either internally or externally applied, the fault event is latched until cleared.
Datasheet
16
v2.1
2021-02-15
EiceDRIVER™ 1ED34x1Mc12M Enhanced
Datasheet
4 Functional description
The FLT_N fault-off input is active low.
IN
FLT_N ext.
FLT_N ext.
FLT_N
<tFLT_NMIN
>tFLT_NMIN
<tFLT_NMIN
>tFLT_NMIN
tPDFLT_N
ON+OFF
RDYC
>tCLRMIN
>tCLRMIN
Figure 12
FLT_N short pulse behavior of external manipulation of the FLT_N pin cleared by RDYC
Datasheet
17
v2.1
2021-02-15
EiceDRIVER™ 1ED34x1Mc12M Enhanced
Datasheet
4 Functional description
4.4
Desaturation protection
The desaturation detection circuit protects the external IGBT from destruction at a short circuit. The
desaturation protection follows the given sequence:
1.
2.
3.
4.
Voltage at DESAT pin reaches DESAT threshold level, for a period of time exceeding the filter time
Gate driver IC output switches the external IGBT off, using the soꢀ-off method
Gate driver IC switches FLT_N pin to low to indicate the fault to a connected microcontroller
Short circuit situation is resolved
•
•
•
•
aꢀer the voltage at the ON pin has dropped below the VEE2+2 V threshold,
no other fault condition is present,
the input has been turned off and
the fault has been cleared using the RDYC low cycle method
+15V
VCC2
D
A
CVCC2
RDESAT
DDESAT
DESAT
LOGIC
RG
FLT_off
OFF
GND2
Figure 13
DESAT circuit (only relevant pins shown)
The 1ED34x1Mc12M family (X3 Analog) has a fixed DESAT threshold level of typical 9.18 V. If lower threshold
levels are required, the DESAT resistor can be increased. Larger DESAT resistor values lead to lower DESAT
threshold voltages. The threshold voltage reduction is equal to the DESAT current multiplied by the DESAT
resistance.
The high-precision internal current source results in a minimum impact on the DESAT detection variation.
4.4.1
DESAT behavior
The DESAT function offers a leading edge blanking time and filters to optimize the DESAT detection for
application usage.
The leading edge blanking inhibits threshold detection during an IGBT turn on phase. The typical IGBT turn on
behavior starts with charging of the gate, commutation of the application load current and finally VCE voltage
decrease to VCEsat voltage levels. To prevent the gate driver IC from detecting a false DESAT event, leading edge
blanking pauses the DESAT circuit until the time tDESATleb has elapsed.
Following the leading edge blanking time, the gate driver IC forces the DESAT current into the external
DESAT circuit. The current typically flows through a protection resistor, a fast high voltage diode and the
collector-emitter path of the IGBT. The resulting voltage at the DESAT pin is the sum of the voltage drop across
this path.
During a short circuit condition, the VCE voltage increases, resulting in a reverse polarity condition of the DESAT
diode. The remaining DESAT current also increases the voltage level at the DESAT pin and triggers the DESAT
threshold. If the pin voltage level stays above the threshold for the duration of the DESAT filter time tDESATfilter
,
the gate driver IC registers the DESAT event and acts accordingly.
Datasheet
18
v2.1
2021-02-15
EiceDRIVER™ 1ED34x1Mc12M Enhanced
Datasheet
4 Functional description
The internal processing time aꢀer DESAT threshold crossing, filtering and beginning of fault-off is defined as
tDESATOUT. The duration of the gate discharge during fault-off is defined as tFLTOFFtot and is depending on the
soꢀ-off function and the gate load.
IN
tPDRDYC
tPDON
tFLTOFFtot
OUT
tDESATfilter
tDESATOUTS
VDESAT
tDESATleb
DESAT
VCE
tDESATFLT
FLT_N
RDYC
>tCLRMIN
Figure 14
DESAT timing with leading edge blanking, filter and reaction times
4.4.2
DESAT filter and leading edge blanking time adjustment with ADJB
The ADJB pin configures the DESAT leading edge blanking time and DESAT filter time:
•
A resistor from ADJB to GND1 sets the DESAT leading edge blanking time and the DESAT filter time used
during DESAT detection
•
Use resistors from the E96 resistor-series with 1% tolerance values to achieve accurate parameter
configuration
•
•
•
The gate driver IC reads the resistor value once during start-up
Connecting ADJB to GND1 inhibits the gate driver operation and stops the start-up sequence
Connecting ADJB to VCC1 disables the filtering resulting in minimum response times
Table 4
DESAT filter timing ADJB adjustment
DESAT filter time stopped 0
set up
1
2
3
4
5
6
7
Resistance at ADJB
to GND1
<
1.33 kΩ 1.58 kΩ 1.91 kΩ 2.26 kΩ 2.74 kΩ 3.32 kΩ 4.02 kΩ 4.87 kΩ
1.05 kΩ
or tied
to GND1
typ. tDESATleb
typ. tDESATfilter
inhibit 650 ns
gate
driver
operatio
n
650 ns
650 ns
650 ns
650 ns
650 ns
650 ns
650 ns
1575 ns 1775 ns 1975 ns 2375 ns 2775 ns 3175 ns 3575 ns 3975 ns
Datasheet
19
v2.1
2021-02-15
EiceDRIVER™ 1ED34x1Mc12M Enhanced
Datasheet
4 Functional description
Table 4
DESAT filter timing ADJB adjustment
10 11
DESAT filter time
set up
8
9
12
13
14
15
default
Resistance at ADJB 5.90 kΩ 7.15 kΩ 8.66 kΩ 10.7 kΩ 13.7 kΩ 17.4 kΩ 23.2 kΩ 28.0 kΩ >45.3 kΩ
to GND1
or tied
to VCC1
typ. tDESATleb
typ. tDESATfilter
1150 ns 1150 ns 1150 ns 1150 ns 1150 ns 1150 ns 1150 ns 1150 ns 400 ns
3975 ns 3575 ns 3175 ns 2775 ns 2375 ns 1975 ns 1775 ns 1575 ns 225 ns
Datasheet
20
v2.1
2021-02-15
EiceDRIVER™ 1ED34x1Mc12M Enhanced
Datasheet
4 Functional description
4.5
Gate driver output
The gate driver output side uses MOSFETs to provide a rail-to-rail output. Therefore, the gate drive voltage
follows the supply voltage closely.
Due to the low internal voltage drop, the switching behavior of the IGBT is predominantly governed by the
external gate resistor. The gate driver IC offers separate sink and source outputs to adapt the gate resistor for
turn-on and turn-off separately without additional bypass components.
The cell value x in the following table is placeholder for high or low and indicates that this pin does not
influence the resulting gate driver output state. The arrow (→) in cells indicate the transition initiated by the pin
of the logic input and gate driver supply pins resulting in a transition to the gate driver output state as listed.
Table 5
Driver output state including transition behavior
Logic input and gate driver supply
IN RDYC FLT_N
Static gate driver output state: on and off
Gate driver output
VCC1
VCC2
ON
OFF
high
low
high
high
high
high
high
high
high
high
high
tri-state
low
tri-state
Transition to not ready and static not ready state
x
x
high → low
low
high
high
high
high
high
high
→ tri-state
tri-state
→ fault off
low
Transition to fault and static fault state
x
x
high
high
high → low
low
high
high
high
high
→ tri-state
tri-state
→ fault off
low
Transition with VCC1 power loss and unsupplied input side
x
x
x
x
x
x
high → low
low
high
high
→ tri-state
tri-state
→ fault off
low
Transition with VCC2 power loss and unsupplied output side
x
x
x
x
x
x
x
x
high → low
low
→ tri-state
tri-state
→ fault off
active shut down
Datasheet
21
v2.1
2021-02-15
EiceDRIVER™ 1ED34x1Mc12M Enhanced
Datasheet
4 Functional description
4.5.1
Turn-on behavior
The 1ED34x1Mc12M family (X3 Analog) is optimized for hard switching turn-on. A turn-on command switches
the ON pin internally to VCC2.
4.5.2
Turn-off and fault turn-off behavior
The gate driver IC supports different turn-off sequences to adapt to different applications and IGBT currents
during normal switching operation and in the case of a fault.
Table 6
Turn-off sequences
Turn-off sequence
Turn-off reason
Remark
Hard switching
Soꢀ turn-off
normal off
X
fault turn-off
X
adjustable via ADJA
The gate driver fault turn-off behavior can be configured with the ADJA pin
Once started, the fault turn-off sequence cannot be interrupted by an IN = low turn-off signal.
FLT_N or RDYC
tPDRDYCS, tPDFLT_NS
VOUT = 80%
ON + OFF (soft-off)
Figure 15
Fault turn-off sequence initiated by FLT_N or RDYC
VDESAT
DESAT
tDESATfilter,n
tDESATOUTS
VOUT = 80%
ON + OFF (soft-off)
Figure 16
Fault turn-off sequence initiated by DESAT event
4.5.2.1
Hard switching turn-off
The gate driver IC supports hard switching turn-off during normal switching operation. Switching the IGBT gate
off by turning on the discharge MOSFET in the output stage, the OFF pin is switched to VEE2 pin.
4.5.2.2
Soꢀ turn-off
The soꢀ turn-off function protects the IGBT against collector-emitter overvoltage during turn off in an
overcurrent condition. It turns-off the IGBT with a reduced gate current to reduce the di/dt induced
overvoltage..
The IGBT gate is connected via OFF to an internal current sink circuit. The discharge current is typically lower
than the hard switch-off current used for normal operation. Since soꢀ turn-off is a single event aꢀer a failure,
the gate driver IC can handle the additional power dissipation internally.
Soꢀ turn-off can be configured with the ADJA pin. The function is only active during fault turn-off.
The adjustable range depends on the current strength of the gate driver IC:
Datasheet
22
v2.1
2021-02-15
EiceDRIVER™ 1ED34x1Mc12M Enhanced
Datasheet
4 Functional description
•
•
•
1ED3431M: 15 mA - 233 mA
1ED3461M: 29 mA - 466 mA
1ED3491M: 44 mA - 699 mA
4.5.2.2.1
Soꢀ-off current source adjustment with ADJA
The ADJA pin configures the Soꢀ-off function and current level:
•
•
A resistor from ADJA pin to GND1 sets the Soꢀ-off current level for the fault-off function
Use resistors from the E96 resistor-series with 1% tolerance values to achieve accurate parameter
configuration
•
•
•
The gate driver IC reads the resistor value once during start-up
Connecting ADJA to GND1 results in a Soꢀ-off function for fault-off with a predefined value
Connecting ADJA to VCC1 inhibits the gate driver operation and stops the start-up sequence
Table 7
Soꢀ-off adjustment with ADJA
Soꢀ-off set up default
0
1
2
3
4
5
6
7
Resistance from < 1.05 kΩ
1.33 kΩ 1.58 kΩ 1.91 kΩ 2.26 kΩ 2.74 kΩ 3.32 kΩ 4.02 kΩ 4.87 kΩ
ADJA to GND1
or tied to
GND1
typ. ICSOFF
1ED3431M
146 mA
291 mA
437 mA
15 mA
29 mA
44 mA
29 mA
58 mA
87 mA
44 mA
87 mA
58 mA
73 mA
87 mA
102 mA 116 mA
typ. ICSOFF
1ED3461M
116 mA 146 mA 175 mA 204 mA 233 mA
typ. ICSOFF
1ED3491M
131 mA 175 mA 218 mA 262 mA 306 mA 349 mA
Table 7
Soꢀ-off adjustment with ADJA
10 11
Soꢀ-off set up
8
9
12
13
14
15
stopped
Resistance from 5.90 kΩ 7.15 kΩ 8.66 kΩ 10.7 kΩ 13.7 kΩ 17.4 kΩ 23.2 kΩ 28.0 kΩ >45.3 kΩ or
ADJA to GND1
tied to VCC1
typ. ICSOFF
1ED3431M
131 mA 146 mA 160 mA 175 mA 189 mA 204 mA 218 mA 233 mA inhibit gate
driver
operation
typ. ICSOFF
1ED3461M
262 mA 291 mA 320 mA 349 mA 379 mA 408 mA 437 mA 466 mA
typ. ICSOFF
1ED3491M
393 mA 437 mA 480 mA 524 mA 568 mA 612 mA 655 mA 699 mA
Datasheet
23
v2.1
2021-02-15
EiceDRIVER™ 1ED34x1Mc12M Enhanced
Datasheet
4 Functional description
4.5.3
Active shut-down
The active shut-down feature ensures a safe IGBT off-state, if the output chip is not supplied. It protects the
IGBT against a floating gate. The IGBT gate is always clamped via OFF to VEE2.
4.5.4
Active Miller clamp
The 1ED34x1Mc12M family (X3 Analog) is equipped with an active Miller clamp function to protect the IGBT from
parasitic turn-on in fast switching applications.
Aꢀer a turn-off command the gate driver IC follows the implemented sequence:
1.
2.
3.
4.
Discharge of the IGBT gate while monitoring the voltage level at the ON pin
Detection of a voltage at the ON pin less than a level of VEE2 + 2.0 V
Filtering of the detection to avoid false CLAMP activation and not to influence regular turn-off behavior
Activating clamp function to keep IGBT gate at VEE2 level
4.5.4.1
CLAMP output types
The CLAMP output stage offers two operating modes:
•
•
direct gate clamping with an open drain output for medium clamping current, 1ED3431M variants
pre-driver output, to clamp IGBT gate with external transistor for high clamping current, 1ED3461M and
1ED3491M variants
Direct gate clamping
Direct gate clamping with an open drain output is tailored for direct clamping of IGBT gate to VEE2. The output
current capability is typically 2 A. Useful IGBT current rating for direct gate clamping is a collector current of
typically smaller than 100 A. Connect the CLAMP pin directly to the gate with low inductive tracks.
+3V3
+15V
VCC1
VCC2
100n
1µ
1k
DESAT
ON
SGND
GND1
1R
1R
IN
IN
OFF
RDYC
FLT_N
RDYC
FLT_N
ADJA
ADJB
CLAMP
GND2
VEE2
Figure 17
Application example with unipolar supply (1ED3431M)
Datasheet
24
v2.1
2021-02-15
EiceDRIVER™ 1ED34x1Mc12M Enhanced
Datasheet
4 Functional description
IN
tPDOFF
VVEE2 +2V
ON
tCLAMPfilter
tONCLAMP
OFF
CLAMP
CLAMP tri state
CLAMP active low
CLAMP tri state
Figure 18
Direct clamp output behavior
Pre-driver output
Track inductance and clamp output resistance reduces the clamping capability for large IGBTs. In this case,
select the pre-driver output product variant with an external MOSFET.
The external small signal n-channel MOSFET transistor in combination with the pre-driver output enables
clamping of high gate currents. Connect the MOSFET between the CLAMPDRV output, VEE2 pin, and IGBT gate.
Due to the pre-driver configuration the clamp current is only limited by the external clamp MOSFET transistor.
Depending on the external MOSFET a Miller current clamping up to 20 A can be reached. The clamping MOSFET
has to be placed close to the IGBT gate to minimize track resistance and inductance.
+3V3
+15V
VCC1
VCC2
100n
1µ
1k
DESAT
ON
SGND
GND1
1R
1R
IN
IN
OFF
RDYC
FLT_N
RDYC
FLT_N
ADJA
ADJB
CLAMPDRV
GND2
1µ
-8V
VEE2
Figure 19
Application example with bipolar supply and CLAMP pre-driver output (1ED3461M,
1ED3491M)
Datasheet
25
v2.1
2021-02-15
EiceDRIVER™ 1ED34x1Mc12M Enhanced
Datasheet
4 Functional description
IN
tPDOFF
VVEE2 +2V
ON
tCLAMPfilter
tONCLAMP
OFF
CLAMPDRV
CLAMP DRV low
CLAMP DRV active high
CLAMP DRV low
Figure 20
Clamp pre-driver output behavior
4.5.5
Switch-off timeout until forced switch-off
The gate driver IC is equipped with a switch-off timeout monitoring feature. In case the pin monitoring
comparator has not registered an off-state within the timeout time this feature activates a forced switch-off.
The monitoring feature secures the IGBT switch-off in case of a connection failure between the OFF output
and the IGBT gate or a faulty gate resistor. In a forced switch-off all available output switch-off paths (OFF and
CLAMP/CLAMPDRV) will be used to hard switch-off the IGBT aꢀer such an event.
OFF activated
VVEE2 +2V
ON
(soft-off)
tCTSOOS
tCTT
VVEE2 +2V
ON
(hard switch-off)
tCTT
TO switch-off inactive
TO switch-off active
Figure 21
Switch-off timeout behavior
The timing diagram shows the switch-off timeout behavior from the moment of OFF output activation until the
timeout has elapsed and the CLAMP output is activated.
4.6
Short circuit clamping
The integrated short circuit clamping diode limits the IGBT gate over voltage during a short circuit. The over
voltage is typically triggered by the capacitive feedback of the Miller capacitance.
The internal diodes from ON and CLAMP to VCC2 limit the gate driver voltage to a value slightly higher than the
supply voltage. These diode paths are rated for a maximum current of 0.75 A and the duration of 6 µs. Add an
external Schottky diode if higher currents are expected or a tighter clamping is desired. Also use an external
diode if the active Miller clamping circuit uses the pre-driver output configuration.
Datasheet
26
v2.1
2021-02-15
EiceDRIVER™ 1ED34x1Mc12M Enhanced
Datasheet
4 Functional description
+15V
+15V
VCC2
VCC2
ON
ON
OFF
OFF
CLAMP
CLAMP
GND2
VEE2
GND2
VEE2
Figure 22
Short circuit clamping circuitry
Datasheet
27
v2.1
2021-02-15
EiceDRIVER™ 1ED34x1Mc12M Enhanced
Datasheet
5 Electrical parameters
5
Electrical parameters
5.1
Absolute maximum ratings
Note:
Absolute maximum ratings are defined as ratings, which when being exceeded may lead to
destruction of the integrated circuit. Unless otherwise noted all voltages are given with respect to
their respective GND (GND1 for pins 1 to 8, GND2 for pins 9 to 16).
Table 8
Absolute maximum ratings
Parameter
Symbol Values
Min.
Unit
Note /
Test Condition
Max.
Input to output offset voltage
VOFFSET
–
2300
V
VVEE2,max-VVEE2,min
with VVEE2,max
≥
VGND1
≥ VVEE2,min
1) 2)
Supply voltage input side
VVCC1
-0.3
-0.3
-0.3
-0.3
–
6.5
6.5
6.5
6.5
10
V
–
–
–
–
–
–
–
–
Logic input voltage (IN)
VLogicIN
VLogicRF
VLogicAD
V
Logic input voltage (RDYC, FLT_N)
Logic input voltage (ADJA, ADJB)
V
V
Open drain logic output current (RDYC, FLT_N) ILogicOC
mA
V
Positive supply voltage output side
Negative supply voltage output side
Maximum supply voltage difference output
VVCC2
VVEE2
Vmax2
-0.3
-40
–
40
0.3
40
V
V
side (VVCC2 - VVEE2
)
DESAT input voltage
VDESAT
VCLAMP
ICLAMP
VOUT
-0.3
VVCC2 +0.3
V
V
A
–
3)
CLAMP input voltage
VVEE2 -0.3 VVCC2 +0.3
2.4
Maximum CLAMP output current
Gate driver output voltage (ON, OFF)
–
t < 5 µs
VVEE2 -0.3 Vmax2 +0.3 V
–
Maximum CLAMP to VCC2 diode IGBT short
tCLP
–
6
µs
ICLAMP/OUT = 0.75 A
circuit clamping time
Junction temperature
TJ
-40
-55
–
150
150
100
700
2
°C
–
Storage temperature
TStg
°C
–
Power dissipation, input side
Power dissipation, output side
ESD capability: Human body model
ESD capability: Charged device model
PD,IN
mW
mW
kV
V
@TA = 25 °C
@TA = 25°C4)
PD,OUT
VESDHBM
VESDCDM
–
5)
–
6)
–
500
1) for functional operation only
2) See also Chapter 6 on page 41
3) May be exceeded during short circuit clamping.
4) Derating the power above 65°C with 8 mW/°C
Datasheet
28
v2.1
2021-02-15
EiceDRIVER™ 1ED34x1Mc12M Enhanced
Datasheet
5 Electrical parameters
5) According to ANSI/ESDA/JEDEC-JS-001-2017 (discharging a 100 pF capacitor through a 1.5 kΩ series
resistor).
6) According to ANSI/ESDA/JEDEC-JS-002-2014 (TC = test condition in volt)
5.2
Thermal parameters
Thermal performance may change significantly with layout and heat dissipation of components in close
proximity.
Figure 23
Reference layout for thermal data (Two layer PCB; copper thickness 35 μm; leꢀ: top
layer; right: bottom layer)
The PCB layout represents the reference layout used for the thermal characterization. Pins 1 and 8 (GND1)
and pins 9 and 16 (VEE2) require ground plane connections for achieving maximum power dissipation. The
1ED34x1Mc12M family (X3 Analog) is conceived to dissipate most of the heat generated through these pins.
Table 9
Thermal parameters
Parameter
Symbol
Value
Unit
Note / Test Condition
Thermal resistance junction to
ambient
RTHJA,OUT
122
K/W
@TA = 65°C, PD, OUT = 400 mW,
PD, IN = 50 mW, 4 layer test PCB,
PG-DSO-16
Characterization parameter junction ΨJtop
to package top input side
8
K/W
5.3
Operating parameters
Note:
Within the operating range the IC operates as described in the functional description. Unless
otherwise noted all voltages are given with respect to their respective GND (GND1 for pins 1 to 8,
GND2 for pins 9 to 16).
Table 10
Operating parameters
Parameter1)
Symbol
Values
Min.
3.0
Unit
Note /
Test Condition
Max.
5.5
5.5
25
Supply voltage input side
VVCC1
V
V
V
V
–
–
–
–
Logic input voltages (IN, RDYC, FLT_N) VLogicIN
-0.3
13
Positive supply voltage output side
Negative supply voltage output side
VVCC2
VVEE2
-25
0
Datasheet
29
v2.1
2021-02-15
EiceDRIVER™ 1ED34x1Mc12M Enhanced
Datasheet
5 Electrical parameters
Table 10
Operating parameters (continued)
Symbol Values
Parameter1)
Unit
Note /
Test Condition
Min.
Max.
Supply voltage difference output side Vmax2
(VVCC2 - VVEE2
13
35
V
–
)
2)
Ambient temperature
TA
-40
0
125
250
200
°C
Switching frequency
fSW
kHz
V/ns
max PD applies
Common mode transient immunity
|CMTI|
0
VOFFSET,test =
1500 V
1) Parameter is not subject to production test - verified by design/characterization
2) TJ has to be below over temperature protection temperature TOTPOFF
Datasheet
30
v2.1
2021-02-15
EiceDRIVER™ 1ED34x1Mc12M Enhanced
Datasheet
5 Electrical parameters
5.4
Electrical characteristics
Note:
The electrical characteristics include the spread of values in supply voltages, load, and junction
temperatures within the operating parameters unless specified otherwise. Typical values represent
the median values at TA = 25°C. Unless otherwise noted all voltages are given with respect to their
respective GND (GND1 for pins 1 to 8, GND2 for pins 9 to 16).
5.4.1
Voltage supply
Table 11
Voltage supply
Parameter
Symbol
Values
Typ.
Unit
Note or Test
Condition
Min.
Max.
3.05
VCC1 UVLO threshold
VUVLO1H
VUVLO1L
VHYS1
–
2.95
V
V
V
–
–
–
2.6
0.1
2.8
–
–
VCC1 UVLO hysteresis
0.14
(VUVLO1H - VUVLO1L
)
VCC1 quiescent current IQ1
–
–
–
2.4
2.4
4.0
4.0
mA
mA
VVCC1 = 3.3 V, IN =
High, RDYC = High,
FLT_N = High
VCC1 operating current IO1
VVCC1 = 3.3 V, IN =
16 kHz, 50%, RDYC =
High, FLT_N = High
VCC2 UVLO threshold
VCC2 UVLO hysteresis
VUVLO2H,0
VUVLO2L,0
VHYS2,0
12.0
11.0
1.0
12.6
V
V
V
10.4
0.75
–
–
(VUVLO2H,0 - VUVLO2L,0
)
VEE2 not connected
detection threshold
VVEE2,NC
–
–
0.5
3.9
–
5
V
VVEE2 - VGND2
VCC2 quiescent current IQ2
mA
VVCC2 = 15 V, VVEE2
= -8 V, OUT = High,
DESAT = Low
VCC2 operating current IO2
–
3.9
5
mA
VVCC2 = 15 V, VVEE2 =
-8 V, OUT = 16 kHz,
50%, DESAT = Low,
CLOAD = 100 pF
Datasheet
31
v2.1
2021-02-15
EiceDRIVER™ 1ED34x1Mc12M Enhanced
Datasheet
5 Electrical parameters
5.4.2
Logic input and output
Table 12
Logic input and output
Symbol
Parameter
Values
Typ.
Unit
Note or Test
Condition
Min.
Max.
30
Logic low input voltage (IN,
RDYC, FLT_N)
VLogicINL
VLogicINH
–
–
–
–
%
of VVCC1
Logic high input voltage (IN,
RDYC, FLT_N)
70
–
–
%
of VVCC1
Logic low output voltage (RDYC, VRDYC5
,
300
47
1.2
mV
kΩ
MΩ
ISINK = 5 mA
FLT_N) VFLT_N5
Logic input pull down resistor RINPD
(IN)
33
40
–
–
Logic input pull down resistor RRDYCPD
,
0.8
1.0
(RDYC, FLT_N)
RFLT_NPD
5.4.3
Analog input
Resistor values outside of the 1% tolerance range results in the gate driver IC selecting either the lower or higher
step for the corresponding function.
Table 13
Analog input
Parameter1)
Symbol
Values
Typ.
Unit
Note or Test
Condition
Min.
Max.
Analog input resistor (ADJA,
ADJB)
RADJx0
RADJx1
RADJx2
RADJx3
RADJx4
RADJx5
RADJx6
RADJx7
RADJx8
RADJx9
RADJx10
RADJx11
RADJx12
RADJx13
RADJx14
RADJx15
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
1.33
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
kΩ
all resistor values are
from the E96-series
with 1% tolerance
1.58
1.91
2.26
2.74
3.32
4.02
4.87
5.90
7.15
8.66
10.7
13.7
17.4
23.2
28.0
Datasheet
32
v2.1
2021-02-15
EiceDRIVER™ 1ED34x1Mc12M Enhanced
Datasheet
5 Electrical parameters
1) Parameter is not subject to production test - verified by design/characterization
Datasheet
33
v2.1
2021-02-15
EiceDRIVER™ 1ED34x1Mc12M Enhanced
Datasheet
5 Electrical parameters
5.4.4
Gate driver
Note:
High and low level output currents are absolute values without an information of current direction.
Table 14
Gate driver
Parameter
Symbol
Values
Typ.
Unit
Note or Test
Condition
Min.
Max.
High level output
voltage
VON0
–
VVCC2 + 0.87 VVCC2 + 1.01
V
ION = 500 mA1)
2) 3)
High level output peak ION
current 1ED3431M
2.6
3.8
1.12
2.5
0.82
7.5
0.56
5.0
0.41
11
–
A
Ω
A
Ω
A
Ω
A
Ω
A
Ω
A
Ω
V
C
= 33 nF
LOAD
High level output on
resistance 1ED3431M
RDSON,H
0.51
2.0
0.31
5.2
0.26
4.0
0.16
7.9
0.17
6.0
0.11
–
2.24
ION = 67 mA3)
2) 4)
Low level output peak IOFF
current 1ED3431M
–
C
LOAD
= 33 nF
Low level ouput on
RDSON,L
1.64
IOFF = 67 mA4)
resistance 1ED3431M
2) 3)
High level output peak ION
current 1ED3461M
–
C
LOAD
= 68 nF
High level output on
resistance 1ED3461M
RDSON,H
1.13
ION = 133 mA3)
2) 4)
Low level output peak IOFF
current 1ED3461M
–
C
LOAD
= 68 nF
Low level ouput on
RDSON,L
0.83
IOFF = 133 mA4)
resistance 1ED3461M
2) 3)
High Level output peak ION
current 1ED3491M
–
C
LOAD
= 100 nF
High level output on
resistance 1ED3491M
RDSON,H
0.38
7.5
0.28
–
0.75
ION = 200 mA3)
2) 4)
Low Level output peak IOFF
current 1ED3491M
–
C
LOAD
= 100 nF
Low level ouput on
RDSON,L
0.55
IOFF = 200 mA4)
resistance 1ED3491M
5)
5)
5)
Active Shut Down
Voltage OFF 1ED3431M
VACTSD
VACTSD
VACTSD
VVEE2 +2.4
VVEE2 +2.4
VVEE2 +2.4
IOUT = 67 mA,VVCC2
open
Active Shut Down
Voltage OFF 1ED3461M
–
–
V
IOUT = 133 mA,VVCC2
open
Active Shut Down
–
–
V
IOUT = 200 mA,VVCC2
Voltage OFF 1ED3491M
open
1) Integrated diode ON vs. VCC2 clamping test
2) Parameter is not subject to production test - verified by design/characterization
3) IN = High, ON = High; VCC2-ON = 15 V; RG = 0.1 Ω; VCC2 = 15 V; VEE2 = -8 V
4) IN = Low, OFF = Low; OFF-VEE2 = 15 V; RG = 0.1 Ω; VCC2 = 15 V; VEE2 = -8 V
Datasheet
34
v2.1
2021-02-15
EiceDRIVER™ 1ED34x1Mc12M Enhanced
Datasheet
5 Electrical parameters
5) With reference to VEE2
5.4.5
Active Miller clamp
Table 15
Active Miller clamp
Parameter
Symbol
Min.
Values
Typ.
Unit
Note or Test
Condition
Max.
VVCC2 +1.63
VVCC2 +1.1
VVEE2+11.5
–
High level clamp
voltage
VCLAMPH0
VCLAMPH1
–
–
VVCC2 +1.5
VVCC2 +0.9
VVEE2+9.5
VVEE2+6.7
V
V
V
V
ICLAMP = 500 mA1) 2)
ICLAMP = 50 mA1) 2)
ICLAMPH = 5 mA3)
ICLAMPH = 50 mA3)
Clamp-driver high
level output voltage
(1ED3461M, 1ED3491M)
VCLAMPDH1 VVEE2+7.5
VCLAMPDH2 VVEE2+4.5
Clamp-driver high level ICLAMPH
output peak current
(1ED3461M, 1ED3491M)
0.20
0.27
–
A
4) VCC2 = 15 V; VEE2 =
0 V; CCLAMP = 100 nF;
RCLAMP = 1 Ω
Clamp/Clamp-driver
output low level
current
ICLAMPL,2
1.1
1.8
–
A
4) VCC2 = 15 V; VEE2
= 0 V; VCLAMP = 2 V;
CCLAMP = 100 nF;
RCLAMP = 0.1 Ω
Clamp/Clamp-driver
output low level
current
ICLAMPL,5
2.2
3.5
–
A
4) VCC2 = 15 V; VEE2
= 0 V; VCLAMP = 5 V;
CCLAMP = 100 nF;
RCLAMP = 0.1 Ω
Clamp/Clamp-driver
output low level ON
resistance
RDSON,CLP 0.50
0.85
1.35
Ω
V
ICLAMPL = 200 mA
Clamp threshold
voltage
VON_CLAMP 1.5
tCLAMPfilter 195
2.0
2.5
Related to VEE2
Clamp filter time
235
275
ns
ns
4) 5)
CLAMP reaction time in tCLAMP_ON 16 +
CLAMP mode
23 +
tCLAMPfilter
35 +
tCLAMPfilter
C
C
= 100 pF
= 100 pF
LOAD
tCLAMPfilter
4) 6)
4)
CLAMP reaction time in tCLAMPD_ON 24 +
CLAMP driver mode
35 +
tCLAMPfilter
53 +
tCLAMPfilter
ns
µs
µs
LOAD
tCLAMPfilter
Switch-off time-out
time
tCTT
–
–
2.4
–
–
Switch-off time-out
soꢀ-off offset time
tCTSOOS
2.4
4) additional time-out
delay during soꢀ-off
1) Integrated diode CLAMP vs. VCC2 clamping test
2) only valid for direct clamping: IN = High, OUT = High
3) only valid for clamp pre-driver output: IN = Low, OUT = Low
4) Parameter is not subject to production test - verified by design/characterization
5) CLAMP mode reaction time specified with 3.3 kΩ pull-up from CLAMP to 3.3 V, from CLAMP threshold until
reaching 0.8 V (falling) at CLAMP pin
Datasheet
35
v2.1
2021-02-15
EiceDRIVER™ 1ED34x1Mc12M Enhanced
Datasheet
5 Electrical parameters
6) CLAMP driver mode reaction time specified from CLAMP threshold until reaching 0.8 V (rising) at
CLAMP(DRV) pin
5.4.6
Dynamic characteristics
Dynamic characteristics are measured with VVCC1 = 5 V, VVCC2 = 15 V and VVEE2 = -8 V unless specified otherwise.
Table 16
Dynamic characteristics
Symbol
Parameter
Values
Typ.
Unit
Note or Test
Condition
Min.
Max.
Input pulse suppression tINMIN
time IN
98
85
103
108
115
ns
ns
–
–
Input pulse suppression tRDYCMIN
,
100
1.0
time RDYC/FLT_N for
enable / fault off
tFLT_NMIN
Input pulse width RDYC
for FLT_N reset (Fault
clear time)
tCLRMIN
–
1.2
µs
Input IN to output
propagation delay ON
tPDON
226
218
-23
244
236
-8
270
262
7
ns
ns
ns
CLOAD = 100 pF, VIN
70%, VOUT=20%
=
=
Input IN to output
propagation delay OFF
tPDOFF
tPDISTO
CLOAD = 100 pF, VIN
30%, VOUT=80%
Input to output
CLOAD = 100 pF
propagation delay
distortion (tPDOFF - tPDON
)
Input IN to output
propagation delay
distortion between any
devices (tPDON-tPDON) or
tPDD
–
–
30
ns
1) same conditions
(VIN, VVCC1, VVCC2 and
VVEE2, CLOAD, TA)
(tPDOFF-tPDOFF
)
1)
State synchronization
time between input and
output
tSSIO
–
–
13
µs
ns
ns
Input RDYC to output on tPDRDYC
propagation delay
447
323
523
361
600
407
CLOAD = 100 pF; IN
high; VRDYC = 70%,
VOUT=20%
Input RDYC or FLT_N
to Soꢀ-off output
propagation delay
tPDRDYCS
tPDFLT_NS
,
CLOAD = 100 pF, VSignal
= 30%, VOUT=80%,
Soꢀ-off function
ICSOFF,15
Input RDYC or FLT_N to
hard switch-off output
propagation delay
tPDRDYCH
tPDFLT_NH
,
303
–
342
15
384
30
ns
ns
CLOAD = 100 pF, VSignal
= 30%, VOUT=80%,
OFF function
Rise time 1ED3431M
tRISE
CLOAD = 1 nF, VOUT:
20% to 80%
Datasheet
36
v2.1
2021-02-15
EiceDRIVER™ 1ED34x1Mc12M Enhanced
Datasheet
5 Electrical parameters
Table 16
Dynamic characteristics (continued)
Parameter
Symbol
Values
Typ.
Unit
Note or Test
Condition
Min.
Max.
Fall time 1ED3431M
Rise time 1ED3461M
Fall Time 1ED3461M
Rise Time 1ED3491M
Fall Time 1ED3491M
tFALL
tRISE
tFALL
tRISE
tFALL
–
–
–
–
–
15
15
15
15
15
30
30
30
30
30
ns
ns
ns
ns
ns
CLOAD = 1 nF, VOUT:
80% to 20%
CLOAD = 2.2 nF, VOUT
20% to 80%
:
:
:
:
CLOAD = 2.2 nF, VOUT
80% to 20%
CLOAD = 3.3 nF, VOUT
20% to 80%
CLOAD = 3.3 nF, VOUT
80% to 20%
1) Parameter is not subject to production test - verified by design/characterization
5.4.7
Desaturation protection
All parameters valid for VCC1 = 5 V, VCC2 = 15 V, and VEE2 = 0 V unless specified otherwise.
Table 17
Desaturation protection
Symbol
Parameter
Values
Typ.
Unit
Note or Test
Condition
Min.
Max.
DESAT charge current
IDESATC
470
259
500
525
366
µA
kΩ
VDESAT = 0 V
DESAT voltage divider RDVD
resistance
312.5
between DESAT and
GND2 pins
DESAT clamp and
discharge ON
resistance
RDSON,D
–
7.7
25.0
Ω
IDESATD = 200 mA
DESAT threshold level VDESAT
8.88
356
9.18
400
650
1150
225
9.48
444
V
–
DESAT leading edge
blanking time
tDESATleb,d
tDESATleb,s
tDESATleb,l
ns
ns
ns
ns
ADJB depending, VON
20% rising to VDESAT
= 1 V, CLOAD = 100 pF,
CDESAT = 2 pF,
597
703
1077
1223
263
DESAT filter time
(default)
tDESATfilter,def 190
ADJB = VCC1
DESAT filter time (ADJB tDESATfilter,A 1476
1575
1775
1975
2375
2775
3175
1684
1895
2105
2526
2947
3368
ns
ns
ns
ns
ns
ns
ADJB depending
adjustable)
tDESATfilter,B 1667
tDESATfilter,C 1857
tDESATfilter,D 2238
tDESATfilter,E 2619
tDESATfilter,F 3000
Datasheet
37
v2.1
2021-02-15
EiceDRIVER™ 1ED34x1Mc12M Enhanced
Datasheet
5 Electrical parameters
Table 17
Desaturation protection (continued)
Symbol Values
Typ.
3575
Parameter
Unit
Note or Test
Condition
Min.
Max.
3789
tDESATfilter,G 3381
tDESATfilter,H 3762
ns
ns
ns
3975
743
4211
883
DESAT sense to FLT_N
tDESATFLT
623
VFLT_N = 30%, IFLT _N
= 5 mA, tDESATfilter,def
CFLT_N = 100 pF
low delay
,
DESAT sense to OFF low tDESATOUTS
delay, Soꢀ-off
287 +
tDESATfilter
333 +
tDESATfilter
382 +
tDESATfilter
ns
VOUT = 80%, CLOAD
100 pF, ICSOFF,15
=
Datasheet
38
v2.1
2021-02-15
EiceDRIVER™ 1ED34x1Mc12M Enhanced
Datasheet
5 Electrical parameters
5.4.8
Soꢀ-off current source
Soꢀ-off current source values specified at OFF pin at VOFF = 3 V with unipolar supply of VVCC2 = 15 V.
Table 18
Current source turn-off
Parameter
Symbol
Values
Typ.
Unit
Note or Test
Condition
Min.
Max.
Soꢀ-off current source
current 1ED3431M
ICSOFF,0
ICSOFF,1
ICSOFF,2
ICSOFF,3
ICSOFF,4
ICSOFF5
ICSOFF,6
ICSOFF,7
ICSOFF,8
ICSOFF,9
ICSOFF,10
ICSOFF,11
ICSOFF,12
ICSOFF,13
ICSOFF,14
ICSOFF,15
ICSOFF,0
ICSOFF,1
ICSOFF,2
ICSOFF,3
ICSOFF,4
ICSOFF,5
ICSOFF,6
ICSOFF,7
ICSOFF,8
ICSOFF,9
ICSOFF,10
ICSOFF,11
ICSOFF,12
ICSOFF,13
ICSOFF,14
10
24
35
47
58
70
82
93
15
19
36
52
70
87
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
depends on resistor
value at ADJA
29
44
58
73
87
105
122
140
157
175
192
210
227
245
262
280
36
102
116
131
146
160
175
189
204
218
233
29
105
116
128
140
151
163
175
186
22
Soꢀ-off current source
current 1ED3461M
depends on resistor
value at ADJA
45
58
72
70
87
105
140
175
210
245
280
314
349
384
419
454
489
524
93
116
146
175
204
233
262
291
320
349
379
408
437
116
140
163
186
210
233
256
280
303
326
349
Datasheet
39
v2.1
2021-02-15
EiceDRIVER™ 1ED34x1Mc12M Enhanced
Datasheet
5 Electrical parameters
Table 18
Current source turn-off (continued)
Parameter
Symbol
Min.
Values
Typ.
Unit
Note or Test
Condition
Max.
559
ICSOFF,15
ICSOFF,0
ICSOFF,1
ICSOFF,2
ICSOFF,3
ICSOFF,4
ICSOFF,5
ICSOFF,6
ICSOFF,7
ICSOFF,8
ICSOFF,9
ICSOFF,10
ICSOFF,11
ICSOFF,12
ICSOFF,13
ICSOFF,14
ICSOFF,15
373
34
466
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
Soꢀ-off current source
current 1ED3491M
44
54
depends on resistor
value at ADJA
70
87
105
157
210
262
314
367
419
472
524
577
629
681
734
786
839
105
140
175
210
245
280
314
349
384
419
454
489
524
559
131
175
218
262
306
349
393
437
480
524
568
612
655
699
5.4.9
Over-temperature protection
Table 19
Over-temperature protection
Parameter1)
Symbol
Values
Typ.
160
Unit
Note or Test
Condition
Min.
150
Max.
170
Over-temperature
protection level
TOTPOFF
°C
1) Parameter is not subject to production test - verified by design/characterization
Datasheet
40
v2.1
2021-02-15
EiceDRIVER™ 1ED34x1Mc12M Enhanced
Datasheet
6 Insulation characteristics
6
Insulation characteristics
The following isolation classes are available for the 1ED34x1Mc12M family (X3 Analog).
Table 20
Product isolation classes
Marking Insulation characteristics
Product name
Values specified in
UL values
Table 23
Table 23
1ED34x1MU12M 34x1MU12
UL 1577 certified insulation
Reinforced insulation
-
1ED34x1MC12M
34x1MC12
Table 22
Table 21
Safety limiting values
This coupler is suitable for rated insulation only within the given safety ratings. Compliance with the safety
ratings shall be ensured by means of suitable protective circuits.
Description
Symbol
TS
Characteristic
Unit
°C
Maximum ambient safety temperature
Maximum input-side power dissipation at TA = 25°C
Maximum output-side power dissipation at TA = 25°C1)
150
PSI
100
mW
mW
A
PSO
1000
Maximum driver output current (ON, OFF)2)
IOUT
1ED3431MC
1ED3461MC
1ED3491MC
2.4
4.8
7.2
1) IC output-side power dissipation is derated linearly at 8 mW/°C above 65 °C
2) Maximum pulse length of t = 5 µs
6.1
Certified according to VDE 0884-11 reinforced insulation (pending)
Valid for parts with part name 1ED34x1MC12M, x indicate different variants.
This coupler is suitable for safe electrical insulation only within the safety ratings. Compliance with the safety
ratings shall be ensured by means of suitable protective circuits.
Table 22
Reinforced insulation according to VDE 0884-11
Symbol
Description
Characteristic
Unit
Installation classification per EN 60664-1, Table 1
for rated mains voltage ≤ 150 V (rms)
for rated mains voltage ≤ 300 V (rms)
for rated mains voltage ≤ 600 V (rms)
for rated mains voltage ≤1000 V (rms)
–
I-IV
I-IV
I-III
I-II
Climatic classification
40/125/21
–
Pollution degree (EN 60664-1)
Minimum external clearance
Minimum external creepage
Minimum comparative tracking index
2
–
CLR
CPG
CTI
>8
>8
400
mm
mm
–
Datasheet
41
v2.1
2021-02-15
EiceDRIVER™ 1ED34x1Mc12M Enhanced
Datasheet
6 Insulation characteristics
Table 22
Reinforced insulation according to VDE 0884-11 (continued)
Description
Symbol
Characteristic
Unit
Apparent charge, method a
qC
<5
nC
Vpd(ini),a = VIOTM, Vpd(m) = 4500 V, tini = 1 min
Apparent charge, method b
qC
<5
nC
Vpd(ini),b = VIOTM × 1.2, Vpd(m) = 4500 V, tini = 1 s
Isolation resistance at TA,max
RIO
> 1011
> 109
8000
1767
6875
Ω
Isolation resistance at TS
RIO_S
VIOTM
VIORM
VIOSM
Ω
Maximum rated transient isolation voltage
Maximum repetitive insulation voltage
V (peak)
V (peak)
V (peak)
Maximum surge isolation voltage for reinforced isolation
VTEST = VIOSM × 1.6
Insulation capacitance
CIO
1.7
pF
6.2
Recognized under UL 1577 (File E311313)
Table 23
Recognized under UL 1577
Description
Symbol
VISO
Characteristic
Unit
Insulation withstand voltage/1 min
Insulation test voltage/1 s
5700
6840
V (rms)
V (rms)
VISO, TEST
Datasheet
42
v2.1
2021-02-15
EiceDRIVER™ 1ED34x1Mc12M Enhanced
Datasheet
7 Package information
7
Package information
1)
1)
6.4
7.5
0.35 x 45°
0.7±0.2
Seating plane
Coplanarity
Bottom View
16
9
9
16
Pin1 Marking
1
8
8
1
2)
0.65
0.33±0.08
1) Does not include plastic or metal protrusion of 0.15 max. per side
2) Dambar protrusion shall be maximum 0.1 mm total in excess of lead width
All dimensions are in units mm
The drawing is in compliance with ISO 128-30, Projection Method 1 [
]
Figure 24
PG-DSO-16-28/33 - 300 mil 16-pin fine pitch plastic green dual small outline package
Datasheet
43
v2.1
2021-02-15
EiceDRIVER™ 1ED34x1Mc12M Enhanced
Datasheet
8 Application notes
8
Application notes
8.1
Reference layout for thermal data
Figure 25
Reference layout for thermal data (Two layer PCB; copper thickness 35 μm; leꢀ: top
layer; right: bottom layer)
The PCB layout represents the reference layout used for the thermal characterization. Pins 1 and 8 (GND1)
and pins 9 and 16 (VEE2) require ground plane connections for achieving maximum power dissipation. The
1ED34x1Mc12M family (X3 Analog) is conceived to dissipate most of the heat generated through these pins.
8.2
Printed circuit board guidelines
Following factors should be taken into account for an optimum PCB layout.
•
•
Sufficient spacing should be kept between high voltage isolated side and low voltage side circuits.
The same minimum distance between two adjacent high-side isolated parts of the PCB should be
maintained to increase the effective isolation and reduce parasitic coupling.
•
In order to ensure low supply ripple and clean switching signals, bypass capacitor trace lengths should be
kept as short as possible.
Revision history
Revision history
Reference
Description
v2.1
•
•
•
•
Change footnotes to table notes
added param VOFFSET
update package drawing to latest revision
update certification status
v2.0
v1.0
v0.8
Editorial changes
Parameter tables completed and editorial changes in functional description
Editorial changes in functional description and parameter tables
Datasheet
44
v2.1
2021-02-15
Trademarks
All referenced product or service names and trademarks are the property of their respective owners.
Edition 2021-02-15
Published by
IMPORTANT NOTICE
WARNINGS
The information given in this document shall in no
event be regarded as a guarantee of conditions or
characteristics (“Beschaffenheitsgarantie”).
With respect to any examples, hints or any typical
values stated herein and/or any information regarding
the application of the product, Infineon Technologies
hereby disclaims any and all warranties and liabilities
of any kind, including without limitation warranties of
non-infringement of intellectual property rights of any
third party.
In addition, any information given in this document is
subject to customer’s compliance with its obligations
stated in this document and any applicable legal
requirements, norms and standards concerning
customer’s products and any use of the product of
Infineon Technologies in customer’s applications.
Due to technical requirements products may contain
dangerous substances. For information on the types
in question please contact your nearest Infineon
Technologies office.
Except as otherwise explicitly approved by Infineon
Technologies in a written document signed by
authorized representatives of Infineon Technologies,
Infineon Technologies’ products may not be used in
any applications where a failure of the product or
any consequences of the use thereof can reasonably
be expected to result in personal injury.
Infineon Technologies AG
81726 Munich, Germany
©
2021 Infineon Technologies AG
All Rights Reserved.
Do you have a question about any
aspect of this document?
Email: erratum@infineon.com
Document reference
IFX-fiz1584344472005
The data contained in this document is exclusively
intended for technically trained staff. It is the
responsibility of customer’s technical departments to
evaluate the suitability of the product for the intended
application and the completeness of the product
information given in this document with respect to such
application.
相关型号：
SI9130DB
5- and 3.3-V Step-Down Synchronous ConvertersWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1-E3
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135_11
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9136_11
Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130CG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130LG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130_11
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137DB
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137LG
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9122E
500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
©2020 ICPDF网 联系我们和版权申明