1EDC20I12MH [INFINEON]
1200 V单边高侧栅极驱动器IC，具有UL认证的电流隔离、有源米勒箝位和短路箝位;
| 型号： | 1EDC20I12MH |
| 厂家： | 
Infineon |
| 描述： | 1200 V单边高侧栅极驱动器IC，具有UL认证的电流隔离、有源米勒箝位和短路箝位 栅极驱动 驱动器 |
| 文件： | 总19页 (文件大小：506K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
1EDCxxI12MH
EiceDRIVER™ 1EDC Compact
Single channel IGBT gate driver IC with clamp in wide body package
Features
•
•
•
•
•
•
•
•
Single channel isolated gate driver
For 600 V/650 V/1200 V IGBTs, MOSFETs, and SiC MOSFETs
Up to 6 A typical peak current at rail-to-rail output
Active Miller clamp
Galvanically isolated coreless transformer driver
Wide input voltage operating range
Suitable for operation at high ambient temperature and in fast switching applications
Recognized under UL 1577 with an insulation test voltage of VISO = 3000 V (rms) for 1 s
Potential applications
•
•
•
•
•
•
AC and brushless DC motor drives
High voltage DC/DC-converter and DC/AC-inverter
Induction heating resonant application
UPS-systems
Welding
Solar
Product type
1EDC10I12MH
1EDC20I12MH
1EDC30I12MH
Minimum output current and configuration
±1.0 A with 1.0 A Miller clamp
Package
PG-DSO-8-59
PG-DSO-8-59
PG-DSO-8-59
±2.0 A with 2.0 A Miller clamp
±3.0 A with 3.0 A Miller clamp
Product validation
Qualified for industrial applications according to the relevant tests of JEDEC47/20/22.
Datasheet
Please read the Important Notice and Warnings at the end of this document
2.1
www.infineon.com/eicedriver
2017-09-04
EiceDRIVER™ 1EDC Compact
Single channel IGBT gate driver IC with clamp in wide body package
Description
Description
The 1EDCxxI12MH are galvanically isolated single channel IGBT driver in a PG-DSO-8-59 package that provide
output currents up to 3 A and an integrated active Miller clamp circuit with the same current rating to protect
against parasitic turn on.
The input logic pins operate on a wide input voltage range from 3 V to 15 V using scaled CMOS threshold levels
to support even 3.3 V microcontrollers.
Data transfer across the isolation barrier is realized by the coreless transformer technology.
Every driver family member comes with logic input and driver output undervoltage lockout (UVLO) and active
shutdown.
VCC1
VCC2,H
OUT
IN+
IN-
Single channel
with CLAMP
EiceDRIVERTM
CLAMP
GND1
VCC1
GND2,H
VCC2,L
Control
OUT
IN+
IN-
Single channel
with CLAMP
EiceDRIVERTM
CLAMP
GND1
GND2,L
Figure 1
Typical application
Datasheet
2
2.1
2017-09-04
EiceDRIVER™ 1EDC Compact
Single channel IGBT gate driver IC with clamp in wide body package
Table of contents
Table of contents
Table of contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2
2.1
2.2
Pin configuration and functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pin functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
3
3.1
3.2
3.2.1
3.2.2
3.2.3
3.2.4
3.3
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Protection features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Undervoltage lockout (UVLO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Active shut-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Short circuit clamping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Active Miller clamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Non-inverting and inverting inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Driver output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
3.4
4
4.1
4.2
4.3
4.3.1
4.3.2
4.3.3
4.3.4
4.3.5
4.3.6
4.3.7
Electrical parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Operating parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Voltage supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Logic input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Gate driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Short circuit clamping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Active Miller clamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Active shut down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5
6
Recognized under UL 1577 (File E311313) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
7
7.1
7.2
Application notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Reference layout for thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Printed circuit board guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Datasheet
3
2.1
2017-09-04
EiceDRIVER™ 1EDC Compact
Single channel IGBT gate driver IC with clamp in wide body package
Block diagram
1
Block diagram
VCC2
2V
VCC1
1
2
UVLO
CLAMP
8
&
GND2
VCC2
input
filter
IN+
&
active
TX
RX
GND1
filter
&
VCC1
OUT
7
input
filter
IN-
3
4
GND2
VCC2
GND2
UVLO
6
5
GND1
Figure 2
Block diagram
Datasheet
4
2.1
2017-09-04
EiceDRIVER™ 1EDC Compact
Single channel IGBT gate driver IC with clamp in wide body package
Pin configuration and functionality
2
Pin configuration and functionality
2.1
Pin configuration
Table 1
Pin configuration
Pin No. Name
Function
1
2
3
4
5
6
7
8
VCC1
IN+
Positive logic supply
Non-inverted driver input (active high)
Inverted driver input (active low)
Logic ground
IN-
GND1
GND2
VCC2
OUT
Power ground
Positive power supply voltage
Driver output
CLAMP
Active Miller clamp
1
2
3
4
VCC1
IN+
CLAMP
OUT
8
7
6
5
IN-
VCC2
GND2
GND1
Figure 3
PG-DSO-8-59 (top view)
2.2
Pin functionality
VCC1
Logic input supply voltage of 3.3 V up to 15 V wide operating range.
IN+ non inverting driver input
IN+ non-inverted control signal for driver output if IN- is set to low. (Output sourcing active at IN+ = high and
IN- = low)
Due to internal filtering a minimum pulse width is defined to ensure robustness against noise at IN+. An internal
weak pull-down-resistor favors off-state.
IN- inverting driver input
IN- inverted control signal for driver output if IN+ is set to high. (Output sourcing active at IN- = low and
IN+ = high)
Due to internal filtering a minimum pulse width is defined to ensure robustness against noise at IN-. An internal
weak pull-up-resistor favors off-state.
Datasheet
5
2.1
2017-09-04
EiceDRIVER™ 1EDC Compact
Single channel IGBT gate driver IC with clamp in wide body package
Pin configuration and functionality
GND1
Ground connection of input circuit.
GND2 reference ground
Reference ground of the output driving circuit.
VCC2
Positive power supply pin of output driving circuit. A proper blocking capacitor has to be placed close to this
supply pin.
OUT driver output
Combined source and sink output pin to external IGBT. The output voltage will be switched between VCC2 and
GND2 and is controlled by IN+ and IN-. In case of an UVLO event this output will be switched off and an active
shut down keeps the output voltage at a low level.
CLAMP active Miller clamp
Connect gate of external IGBT directly to this pin. As soon as the gate voltage has dropped below 2 V referred to
GND2 during turn off state the Miller clamp function ties its output to GND2 to avoid parasitic turn on of the
connected IGBT.
Datasheet
6
2.1
2017-09-04
EiceDRIVER™ 1EDC Compact
Single channel IGBT gate driver IC with clamp in wide body package
Functional description
3
Functional description
The 1EDCxxI12MH is a general purpose IGBT gate driver. Basic control and protection features support fast and
easy design of highly reliable systems.
The integrated galvanic isolation between control input logic and driving output stage grants additional safety.
Its wide input voltage supply range supports the direct connection of various signal sources like DSPs and
microcontrollers.
With the rail-to-rail output and the additional active Miller clamp, dynamic turn on due to Miller capacitance is
suppressed.
3.1
Supply
The driver can operate over a wide supply voltage range.
10R
+5 V
VCC1
OUT
100n
CLAMP
SGND
IN
GND1
IN+
+15 V
VCC2
GND2
1µ
IN-
Figure 4
Application example
The typical positive supply voltage for the driver is 15 V at VCC2. Erratical dynamic turn on of the IGBT can be
prevented with the active Miller clamp function, in which the CLAMP output is directly connected to the IGBT
gate.
Datasheet
7
2.1
2017-09-04
EiceDRIVER™ 1EDC Compact
Single channel IGBT gate driver IC with clamp in wide body package
Functional description
3.2
Protection features
3.2.1
Undervoltage lockout (UVLO)
IN+
VUVLOH1
VUVLOL1
VCC1
VUVLOH2
VUVLOL2
VCC2
OUT
Figure 5
UVLO behavior
To ensure correct switching of IGBTs the device is equipped with an undervoltage lockout for input and output
independently. Operation starts only aꢀer both VCC levels have increased beyond the respective VUVLOH levels
If the power supply voltage VVCC1 of the input chip drops below VUVLOL1 a turn-off signal is sent to the output
chip before power-down. The IGBT is switched off and the signals at IN+ and IN- are ignored until VVCC1 reaches
the power-up voltage VUVLOH1 again.
If the power supply voltage VVCC2 of the output chip goes down below VUVLOL2 the IGBT is switched off and
signals from the input chip are ignored until VVCC2 reaches the power-up voltage VUVLOH2 again.
3.2.2
Active shut-down
The active shut-down feature ensures a safe IGBT off-state if the output chip is not connected to the power
supply or an undervoltage lockout is in effect. The IGBT gate is clamped at OUT to GND2.
3.2.3
Short circuit clamping
During short circuit the IGBT’s gate voltage tends to rise because of the feedback via the Miller capacitance. An
additional protection circuit connected to OUT and CLAMP limits this voltage to a value slightly higher than the
supply voltage. A maximum current of 500 mA may be fed back to the supply through one of these paths for
10 μs. If higher currents are expected or tighter clamping is desired external Schottky diodes may be added.
3.2.4
Active Miller clamp
In a half bridge configuration the switched off IGBT tends to dynamically turn on during turn on phase of the
opposite IGBT. A Miller clamp allows sinking the Miller current across a low impedance path in this high dV/dt
situation. Therefore in many applications, the use of a negative supply voltage can be avoided. During turn-off,
the gate voltage is monitored and the clamp output is activated when the gate voltage drops below typical 2 V
(referred to GND2). The clamp is designed for a Miller current in the same range as the nominal output current.
Datasheet
8
2.1
2017-09-04
EiceDRIVER™ 1EDC Compact
Single channel IGBT gate driver IC with clamp in wide body package
Functional description
3.3
Non-inverting and inverting inputs
IN+
IN-
OUT
Figure 6
Logic input to output switching behavior
There are two possible input modes to control the IGBT. At non-inverting mode IN+ controls the driver output
while IN- is set to low. At inverting mode IN- controls the driver output while IN+ is set to high. A minimum input
pulse width is defined to filter occasional glitches.
3.4
Driver output
The output driver section uses MOSFETs to provide a rail-to-rail output. This feature permits that tight control of
gate voltage during on-state and short circuit can be maintained as long as the driver’s supply is stable. Due to
the low internal voltage drop, switching behavior of the IGBT is predominantly governed by the gate resistor.
Furthermore, it reduces the power to be dissipated by the driver.
Datasheet
9
2.1
2017-09-04
EiceDRIVER™ 1EDC Compact
Single channel IGBT gate driver IC with clamp in wide body package
Electrical parameters
4
Electrical parameters
4.1
Absolute maximum ratings
Note:
Absolute maximum ratings are defined as ratings, which when being exceeded may lead to
destruction of the integrated circuit. Unless otherwise noted all parameters refer to GND1
Table 2
Absolute maximum ratings
Parameter
Symbol
Values
Max.
201)
Unit Note or
Test Condition
Min.
2)
2)
Power supply output side
Gate driver output
VVCC2
VOUT
-0.3
V
VGND2-0.3 VVCC2+0.3
V
Maximum short circuit clamping time
Positive power supply input side
Logic input voltages (IN+,IN-)
Pin CLAMP voltage
tCLP
–
10
μs
V
ICLAMP/OUT = 500 mA
VVCC1
VLogicIN
VCLAMP
-0.3
-0.3
-0.3
18.0
18.0
–
V
–
2)
VVCC2
V
+0.31)
Junction temperature
Storage temperature
TJ
-40
-55
400
150
150
–
°C
°C
–
–
TS
Comparative tracking index
CTI
IEC 60601-1: Material
group II
Power dissipation (Input side)
Power dissipation (Output side)
Thermal resistance (Input side)
Thermal resistance (Output side)
ESD capability
PD, IN
–
–
–
–
–
–
25
400
145
165
2
mW
mW
K/W
K/W
kV
3) @TA = 25°C
3) @TA = 25°C
3) @TA = 85°C
3) @TA = 85°C
PD, OUT
RTHJA,IN
RTHJA,OUT
VESD,HBM
VESD,CDM
Human body model4)
1
kV
Charged device
model5)
1
May be exceeded during short circuit clamping.
With respect to GND2.
See Figure 10 for reference layouts for these thermal data. Thermal performance may change significantly
with layout and heat dissipation of components in close proximity.
According to EIA/JESD22-A114-C (discharging a 100 pF capacitor through a 1.5 kΩ series resistor).
According to EIA/JESD22-C101 (specified waveform characteristics)
2
3
4
5
Datasheet
10
2.1
2017-09-04
EiceDRIVER™ 1EDC Compact
Single channel IGBT gate driver IC with clamp in wide body package
Electrical parameters
4.2
Operating parameters
Note:
Within the operating range the IC operates as described in the functional description. Unless
otherwise noted all parameters refer to GND1.
Table 3
Operating parameters
Parameter
Symbol
Values
Max.
Unit Note or
Test Condition
Min.
13
6)
Power supply output side
Power supply input side
Logic input voltages (IN+,IN-)
Pin CLAMP voltage
VVCC2
VVCC1
VLogicIN
VCLAMP
fsw
18
17
17
V
3.1
V
–
-0.3
V
–
7)
6)
VGND2-0.3 VVCC2
V
8)9)
Switching frequency
–
1.0
125
4.8
100
MHz
°C
K/W
Ambient temperature
TA
-40
–
–
Thermal coefficient, junction-top
Common mode transient immunity
Ψth,jt
|dVISO/dt|
9)@TA = 85°C
–
kV/μs 9) @ 1000 V
4.3
Electrical characteristics
Note:
The electrical characteristics include the spread of values in supply voltages, load and junction
temperatures given below. Typical values represent the median values at TA = 25°C. Unless otherwise
noted all voltages are given with respect to their respective GND (GND1 for pins 1 to 3, GND2 for pins 6
to 8).
4.3.1
Voltage supply
Table 4
Voltage supply
Parameter
Symbol
Values
Typ.
Unit Note or Test
Condition
Min.
Max.
3.1
UVLO threshold input chip
VUVLOH1
VUVLOL1
VHYS1
–
2.85
V
V
V
–
–
–
2.55
0.09
2.75
0.10
–
–
UVLO hysteresis input chip
(VUVLOH1 - VUVLOL1
)
6
With respect to GND2.
May be exceeded during short circuit clamping.
do not exceed max. power dissipation
7
8
9
Parameter is not subject to production test - verified by design/characterization
Datasheet
11
2.1
2017-09-04
EiceDRIVER™ 1EDC Compact
Single channel IGBT gate driver IC with clamp in wide body package
Electrical parameters
Table 4
Voltage supply (continued)
Symbol
Parameter
Values
Typ.
Unit Note or Test
Condition
Min.
Max.
12.7
10)
UVLO threshold output chip (IGBT VUVLOH2
–
11.9
V
supply)
10)
VUVLOL2
10.5
0.7
11.0
0.85
–
–
V
UVLO hysteresis output chip
(VUVLOH1 - VUVLOL1
VHYS2
V
–
)
Quiescent current input chip
IQ1
–
0.6
1
mA
VVCC1 = 5 V
IN+ = High, IN- = Low
=>OUT = High
Quiescent current output chip
IQ2
–
1.2
2
mA
VVCC2 = 15 V
IN+ = High, IN- = Low
=>OUT = High
4.3.2
Logic input
V
IN+L ,VIN-L
VIN+H ,VIN-H
0.7×15V
10
UVLO
No driver
operation
5
0.3×15V
0.7×5V
0.7×3.3V
0.3×5V
0.3×3.3V
15
10
3.3
5
VVCC1
Figure 7
VCC1 scaled input threshold voltage of IN+ and IN-
Beginning from the input undervoltage lockout level, threshold levels for IN+ and IN- are scaled to VVCC1. The
high input threshold is 70% of VVCC1 and the low input threshold is at 30% of VVCC1
.
10
With respect to GND2.
Datasheet
12
2.1
2017-09-04
EiceDRIVER™ 1EDC Compact
Single channel IGBT gate driver IC with clamp in wide body package
Electrical parameters
Table 5
Logic input
Parameter
Symbol
Values
Typ.
Unit Note or Test
Condition
Min.
Max.
0.3 ×
VVCC1
IN+,IN- low input voltage
IN+,IN- high input voltage
IN+,IN- low input voltage
IN+,IN- high input voltage
VIN+L
,
–
–
–
–
–
11)3.1 V ≤ VVCC1 ≤ 17 V
VIN-L
VIN+H
VIN-H
,
0.7 ×
VVCC1
–
VIN+L
VIN-L
,
–
1.5
–
V
V
VVCC1 = 5.0 V
VIN+H
VIN-H
,
3.5
IN- input current
IN+ input current
IIN-
–
–
70
70
200
200
μA
μA
VVCC1 = 5.0 V, VIN- =
GND1
IIN+
VVCC1 = 5.0 V, VIN+ =
VVCC1
4.3.3
Gate driver
Note:
minimum Peak current rating valid over temperature range!
Table 6
Gate driver
Parameter
Symbol
Values
Typ.
Unit Note or Test
Condition
Min.
Max.
12)
High level output peak current
(source)
1EDC10I12MH
1EDC20I12MH
1EDC30I12MH
IOUT,H,PEAK
–
–
A
IN+ = High,
IN- = Low,
VVCC2 = 15 V
1.0
2.0
3.0
2.2
4.4
5.9
12)
Low level output peak current
(sink)
1EDC10I12MH
1EDC20I12MH
1EDC30I12MH
IOUT,L,PEAK
A
IN+ = Low,
IN- = Low,
VVCC2 = 15 V
1.0
2.0
3.0
2.3
4.1
6.2
11
Parameter is not subject to production test - verified by design/characterization
specified min. output current is forced; voltage across the device V(VCC2 - OUT) or V(OUT - GND2) < VVCC2
12
.
Datasheet
13
2.1
2017-09-04
EiceDRIVER™ 1EDC Compact
Single channel IGBT gate driver IC with clamp in wide body package
Electrical parameters
4.3.4
Short circuit clamping
Table 7
Short circuit clamping
Parameter
Symbol
Values
Typ.
Unit Note or Test
Condition
Min.
Max.
1.3
Clamping voltage (OUT)
(VOUT - VVCC2
VCLPout
–
–
–
0.9
V
V
V
13)IN+ = High, IN- =
Low,
IOUT = 500 mA
(pulse test tCLPmax
10 μs)
13)IN+ = High, IN- =
Low,
ICLAMP = 500 mA
)
=
=
Clamping voltage (CLAMP)
(VVCLAMP - VVCC2
VCLPclamp1
1.3
0.7
–
)
(pulse test tCLPmax
10 μs)
13)IN+ = High, IN- =
Clamping voltage (CLAMP)
VCLPclamp2
1.1
Low,
ICLAMP = 20 mA
4.3.5
Active Miller clamp
Table 8
Active Miller clamp
Parameter
Symbol
Values
Typ.
Unit Note or Test
Condition
Min.
Max.
14)
ICLAMP,PEAK
–
–
A
Low level clamp current
1EDC10I12MH
1EDC20I12MH
IN+ = Low,
IN- = Low,
VCLAMP = 15 V
1.0
2.0
3.0
1EDC30I12MH
pulsed tpulse = 2 μs
15)
Clamp threshold voltage
VCLAMP
1.6
2.0
2.4
V
13
With respect to GND2.
Parameter is not subject to production test - verified by design/characterization
With respect to GND2.
14
15
Datasheet
14
2.1
2017-09-04
EiceDRIVER™ 1EDC Compact
Single channel IGBT gate driver IC with clamp in wide body package
Electrical parameters
4.3.6
Dynamic characteristics
Dynamic characteristics are measured with VVCC1 = 5 V and VVCC2 = 15 V.
50%
IN+
80%
50%
20%
OUT
tRISE
tFALL
tPDON
tPDOFF
Figure 8
Propagation delay, rise and fall time
Table 9
Dynamic characteristics
Symbol
Parameter
Values
Typ.
Unit Note or Test
Condition
Min.
270
Max.
Input IN to output propagation
delay ON
tPDON
300
330
330
40
ns
ns
ns
ns
CLOAD = 100 pF
VIN+ = 50%,
VOUT=50% @ 25°C
Input IN to output propagation
delay OFF
tPDOFF
tPDISTO
270
-30
230
300
5
Input IN to output propagation
delay distortion (tPDOFF - tPDON
)
Input pulse suppression time IN+, tMININ+
,
240
–
IN-
tMININ-
tPDONt
16)
IN input to output propagation
delay ON variation due to temp
–
–
–
–
–
–
14
14
8
ns
ns
ns
C
= 100 pF
LOAD
VIN+ = 50%,
VOUT=50%
IN input to output propagation
delay OFF variation due to temp
tPDOFFt
tPDISTOt
IN input to output propagation
delay distortion variation due to
temp (tPDOFF-tPDON
)
Rise time
tRISE
tFALL
5
3
10
9
20
19
ns
ns
CLOAD = 1 nF
VL 20%, VH 80%
Fall time
4.3.7
Active shut down
Table 10
Active shut down
Parameter
Symbol
Values
Typ.
2.0
Unit Note or Test
Condition
Min.
Max.
2.3
17)
Active shut down voltage
VACTSD
–
V
I
/IOUT-,PEAK=0.1,
OUT-
VCC2 open
16
Parameter is not subject to production test - verified by design/characterization
With respect to GND2.
17
Datasheet
15
2.1
2017-09-04
EiceDRIVER™ 1EDC Compact
Single channel IGBT gate driver IC with clamp in wide body package
Recognized under UL 1577 (File E311313)
5
Recognized under UL 1577 (File E311313)
Table 11
Recognized under UL 1577
Description
Symbol
VISO
Characteristic
2500
Unit
Insulation Withstand Voltage / 1 min
Insulation Test Voltage / 1 s
V (rms)
V (rms)
VISO
3000
Datasheet
16
2.1
2017-09-04
EiceDRIVER™ 1EDC Compact
Single channel IGBT gate driver IC with clamp in wide body package
Package outline
6
Package outline
DOCUMENT NO.
Z8B00179262
0
MILLIMETERS
DIM
INCHES
SCALE
MIN
-
MAX
MIN
-
MAX
0.104
0.008
0.096
0.020
0.013
0.252
0.417
0.299
A
A1
A2
b
2.65
0.20
2.45
0.50
0.32
6.40
10.60
7.60
2
0.10
2.25
0.30
0.23
6.20
10.00
7.40
0.004
0.089
0.012
0.009
0.244
0.394
0.291
0
2
4mm
c
D
EUROPEAN PROJECTION
E
E1
e
1.27 BSC
8
0.050 BSC
8
N
L
0.50
0.90
0.020
0.035
L2
h
0.25 BSC
0.010 BSC
ISSUE DATE
05.11.2015
0.25
0.45
0.010
0.018
Ĭ
ꢀ
ꢁ
ꢀ
ꢁ
REVISION
01
ccc
ddd
0.10
0.25
0.004
0.010
Figure 9
PG-DSO-8-59 (Plastic (green) dual small outline package)
Datasheet
17
2.1
2017-09-04
EiceDRIVER™ 1EDC Compact
Single channel IGBT gate driver IC with clamp in wide body package
Application notes
7
Application notes
7.1
Reference layout for thermal data
Figure 10 Reference layout for thermal data (Copper thickness 35 μm)
This PCB layout represents the reference layout used for the thermal characterization.
Pin 4 (GND1) and pin 5 (GND2) require each a ground plane of 100 mm² for achieving maximum power
dissipation. The package is built to dissipate most of the heat generated through these pins.
The thermal coefficient junction-top (Ψth,jt) can be used to calculate the junction temperature at a given top
case temperature and driver power dissipation:
T j = Ψth,jt ⋅ PD + Ttop
7.2
Printed circuit board guidelines
The following factors should be taken into account for an optimum PCB layout.
•
•
Sufficient spacing should be kept between high voltage isolated side and low voltage side circuits.
The same minimum distance between two adjacent high-side isolated parts of the PCB should be
maintained to increase the effective isolation and to reduce parasitic coupling.
•
In order to ensure low supply ripple and clean switching signals, bypass capacitor trace lengths should be
kept as short as possible.
Revision history
Document
version
Date of
release
Description of changes
2.1
2017-09-04
Increase of typical gate driver output current values; formatting updated for
electrical parameters and pins
2.0
1.0
0.5
2017-07-17
2017-03-28
2016-10-04
UL file number added
Comparative tracking index added
initial version
Datasheet
18
2.1
2017-09-04
Trademarks
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Edition 2017-09-04
Published by
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