1EDN7116U_技术文档

1EDN71x6U EiceDRIVER^™

200 V high-side TDI gate driver IC for GaN SG HEMTs and MOSFETs

Features

•

Optimized for driving GaN SG HEMTs and Si MOSFETs

Fully diꢀerential logic input circuitry to avoid false triggering

in low-side or high-side operation

•

High common-mode input voltage range (CMR) up to ꢁ22 ꢂ

for high side operation

High immunity to common-mode voltage transitions (122

ꢂ/ns) for robust operation during fast switching

•

Compatible with 3.3 ꢂ or 5 ꢂ input logic

Four driving strength variants to optimize switching speed

without external gate resistors - up to ꢁ A source/sink current

capability

•

Active bootstrap clamp to avoid bootstrap capacitor

overcharging during dead-time

Active Miller clamp with 5 A sink capability to avoid induced

turn-on

Qualified for industrial applications according to the relevant

tests of JEDEC47/ꢁ2/ꢁꢁ

Description

™

The 1EDN71x6U is a single-channel gate-driver IC optimized for driving Infineon CoolGaN Schottky Gate

HEMTs, as well as other GaN SG HEMTs and Si MOSFETs. This gate driver includes several key features that

enable a high-performance system design with GaN SG HEMTs, including Truly Diꢀerential Input, four driving

strength options, active Miller clamp, and bootstrap voltage clamp.

Potential applications

•

Single channel:

•

Half-bridge (ꢁ x 1EDN71x6U):

-

Synchronous rectifier

Class-E resonant wireless power

-

DC-DC converter

BLDC/PMSM motor drive

Class-D audio amplifier

Class-D resonant wireless power

Product portfolio

Part number

1EDN7116U

1EDN71ꢁ6U

1EDN7136U

1EDN7146U

Peak source/sink current

Input pulse blanking time

Package

PG-TSNP-7

ꢁ.2 A

1.5 A

1.2 A

2.5 A

ꢁ2 ns

42 ns

62 ns

82 ns

Datasheet

www.infineon.com

Please read the sections "Important notice" and "Warnings" at the end of this document

Rev. ꢁ.2

ꢁ2ꢁꢁ-27-ꢁ2

1EDN71x6U EiceDRIVER^™

200 V high-side TDI gate driver IC for GaN SG HEMTs and MOSFETs

Table of contents

Table of contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ꢁ

1

Pin configuration and description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

2

Product information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

Truly diꢀerential input (TDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Undervoltage lockout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Minimum input pulse . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Driver outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Active Miller clamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Active bootstrap clamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Unpowered gate clamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

ꢁ.1

ꢁ.ꢁ

ꢁ.3

ꢁ.4

ꢁ.5

ꢁ.6

ꢁ.7

ꢁ.8

3

General product characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

ESD ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Thermal resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Static electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1ꢁ

Driver output characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3.1

3.ꢁ

3.3

3.4

3.5

3.6

3.7

4

Typical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

5

Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ꢁ4

Typical application circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .ꢁ4

Selection of TDI input resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ꢁ6

Selection of ꢂDD bypass capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ꢁ6

Selection of external bootstrap diode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ꢁ7

Selection of bootstrap capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .ꢁ7

Selection of external gate resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .ꢁ8

PCB layout recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ꢁ9

5.1

5.ꢁ

5.3

5.4

5.5

5.6

5.7

6

7

Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3ꢁ

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

Disclaimer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Datasheet

ꢁ

Rev. ꢁ.2

ꢁ2ꢁꢁ-27-ꢁ2

1EDN71x6U EiceDRIVER^™

200 V high-side TDI gate driver IC for GaN SG HEMTs and MOSFETs

1 Pin configuration and description

1

Pin configuration and description

Figure 1

Table 1

Pin configuration 1EDN71X6U in PG-TSNP-7 package, top view

Pin definitions and functions

Name

Function

1

ꢁ

3

4

5

ꢂDD

IN+

IN-

Gate drive supply.

Connected to PWM output of controller via 47 kΩ or 75 kΩ resistor.

Connected to controller ground via 47 kΩ or 75 kΩ resistor.

Return path for ꢂDD and thermal dissipation pad.

ꢂSS

BST

Bootstrap diode anode connection point, when used as a low-side

driver in a half-bridge configuration.

6

7

OUT_SNK

OUT_SRC

Low-impedance gate pull-down to ꢂSS (including active Miller clamp).

Low-impedance gate pull-up to ꢂDD.

Datasheet

3

Rev. ꢁ.2

ꢁ2ꢁꢁ-27-ꢁ2

1EDN71x6U EiceDRIVER^™

200 V high-side TDI gate driver IC for GaN SG HEMTs and MOSFETs

2 Product information

2

Product information

2.1

Functional description

™

The 1EDN71x6U is a single-channel gate-driver IC optimized for compatibility with Infineon CoolGaN SG

HEMTs, as well as other GaN HEMTs and Silicon MOSFETs. Thanks to the truly diꢀerential input feature, the

gate driver output state is exclusively controlled by the voltage diꢀerence between the two inputs, independent

of the driver’s reference (ground) potential as long as the common-mode voltage is below 152 ꢂ (static) and ꢁ22

ꢂ (dynamic). This eliminates the risk of false triggering due to ground bounce in low-side applications, while

also allowing 1EDN71x6U to address even high-side applications.

The product is equipped with several key features especially designed to enhance the performance of

™

CoolGaN SG HEMTs:

•

four driving strength variants to optimize switching speed without external gate resistors

active bootstrap clamping to avoid overcharging the bootstrap capacitor during dead-time

an active Miller clamp with exceptionally strong pull-down to avoid induced turn-on

Figure 2

Typical circuit for low-side single-channel application using 1EDN71X6U to drive a

™

CoolGaN SG HEMT

2.2

Truly diꢀerential input (TDI)

The TDI feature oꢀers common-mode voltage rejection up to 152 ꢂ for static voltage and ꢁ22 ꢂ for dynamic

voltage transients, enabling both low-side and high-side gate driving without the need for a digital isolator at

the input. The dynamic voltage rating is relevant for any voltage spikes shorter than the specified blanking time

(that is, minimum pulse width). When used as a low-side gate driver, the TDI greatly enhances ground bounce

immunity during fast GaN switching transitions.

At the positive and negative signal inputs two symmetrical resistor dividers are used to scale down and

compensate common mode bouncing voltages. A fully diꢀerential amplifier stage provides high common mode

rejection and high sensitivity to diꢀerential input signals. The amplified diꢀerential output voltage is finally

evaluated by the subsequent diꢀerential Schmitt-Trigger circuit.

At the IN+ and IN- pins, two external resistors R_in1and R_inꢁare used to scale down common mode voltages

of up to 152 ꢂ to a level which can be processed by low voltage CMOS circuitry. These input resistors serve

the function of "blocking" the high common-mode voltage, so that the IN+ and IN- pins of the driver are not

exposed to this high voltage. As such, the selection of these resistors is critical to the proper operation of the

TDI circuit.

Datasheet

4

Rev. ꢁ.2

ꢁ2ꢁꢁ-27-ꢁ2

1EDN71x6U EiceDRIVER^™

200 V high-side TDI gate driver IC for GaN SG HEMTs and MOSFETs

2 Product information

Figure 3

Functional block diagram

The resistance values for R_in1and R_inꢁmust be selected based on the logic level of the input signals. For a

3.3 ꢂ logic, both external input resistors must be 47 kΩ. For a 5 ꢂ logic, they must be 75 kΩ. Furthermore,

R_in1and R_inꢁmust be very closely matched. A tolerance of 2.1 ꢃ is required to maintain control over the

full common mode swing. Resistors with wider tolerance limit the common-mode range of the TDI driving

circuit. Any asymmetries in these resistors may cause a a common-mode voltage to be interpreted as an input

signal, including stray impedances in the PCB layout. Recommendations for a PCB layout are given later in this

datasheet.

To compensate for small asymmetries in the TDI circuit, low pass filters are used to further enhance the high

frequency common mode rejection. Two diꢀerent input filter options are available to accommodate diꢀerent

designs, with a total blanking time of ꢁ2 ns for 1EDN7116U, 42 ns for 1EDN71ꢁ6U, 62 ns for 1EDN7136U, and 82

ns for 1EDN7146U.

2.3

Undervoltage lockout

The undervoltage lockout (UꢂLO) functions ensure that the output can be switched to its high level only if the

ꢂDD supply voltage exceeds the UꢂLO threshold voltage.

The UꢂLO ensures that the transistors are not switched on if the driving voltage is too low, thereby avoiding

excessive power dissipation due to linear-mode operation. The UꢂLO must be inactive to allow the propagation

of the input control signals (IN+, IN-) to the output.

The ꢂDD UꢂLO level is set to a typical value of 3.85 ꢂ, with a maximum of 4.2 ꢂ. The maximum value of the rising

edge is the value that ensures all the device among the production is turned on during start up. The designer

must provide a voltage higher than 4.2 ꢂ to turn on all the devices in the production of their equipment within

the specified temperature range. On the opposite side, the minimum voltage necessary to switch oꢀ all the

devices is the minimum of the falling edge, which is 3.6 ꢂ. Therefore, a voltage lower than 3.6 ꢂ ensures that the

driver does not start switching. Once the driver has exceeded the UꢂLO, the supply voltage must remain above

the maximum falling edge level of 3.9 ꢂ to avoid a UꢂLO shutdown. The hysteresis is the voltage gap between

rising edge and falling edge, which ensures some margin on noise eꢀects such as false turn oꢀ.

Datasheet

5

Rev. ꢁ.2

ꢁ2ꢁꢁ-27-ꢁ2

1EDN71x6U EiceDRIVER^™

200 V high-side TDI gate driver IC for GaN SG HEMTs and MOSFETs

2 Product information

The output states depend on the inputs configuration and the status of the ꢂDD UꢂLO. The truth table of the

driver is represented below.

Table 2

Input logic truth table

Diꢀerential input

UVLO VDD

ACTIꢂE

OUT_SNK

OUT_SRC

BST

HiZ

L

X

L

HiZ

L

HiZ

H

INACTIꢂE

H

HiZ

H

Where:

•

UꢂLO active means V_DD< UꢂLOꢂDDL

UꢂLO inactive means V_DD> UꢂLOꢂDDH

Diꢀerential input = L means (ꢂ_IN+- ꢂ_IN-) < input logic threshold

Diꢀerential input = H means (ꢂ_IN+- ꢂ_IN-) > input logic threshold

2.4

Minimum input pulse

The minimum input pulse is the shortest duration pulse at the diꢀerential input that will generate an output

pulse. Pulses with durations shorter than the minimum pulse are neglected and therefore will not generate any

output pulse. Once the input pulse has suꢀicient duration to be propagated, the duration of the output pulse is

equal to the duration of the input pulse, having therefore a linear transfer function between input and output.

The minimum input pulse is specified here as "shortest input pulse transferred to the output." The maximum

value for this parameter is the pulse width at which all the drivers in production will provide an output signal.

In other words, the designer must provide a pulse width longer than the maximum specified value to ensure

an output pulse for every driver of their equipment. Likewise, any pulses shorter than the minimum specified

value will be ignored by all drivers in production. This minimum specification can be treated as the guaranteed

blanking time for de-glitching, which helps to prevent spurious switching during common-mode transient

events.

2.5

Driver outputs

The output stage of the driver has a peak source and sink current as defined for the given product variant,

which corresponds to an equivalent resistance of the pull-up and pull-down transistor. The designer can

optimize the switching speed of the driven transistor by selecting one of the four product variants, without the

need for external gate resistors. If external gate resistors are used, it is highly recommended to avoid placing

a resistor in the output sinking path, as this limits the eꢀectiveness of the active Miller clamp described in the

next section.

Source and sink outputs are actively held low with a clamp in case of floating inputs or during startup or power

down. Under any situation, outputs are held under defined conditions to avoid unstable or unknown behavior

of the driven transistor.

2.6

Active Miller clamp

The sink output of the gate driver has an active Miller clamp feature to provide high immunity to spurious

turn-on events. During a turn-oꢀ transition, the peak sinking current and equivalent pull-down resistance

is defined according to the product variant. However, once the driver detects that the gate voltage (at the

sink output) has fallen below 2.4 ꢂ, the active Miller clamp is engaged within 3 ns, increasing the strength

of the Sink output significantly. With the clamp engaged, all four product variants can sink up to 5 A, with

an equivalent pull-down resistance of 2.3 Ω. This feature allows the designer to optimize the turn-oꢀ speed

without sacrificing the driver's "keep-oꢀ" strength. If an external gate resistor is placed at the sink output, the

eꢀectiveness of the active Miller clamp is reduced.

Datasheet

6

Rev. ꢁ.2

ꢁ2ꢁꢁ-27-ꢁ2

1EDN71x6U EiceDRIVER^™

200 V high-side TDI gate driver IC for GaN SG HEMTs and MOSFETs

2 Product information

2.7

Active bootstrap clamp

When using the bootstrapping technique to supply the high-side gate driver in a half-bridge topology, it is

sometimes necessary to regulate the bootstrap capacitor voltage to avoid damaging the gate of the high-side

transistor. This is especially important for GaN transistors for two reasons:

1.

GaN SG HEMTs are oꢄen sensitive to gate over-voltage, with driving voltages typically in the range of 5 ꢂ

+/- 1 ꢂ.

2.

The "body diode" mechanism of GaN transistors causes a higher voltage drop than MOSFETs, which

leads to excessive over-charging of the bootstrap capacitor during dead-time conduction.

In a half-bridge configuration, the bootstrap capacitor is normally charged during the low-side switch

conduction time. Figure 4 shows this charging path, which includes the power supply (ꢂDD), the bootstrap

diode, current-limiting resistor, the bootstrap capacitor, and the low-side switch. When the low-side switching

is turned fully on, the voltage applied to the bootstrap capacitor is slightly lower than ꢂDD, due to the drop

across the bootstrap diode, which can be partially compensated by the drop across the low-side transistor.

However, during dead-time intervals, the low-side transistor operates in "body diode" mode, with a voltage

drop in the range of 1.5 ~ ꢁ.5 ꢂ, or even higher when a negative oꢀ-state ꢂ_GSis applied. This causes

over-charging of the bootstrap capacitor during the dead-time, resulting in a bootstrap voltage that varies

significantly with dead-time duration and operating current, with a high risk of exceeding the maximum rated

V_GSof the driven transistor.

This is not a problem for a typical MOSFET, since the operating range of the gate is fairly wide. However, this

variable bootstrap capacitor voltage may pose a serious risk of damage to GaN Schottky gates. Therefore, it is

necessary to apply some form of regulation to this circuit. For example, a Zener diode can be used as shown

in Figure 4 , as long as the dead-time interval is well-controlled and paired with a current-limiting resistor that

avoids overheating the Zener diode.

The 1EDN71X6U driver oꢀers an alternative bootstrap clamping scheme. Figure 5 shows the implementation of

this bootstrap clamping scheme in a half-bridge circuit. The clamp circuit avoids over-charging the bootstrap

capacitor instead of directly regulating the capacitor voltage, which would likely contribute additional losses.

Rather than connecting the bootstrap diode to the ꢂDD supply rail, it is connected to the BST output of the

low-side driver. The BST output operates as a clone of the source and sink output pins, synchronized to the

timing of the low-side transistor turning on and oꢀ. Therefore, the bootstrap diode can only conduct current

when the low-side transistor is turned fully on, but not when it is operating in "body diode" mode during

dead-time.

The active bootstrap clamping scheme is very useful in regulating the high-side driving voltage without the

need for additional components. However, in applications where over-charging of the bootstrap capacitor is

desired, the bootstrap diode can be connected to the ꢂDD pin instead of the BST pin. A Zener-based regulation

scheme is recommended in this case, as shown in Figure 4.

Datasheet

7

Rev. ꢁ.2

ꢁ2ꢁꢁ-27-ꢁ2

1EDN71x6U EiceDRIVER^™

200 V high-side TDI gate driver IC for GaN SG HEMTs and MOSFETs

2 Product information

Figure 4

Half-bridge with Zener bootstrap regulation

Datasheet

8

Rev. ꢁ.2

ꢁ2ꢁꢁ-27-ꢁ2

1EDN71x6U EiceDRIVER^™

200 V high-side TDI gate driver IC for GaN SG HEMTs and MOSFETs

2 Product information

Figure 5

Half-bridge with active bootstrap clamping

2.8

Unpowered gate clamp

The unpowered gate clamp circuit ensures that the driver output is pulled low when no supply voltage is

applied to the driver. It is common practice to place a resistor between the gate and source of transistors to

ensure that there is no spurious voltage when the system is powered oꢀ. However, this is not necessary with the

1EDN71x6U. The driver has an internal pull-down MOSFET between the OUT_SNK pin and ꢂSS pin, which pulls

down the gate voltage to ꢂSS with a peak current capability of 3 mA, whenever ꢂDD is not suꢀiciently supplied

to turn on the driver. Once the 1EDN71x6U is fully powered on, this pull-down MOSFET is disabled.

OUT_SNK

Power_on

VSS

Figure 6

Functional diagram of unpowered gate clamp circuit

Datasheet

9

Rev. ꢁ.2

ꢁ2ꢁꢁ-27-ꢁ2

1EDN71x6U EiceDRIVER^™

200 V high-side TDI gate driver IC for GaN SG HEMTs and MOSFETs

3 General product characteristics

3

General product characteristics

3.1

Absolute maximum ratings

All voltages are referred to ꢂSS unless otherwise specified.

Table 3

Absolute maximum ratings

Parameter

Symbol

Values

Unit

Note or condition

Min. Typ. Max.

Driver supply

V_DD

-2.3

–

1ꢁ

ꢂ

Driver supply, V_DD

transient

13.ꢁ

< 3 ns

ꢂoltage at IN+ V_IN+

-8.5

-2.3

–

-

8.5

ꢂ

ꢂoltage at IN- V_IN-

ꢂoltage at

OUT_SRC,

V_{OUT_SRC}

,

ꢂDD + ꢂ

2.3

V_{OUT_SNK}

OUT_SNK, BST V_BST

pins

Junction

temperature

T_J

-42

-55

–

152

ꢁ62

^oC

Storage

temperature

T_S

^oC

Soldering

temperature

3.2

Recommended operating conditions

The following operating conditions must not be exceeded to ensure correct operation and reliability of the

device. All parameters specified in the following tables refer to these operating conditions, unless noted

otherwise.

Table 4

Recommended operating conditions

Parameter

Symbol

Values

Unit

Note or condition

Min. Typ. Max.

Supply voltage V_DD

4.ꢁ

–

11

15

ꢂ

1)

Operating

frequency

F_SW

MHz

Common

mode voltage

range (static)

CMR

-152

–

152

ꢂ

R_ext= 47k 2.1ꢃ, V_logic= 3.3 ꢂ.

(table continues...)

1

ꢂerified by design/characterization. Not subject to production test.

12

Datasheet

Rev. ꢁ.2

ꢁ2ꢁꢁ-27-ꢁ2

1EDN71x6U EiceDRIVER^™

200 V high-side TDI gate driver IC for GaN SG HEMTs and MOSFETs

3 General product characteristics

Table 4

(continued) Recommended operating conditions

Parameter

Symbol

Values

Unit

Note or condition

Min. Typ. Max.

Common

mode voltage

range

CMR_dyn

-ꢁ22

–

ꢁ22

ꢂ

R_ext= 47k 2.1ꢃ, V_logic= 3.3 ꢂ.

Duration of voltage transient event must be

shorter than specified blanking time. ¹⁾

(dynamic)

1)

Common

mode voltage

slew rate

CMSR

–

122

ꢂ/ns

3.3

ESD ratings

Table 5

ESD ratings

Symbol

ESD_HBM

ESD_CDM

Description

Value

1522

1222

Unit

Human Body Model sensitivity as per ANSI/ESDA/JEDEC JS-221

Charged Device Model sensitivity as per ANSI/ESDA/JEDEC JS-22ꢁ

ꢂ

3.4

Thermal resistance

Table 6

Parameter

Thermal resistance

Symbol

Values

Unit

Note or condition

Min. Typ. Max.

Junction-to-

ambient

thermal

R_thJA

–

82

–

°C/W

JEDEC ꢁsꢁp with thermal vias. ²⁾

resistance

Junction-to-

case thermal

resistance -

bottom

R_thJC(BOT)

ꢁ8

°C/W

Junction-to-

case thermal

resistance - top

R_thJC(TOP)

114

1

ꢂerified by design/characterization. Not subject to production test.

Obtained in a simulation on a JEDEC-standard ꢁsꢁp four-layer PCB with thermal vias, as specified in JESD51-7, in an environment

described in JESD51-ꢁa.

2

Datasheet

11

Rev. ꢁ.2

ꢁ2ꢁꢁ-27-ꢁ2

1EDN71x6U EiceDRIVER^™

200 V high-side TDI gate driver IC for GaN SG HEMTs and MOSFETs

3 General product characteristics

3.5

Static electrical characteristics

V_DD- V_SS= 5 ꢂ, T_c= - 42^oC to 1ꢁ5ºC unless otherwise specified.

Table 7

Static electrical characteristics

Parameter

Symbol

Values

Unit

Note or condition

Min. Typ. Max.

Undervoltage lockout thresholds

ꢂDD supply

UꢂLO rising

threshold

UVLO_ꢂDDH

3.7

3.6

3.85

4

ꢂ

ꢂDD supply

UꢂLO falling

threshold

UVLO_ꢂDDL

3.75 3.9

Current consumption

ꢂDD quiescent I_QDD

current

–

1.8

ꢁ.6

mA

IN+ = IN- = 2 ꢂ.

ꢂDD current

consumption

when

I_ODD

f_SW= 522 kHz, no load on OUT_SRC/

OUT_SNK and no load on BST.

Apply PWM to IN+, set IN- = 2 ꢂ.

Common mode = 2 ꢂ.

switching

Input characteristics

Diꢀerential

input voltage

threshold for

low-high

ΔV_RinH

ΔV_RinL

1.7

1.ꢁ

1.1

2.7

1.95 ꢁ.ꢁ

1.95 ꢁ.65

1.35 1.6

1.35 ꢁ.15

ꢂ

Thresholds valid for R_EXT= 47 kΩ.

ꢂCM = 2 ꢂ and T = ꢁ5 ºC.

transition

Diꢀerential

input voltage

threshold for

low-high

Thresholds valid for R_EXT= 47 kΩ.

ꢂCM = -152 ꢂ to 152 ꢂ.

transition

Diꢀerential

input voltage

threshold for

high-low

Thresholds valid for R_EXT= 47 kΩ.

ꢂCM = 2 ꢂ and T = ꢁ5 ºC.

transition

Diꢀerential

input voltage

threshold for

high-low

Thresholds valid for R_EXT= 47 kΩ.

ꢂCM = -152 ꢂ to 152 ꢂ.

transition

Datasheet

1ꢁ

Rev. ꢁ.2

ꢁ2ꢁꢁ-27-ꢁ2

1EDN71x6U EiceDRIVER^™

200 V high-side TDI gate driver IC for GaN SG HEMTs and MOSFETs

3 General product characteristics

3.6

Driver output characteristics

Table 8

Driver output characteristics

Parameter

Symbol

Typical values

1EDN7116U 1EDN7126U 1EDN7136U 1EDN7146U

Unit Note or

condition

Peak source

current

I_{OUT_SRC}

ꢁ

5

1.5

5

1

5

2.5

5

A

ꢂDD = 5 ꢂ,

OUT_SRC = 2 ꢂ ¹⁾

Peak sink

current

I_{OUT_SNK}

ꢂDD = 5 ꢂ,

OUT_SNK = 5 ꢂ ¹⁾

Peak sink

current w/

Miller clamp

I_{OUT_SNK}

ꢂDD = 5 ꢂ,

OUT_SNK = 5 ꢂ ¹⁾

_MC

Pull-up

resistance

R_PU

2.8

2.7

1.1

1.2

2.3

1.6

1.5

2.3

3.3

3.2

2.3

Ω

I_SRC = 122 mA

I_SNK = 122 mA

Pull-down

resistance

R_PD

Pull-down

resistance w/

Miller clamp

R_{PD_MC}2.3

1)

Active Miller

clamp voltage

threshold

V_{MC_TH}2.4

2.4

3

2.4

3

2.4

3

ꢂ

Active Miller

clamp

propagation

delay

T_MCD

3

ns

No load. ¹⁾

Unpowered

gate clamp

sinking current

I_{OUT_SNK}

3

mA

ꢂDD floating. 1.ꢁ

ꢂ applied

externally to

OUT_SNK.

_UGC

Rise time

Fall time

T_R

T_F

3

4

5.5

11

ns

OUT_SRC and

OUT_SNK

shorted. C_L= 1

nF, ꢂDD = 5 ꢂ ¹⁾

BST peak

source current

I_{BST_SRC}

ꢁ

A

ꢂDD = 5 ꢂ, BST = 2

ꢂ ¹⁾

BST peak sink I_{BST_SNK}

current

ꢁ

A

ꢂDD = 5 ꢂ, BST = 5

ꢂ ¹⁾

BST pull-up

resistance

R_{BST_PU}2.8

2.8

2.7

2.8

2.7

2.8

2.7

Ω

I_BST_SRC = 122

mA

BST pull-down R_{BST_PD}2.7

resistance

I_BST_SNK = 122

mA

1) ꢂerified by design/characterization. Not subject to production test.

Datasheet

13

Rev. ꢁ.2

ꢁ2ꢁꢁ-27-ꢁ2

1EDN71x6U EiceDRIVER^™

200 V high-side TDI gate driver IC for GaN SG HEMTs and MOSFETs

3 General product characteristics

3.7

Timing characteristics

Timings are obtained considering OUT_SRC and OUT_SNK shorted together, C_LOAD= 2 nF and over common

mode range -152 ꢂ to 152 ꢂ, ꢂDD = 5 ꢂ, R_EXT= 47 kΩ unless specified otherwise.

Table 9

Timing characteristics

Parameter

Symbol

Values

Unit

Note or condition

Min. Typ. Max.

Startup time,

aꢄer UꢂLO

threshold is

reached

t_ST

1ꢁ

ꢁ2

μs

ꢂSS = 2 ꢂ, T_j= ꢁ5^oC.

–

Turn-on

propagation

delay

matching OUT

to BST

ΔT_{LH_BST}

-ꢁ

–

ꢁ

ns

Calculated as TLH - TLH_BST.

ꢂCM = 2 ꢂ, T_j= ꢁ5ºC.

Turn-oꢀ

propagation

delay

ΔT_{HL_BST}

-ꢁ

–

ꢁ

Calculated as THL - THL_BST.

ꢂCM = 2 ꢂ, T_j= ꢁ5ºC.

matching OUT

to BST

1EDN7116U

Turn-on

propagation

delay

TLH

53

55

2

57

ꢁ.ꢁ

ꢁ5

ns

ꢂCM = 2 ꢂ, T_j= ꢁ5ºC.

Turn-oꢀ

propagation

delay

THL

53

Propagation

delay

matching

ΔTLH_HL

-ꢁ.ꢁ

ꢁ2

Calculated as TLH - THL.

ꢂCM = 2 ꢂ, T_j= ꢁ5ºC.

Shortest input TPW_MIN

pulse

–

ꢂCM = 2 ꢂ, T_j= ꢁ5ºC.

transferred to

the output

1EDN7126U

Turn-on

propagation

delay

TLH

THL

73

75

77

ns

ꢂCM = 2 ꢂ, T_j= ꢁ5ºC.

Turn-oꢀ

propagation

delay

(table continues...)

Datasheet

14

Rev. ꢁ.2

ꢁ2ꢁꢁ-27-ꢁ2

1EDN71x6U EiceDRIVER^™

200 V high-side TDI gate driver IC for GaN SG HEMTs and MOSFETs

3 General product characteristics

Table 9

(continued) Timing characteristics

Parameter

Symbol

Values

Unit

Note or condition

Min. Typ. Max.

Propagation

delay

matching

ΔTLH_HL

-ꢁ.8

–

ꢁ.8

ns

Calculated as TLH - THL.

ꢂCM = 2 ꢂ, T_j= ꢁ5ºC.

Shortest input TPW_MIN

pulse

42

47

ꢂCM = 2 ꢂ, T_j= ꢁ5ºC.

transferred to

the output

1EDN7136U

Turn-on

propagation

delay

TLH

121

-3.4

62

125

–

129

3.4

71

ns

ꢂCM = 2 ꢂ, T_j= ꢁ5ºC.

Turn-oꢀ

propagation

delay

THL

Propagation

delay

matching

ΔTLH_HL

Calculated as TLH - THL.

ꢂCM = 2 ꢂ, T_j= ꢁ5ºC.

Shortest input TPW_MIN

pulse

–

ꢂCM = 2 ꢂ, T_j= ꢁ5ºC.

transferred to

the output

1EDN7146U

Turn-on

propagation

delay

TLH

1ꢁ1

-3.8

82

1ꢁ5

–

1ꢁ9

3.8

93

ns

ꢂCM = 2 ꢂ, T_j= ꢁ5ºC.

Turn-oꢀ

propagation

delay

THL

Propagation

delay

matching

ΔTLH_HL

Calculated as TLH - THL.

ꢂCM = 2 ꢂ, T_j= ꢁ5ºC.

Shortest input TPW_MIN

pulse

–

ꢂCM = 2 ꢂ, T_j= ꢁ5ºC.

transferred to

the output

Datasheet

15

Rev. ꢁ.2

ꢁ2ꢁꢁ-27-ꢁ2

1EDN71x6U EiceDRIVER^™

200 V high-side TDI gate driver IC for GaN SG HEMTs and MOSFETs

4 Typical characteristics

4

Typical characteristics

Figure 7

Diꢀerential input voltage threshold versus temperature

Figure 8

Diꢀerential input voltage threshold versus common mode voltage

Datasheet

16

Rev. ꢁ.2

ꢁ2ꢁꢁ-27-ꢁ2

1EDN71x6U EiceDRIVER^™

200 V high-side TDI gate driver IC for GaN SG HEMTs and MOSFETs

4 Typical characteristics

Figure 9

Quiescent current versus temperature

Figure 10

Quiescent current versus supply voltage

Datasheet

17

Rev. ꢁ.2

ꢁ2ꢁꢁ-27-ꢁ2

1EDN71x6U EiceDRIVER^™

200 V high-side TDI gate driver IC for GaN SG HEMTs and MOSFETs

4 Typical characteristics

Figure 11

Operating current with load versus frequency

Figure 12

Turn-on propagation delay versus temperature

Datasheet

18

Rev. ꢁ.2

ꢁ2ꢁꢁ-27-ꢁ2

1EDN71x6U EiceDRIVER^™

200 V high-side TDI gate driver IC for GaN SG HEMTs and MOSFETs

4 Typical characteristics

Figure 13

Turn-oꢀ propagation delay versus temperature

Figure 14

Turn-on propagation delay versus common mode voltage

Datasheet

19

Rev. ꢁ.2

ꢁ2ꢁꢁ-27-ꢁ2

1EDN71x6U EiceDRIVER^™

200 V high-side TDI gate driver IC for GaN SG HEMTs and MOSFETs

4 Typical characteristics

Figure 15

Turn-oꢀ propagation delay versus common mode voltage

Figure 16

OUT_SRC pull-up resistance versus temperature

Datasheet

ꢁ2

Rev. ꢁ.2

ꢁ2ꢁꢁ-27-ꢁ2

1EDN71x6U EiceDRIVER^™

200 V high-side TDI gate driver IC for GaN SG HEMTs and MOSFETs

4 Typical characteristics

Figure 17

OUT_SNK pull-down resistance versus temperature (before active Miller clamp is

engaged)

Figure 18

OUT_SNK pull-down resistance versus temperature (aꢁer Miller clamp is engaged)

Datasheet

ꢁ1

Rev. ꢁ.2

ꢁ2ꢁꢁ-27-ꢁ2

1EDN71x6U EiceDRIVER^™

200 V high-side TDI gate driver IC for GaN SG HEMTs and MOSFETs

4 Typical characteristics

Figure 19

BST pull-up and pull-down resistance versus temperature

Figure 20

Undervoltage lockout threshold versus temperature

Datasheet

ꢁꢁ

Rev. ꢁ.2

ꢁ2ꢁꢁ-27-ꢁ2

1EDN71x6U EiceDRIVER^™

200 V high-side TDI gate driver IC for GaN SG HEMTs and MOSFETs

4 Typical characteristics

Figure 21

Shortest input pulse transferred to output versus temperature

Datasheet

ꢁ3

Rev. ꢁ.2

ꢁ2ꢁꢁ-27-ꢁ2

1EDN71x6U EiceDRIVER^™

200 V high-side TDI gate driver IC for GaN SG HEMTs and MOSFETs

5 Application information

5

Application information

5.1

Typical application circuits

The 1EDN71x6U can be used as a single low-side driver or a single high-side driver, and two can be used

together to drive a half-bridge. Figure ꢁꢁ depicts an example circuit schematic for a single-device driver. Figure

4 and Figure 5 show two examples of half-bridge circuit schematics with two 1EDN71x6U, with conventional

bootstrapping and Zener regulation in the first, and active bootstrap clamping enabled in the second. Figure

ꢁ3 shows an additional example of half-bridge implementation, in this case with cross-connected PWM inputs

for the high-side and low-side drivers. This option adds robustness against accidental cross-conduction in case

the controller ever generates overlapping PWM signal. However, it may also limit the minimum dead-time as

measured at the gate signals of the driven devices, due to asymmetrical turn-on and turn-oꢀ delay times of the

driven transistors.

Figure 22

Single channel application circuit

Datasheet

ꢁ4

Rev. ꢁ.2

ꢁ2ꢁꢁ-27-ꢁ2

1EDN71x6U EiceDRIVER^™

200 V high-side TDI gate driver IC for GaN SG HEMTs and MOSFETs

5 Application information

Figure 23

Half-bridge with cross-connected signal inputs and active bootstrap clamping

Figure 24

TDI application circuit, including input external resistors and stray capacitance

Datasheet

ꢁ5

Rev. ꢁ.2

ꢁ2ꢁꢁ-27-ꢁ2

1EDN71x6U EiceDRIVER^™

200 V high-side TDI gate driver IC for GaN SG HEMTs and MOSFETs

5 Application information

5.2

Selection of TDI input resistors

The 1EDN71X6U requires precise input resistors at the IN+ and IN- pins, with resistance values of 47 kΩ or

75 kΩ, depending on the voltage level of the input logic signals. The driver is compatible with either a 3.3 ꢂ

or a 5 ꢂ logic. These resistors are not optional, even if the application does not require the TDI function (for

example low-side applications with no ground bounce concerns). The input logic thresholds at the IN+ and

IN- pins are designed to be paired with the specified input resistor values. These input resistors should be

selected with a 2.1ꢃ tolerance, especially in high-side applications, where the common-mode voltage rating is

contingent upon tight matching of R_IN1and R_IN1. Extra care should be taken to ensure that these resistors are

symmetrical, so that stray capacitance across them is also tightly matched. Figure ꢁ4 shows an example of how

stray capacitances C_p1and C_pꢁcould interfere with the symmetry and matching of R_IN1and R_INꢁ. To optimize

this symmetry, the two resistors should have identical part numbers with the same package and footprint.

Further PCB layout recommendations for ensuring symmetry are given later.

In high-side applications, the input resistors must also be rated for the power dissipation expected in the

worst-case operating conditions. The common-mode voltage observed by the high-side transistor is "blocked"

by each input resistor, so that the 1EDN71X6U is not exposed to the high voltage. The resistors dissipate power

during the intervals where CM voltage is high, typically during the high-side transistor's duty ratio of each

switching period. The power rating of the resistors should therefore be selected based on

2

V_{dc, max}

P_Rin1= P_Rin2

=

× D

R_in1

Equation 1

where:

P_Rin1= Required power rating for R_in1

P_Rinꢁ= Required power rating for R_inꢁ

D = High-side duty ratio

V_dc,max= Maximum expected dc bus voltage, experienced as CM voltage during the high-side duty ratio

It is important to consider that the duty ratio may not be constant, so D should be selected as the duty ratio

when operating at the maximum dc bus voltage.

The table below lists some examples for selecting the input resistors, based on logic voltage level, expected dc

bus voltage, and duty ratio. For most applications, the power requirement is quite low, thereby allowing the

designer to select very small resistor packages such as 242ꢁ or 2623. In some extreme scenarios with a high dc

voltage and high duty ratio simultaneously, larger packages with higher power ratings may be needed.

Table 10

Examples for selected input resistors

Maximum dc bus

voltage

Logic

voltage

TDI input

resistance

Resistor

tolerance

Minimum Rin

power rating

Duty ratio

62 ꢂ

82 ꢂ

3.3 ꢂ

5 ꢂ

2.ꢁ5

2.75

47 kΩ

2.1ꢃ

2.2ꢁ W

2.21 W

2.12 W

2.26 W

75 kΩ

3.3 ꢂ

5 ꢂ

47 kΩ

75 kΩ

5.3

Selection of VDD bypass capacitor

The ꢂDD bypass capacitor provides the gate charge to drive the transistor, as well as additional power

consumption by the driver itself. It should be placed as close as possible to the ꢂDD and ꢂSS pins of the gate

driver, which may require a particular footprint size for most applications.

The minimum value for this bypass capacitor can be calculated based on the maximum allowable voltage

ripple in the design. This ripple should be minimized such that the lowest possible ꢂDD is above the UꢂLO

limit of the gate driver as well as above the safe driving voltage of the transistor. The charge dissipated per

Datasheet

ꢁ6

Rev. ꢁ.2

ꢁ2ꢁꢁ-27-ꢁ2

1EDN71x6U EiceDRIVER^™

200 V high-side TDI gate driver IC for GaN SG HEMTs and MOSFETs

5 Application information

switching event is approximately equal to the driven transistor's gate charge. The minimum value can therefore

be calculated as

Q_G

∆V_{DD, max}

C_Vdd

≫

Equation 2

In a half-bridge configuration, the ꢂDD bypass capacitor also provides the charge for the bootstrap capacitor

during the charging period. Therefore, the ꢂDD bypass capacitor should be sized to be much larger than the

bootstrap capacitor. The minimum value should be calculated as

Q_G+ Q_BOOT

∆V_{DD, max}

C_Vdd

≫

Equation 3

where QBOOT is the charge consumed by the bootstrapping circuit each cycle. This value is calculated in a later

section.

In practice, this capacitance value should be increased somewhat to account for dc bias eꢀects in the capacitor

and other non-idealities in the circuit.

5.4

Selection of external bootstrap diode

When used in a half-bridge configuration, a bootstrapping circuit is oꢄen used to supply the high-side driver's

ꢂ_DD. A fast recovery or schottky diode with low forward voltage drop is recommended in order to minimize

the losses and leakage current. It should be chosen such that it can handle the peak transient current during

start-up conditions and the blocking voltage rating should be higher than the maximum input voltage (ꢂ_IN) with

added margin. It is important to consider that the output capacitance and reverse recovery of this bootstrap

diode contributes to the total switch-node capacitance of the half-bridge, thereby increasing the total switching

losses of the application circuit. A schottky diode with low output capacitance is therefore the best choice for

most applications.

The 1EDN71x6U gate driver provides two options for bootstrap diode connection. The conventional approach is

to connect the anode of the diode to the low-side ꢂ_DDrail, oꢄen with a current-limiting resistor between them

to limit surge current during startup. However, the recommended approach with 1EDN71x6U is to connect the

anode of the bootstrap diode to the BST pin of the low-side driver as shown in Figure 4 . This enables the

integrated bootstrap clamping function of the driver, and it also provides current-limiting at startup without the

need for an added resistor.

5.5

Selection of bootstrap capacitor

The bootstrap capacitor provides the necessary charge to drive the high-side transistor. It must be sized in such

a way that its lowest voltage will be much higher than the UꢂLO threshold as well as above the minimum safe

driving voltage of the transistor, during transient and normal operations.

To determine the minimum required bootstrap capacitance, the maximum allowable ripple in ꢂ_BOOTmust be

calculated as follows.

∆V_{BOOT, max}= V_DD− V_F− V_{BOOT, min}

Equation 4

where:

ꢂ_DD= Low-side gate driver supply voltage

ꢂ_F= Bootstrap diode forward voltage drop

Datasheet

ꢁ7

Rev. ꢁ.2

ꢁ2ꢁꢁ-27-ꢁ2

1EDN71x6U EiceDRIVER^™

200 V high-side TDI gate driver IC for GaN SG HEMTs and MOSFETs

5 Application information

ꢂ_BOOT,minis the minimum allowable voltage for the bootstrap capacitor, including transient events. This voltage

must be at least high enough to avoid UꢂLO shutdown, as given by:

V_{BOOT, min}≥ V_HBR+ V_HBH

Equation 5

where:

ꢂ_HBR= High-side driver UꢂLO rising threshold

ꢂ_HBH= High-side driver UꢂLO threshold hysteresis

However, the driven transistor may require a higher voltage than this UꢂLO minimum, in order to remain fully

on and avoid linear-mode operation. If the calculated minimum ꢂ_BOOTis lower than the safe driving voltage of

the transistor, then ꢂ_BOOT,minshould be increased accordingly.

Next, determine the total charge (Q_BOOT) that must be delivered by the bootstrap capacitor at maximum duty

cycle. There are several factors that contribute to the discharge of the bootstrap capacitor such as the high-side

transistor’s total gate charge and gate-source leakage current, bootstrap diode reverse bias leakage current,

and bootstrap capacitor leakage current. For the sake of simplicity, the bootstrap capacitor leakage current

can typically be neglected. The total bootstrap charge can be estimated as follows:

I_Vdd+ I_diode× D_max

Q_BOOT≈ Q_G+

f_sw

Equation 6

where:

Q_G= High-side transistor total gate charge

I_ꢂdd= High-side driver maximum quiescent current

I_diode= Bootstrap diode reverse bias leakage current

D_max= Maximum high-side duty cycle

f_sw= Switching frequency

The minimum bootstrap capacitor value can then be calculated using the formula:

Q_BOOT

∆ V_{BOOT, max}

C_BOOT

≫

Equation 7

In practice, this capacitance value should be increased somewhat to account for dc bias eꢀects in the capacitor

and other non-idealities in the circuit.

5.6

Selection of external gate resistors

The turn-on and turn-oꢀ external gate resistors control the turn-on and turn-oꢀ current of the gate driver

providing an external way to control the switching speed of the MOSFET for purposes such as voltage overshoot

control, ringing reduction, EMI mitigation, spurious turn-on protection, shoot –through protection, etc. In most

designs, no external gate resistor is needed. Each of the four product variants oꢀers a diꢀerent pull-up and

pull-down resistance, along with a corresponding peak source and sink current. However, in cases where the

designers prefers a diꢀerent source and sink driving strength, an external gate resistor may be used.

The following formulas show the eꢀect of the external gate resistor to the output current capability of the gate

driver.

V_DD

I_{SRC, PK}

≤

R_PU+ R_{G, int}+ R_{Gon, ext}

Equation 8

Datasheet

ꢁ8

Rev. ꢁ.2

ꢁ2ꢁꢁ-27-ꢁ2

1EDN71x6U EiceDRIVER^™

200 V high-side TDI gate driver IC for GaN SG HEMTs and MOSFETs

5 Application information

V_DD

I_{SNK, PK}

≤

R_PD+ R_{G, int}+ R_{Goff, ext}

Equation 9

where:

I_SRC,PK= Peak source current

I_SNK,PK= Peak sink current

R_PU= Gate driver pull-up resistance

R_PD= Gate driver pull-down resistance

ꢂ_DD= Gate driver supply voltage (equivalent to ꢂ_BOOTfor high-side transistor)

R_G,int= Internal gate resistance of driven transistor

R_Gon,ext= External gate resistance connected between Source output and gate

R_Goꢀ,ext= External gate resistance connected between Sink output and gate

It is important to consider that the peak current may not reach this level during a fast switching transition, as

is typical with GaN transistors. It is also worth nothing that this peak current cannot exceed the specified peak

source/sink current of the gate driver, as the pull-up and pull-down transistors within the driver saturate at that

current. However, the selection of product variant according to pull-up and pull-down resistance provides a

close approximation to selection of external gate resistance in most cases.

Use of a non-zero R_{Goꢀ_ext}is not recommended for most designs, as this limits the eꢀectiveness of the active

Miller clamp feature. It is therefore preferable to choose the product variant based on the desired sinking or

pull-down strength, and then add R_{Gon_ext}only if needed to optimize the design.

5.7

PCB layout recommendations

The combination of the gate driver, bypass capacitors, and driven transistor forms a high-frequency current

loop that defines the parasitic inductance in series with that loop. Likewise, in a half-bridge, the combination

of the high-side and low-side transistors forms a high-frequency current loop with the bypass capacitors for the

dc bus (for example ꢂin for a buck converter). The relative location on the PCB of those components is essential

to reach high level of performance. The parasitic inductances within these loops can cause serious eꢀiciency

degradation due to dynamic eꢀects. In addition, any coupling between the gate driving loops and half-bridge

power loop can cause spurious switching events or other performance degradation. Coupling between either of

these loops and the signal paths feeding to the TDI input resistors can also cause spurious switching. Finally, as

mentioned previously, the TDI input circuit may be aꢀected by stray capacitance and other asymmetries in the

PCB design. Careful layout can help minimize or eliminate such unwanted eꢀects.

The following recommendations help the designer to optimize the PCB layout, as demonstrated in the half-

bridge example pictures below.

1.

Keep all high-frequency loops as short as possible, and use diꢀerential returns for current paths to

cancel the magnetic fields and reduce parasitic inductance.

2.

Minimize stray inductance, especially on low impedance lines. All high-current traces (ꢂDD, ꢂSS,

OUT_SRC, OUT_SNK) should be short and wide, and copper pours are recommended over traces when

the design allows.

3.

To optimize heat spreading, electrical shielding, and magnetic field cancellation, a ꢂSS-connected

copper pour should be placed directly underneath the IC as well as all components encompassed by the

gate driving loop (for example bypass capacitors, gate and source pads of transistor). For the low-side

driver, this shielding pour should be connected to PGND. For the high-side driver, it should be connected

to the switch-node, which is the mid-point of the half-bridge.

4.

5.

To avoid interference between the power loop and gate loops, separate shielding layers should be used

for each loop, even if they are both connected to the same net.

To optimize the symmetry of the TDI input resistors, they should be placed directly beside each other

and symmetrically shielded on the first inner layer. The controller-side of the two resistors should be

Datasheet

ꢁ9

Rev. ꢁ.2

ꢁ2ꢁꢁ-27-ꢁ2

1EDN71x6U EiceDRIVER^™

200 V high-side TDI gate driver IC for GaN SG HEMTs and MOSFETs

5 Application information

shielded by the controller ground net (SGND), and the driver-side of the two resistors should be shielded

by the same ꢂSS-connected copper used to shield the rest of the driving circuit.

6.

The dielectric spacing between the top copper layer and first inner layer should be minimized to

enhance the magnetic field cancellation eꢀects. A spacing of 82 ~ 122 microns is used in the example

below.

Figure 25

3D top-side view of example half-bridge implementation

Datasheet

32

Rev. ꢁ.2

ꢁ2ꢁꢁ-27-ꢁ2

1EDN71x6U EiceDRIVER^™

200 V high-side TDI gate driver IC for GaN SG HEMTs and MOSFETs

5 Application information

Figure 26

Top copper layer of example half-bridge implementation

Figure 27

First inner layer of example half-bridge implementation, separated from top layer by

80~100 µm dielectric

Datasheet

31

Rev. ꢁ.2

ꢁ2ꢁꢁ-27-ꢁ2

1EDN71x6U EiceDRIVER^™

200 V high-side TDI gate driver IC for GaN SG HEMTs and MOSFETs

6 Package information

6

Package information

Base part

number

Package type

From

Quantity

Orderable part number

Marking code

1EDN7116U PG-TSNP-7-11 Tape and reel

1EDN71ꢁ6U PG-TSNP-7-11 Tape and reel

1EDN7136U PG-TSNP-7-11 Tape and reel

1EDN7146U PG-TSNP-7-11 Tape and reel

4522

1EDN7116UXTSA1

1EDN71ꢁ6UXTSA1

1EDN7136UXTSA1

1EDN7146UXTSA1

1EDN7116U

1EDN71ꢁ6U

1EDN7136U

1EDN7146U

Figure 28

PG-TSNP-7-11 packaging

Datasheet

3ꢁ

Rev. ꢁ.2

ꢁ2ꢁꢁ-27-ꢁ2

1EDN71x6U EiceDRIVER^™

200 V high-side TDI gate driver IC for GaN SG HEMTs and MOSFETs

6 Package information

Figure 29

PG-TSNP-7-11 package dimensions

Figure 30

PG-TSNP-7-11 recommended landing pattern

Datasheet

33

Rev. ꢁ.2

ꢁ2ꢁꢁ-27-ꢁ2

200ꢀVꢀhigh-sideꢀTDIꢀgateꢀdriverꢀICꢀforꢀGaNꢀSGꢀHEMTsꢀandꢀMOSFETs

1EDN71x6U

RevisionꢀHistory

1EDN71x6U

Revision:ꢀ2022-07-29,ꢀRev.ꢀ2.0

Previous Revision

Revision Date

Subjects (major changes since last revision)

Release of final version

2.0

2022-07-29

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aerospaceꢀdeviceꢀorꢀsystemꢀorꢀtoꢀaffectꢀtheꢀsafetyꢀorꢀeffectivenessꢀofꢀthatꢀdeviceꢀorꢀsystem.ꢀLifeꢀsupportꢀdevicesꢀorꢀsystemsꢀare

intendedꢀtoꢀbeꢀimplantedꢀinꢀtheꢀhumanꢀbodyꢀorꢀtoꢀsupportꢀand/orꢀmaintainꢀandꢀsustainꢀand/orꢀprotectꢀhumanꢀlife.ꢀIfꢀtheyꢀfail,ꢀitꢀis

reasonableꢀtoꢀassumeꢀthatꢀtheꢀhealthꢀofꢀtheꢀuserꢀorꢀotherꢀpersonsꢀmayꢀbeꢀendangered.

34

Rev.ꢀ2.0,ꢀꢀ2022-07-29


型号：	1EDN7116U
厂家：	Infineon
描述：	适用于GaN SG HEMT 和 MOSFET 的 200 V 高边 TDI 栅极驱动器 IC 栅极驱动驱动器
文件：	总34页 (文件大小：1594K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

1EDN7116U [INFINEON]

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