1EDN7146G_技术文档

EiceDRIVER^™ꢀEDNꢁꢀxꢂG

ꢃꢄꢄ V high-side TDI gate driver IC for GaN SG HEMTs and MOSFETs

Features

•

Optimized for driving GaN SG HEMTs and Si MOSFETs

Fully diꢀerential logic input circuitry to avoid false triggering

in low-side or high-side operation

•

High common-mode input voltage range ꢁCMRꢂ up to ± ꢃꢄꢄ V

for high side operation

High immunity to common-mode voltage transitions ꢁꢅꢄꢄ

V/nsꢂ for robust operation during fast switching

•

Compatible with ꢆ.ꢆ V or ꢇ V input logic

V_DD

Four driving strength variants to optimize switching speed

without external gate resistors - up to ꢃ A source/sink current

capability

Active bootstrap clamp to avoid bootstrap capacitor

overcharging during dead-time

VOFF

CF-

OUT_SRC

OUT_SNK

CF+

•

VOFF_ADJ

BST

IN+

VDD

IN-

Active Miller clamp with ꢇ A sink capability to avoid induced

turn-on

VSS

•

Adjustable charge pump for negative turn-oꢀ supply voltage

Qualified for industrial applications according to the relevant

tests of JEDECꢈꢉ/ꢃꢄ/ꢃꢃ

Description

™

The ꢅEDNꢉꢅxꢊG is a single-channel gate-driver IC optimized for driving Infineon CoolGaN Schottky Gate

HEMTs, as well as other GaN SG HEMTs and Si MOSFETs. This gate driver includes several key features that

enable a high-performance system design with fast-switching transistors, including Truly Diꢀerential Input

ꢁTDIꢂ, four driving strength options, active Miller clamp, bootstrap voltage clamp, and adjustable charge pump.

Potential applications

•

Single channel:

•

Half-bridge ꢁꢃ x ꢅEDNꢉꢅxꢊGꢂ:

-

Synchronous rectifier

Class-E resonant wireless power

-

DC-DC converter

BLDC/PMSM motor drive

Class-D audio amplifier

Class-D resonant wireless power

Product portfolio

Part number

ꢅEDNꢉꢅꢅꢊG

ꢅEDNꢉꢅꢃꢊG

ꢅEDNꢉꢅꢆꢊG

ꢅEDNꢉꢅꢈꢊG

Peak source/ sink current

Input pulse blanking time

Package

ꢃ.ꢄ A

ꢅ.ꢇ A

ꢅ.ꢄ A

ꢄ.ꢇ A

ꢃꢄ ns

ꢈꢄ ns

ꢊꢄ ns

ꢋꢄ ns

PG-VSON-ꢅꢄ

Datasheet

www.infineon.com

Please read the Important Notice and Warnings at the end of this document

Rev. ꢃ.ꢅ

ꢃꢄꢃꢅ-ꢅꢄ-ꢅꢃ

EiceDRIVER^™ꢀEDNꢁꢀxꢂG

ꢃꢄꢄ V high-side TDI gate driver IC for GaN SG HEMTs and MOSFETs

Table of contents

Table of contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ꢃ

ꢀ

Pin configuration and description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ꢆ

ꢃ

Product information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ꢈ

Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ꢈ

Truly diꢀerential input ꢁTDIꢂ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ꢈ

Undervoltage lockout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ꢇ

Minimum input pulse . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ꢊ

Driver outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .ꢊ

Active Miller clamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ꢉ

Adjustable negative charge pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ꢉ

Active bootstrap clamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .ꢋ

Unpowered gate clamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ꢅꢄ

ꢃ.ꢅ

ꢃ.ꢃ

ꢃ.ꢆ

ꢃ.ꢈ

ꢃ.ꢇ

ꢃ.ꢊ

ꢃ.ꢉ

ꢃ.ꢋ

ꢃ.ꢌ

ꢅ

General product characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ꢅꢅ

Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ꢅꢅ

Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ꢅꢃ

ESD ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ꢅꢃ

Thermal resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ꢅꢆ

Static electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .ꢅꢆ

Driver output characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ꢅꢇ

Timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ꢅꢊ

ꢆ.ꢅ

ꢆ.ꢃ

ꢆ.ꢆ

ꢆ.ꢈ

ꢆ.ꢇ

ꢆ.ꢊ

ꢆ.ꢉ

ꢆ

Typical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ꢅꢌ

ꢇ

Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ꢃꢉ

Typical application circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ꢃꢉ

Selection of TDI input resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .ꢃꢌ

Selection of VDD bypass capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ꢆꢄ

Selection of external bootstrap diode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .ꢆꢅ

Selection of bootstrap capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ꢆꢅ

Selection of external gate resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ꢆꢃ

Selection of adjustable charge pump circuit components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .ꢆꢆ

PCB layout recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ꢆꢆ

ꢇ.ꢅ

ꢇ.ꢃ

ꢇ.ꢆ

ꢇ.ꢈ

ꢇ.ꢇ

ꢇ.ꢊ

ꢇ.ꢉ

ꢇ.ꢋ

ꢂ

ꢁ

Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ꢆꢊ

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ꢆꢋ

Disclaimer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ꢆꢌ

Datasheet

ꢃ

Rev. ꢃ.ꢅ

ꢃꢄꢃꢅ-ꢅꢄ-ꢅꢃ

EiceDRIVER^™ꢀEDNꢁꢀxꢂG

ꢃꢄꢄ V high-side TDI gate driver IC for GaN SG HEMTs and MOSFETs

ꢀ Pin configuration and description

ꢀ

Pin configuration and description

Figure ꢀ

Table ꢀ

Pin configuration ꢀEDNꢁꢀXꢂG in PG-VSON-ꢀꢄ package, top view

Pin definitions and functions

Name

Function

ꢅ

ꢃ

ꢆ

CF-

Flying capacitor charge pump negative connection.

Flying capacitor charge pump positive connection.

CF+

VOFF_ADJ

Connect a resistance between this pin and VSS to select the negative rail

voltage.

ꢈ

ꢇ

ꢊ

ꢉ

IN+

IN-

Connected to PWM output of controller via ꢈꢉ kΩ or ꢉꢇ kΩ resistor.

Connected to controller ground via ꢈꢉ kΩ or ꢉꢇ kΩ resistor.

Gate drive supply.

VDD

BST

Bootstrap diode anode connection point, when used as a low-side driver

in a half-bridge configuration.

ꢋ

OUT_SNK

OUT_SRC

VOFF

Low-impedance gate pull-down to V_OFFꢁincluding active Miller clampꢂ.

ꢌ

Low-impedance gate pull-up to V_DD.

ꢅꢄ

ꢅꢅ

Negative rail voltage for the turn-oꢀ.

VSS

Return path for VDD and thermal dissipation pad.

Datasheet

ꢆ

Rev. ꢃ.ꢅ

ꢃꢄꢃꢅ-ꢅꢄ-ꢅꢃ

EiceDRIVER^™ꢀEDNꢁꢀxꢂG

ꢃꢄꢄ V high-side TDI gate driver IC for GaN SG HEMTs and MOSFETs

ꢃ Product information

ꢃ

Product information

ꢃ.ꢀ

Functional description

™

The ꢅEDNꢉꢅxꢊG is a single-channel gate-driver IC optimized for driving Infineon CoolGaN SG HEMTs, as well

as other GaN SG HEMTs and Si MOSFETs. Thanks to the truly diꢀerential input feature, the gate driver output

state is exclusively controlled by the voltage diꢀerence between the two inputs, independent of the driver’s

reference ꢁgroundꢂ potential as long as the common-mode voltage is below ꢅꢇꢄ V ꢁstaticꢂ and ꢃꢄꢄ V ꢁdynamicꢂ.

This eliminates the risk of false triggering due to ground bounce in low-side applications, while also allowing

ꢅEDNꢉꢅxꢊG to address even high-side applications.

The product is equipped with several key features especially designed to enhance the performance of GaN SG

HEMTs:

•

four driving strength variants to optimize switching speed without external gate resistors

active bootstrap clamping to avoid overcharging the bootstrap capacitor during dead-time

an active Miller clamp with exceptionally strong pull-down to avoid induced turn-on

and an optional charge pump to provide an adjustable negative turn-oꢀ supply, for additional induced

turn-on immunity when needed.

V_DD

VOFF

CF-

OUT_SRC

OUT_SNK

CF+

VOFF_ADJ

BST

IN+

VDD

IN-

VSS

Figure ꢃ

Typical circuit for low-side single-channel application using ꢀEDNꢁꢀXꢂG to drive a GaN

SG HEMT

ꢃ.ꢃ

Truly diꢈerential input (TDIꢉ

The TDI feature oꢀers common-mode voltage rejection up to ꢅꢇꢄ V for static voltage and ꢃꢄꢄ V for dynamic

voltage transients, enabling both low-side and high-side gate driving without the need for a digital isolator at

the input. The dynamic voltage rating is relevant for any voltage spikes shorter than the specified blanking time

ꢁthat is, minimum pulse widthꢂ. When used as a low-side gate driver, the TDI greatly enhances ground bounce

immunity during fast GaN switching transitions.

Datasheet

ꢈ

Rev. ꢃ.ꢅ

ꢃꢄꢃꢅ-ꢅꢄ-ꢅꢃ

EiceDRIVER^™ꢀEDNꢁꢀxꢂG

ꢃꢄꢄ V high-side TDI gate driver IC for GaN SG HEMTs and MOSFETs

ꢃ Product information

At the positive and negative signal inputs two symmetrical resistor dividers are used to scale down and

compensate common mode bouncing voltages. A fully diꢀerential amplifier stage provides high common mode

rejection and high sensitivity to diꢀerential input signals. The amplified diꢀerential output voltage is finally

evaluated by the subsequent diꢀerential Schmitt-Trigger circuit.

At the IN+ and IN- pins, two external resistors R_inꢅand R_inꢃare used to scale down common mode voltages

of up to ± ꢅꢇꢄ V to a level which can be processed by low voltage CMOS circuitry. These input resistors serve

the function of "blocking" the high common-mode voltage, so that the IN+ and IN- pins of the driver are not

exposed to this high voltage. As such, the selection of these resistors is critical to the proper operation of the TDI

circuit.

Figure ꢅ

Functional block diagram

The resistance values for R_inꢅand R_inꢃmust be selected based on the logic level of the input signals. For a

ꢆ.ꢆ V logic, both external input resistors must be ꢈꢉ kΩ. For a ꢇ V logic, they must be ꢉꢇ kΩ. Furthermore,

R_inꢅand R_inꢃmust be very closely matched. A tolerance of ± ꢄ.ꢅ % is required to maintain control over the

full common mode swing. Resistors with wider tolerance limit the common-mode range of the TDI driving

circuit. Any asymmetries in these resistors may cause a a common-mode voltage to be interpreted as an input

signal, including stray impedances in the PCB layout. Recommendations for a PCB layout are given later in this

datasheet.

To compensate for small asymmetries in the TDI circuit, low pass filters are used to further enhance the high

frequency common mode rejection. Two diꢀerent input filter options are available to accommodate diꢀerent

designs, with a total blanking time of ꢃꢄ ns for ꢅEDNꢉꢅꢅꢊG, ꢈꢄ ns for ꢅEDNꢉꢅꢃꢊG, ꢊꢄ ns for ꢅEDNꢉꢅꢆꢊG, and ꢋꢄ

ns for ꢅEDNꢉꢅꢈꢊG.

ꢃ.ꢅ

Undervoltage lockout

The undervoltage lockout ꢁUVLOꢂ functions ensure that the output can be switched to its high level only if the

supply voltage exceeds the UVLO threshold voltages. In the ꢅEDNꢉꢅxꢊG, two UVLOs are implemented: one for

the VDD pin, and one for the adjustable charge pump voltage.

The UVLO for VDD ensures that the transistors are not switched on if the driving voltage is too low, thereby

avoiding excessive power dissipation due to linear-mode operation. The charge pump UVLO ensures the desired

negative voltage is available for VOFF before any switching activity starts. Both UVLOs must be inactive to allow

the propagation of the input control signals ꢁIN+, IN-ꢂ to the output.

The VDD UVLO level is set to a typical value of ꢆ.ꢋꢇ V, with a maximum of ꢈ.ꢄ V. The maximum value of the rising

edge is the value that ensures all the device among the production is turned on during start up. The designer

Datasheet

ꢇ

Rev. ꢃ.ꢅ

ꢃꢄꢃꢅ-ꢅꢄ-ꢅꢃ

EiceDRIVER^™ꢀEDNꢁꢀxꢂG

ꢃꢄꢄ V high-side TDI gate driver IC for GaN SG HEMTs and MOSFETs

ꢃ Product information

must provide a voltage higher than ꢈ.ꢄ V to turn on all the devices in the production of their equipment within

the specified temperature range. On the opposite side, the minimum voltage necessary to switch oꢀ all the

devices is the minimum of the falling edge, which is ꢆ.ꢊ V. Therefore, a voltage lower than ꢆ.ꢊ V ensures that the

driver does not start switching. Once the driver has exceeded the UVLO, the supply voltage must remain above

the maximum falling edge level of ꢆ.ꢌ V to avoid a UVLO shutdown. The hysteresis is the voltage gap between

rising edge and falling edge, which ensures some margin on noise eꢀects such as false turn oꢀ.

The charge pump also have a UVLO function that is only active at the power-up of the ꢅEDNꢉꢅxꢊG. If the charge

pump is disabled, then this UVLO can be ignored. If it is enabled, then the driver does not transfer signals to

the output until the charge pump UVLO threshold has been exceeded. Aꢍer that time, the UVLO latches and

does not trigger a shutdown of the driver, even if the charge pump voltage drops below its UVLO threshold

later. The UVLO threshold level is a function of the voltage selected for the adjustable charge pump.

The output states depend on the inputs configuration and the status of the two UVLOs. The truth table of the

driver is represented below.

Table ꢃ

CP

Input logic truth table

Diꢈerential

input

UVLO VDD

UVLO VOFF

OUT_SNK

OUT_SRC

BST

ENABLED

DISABLED

X

L

ACTIVE

INACTIVE

ACTIVE

INACTIVE

X

HiZ

L

HiZ

H

HiZ

L

INACTIVE

ACTIVE

L

H

X

L

HiZ

L

H

HiZ

H

HiZ

L

INACTIVE

X

H

X

HiZ

H

Where:

•

UVLO active means V_DD< UVLOVDDL

UVLO inactive means V_DD> UVLOVDDH

Diꢀerential input = L means ꢁV_IN+- V_IN-ꢂ < input logic threshold

Diꢀerential input = H means ꢁV_IN+- V_IN-ꢂ > input logic threshold

ꢃ.ꢆ

Minimum input pulse

The minimum input pulse is the shortest duration pulse at the diꢀerential input that will generate an output

pulse. Pulses with durations shorter than the minimum pulse are neglected and therefore will not generate any

output pulse. Once the input pulse has suꢀicient duration to be propagated, the duration of the output pulse is

equal to the duration of the input pulse, having therefore a linear transfer function between input and output.

The minimum input pulse is specified here as "shortest input pulse transferred to the output." The maximum

value for this parameter is the pulse width at which all the drivers in production will provide an output signal.

In other words, the designer must provide a pulse width longer than the maximum specified value to ensure

an output pulse for every driver of their equipment. Likewise, any pulses shorter than the minimum specified

value will be ignored by all drivers in production. This minimum specification can be treated as the guaranteed

blanking time for de-glitching, which helps to prevent spurious switching during common-mode transient

events.

ꢃ.ꢇ

Driver outputs

The output stage of the driver has a peak source and sink current as defined for the given product variant,

which corresponds to an equivalent resistance of the pull-up and pull-down transistor. The designer can

Datasheet

ꢊ

Rev. ꢃ.ꢅ

ꢃꢄꢃꢅ-ꢅꢄ-ꢅꢃ

EiceDRIVER^™ꢀEDNꢁꢀxꢂG

ꢃꢄꢄ V high-side TDI gate driver IC for GaN SG HEMTs and MOSFETs

ꢃ Product information

optimize the switching speed of the driven transistor by selecting one of the four product variants, without the

need for external gate resistors. If external gate resistors are used, it is highly recommended to avoid placing

a resistor in the output sinking path, as this limits the eꢀectiveness of the active Miller clamp described in the

next section.

Source and sink outputs are actively held low with a clamp in case of floating inputs or during startup or power

down. Under any situation, outputs are held under defined conditions to avoid unstable or unknown behavior

of the driven transistor.

ꢃ.ꢂ

Active Miller clamp

The sink output of the gate driver has an active Miller clamp feature to provide high immunity to spurious

turn-on events. During a turn-oꢀ transition, the peak sinking current and equivalent pull-down resistance is

defined according to the product variant. However, once the driver detects that the gate voltage ꢁat the sink

outputꢂ has fallen below ꢄ.ꢈ V, the active Miller clamp is engaged within ꢆ ns, increasing the strength of the Sink

output significantly. With the clamp engaged, all four product variants can sink up to ꢇ A, with an equivalent

pull-down resistance of ꢄ.ꢆ Ω. This feature allows the designer to optimize the turn-oꢀ speed without sacrificing

the driver's "keep-oꢀ" strength. If an external gate resistor is placed at the sink output, the eꢀectiveness of the

active Miller clamp is reduced.

ꢃ.ꢁ

Adjustable negative charge pump

GaN HEMTs are more susceptible to spurious turn-on events, owing to their low threshold voltage, lower gate

capacitance, and faster switching transitions. A good PCB layout with low parasitic inductances can help to

minimize the risk, but this is not feasible in all designs. In situations where spurious turn-on is likely to occur,

the ꢅEDNꢉꢅxꢊG gate driver provides an adjustable negative power supply to reinforce the oꢀ-state of the

driven transistor during a fast switching event. This is achieved by the integrated negative charge pump. The

negative voltage is adjustable to allow designers to optimize the tradeoꢀ between spurious turn-on risk and

higher reverse conduction losses during dead-time. GaN HEMTs have a reverse conduction mechanism that

mimics a MOSFET body diode, with the exception that the "body diode" voltage drop is directly proportional

to the negative voltage applied. Therefore, applying a more negative oꢀ-state voltage than necessary produces

higher losses during the dead-time.

The negative voltage can be adjusted according to the resistance value connected to VOFF_ADJ in according to

the following table:

Table ꢅ

Resistance value connected to VOFF_ADJ

R_{VOFF_ADJ}

Unit

Negative voltage

Unit

@VOFF

Disabled

-ꢄ.ꢇ

< ꢄ.ꢉꢇ

ꢅ.ꢇ

ꢆ.ꢆ

ꢊ.ꢋ

ꢅꢇ

kΩ

V

-ꢅ.ꢄ

-ꢅ.ꢇ

-ꢃ.ꢄ

ꢆꢆ

-ꢃ.ꢇ

ꢊꢋ

-ꢆ.ꢄ

With a resistance of lower than ꢄ.ꢉꢇ kΩ, the negative charge pump is disabled, and the VOFF output is floating

with respect to VSS. In this case, the VOFF pin must be directly connected to VSS on the PCB. Resistances with

± ꢅꢄ% accuracy are recommended to avoid overlapping of diꢀerent levels. The resistance value is sampled

during the startup transition of the gate driver, so the charge pump voltage cannot be adjusted on-the-fly

during operation. As described in the absolute maximums and recommended operating condition tables, the

driver's supply voltage rating is specified as the voltage swing between VDD and VOFF. If the charge pump is

active with VOFF = - ꢆ V, the maximum voltage supplied to VDD is ꢆ V lower than it would be with the charge

Datasheet

ꢉ

Rev. ꢃ.ꢅ

ꢃꢄꢃꢅ-ꢅꢄ-ꢅꢃ

EiceDRIVER^™ꢀEDNꢁꢀxꢂG

ꢃꢄꢄ V high-side TDI gate driver IC for GaN SG HEMTs and MOSFETs

ꢃ Product information

pump disabled. In this way, designers can supply the driver with up to ꢅꢅ V ꢁfor example for normal-level

MOSFETsꢂ when the charge pump is disabled, or they can instead choose to enable the charge pump and

slightly reduce the positive supply voltage accordingly.

The charge pump is designed to absorb current coming from the Miller capacitance C_GD, with a typical rms value

of ꢇꢄ mA and a peak value up to ꢇ A, while maintaining ± ꢇ% regulation.

ꢃ.ꢊ

Active bootstrap clamp

When using the bootstrapping technique to supply the high-side gate driver in a half-bridge topology, it is

sometimes necessary to regulate the bootstrap capacitor voltage to avoid damaging the gate of the high-side

transistor. This is especially important for GaN HEMTs for two reasons:

ꢀ.

GaN SG HEMTs are oꢍen sensitive to gate over-voltage, with driving voltages typically in the range of ꢇ V

+/- ꢅ V.

ꢃ.

The "body diode" mechanism of GaN HEMTs causes a higher voltage drop than MOSFETs, which leads to

excessive over-charging of the bootstrap capacitor during dead-time conduction.

In a half-bridge configuration, the bootstrap capacitor is normally charged during the low-side switch

conduction time. Figure ꢈ shows this charging path, which includes the power supply ꢁVDDꢂ, the bootstrap

diode, current-limiting resistor, the bootstrap capacitor, and the low-side switch. When the low-side switching is

turned fully on, the voltage applied to the bootstrap capacitor is slightly lower than VDD, due to the drop across

the bootstrap diode, which can be partially compensated by the drop across the low-side transistor. However,

during dead-time intervals, the low-side transistor operates in "body diode" mode, with a voltage drop in

the range of ꢅ.ꢇ ~ ꢃ.ꢇ V, or even higher when a negative oꢀ-state V_GSis applied. This causes over-charging

of the bootstrap capacitor during the dead-time, resulting in a bootstrap voltage that varies significantly with

dead-time duration and operating current, with a high risk of exceeding the maximum rated V_GSof the driven

transistor.

This is not a problem for a typical MOSFET, since the operating range of the gate is fairly wide. However, this

variable bootstrap capacitor voltage may pose a serious risk of damage to the Schottky gate of a GaN SG HEMT.

Therefore, it is necessary to apply some form of regulation to this circuit. For example, a Zener diode can be

used as shown in Figure ꢈ, as long as the dead-time interval is well-controlled and paired with a current-limiting

resistor that avoids overheating the Zener diode.

The ꢅEDNꢉꢅXꢊG driver oꢀers an alternative bootstrap clamping scheme. Figure ꢇ shows the implementation of

this bootstrap clamping scheme in a half-bridge circuit. The clamp circuit avoids over-charging the bootstrap

capacitor instead of directly regulating the capacitor voltage, which would likely contribute additional losses.

Rather than connecting the bootstrap diode to the VDD supply rail, it is connected to the BST output of the

low-side driver. The BST output operates as a clone of the source and sink output pins, synchronized to the

timing of the low-side transistor turning on and oꢀ. Therefore, the bootstrap diode can only conduct current

when the low-side transistor is turned fully on, but not when it is operating in "body diode" mode during

dead-time.

The active bootstrap clamping scheme is very useful in regulating the high-side driving voltage without the

need for additional components. However, in applications where over-charging of the bootstrap capacitor is

desired, the bootstrap diode can be connected to the VDD pin instead of the BST pin. A Zener-based regulation

scheme is recommended in this case, as shown in Figure ꢈ .

Datasheet

ꢋ

Rev. ꢃ.ꢅ

ꢃꢄꢃꢅ-ꢅꢄ-ꢅꢃ

EiceDRIVER^™ꢀEDNꢁꢀxꢂG

ꢃꢄꢄ V high-side TDI gate driver IC for GaN SG HEMTs and MOSFETs

ꢃ Product information

Figure ꢆ

Half-bridge with Zener bootstrap regulation (CP enabledꢉ

Datasheet

ꢌ

Rev. ꢃ.ꢅ

ꢃꢄꢃꢅ-ꢅꢄ-ꢅꢃ

EiceDRIVER^™ꢀEDNꢁꢀxꢂG

ꢃꢄꢄ V high-side TDI gate driver IC for GaN SG HEMTs and MOSFETs

ꢃ Product information

Figure ꢇ

Half-bridge with active bootstrap clamping (CP enabledꢉ

ꢃ.ꢋ

Unpowered gate clamp

The unpowered gate clamp circuit ensures that the driver output is pullowed low when no supply voltage is

applied to the driver. It is common practice to place a resistor between the gate and source of transistors to

ensure that there is no spurious voltage when the system is powered oꢀ. However, this is not necessary with the

ꢅEDNꢉꢅxꢊG. The driver has an internal pull-down MOSFET between the OUT_SNK pin and VSS pin, which pulls

down the gate voltage to VSS with a peak current capability of ꢆ mA, whenever VDD is not suꢀiciently supplied

to turn on the driver. Once the ꢅEDNꢉꢅxꢊG is fully powered on, this pull-down MOSFET is disabled.

OUT_SNK

Power_on

VSS

Figure ꢂ

Functional diagram of unpowered gate clamp circuit

Datasheet

ꢅꢄ

Rev. ꢃ.ꢅ

ꢃꢄꢃꢅ-ꢅꢄ-ꢅꢃ

EiceDRIVER^™ꢀEDNꢁꢀxꢂG

ꢃꢄꢄ V high-side TDI gate driver IC for GaN SG HEMTs and MOSFETs

ꢅ General product characteristics

ꢅ

General product characteristics

ꢅ.ꢀ

Absolute maximum ratings

All voltages are referred to VSS unless otherwise specified.

Table ꢆ

Absolute maximum ratings

Parameter

Symbol

Values

Unit

Note or condition

Min. Typ. Max.

Positive supply V_DD

voltage

-ꢄ.ꢆ

–

ꢅꢃ

V

Driver supply

to negative rail

LS, DC

V_DD- V_OFF

–

ꢅꢃ

Driver supply

to negative rail

LS, AC

V_DD- V_OFF

V_OFF- V_SS

V_{OFF_ADJ}

–

ꢅꢆ.ꢃ

ꢄ.ꢆ

V

< ꢆ ns

Negative

charge pump

output voltage

-ꢈ

Negative

-ꢄ.ꢆ

V_DD+

charge pump

oꢀset adjust

voltage

ꢄ.ꢆ

Voltage at CF+ V_CF+

-ꢄ.ꢆ

–

ꢈ

V

Voltage at CF- V_CF-

V_OFF

ꢄ.ꢆ

-

ꢄ.ꢆ

ꢋ.ꢇ

Voltage at IN+ V_IN+

-ꢋ.ꢇ

Voltage at IN- V_IN-

-ꢋ.ꢇ

Voltage at

OUT_SRC,

V_{OUT_SRC}

V_{OUT_SNK}

,

V_OFF

ꢄ.ꢆ

pins VDD + V

ꢄ.ꢆ

OUT_SNK, BST V_BST

pins

Junction

temperature

T_J

T_S

-ꢈꢄ

-ꢇꢇ

–

ꢅꢇꢄ

ꢃꢊꢄ

^oC

Storage

temperature

Soldering

temperature

Datasheet

ꢅꢅ

Rev. ꢃ.ꢅ

ꢃꢄꢃꢅ-ꢅꢄ-ꢅꢃ

EiceDRIVER^™ꢀEDNꢁꢀxꢂG

ꢃꢄꢄ V high-side TDI gate driver IC for GaN SG HEMTs and MOSFETs

ꢅ General product characteristics

ꢅ.ꢃ

Recommended operating conditions

The following operating conditions must not be exceeded to ensure correct operation and reliability of the

device. All parameters specified in the following tables refer to these operating conditions, unless noted

otherwise.

Table ꢇ

Recommended operating conditions

Parameter

Symbol

Values

Unit

Note or condition

Min. Typ. Max.

Supply voltage V_DD

ꢈ.ꢃ

–

ꢅꢅ

V

Driver output V_DD- V_OFF

voltage swing

ꢀ)

Operating

frequency w/o

charge pump

F_SW

–

ꢅꢇ

MHz

V

Operating

frequency with

charge pump

F_SW

–

ꢈ

With C_L= ꢅ nF. ^ꢀ)

Common

mode voltage

range ꢁstaticꢂ

CMR

CMR_dyn

-ꢅꢇꢄ

-ꢃꢄꢄ

ꢅꢇꢄ

ꢃꢄꢄ

R_ext= ꢈꢉk ± ꢄ.ꢅ%, V_logic= ꢆ.ꢆ V.

Common

mode voltage

range

V

R_ext= ꢈꢉk ± ꢄ.ꢅ%, V_logic= ꢆ.ꢆ V.

Duration of voltage transient event must be

shorter than specified blanking time. ^ꢀ)

ꢁdynamicꢂ

ꢀ)

Common

mode voltage

slew rate

CMSR

T_J

–

ꢅꢄꢄ

ꢅꢃꢇ

V/ns

^oC

Junction

-ꢈꢄ

temperature

ꢅ.ꢅ

ESD ratings

Table ꢂ

ESD ratings

Symbol

ESD_HBM

ESD_CDM

Description

Value

ꢃꢄꢄꢄ

ꢅꢄꢄꢄ

Unit

Human Body Model sensitivity as per ANSI/ESDA/JEDEC JS-ꢄꢄꢅ

Charged Device Model sensitivity as per ANSI/ESDA/JEDEC JS-ꢄꢄꢃ

V

ꢀ

Verified by design/characterization. Not subject to production test.

Datasheet

ꢅꢃ

Rev. ꢃ.ꢅ

ꢃꢄꢃꢅ-ꢅꢄ-ꢅꢃ

EiceDRIVER^™ꢀEDNꢁꢀxꢂG

ꢃꢄꢄ V high-side TDI gate driver IC for GaN SG HEMTs and MOSFETs

ꢅ General product characteristics

ꢅ.ꢆ

Thermal resistance

Table ꢁ

Parameter

Thermal resistance

Symbol

Values

Unit

Note or condition

Min. Typ. Max.

Junction-to-

ambient

thermal

R_thJA

–

ꢅꢄꢃ

–

°C/W

JEDEC ꢃsꢃp with thermal vias. ^ꢁ)

resistance

Junction-to-

case thermal

resistance -

bottom

R_{thJCꢁBOTꢂ}

ꢈꢊ

°C/W

Junction-to-

case thermal

resistance - top

R_{thJCꢁTOPꢂ}

ꢅꢅꢉ

ꢅ.ꢇ

Static electrical characteristics

V_DD= ꢇ V, V_OFF= V_SS= ꢄ V, T_c= - ꢈꢄ^oC to ꢅꢃꢇºC unless otherwise specified.

Table ꢊ

Static electrical characteristics

Parameter

Symbol

Values

Unit

Note or condition

Min. Typ. Max.

Undervoltage lockout thresholds

VDD supply

UVLO rising

threshold

UVLO_VDDH

ꢆ.ꢉ

ꢆ.ꢋꢇ

ꢈ

V

VDD supply

UVLO falling

threshold

UVLO_VDDL

ꢆ.ꢊ

ꢆ.ꢉꢇ ꢆ.ꢌ

Current consumption

VDD quiescent I_QDD

current w/o

charge pump

–

ꢃ.ꢊ

ꢅꢌ

mA

Charge pump disabled, VOFF and VOFF_ADJ

shorted to VSS.

IN+ = IN- = ꢄ V.

VDD quiescent I_{QDD_CP}

current w/

charge pump

Charge pump set to - ꢄ.ꢇ V ꢁworst caseꢂ.

No load at VOFF.

C_VOFF= ꢊꢋꢄ nF, Cfly = ꢅꢄꢄ nF.

See plots.

(table continues...ꢉ

ꢁ

Obtained in a simulation on a JEDEC-standard ꢃsꢃp four-layer PCB with thermal vias, as specified in

JESDꢇꢅ-ꢉ, in an environment described in JESDꢇꢅ-ꢃa.

Datasheet

ꢅꢆ

Rev. ꢃ.ꢅ

ꢃꢄꢃꢅ-ꢅꢄ-ꢅꢃ

EiceDRIVER^™ꢀEDNꢁꢀxꢂG

ꢃꢄꢄ V high-side TDI gate driver IC for GaN SG HEMTs and MOSFETs

ꢅ General product characteristics

Table ꢊ

(continuedꢉ Static electrical characteristics

Parameter

Symbol

Values

Unit

Note or condition

Min. Typ. Max.

VDD current

consumption

when

switching w/o

charge pump

I_ODD

–

ꢆ.ꢇ

mA

Charge pump disabled.

f_SW= ꢇꢄꢄ kHz, no load on OUT_SRC/

OUT_SNK and no load on BST.

Apply PWM to IN+, set IN- = ꢄ V.

Common mode = ꢄ V.

VDD current

consumption

when

switching w/

charge pump

I_{ODD_CP}

–

ꢃꢄ.ꢇ mA

Charge pump set to -ꢄ.ꢇ V ꢁworst caseꢂ.

f_SW= ꢇꢄꢄ kHz, no load on OUT_SRC/

OUT_SNK and no load on BST.

Apply PWM to IN+, set IN- = ꢄ V.

Common mode = ꢄ V.

See plots.

Input characteristics

Diꢀerential

input voltage

threshold for

low-high

ΔV_RinH

ΔV_RinL

ꢅ.ꢉ

ꢅ.ꢃ

ꢅ.ꢅ

ꢄ.ꢉ

ꢅ.ꢌꢇ ꢃ.ꢃ

ꢅ.ꢌꢇ ꢃ.ꢊꢇ

ꢅ.ꢆꢇ ꢅ.ꢊ

ꢅ.ꢆꢇ ꢃ.ꢅꢇ

V

Thresholds valid for R_EXT= ꢈꢉ kΩ.

VCM = ꢄ V and T = ꢃꢇ ºC.

transition

Diꢀerential

input voltage

threshold for

low-high

Thresholds valid for R_EXT= ꢈꢉ kΩ.

VCM = -ꢅꢇꢄ V to ꢅꢇꢄ V.

transition

Diꢀerential

input voltage

threshold for

high-low

Thresholds valid for R_EXT= ꢈꢉ kΩ.

VCM = ꢄ V and T = ꢃꢇ ºC.

transition

Diꢀerential

input voltage

threshold for

high-low

Thresholds valid for R_EXT= ꢈꢉ kΩ.

VCM = -ꢅꢇꢄ V to ꢅꢇꢄ V.

transition

Negative charge pump

Negative rail

adjusting range

V_{OFF_RANGE}-ꢆ

–

ꢄ

ꢇ

V

Negative rail

voltage

V_{OFF_ACCURAC}-ꢇ

Y

%

accuracy

(table continues...ꢉ

Datasheet

ꢅꢈ

Rev. ꢃ.ꢅ

ꢃꢄꢃꢅ-ꢅꢄ-ꢅꢃ

EiceDRIVER^™ꢀEDNꢁꢀxꢂG

ꢃꢄꢄ V high-side TDI gate driver IC for GaN SG HEMTs and MOSFETs

ꢅ General product characteristics

Table ꢊ

(continuedꢉ Static electrical characteristics

Parameter

Symbol

Values

Unit

Note or condition

Min. Typ. Max.

Charge pump

steady-state

average sink

capability

–

ꢇꢄ

mA

VOFF_ADJ Pin I_{ADJ_OFF}

–

ꢋꢄꢄ

uA

Only for ꢅꢉ us pulse at initial startup of IC. ^ꢂ)

output current

ꢅ.ꢂ

Driver output characteristics

VDD = ꢇ V, VOFF = VSS = ꢄ V, Tc = ꢃꢇºC unless otherwise specified.

Table ꢋ

Driver output characteristics

Symbol Typical values

ꢀEDNꢁꢀꢀꢂG ꢀEDNꢁꢀꢃꢂG ꢀEDNꢁꢀꢅꢂG ꢀEDNꢁꢀꢆꢂG

Parameter

Unit Note or

condition

Peak source

current

I_{OUT_SRC}

ꢃ

ꢇ

ꢅ.ꢇ

ꢇ

ꢅ

ꢇ

ꢄ.ꢇ

ꢇ

A

OUT_SRC = ꢄ V ^ꢆꢂ

Peak sink

current

I_{OUT_SNK}

OUT_SNK = ꢇ V ^ꢆꢂ

Peak sink

I_{OUT_SNK}

current w/

Miller clamp

_MC

Pull-up

resistance

R_PU

R_PD

ꢄ.ꢋ

ꢅ.ꢄ

ꢄ.ꢆ

ꢅ.ꢇ

ꢄ.ꢆ

ꢆ.ꢄ

ꢄ.ꢆ

Ω

I_SRC = ꢅꢄꢄ mA

I_SNK = ꢅꢄꢄ mA

Pull-down

resistance

Pull-down

R_{PD_MC}ꢄ.ꢆ

resistance w/

Miller clamp

ꢆꢂ

Active Miller

clamp voltage

threshold

V_{MC_TH}ꢄ.ꢈ

ꢄ.ꢈ

ꢆ

ꢄ.ꢈ

ꢆ

ꢄ.ꢈ

ꢆ

V

Active Miller

clamp

propagation

delay

T_MCD

ꢆ

ns

No load. ^ꢆꢂ

Unpowered

gate clamp

sinking current

I_{OUT_SNK}

ꢆ

mA

VDD floating.

_UGC

ꢅ.ꢃ V applied

externally to

OUT_SNK.

(table continues...ꢉ

ꢂ

Verified by design/characterization. Not subject to production test.

Datasheet

ꢅꢇ

Rev. ꢃ.ꢅ

ꢃꢄꢃꢅ-ꢅꢄ-ꢅꢃ

EiceDRIVER^™ꢀEDNꢁꢀxꢂG

ꢃꢄꢄ V high-side TDI gate driver IC for GaN SG HEMTs and MOSFETs

ꢅ General product characteristics

Table ꢋ

(continuedꢉ Driver output characteristics

Parameter

Symbol

Typical values

Unit Note or

condition

ꢀEDNꢁꢀꢀꢂG ꢀEDNꢁꢀꢃꢂG ꢀEDNꢁꢀꢅꢂG ꢀEDNꢁꢀꢆꢂG

Rise time

Fall time

T_R

T_F

ꢆ

ꢈ

ꢇ.ꢇ

ꢅꢅ

ns

OUT_SRC and

OUT_SNK

shorted.

C_L= ꢅ nF^ꢆꢂ

BST peak

source current

I_{BST_SRC}

ꢃ

A

BST = ꢄ V ^ꢆꢂ

BST peak sink I_{BST_SNK}

ꢃ

A

BST = ꢇ V ^ꢆꢂ

current

BST pull-up

resistance

R_{BST_PU}ꢄ.ꢋ

ꢄ.ꢋ

Ω

I_BST_SRC = ꢅꢄꢄ

mA

BST pull-down R_{BST_PD}ꢄ.ꢋ

resistance

I_BST_SNK = ꢅꢄꢄ

mA

ꢅ.ꢁ

Timing characteristics

Timings are obtained considering OUT_SRC and OUT_SNK shorted together, C_LOAD= ꢄ nF and over common

mode range -ꢅꢇꢄ V to ꢅꢇꢄ V, VDD = ꢇ V, VOFF = ꢄ V, R_EXT= ꢈꢉ kΩ unless specified otherwise.

Table ꢀꢄ

Timing characteristics

Parameter

Symbol

Values

Unit

Note or condition

Min. Typ. Max.

Startup time,

aꢍer UVLO

threshold is

reached

t_ST

ꢅꢉ

ꢃꢇ

μs

VSS = ꢄ V, T_j= ꢃꢇ^oC.

Including VOFF_ADJ readout.

–

ꢁcharge pump

disabledꢂ

Startup time,

aꢍer UVLO

threshold is

reached

t_STCP

–

ꢇꢇ

ꢅꢆꢇ

μs

VSS = ꢄ V, T_j= ꢃꢇ^oC, V_OFF= -ꢃ V.

C_FLY= ꢅꢄꢄ nF, C_VOFF= ꢊꢋꢄ nF, including VOFF_ADJ

readout.

ꢁcharge pump

enabledꢂ

Turn-on

ΔT_{LH_BST}

-ꢃ

–

ꢃ

ns

Calculated as TLH - TLH_BST.

VCM = ꢄ V, T_j= ꢃꢇºC.

propagation

delay matching

OUT to BST

Turn-oꢀ

ΔT_{HL_BST}

Calculated as THL - THL_BST.

propagation

delay matching

OUT to BST

VCM = ꢄ V, T_j= ꢃꢇºC.

(table continues...ꢉ

Datasheet

ꢅꢊ

Rev. ꢃ.ꢅ

ꢃꢄꢃꢅ-ꢅꢄ-ꢅꢃ

EiceDRIVER^™ꢀEDNꢁꢀxꢂG

ꢃꢄꢄ V high-side TDI gate driver IC for GaN SG HEMTs and MOSFETs

ꢅ General product characteristics

Table ꢀꢄ

(continuedꢉ Timing characteristics

Parameter

Symbol

Values

Unit

Note or condition

Min. Typ. Max.

ꢀEDNꢁꢀꢀꢂG

Turn-on

propagation

delay

TLH

ꢇꢆ

ꢇꢇ

ꢇꢉ

ns

VCM = ꢄ V, T_j= ꢃꢇºC.

Turn-oꢀ

propagation

delay

THL

Propagation

delay matching

ΔTLH_HL

-ꢃ.ꢃ

ꢃꢄ

ꢄ

–

ꢃ.ꢃ

ꢃꢇ

ns

Calculated as TLH - THL.

VCM = ꢄ V, T_j= ꢃꢇºC.

Shortest input TPW_MIN

pulse

VCM = ꢄ V, T_j= ꢃꢇºC.

transferred to

the output

ꢀEDNꢁꢀꢃꢂG

Turn-on

propagation

delay

TLH

ꢉꢆ

ꢉꢇ

ꢉꢉ

ns

VCM = ꢄ V, T_j= ꢃꢇºC.

Turn-oꢀ

propagation

delay

THL

Propagation

delay matching

ΔTLH_HL

-ꢃ.ꢋ

ꢈꢄ

–

ꢃ.ꢋ

ꢈꢉ

ns

Calculated as TLH - THL.

VCM = ꢄ V, T_j= ꢃꢇºC.

Shortest input TPW_MIN

pulse

VCM = ꢄ V, T_j= ꢃꢇºC.

transferred to

the output

ꢀEDNꢁꢀꢅꢂG

Turn-on

propagation

delay

TLH

ꢅꢄꢅ

ꢅꢄꢇ

ꢅꢄꢌ

ns

VCM = ꢄ V, T_j= ꢃꢇºC.

Turn-oꢀ

propagation

delay

THL

Propagation

delay matching

ΔTLH_HL

-ꢆ.ꢈ

ꢊꢄ

–

ꢆ.ꢈ

ꢉꢅ

ns

Calculated as TLH - THL.

VCM = ꢄ V, T_j= ꢃꢇºC.

Shortest input TPW_MIN

pulse

VCM = ꢄ V, T_j= ꢃꢇºC.

transferred to

the output

(table continues...ꢉ

Datasheet

ꢅꢉ

Rev. ꢃ.ꢅ

ꢃꢄꢃꢅ-ꢅꢄ-ꢅꢃ

EiceDRIVER^™ꢀEDNꢁꢀxꢂG

ꢃꢄꢄ V high-side TDI gate driver IC for GaN SG HEMTs and MOSFETs

ꢅ General product characteristics

Table ꢀꢄ

(continuedꢉ Timing characteristics

Parameter

Symbol

Values

Unit

Note or condition

Min. Typ. Max.

ꢀEDNꢁꢀꢆꢂG

Turn-on

propagation

delay

TLH

ꢅꢃꢅ

ꢅꢃꢇ

ꢅꢃꢌ

ns

VCM = ꢄ V, T_j= ꢃꢇºC.

Turn-oꢀ

propagation

delay

THL

Propagation

delay matching

ΔTLH_HL

-ꢆ.ꢋ

ꢋꢄ

–

ꢆ.ꢋ

ꢌꢆ

ns

Calculated as TLH - THL.

VCM = ꢄ V, T_j= ꢃꢇºC.

Shortest input TPW_MIN

pulse

VCM = ꢄ V, T_j= ꢃꢇºC.

transferred to

the output

Datasheet

ꢅꢋ

Rev. ꢃ.ꢅ

ꢃꢄꢃꢅ-ꢅꢄ-ꢅꢃ

EiceDRIVER^™ꢀEDNꢁꢀxꢂG

ꢃꢄꢄ V high-side TDI gate driver IC for GaN SG HEMTs and MOSFETs

ꢆ Typical characteristics

ꢆ

Typical characteristics

Figure ꢁ

Diꢈerential input voltage threshold versus temperature

Figure ꢊ

Diꢈerential input voltage threshold versus common mode voltage

Datasheet

ꢅꢌ

Rev. ꢃ.ꢅ

ꢃꢄꢃꢅ-ꢅꢄ-ꢅꢃ

EiceDRIVER^™ꢀEDNꢁꢀxꢂG

ꢃꢄꢄ V high-side TDI gate driver IC for GaN SG HEMTs and MOSFETs

ꢆ Typical characteristics

Figure ꢋ

Quiescent current versus temperature (with charge pump disabledꢉ

Figure ꢀꢄ

Quiescent current versus supply voltage (with charge pump disabledꢉ

Datasheet

ꢃꢄ

Rev. ꢃ.ꢅ

ꢃꢄꢃꢅ-ꢅꢄ-ꢅꢃ

EiceDRIVER^™ꢀEDNꢁꢀxꢂG

ꢃꢄꢄ V high-side TDI gate driver IC for GaN SG HEMTs and MOSFETs

ꢆ Typical characteristics

Figure ꢀꢀ

Operating current with load versus frequency (with charge pump disabledꢉ

Figure ꢀꢃ

Operating current with load versus charge pump voltage

Datasheet

ꢃꢅ

Rev. ꢃ.ꢅ

ꢃꢄꢃꢅ-ꢅꢄ-ꢅꢃ

EiceDRIVER^™ꢀEDNꢁꢀxꢂG

ꢃꢄꢄ V high-side TDI gate driver IC for GaN SG HEMTs and MOSFETs

ꢆ Typical characteristics

Figure ꢀꢅ

Turn-on propagation delay versus temperature

Figure ꢀꢆ

Turn-oꢈ propagation delay versus temperature

Datasheet

ꢃꢃ

Rev. ꢃ.ꢅ

ꢃꢄꢃꢅ-ꢅꢄ-ꢅꢃ

EiceDRIVER^™ꢀEDNꢁꢀxꢂG

ꢃꢄꢄ V high-side TDI gate driver IC for GaN SG HEMTs and MOSFETs

ꢆ Typical characteristics

Figure ꢀꢇ

Turn-on propagation delay versus common mode voltage

Figure ꢀꢂ

Turn-oꢈ propagation delay versus common mode voltage

Datasheet

ꢃꢆ

Rev. ꢃ.ꢅ

ꢃꢄꢃꢅ-ꢅꢄ-ꢅꢃ

EiceDRIVER^™ꢀEDNꢁꢀxꢂG

ꢃꢄꢄ V high-side TDI gate driver IC for GaN SG HEMTs and MOSFETs

ꢆ Typical characteristics

Figure ꢀꢁ

OUT_SRC pull-up resistance versus temperature

Figure ꢀꢊ

OUT_SNK pull-down resistance versus temperature (before active Miller clamp is

engagedꢉ

Datasheet

ꢃꢈ

Rev. ꢃ.ꢅ

ꢃꢄꢃꢅ-ꢅꢄ-ꢅꢃ

EiceDRIVER^™ꢀEDNꢁꢀxꢂG

ꢃꢄꢄ V high-side TDI gate driver IC for GaN SG HEMTs and MOSFETs

ꢆ Typical characteristics

Figure ꢀꢋ

OUT_SNK pull-down resistance versus temperature (aꢌer Miller clamp is engagedꢉ

Figure ꢃꢄ

BST pull-up and pull-down resistance versus temperature

Datasheet

ꢃꢇ

Rev. ꢃ.ꢅ

ꢃꢄꢃꢅ-ꢅꢄ-ꢅꢃ

EiceDRIVER^™ꢀEDNꢁꢀxꢂG

ꢃꢄꢄ V high-side TDI gate driver IC for GaN SG HEMTs and MOSFETs

ꢆ Typical characteristics

Figure ꢃꢀ

Undervoltage lockout threshold versus temperature

Figure ꢃꢃ

Minimum input pulse versus temperature

Datasheet

ꢃꢊ

Rev. ꢃ.ꢅ

ꢃꢄꢃꢅ-ꢅꢄ-ꢅꢃ

EiceDRIVER^™ꢀEDNꢁꢀxꢂG

ꢃꢄꢄ V high-side TDI gate driver IC for GaN SG HEMTs and MOSFETs

ꢇ Application information

ꢇ

Application information

ꢇ.ꢀ

Typical application circuits

The ꢅEDNꢉꢅxꢊG can be used as a single low-side driver or a single high-side driver, and two can be used

together to drive a half-bridge. Figure ꢃꢆ and Figure ꢃꢈ depict example circuit schematics for single-device

drivers with the optional charge pump enables and disabled respectively, giving the designer the option to

generate a negative oꢀ-state voltage within the IC if this is required to avoid false triggering. Figure ꢈ and Figure

ꢇ show two examples of half-bridge circuit schematics with two ꢅEDNꢉꢅxꢊG, with conventional bootstrapping

and Zener regulation in the first, and active bootstrap clamping enabled in the second. Figure ꢃꢇ shows

an additional example of half-bridge implementation, in this case with cross-connected PWM inputs for the

high-side and low-side drivers. This option adds robustness against accidental cross-conduction in case the

controller ever generates overlapping PWM signal. However, it may also limit the minimum dead-time as

measured at the gate signals of the driven devices, due to asymmetrical turn-on and turn-oꢀ delay times of

the driven transistors. It is important to note that the charge pump is enabled in all three of these example

half-bridge circuits, however it can be easily disabled by modifying each individual driving circuit according to

Figure ꢃꢈ.

Figure ꢃꢅ

Single channel with charge pump enabled

Figure ꢃꢆ

Single channel with charge pump disabled

Datasheet

ꢃꢉ

Rev. ꢃ.ꢅ

ꢃꢄꢃꢅ-ꢅꢄ-ꢅꢃ

EiceDRIVER^™ꢀEDNꢁꢀxꢂG

ꢃꢄꢄ V high-side TDI gate driver IC for GaN SG HEMTs and MOSFETs

ꢇ Application information

Figure ꢃꢇ

Half-bridge with cross-connected signal inputs (CP enabled, active bootstrap

clampingꢉ

Datasheet

ꢃꢋ

Rev. ꢃ.ꢅ

ꢃꢄꢃꢅ-ꢅꢄ-ꢅꢃ

EiceDRIVER^™ꢀEDNꢁꢀxꢂG

ꢃꢄꢄ V high-side TDI gate driver IC for GaN SG HEMTs and MOSFETs

ꢇ Application information

Figure ꢃꢂ

TDI application circuit, including input external resistors and stray capacitance

ꢇ.ꢃ

Selection of TDI input resistors

The ꢅEDNꢉꢅXꢊG requires precise input resistors at the IN+ and IN- pins, with resistance values of ꢈꢉ kΩ or

ꢉꢇ kΩ, depending on the voltage level of the input logic signals. The driver is compatible with either a ꢆ.ꢆ V

or a ꢇ V logic. These resistors are not optional, even if the application does not require the TDI function ꢁfor

example low-side applications with no ground bounce concernsꢂ. The input logic thresholds at the IN+ and

IN- pins are designed to be paired with the specified input resistor values. These input resistors should be

selected with a ꢄ.ꢅ% tolerance, especially in high-side applications, where the common-mode voltage rating is

contingent upon tight matching of R_INꢅand R_INꢅ. Extra care should be taken to ensure that these resistors are

symmetrical, so that stray capacitance across them is also tightly matched. Figure ꢃꢊ shows an example of how

stray capacitances C_pꢅand C_pꢃcould interfere with the symmetry and matching of R_INꢅand R_INꢃ. To optimize this

symmetry, the two resistors should have identical part numbers with the same package and footprint. Further

PCB layout recommendations for ensuring symmetry are given later.

In high-side applications, the input resistors must also be rated for the power dissipation expected in the

worst-case operating conditions. The common-mode voltage observed by the high-side transistor is "blocked"

by each input resistor, so that the ꢅEDNꢉꢅXꢊG is not exposed to the high voltage. The resistors dissipate power

during the intervals where CM voltage is high, typically during the high-side transistor's duty ratio of each

switching period. The power rating of the resistors should therefore be selected based on

2

V_{dc, max}

P_Rin1= P_Rin2

=

× D

R_in1

Equation ꢀ

where:

P_Rinꢅ= Required power rating for R_inꢅ

P_Rinꢃ= Required power rating for R_inꢃ

D = High-side duty ratio

V_dc,max= Maximum expected dc bus voltage, experienced as CM voltage during the high-side duty ratio

It is important to consider that the duty ratio may not be constant, so D should be selected as the duty ratio

when operating at the maximum dc bus voltage.

The table below lists some examples for selecting the input resistors, based on logic voltage level, expected dc

bus voltage, and duty ratio. For most applications, the power requirement is quite low, thereby allowing the

designer to select very small resistor packages such as ꢄꢈꢄꢃ or ꢄꢊꢄꢆ. In some extreme scenarios with a high dc

voltage and high duty ratio simultaneously, larger packages with higher power ratings may be needed.

Datasheet

ꢃꢌ

Rev. ꢃ.ꢅ

ꢃꢄꢃꢅ-ꢅꢄ-ꢅꢃ

EiceDRIVER^™ꢀEDNꢁꢀxꢂG

ꢃꢄꢄ V high-side TDI gate driver IC for GaN SG HEMTs and MOSFETs

ꢇ Application information

Table ꢀꢀ

Examples for selected input resistors

Maximum dc bus

Logic

voltage

TDI input

resistance

Resistor

tolerance

Minimum Rin

power rating

Duty ratio

voltage

ꢊꢄ V

ꢋꢄ V

ꢆ.ꢆ V

ꢇ V

ꢄ.ꢃꢇ

ꢄ.ꢉꢇ

ꢈꢉ kΩ

ꢄ.ꢅ%

ꢄ.ꢄꢃ W

ꢄ.ꢄꢅ W

ꢄ.ꢅꢄ W

ꢄ.ꢄꢊ W

ꢉꢇ kΩ

ꢆ.ꢆ V

ꢇ V

ꢈꢉ kΩ

ꢉꢇ kΩ

ꢇ.ꢅ

Selection of VDD bypass capacitor

The V_DDbypass capacitor provides the gate charge to drive the transistor, as well as additional power

consumption by the driver itself and the charge pump ꢁif enabledꢂ. It should be placed as close as possible

to the VDD and VSS pins of the gate driver, which may require a particular footprint size for most applications.

The minimum value for this bypass capacitor can be calculated based on the maximum allowable voltage ripple

in the design. This ripple should be minimized such that the lowest possible V_DDis above the UVLO limit of

the gate driver as well as above the safe driving voltage of the transistor. The charge dissipated per switching

event is the total of the driven transistor's gate charge and the additional consumption by the charge pump ꢁif

enabledꢂ. The minimum value can therefore be calculated as

Q_G+ Q_CP

∆V_{DD, max}

C_Vdd

≫

Equation ꢃ

where the charge pump consumption can be determined through linear approximation. The typical operating

consumption for the gate driver with a particular charge pump voltage is given in Figure ꢅꢃ for ꢇꢄꢄ kHz with ꢅ

nF of gate capacitance. The equivalent charge for the same charge pump voltage when operating at a diꢀerent

frequency with a diꢀerent gate capacitance ꢁC_ISSꢂ can be approximated as

I_CP

C_ISS

1 nF

Q_CP

≈

×

500 kHz

Equation ꢅ

If the charge pump is disabled, Q_CPcan be ignored.

In a half-bridge configuration, the V_DDbypass capacitor also provides the charge for the bootstrap capacitor

during the charging period. Therefore, the V_DDbypass capacitor should be sized to be much larger than the

bootstrap capacitor. The minimum value should be calculated as

Q_G+ Q_CP+ Q_BOOT

∆V_{DD, max}

C_Vdd

≫

Equation ꢆ

where Q_BOOTis the charge consumed by the bootstrapping circuit each cycle. This value is calculated in a later

section.

In practice, this capacitance value should be increased somewhat to account for dc bias eꢀects in the capacitor

and other non-idealities in the circuit.

Datasheet

ꢆꢄ

Rev. ꢃ.ꢅ

ꢃꢄꢃꢅ-ꢅꢄ-ꢅꢃ

EiceDRIVER^™ꢀEDNꢁꢀxꢂG

ꢃꢄꢄ V high-side TDI gate driver IC for GaN SG HEMTs and MOSFETs

ꢇ Application information

ꢇ.ꢆ

Selection of external bootstrap diode

When used in a half-bridge configuration, a bootstrapping circuit is oꢍen used to supply the high-side driver's

V_DD. A fast recovery or schottky diode with low forward voltage drop is recommended in order to minimize

the losses and leakage current. It should be chosen such that it can handle the peak transient current during

start-up conditions and the blocking voltage rating should be higher than the maximum input voltage ꢁV_INꢂ with

added margin. It is important to consider that the output capacitance and reverse recovery of this bootstrap

diode contributes to the total switch-node capacitance of the half-bridge, thereby increasing the total switching

losses of the application circuit. A schottky diode with low output capacitance is therefore the best choice for

most applications.

The ꢅEDNꢉꢅxꢊG gate driver provides two options for bootstrap diode connection. The conventional approach

is to connect the anode of the diode to the low-side V_DDrail, oꢍen with a current-limiting resistor between

them to limit surge current during startup. However, the recommended approach with ꢅEDNꢉꢅxꢊG is to connect

the anode of the bootstrap diode to the BST pin of the low-side driver as shown in Figure ꢈ . This enables the

integrated bootstrap clamping function of the driver, and it also provides current-limiting at startup without the

need for an added resistor.

ꢇ.ꢇ

Selection of bootstrap capacitor

The bootstrap capacitor provides the necessary charge to drive the high-side transistor. It must be sized in such

a way that its lowest voltage will be much higher than the UVLO threshold as well as above the minimum safe

driving voltage of the transistor, during transient and normal operations.

To determine the minimum required bootstrap capacitance, the maximum allowable ripple in V_BOOTmust be

calculated as follows.

∆V_{BOOT, max}= V_DD− V_F− V_{BOOT, min}

Equation ꢇ

where:

V_DD= Low-side gate driver supply voltage

V_F= Bootstrap diode forward voltage drop

V_BOOT,minis the minimum allowable voltage for the bootstrap capacitor, including transient events. This voltage

must be at least high enough to avoid UVLO shutdown, as given by:

V_{BOOT, min}≥ V_HBR+ V_HBH

Equation ꢂ

where:

V_HBR= High-side driver UVLO rising threshold

V_HBH= High-side driver UVLO threshold hysteresis

However, the driven transistor may require a higher voltage than this UVLO minimum, in order to remain fully

on and avoid linear-mode operation. If the calculated minimum V_BOOTis lower than the safe driving voltage of

the transistor, then V_BOOT,minshould be increased accordingly.

Next, determine the total charge ꢁQ_BOOTꢂ that must be delivered by the bootstrap capacitor at maximum duty

cycle. There are several factors that contribute to the discharge of the bootstrap capacitor such as the high-side

transistor’s total gate charge and gate-source leakage current, charge pump consumption, bootstrap diode

reverse bias leakage current, and bootstrap capacitor leakage current. For the sake of simplicity, the bootstrap

capacitor leakage current can typically be neglected. The total bootstrap charge can be estimated as follows:

I_Vdd+ I_diode× D_max

Q_BOOT≈ Q_G+ Q_CP

+

f_sw

Equation ꢁ

Datasheet

ꢆꢅ

Rev. ꢃ.ꢅ

ꢃꢄꢃꢅ-ꢅꢄ-ꢅꢃ

EiceDRIVER^™ꢀEDNꢁꢀxꢂG

ꢃꢄꢄ V high-side TDI gate driver IC for GaN SG HEMTs and MOSFETs

ꢇ Application information

where:

Q_G= High-side transistor total gate charge

Q_CP= Additional consumption by charge pump, if enabled ꢁequation given in earlier sectionꢂ

I_Vdd= High-side driver maximum quiescent current

I_diode= Bootstrap diode reverse bias leakage current

D_max= Maximum high-side duty cycle

f_sw= Switching frequency

The minimum bootstrap capacitor value can then be calculated using the formula:

Q_BOOT

∆ V_{BOOT, max}

C_BOOT

≫

Equation ꢊ

In practice, this capacitance value should be increased somewhat to account for dc bias eꢀects in the capacitor

and other non-idealities in the circuit.

ꢇ.ꢂ

Selection of external gate resistors

The turn-on and turn-oꢀ external gate resistors control the turn-on and turn-oꢀ current of the gate driver

providing an external way to control the switching speed of the MOSFET for purposes such as voltage overshoot

control, ringing reduction, EMI mitigation, spurious turn-on protection, shoot –through protection, etc. In most

designs, no external gate resistor is needed. Each of the four product variants oꢀers a diꢀerent pull-up and

pull-down resistance, along with a corresponding peak source and sink current. However, in cases where the

designers prefers a diꢀerent source and sink driving strength, an external gate resistor may be used.

The following formulas show the eꢀect of the external gate resistor to the output current capability of the gate

driver.

V_DD

I_{SRC, PK}

≤

R_PU+ R_{G, int}+ R_{Gon, ext}

Equation ꢋ

V_DD

I_{SNK, PK}

≤

R_PD+ R_{G, int}+ R_{Goff, ext}

Equation ꢀꢄ

where:

I_SRC,PK= Peak source current

I_SNK,PK= Peak sink current

R_PU= Gate driver pull-up resistance

R_PD= Gate driver pull-down resistance

V_DD= Gate driver supply voltage ꢁequivalent to V_BOOTfor high-side transistorꢂ

R_G,int= Internal gate resistance of driven transistor

R_Gon,ext= External gate resistance connected between Source output and gate

R_Goꢀ,ext= External gate resistance connected between Sink output and gate

It is important to consider that the peak current may not reach this level during a fast switching transition,

as is typical with GaN HEMTs. It is also worth nothing that this peak current cannot exceed the specified peak

source/sink current of the gate driver, as the pull-up and pull-down transistors within the driver saturate at that

current. However, the selection of product variant according to pull-up and pull-down resistance provides a

close approximation to selection of external gate resistance in most cases.

Datasheet

ꢆꢃ

Rev. ꢃ.ꢅ

ꢃꢄꢃꢅ-ꢅꢄ-ꢅꢃ

EiceDRIVER^™ꢀEDNꢁꢀxꢂG

ꢃꢄꢄ V high-side TDI gate driver IC for GaN SG HEMTs and MOSFETs

ꢇ Application information

Use of a non-zero R_{Goꢀ_ext}is not recommended for most designs, as this limits the eꢀectiveness of the active

Miller clamp feature. It is therefore preferable to choose the product variant based on the desired sinking or

pull-down strength, and then add R_{Gon_ext}only if needed to optimize the design.

ꢇ.ꢁ

Selection of adjustable charge pump circuit components

The charge pump is an optional feature of the ꢅEDNꢉꢅXꢊG gate driver. At power-up of the driver ꢁfor example

system startupꢂ, the driver senses the resistance at the VOFF_ADJ pin, then it enables the charge pump circuit if

it senses a resistance greater than ꢉꢇꢄ Ω.

If the charge pump is not enabled at system startup, then the output of V_OFFis floating with respect to VSS.

There is no configuration that causes the V_OFFoutput to be ꢄ V with respect to VSS, so this short-circuit

connection must be provided externally on the PCB. Otherwise, the oꢀ-state gate voltage of the transistor may

not be ꢄ V.

If the driver senses a resistor greater than ꢉꢇꢄ Ω, the charge pump is enabled with a negative V_OFFvoltage

determined by the resistor value. This resistance must be selected based on the table given earlier in the

datasheet. In this scenario, the designer must add a ꢅꢄꢄ nF flying capacitor between CF+ and CF- pins to

support the internal charge pump circuit. Furthermore, a bypass capacitor must be placed between V_OFFand

VSS to provide a stable VOFF voltage and to supply the dynamic gate current during turn-oꢀ transitions. This

capacitance value should selected based on the gate charge of the driven transistor, similar to the VDD bypass

capacitor. The minimum required V_OFFbypass capacitance can be determined by

C_ISS× V_OFF

∆ V_{OFF, max}

C_Voff

≫

Equation ꢀꢀ

where:

C_ISS= Input capacitance of the driven transistor

V_OFF= Selected charge-pump output voltage

ΔV_OFF,max= Maximum deviation in V_OFFallowable in the design

As with the other bypass capacitors, it is recommended to add some margin to this capacitance value to

account for capacitor dc bias eꢀects and other circuit non-idealities.

ꢇ.ꢊ

PCB layout recommendations

The combination of the gate driver, bypass capacitors, and driven transistor forms a high-frequency current

loop that defines the parasitic inductance in series with that loop. Likewise, in a half-bridge, the combination

of the high-side and low-side transistors forms a high-frequency current loop with the bypass capacitors for the

dc bus ꢁfor example Vin for a buck converterꢂ. The relative location on the PCB of those components is essential

to reach high level of performance. The parasitic inductances within these loops can cause serious eꢀiciency

degradation due to dynamic eꢀects. In addition, any coupling between the gate driving loops and half-bridge

power loop can cause spurious switching events or other performance degradation. Coupling between either of

these loops and the signal paths feeding to the TDI input resistors can also cause spurious switching. Finally, as

mentioned previously, the TDI input circuit may be aꢀected by stray capacitance and other asymmetries in the

PCB design. Careful layout can help minimize or eliminate such unwanted eꢀects.

The following recommendations help the designer to optimize the PCB layout, as demonstrated in the half-

bridge example pictures below.

ꢀ.

Keep all high-frequency loops as short as possible, and use diꢀerential returns for current paths to

cancel the magnetic fields and reduce parasitic inductance.

ꢃ.

Minimize stray inductance, especially on low impedance lines. All high-current traces ꢁVDD, VSS,

OUT_SRC, OUT_SNK, VOFFꢂ should be short and wide, and copper pours are recommended over traces

when the design allows.

ꢅ.

To optimize heat spreading, electrical shielding, and magnetic field cancellation, a VSS-connected

copper pour should be placed directly underneath the IC as well as all components encompassed by the

gate driving loop ꢁfor example bypass capacitors, gate and source pads of transistorꢂ. For the low-side

Datasheet

ꢆꢆ

Rev. ꢃ.ꢅ

ꢃꢄꢃꢅ-ꢅꢄ-ꢅꢃ

EiceDRIVER^™ꢀEDNꢁꢀxꢂG

ꢃꢄꢄ V high-side TDI gate driver IC for GaN SG HEMTs and MOSFETs

ꢇ Application information

driver, this shielding pour should be connected to PGND. For the high-side driver, it should be connected

to the switch-node, which is the mid-point of the half-bridge.

To avoid interference between the power loop and gate loops, separate shielding layers should be used

for each loop, even if they are both connected to the same net.

To optimize the symmetry of the TDI input resistors, they should be placed directly beside each other

and symmetrically shielded on the first inner layer. The controller-side of the two resistors should be

shielded by the controller ground net ꢁSGNDꢂ, and the driver-side of the two resistors should be shielded

by the same VSS-connected copper used to shield the rest of the driving circuit.

ꢆ.

ꢇ.

ꢂ.

The dielectric spacing between the top copper layer and first inner layer should be minimized to enhance

the magnetic field cancellation eꢀects. A spacing of ꢋꢄ ~ ꢅꢄꢄ microns is used in the example below.

Figure ꢃꢁ

ꢅD top-side view of example half-bridge implementation

Datasheet

ꢆꢈ

Rev. ꢃ.ꢅ

ꢃꢄꢃꢅ-ꢅꢄ-ꢅꢃ

EiceDRIVER^™ꢀEDNꢁꢀxꢂG

ꢃꢄꢄ V high-side TDI gate driver IC for GaN SG HEMTs and MOSFETs

ꢇ Application information

Figure ꢃꢊ

Top copper layer of example half-bridge implementation

Figure ꢃꢋ

First inner copper layer of example half-bridge implementation

Datasheet

ꢆꢇ

Rev. ꢃ.ꢅ

ꢃꢄꢃꢅ-ꢅꢄ-ꢅꢃ

EiceDRIVER^™ꢀEDNꢁꢀxꢂG

ꢃꢄꢄ V high-side TDI gate driver IC for GaN SG HEMTs and MOSFETs

ꢂ Package information

ꢂ

Package information

Base part

number

Package type

From

Quantity

Orderable part number

Marking code

ꢅEDNꢉꢅꢅꢊG

ꢅEDNꢉꢅꢃꢊG

ꢅEDNꢉꢅꢆꢊG

ꢅEDNꢉꢅꢈꢊG

PG-VSON-ꢅꢄ Tape and reel

ꢈꢄꢄꢄ

ꢅEDNꢉꢅꢅꢊGXTMAꢅ

ꢅEDNꢉꢅꢃꢊGXTMAꢅ

ꢅEDNꢉꢅꢆꢊGXTMAꢅ

ꢅEDNꢉꢅꢈꢊGXTMAꢅ

ꢅEDNꢉꢅꢅꢊG

ꢅEDNꢉꢅꢃꢊG

ꢅEDNꢉꢅꢆꢊG

ꢅEDNꢉꢅꢈꢊG

Figure ꢅꢄ

PG-VSON-ꢀꢄ packaging

Datasheet

ꢆꢊ

Rev. ꢃ.ꢅ

ꢃꢄꢃꢅ-ꢅꢄ-ꢅꢃ

EiceDRIVER^™ꢀEDNꢁꢀxꢂG

ꢃꢄꢄ V high-side TDI gate driver IC for GaN SG HEMTs and MOSFETs

ꢂ Package information

Figure ꢅꢀ

PG-VSON-ꢀꢄ package dimensions

Figure ꢅꢃ

PG-VSON-ꢀꢄ recommended landing pattern

Datasheet

ꢆꢉ

Rev. ꢃ.ꢅ

ꢃꢄꢃꢅ-ꢅꢄ-ꢅꢃ

200ꢀVꢀhigh-sideꢀTDIꢀgateꢀdriverꢀICꢀforꢀGaNꢀSGꢀHEMTsꢀandꢀMOSFETs

1EDN71x6G

RevisionꢀHistory

1EDN71x6G

Revision:ꢀ2021-10-18,ꢀRev.ꢀ2.1

Previous Revision

Revision Date

Subjects (major changes since last revision)

Release of final version

2.0

2.1

2021-07-26

2021-10-18

Title changed, added package dimension image, other editorial revisions

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Theꢀinformationꢀgivenꢀinꢀthisꢀdocumentꢀshallꢀinꢀnoꢀeventꢀbeꢀregardedꢀasꢀaꢀguaranteeꢀofꢀconditionsꢀorꢀcharacteristicsꢀ

(“Beschaffenheitsgarantie”)ꢀ.

Withꢀrespectꢀtoꢀanyꢀexamples,ꢀhintsꢀorꢀanyꢀtypicalꢀvaluesꢀstatedꢀhereinꢀand/orꢀanyꢀinformationꢀregardingꢀtheꢀapplicationꢀofꢀthe

product,ꢀInfineonꢀTechnologiesꢀherebyꢀdisclaimsꢀanyꢀandꢀallꢀwarrantiesꢀandꢀliabilitiesꢀofꢀanyꢀkind,ꢀincludingꢀwithoutꢀlimitation

warrantiesꢀofꢀnon-infringementꢀofꢀintellectualꢀpropertyꢀrightsꢀofꢀanyꢀthirdꢀparty.

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documentꢀandꢀanyꢀapplicableꢀlegalꢀrequirements,ꢀnormsꢀandꢀstandardsꢀconcerningꢀcustomer’sꢀproductsꢀandꢀanyꢀuseꢀofꢀthe

productꢀofꢀInfineonꢀTechnologiesꢀinꢀcustomer’sꢀapplications.

Theꢀdataꢀcontainedꢀinꢀthisꢀdocumentꢀisꢀexclusivelyꢀintendedꢀforꢀtechnicallyꢀtrainedꢀstaff.ꢀItꢀisꢀtheꢀresponsibilityꢀofꢀcustomer’s

technicalꢀdepartmentsꢀtoꢀevaluateꢀtheꢀsuitabilityꢀofꢀtheꢀproductꢀforꢀtheꢀintendedꢀapplicationꢀandꢀtheꢀcompletenessꢀofꢀtheꢀproduct

informationꢀgivenꢀinꢀthisꢀdocumentꢀwithꢀrespectꢀtoꢀsuchꢀapplication.

Information

Forꢀfurtherꢀinformationꢀonꢀtechnology,ꢀdeliveryꢀtermsꢀandꢀconditionsꢀandꢀpricesꢀpleaseꢀcontactꢀyourꢀnearestꢀInfineon

TechnologiesꢀOfficeꢀ(www.infineon.com).

Warnings

Dueꢀtoꢀtechnicalꢀrequirements,ꢀcomponentsꢀmayꢀcontainꢀdangerousꢀsubstances.ꢀForꢀinformationꢀonꢀtheꢀtypesꢀinꢀquestion,

pleaseꢀcontactꢀtheꢀnearestꢀInfineonꢀTechnologiesꢀOffice.

TheꢀInfineonꢀTechnologiesꢀcomponentꢀdescribedꢀinꢀthisꢀDataꢀSheetꢀmayꢀbeꢀusedꢀinꢀlife-supportꢀdevicesꢀorꢀsystemsꢀand/or

automotive,ꢀaviationꢀandꢀaerospaceꢀapplicationsꢀorꢀsystemsꢀonlyꢀwithꢀtheꢀexpressꢀwrittenꢀapprovalꢀofꢀInfineonꢀTechnologies,ꢀifꢀa

failureꢀofꢀsuchꢀcomponentsꢀcanꢀreasonablyꢀbeꢀexpectedꢀtoꢀcauseꢀtheꢀfailureꢀofꢀthatꢀlife-support,ꢀautomotive,ꢀaviationꢀand

aerospaceꢀdeviceꢀorꢀsystemꢀorꢀtoꢀaffectꢀtheꢀsafetyꢀorꢀeffectivenessꢀofꢀthatꢀdeviceꢀorꢀsystem.ꢀLifeꢀsupportꢀdevicesꢀorꢀsystemsꢀare

intendedꢀtoꢀbeꢀimplantedꢀinꢀtheꢀhumanꢀbodyꢀorꢀtoꢀsupportꢀand/orꢀmaintainꢀandꢀsustainꢀand/orꢀprotectꢀhumanꢀlife.ꢀIfꢀtheyꢀfail,ꢀitꢀis

reasonableꢀtoꢀassumeꢀthatꢀtheꢀhealthꢀofꢀtheꢀuserꢀorꢀotherꢀpersonsꢀmayꢀbeꢀendangered.

38

Rev.ꢀ2.1,ꢀꢀ2021-10-18


型号：	1EDN7146G
厂家：	Infineon
描述：	EiceDRIVER™ 200 V 高侧 TDI 栅极驱动器 IC，专为 CoolGaN™ SG HEMT 和硅 MOSFET 而优化栅极驱动驱动器
文件：	总38页 (文件大小：1662K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

1EDN7146G [INFINEON]

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