1EDN7550B [INFINEON]
Single-channel EiceDRIVER⢠gate-drive IC with true differential inputs;
| 型号： | 1EDN7550B |
| 厂家： | 
Infineon |
| 描述： | Single-channel EiceDRIVER⢠gate-drive IC with true differential inputs 驱动 |
| 文件： | 总27页 (文件大小：1145K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
EiceDRIVER™ 1EDN7550 and 1EDN8550
™
Single-channel EiceDRIVER gate-drive IC with true differential inputs
Features
•
•
•
•
Very large common-mode input voltage range (CMR) up to ± 150 V (Table 1)
Supply voltage (VDD) up to 20 V
2 UVLO options: 4 V and 8 V
Separate low impedance source and sink outputs
-
-
4 A / 0.85 Ω source
8 A / 0.35 Ω sink
•
•
•
45 ns propagation delay with -7 / +10 ns accuracy
SOT23 or TSNP 6-pin package
Fully qualified for industrial applications according to JEDEC
Description
EiceDRIVER™ 1EDNx550 is a new family of single-channel non-isolated gate-driver ICs. Due to the unique fully
differential input circuitry with excellent common-mode rejection, the logic driver state is exclusively controlled
by the voltage difference between the two inputs, completely independent of the driver’s reference (ground)
potential. This eliminates the risk for false triggering and thus is a significant benefit in all applications
exhibiting voltage differences between driver and controller ground, a problem typical for systems with
•
•
•
4-pin packages (Kelvin Source connection)
high parasitic PCB inductances (long distances, single-layer PCB)
bipolar gate drive
In addition, within the common-mode voltage range CMR for PWM signal at 3.3 V as in (Table 1), 1EDNx550
allows to address even high-side and half-bridge applications. For PWM signals other than 3.3. V please see the
Application note Applications of 1EDNx550 single-channel lowside EiceDRIVER™ with truly differential inputs.
Table 1
Part number
Product portfolio
CMR static
+ 72 V / - 84 V
+ 72 V / - 84 V
+ 72 V / - 84 V
CMR dynamic
± 150 V
UVLO
4 V
Package
PG-SOT23-6
PG-SOT23-6
PG-TSNP-6
1EDN7550B
1EDN8550B
1EDN7550U
± 150 V
8 V
± 150 V
4 V
1EDNx550
ZVDD
VDD
Rgoff
Rin1
IN-
GND OUT_SRC
VDD
OUT_SNK
DVRin
SGND
Rgon
IN+
Rin2
CVDD
Figure 1
Typical application
Datasheet
www.infineon.com
Please read the Important Notice and Warnings at the end of this document
Rev. 2.2
2019-12-09
EiceDRIVER™ 1EDN7550 and 1EDN8550
™
Single-channel EiceDRIVER gate-drive IC with true differential inputs
Table of contents
Table of contents
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Table of contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1
2
Pin configuration and description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Differential input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Common mode input range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Driver outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Supply voltage and Undervoltage Lockout (UVLO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.1
3.1.1
3.2
3.3
4
Electrical characteristics and parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Operating range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.1
4.2
4.3
4.4
4.5
5
Typical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
6
Typical applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Switches with Kelvin source connection (4-pin packages) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Applications with significant parasitic PCB-inductances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Switches with bipolar gate drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
High-side switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6.1
6.2
6.3
6.4
7
Layout guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
8
8.1
8.2
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
PG-SOT23-6 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
PG-TSNP-6 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
9
Device numbers and markings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Disclaimer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Datasheet
2
Rev. 2.2
2019-12-09
EiceDRIVER™ 1EDN7550 and 1EDN8550
™
Single-channel EiceDRIVER gate-drive IC with true differential inputs
Pin configuration and description
1
Pin configuration and description
The pin configuration for both SOT23 and TSNP package is illustrated in Figure 2; a description is given in Table
2 . For functional details, please read Chapter 3.
SOT23-6
TSNP-6
IN-
OUT_SNK
1
2
3
6
5
4
OUT_SNK
OUT_SRC
VDD
IN-
1
2
6
5
4
GND
GND OUT_SRC
IN+
3
VDD
IN+
Figure 2
Table 2
Pin configuration SOT23 and TSNP 6-pin packages (top view)
Pin description
Pin number Pin name
Description
1
2
3
4
5
6
IN-
Negative input
connected to controller ground via resistor (typically 33 kΩ)
GND
Ground
negative gate drive voltage ("off" state)
IN+
Positive input
connected to PWM output of controller via resistor (typically 33 kΩ)
VDD
Positive supply voltage
positive gate drive voltage ("on" state)
OUT_SRC
OUT_SNK
Driver output source
low-impedance switch to VDD (4 A / 0.85 Ω)
Driver output sink
low-impedance switch to GND (8 A / 0.35 Ω)
Datasheet
3
Rev. 2.2
2019-12-09
EiceDRIVER™ 1EDN7550 and 1EDN8550
™
Single-channel EiceDRIVER gate-drive IC with true differential inputs
Block diagram
2
Block diagram
A simplified functional block diagram of 1EDNx550 is given in Figure 3.
UVLO
VDD
IN+
OUT_SRC
OUT_SNK
Differential
Schmitt
Trigger
Diff. Amp.
+ LPF
Logic
IN-
GND
Figure 3
Block diagram
Datasheet
4
Rev. 2.2
2019-12-09
EiceDRIVER™ 1EDN7550 and 1EDN8550
™
Single-channel EiceDRIVER gate-drive IC with true differential inputs
Functional description
3
Functional description
Although EiceDRIVER™ 1EDNx550 is a family of non-isolated gate drivers, it extends the range of possible
applications into fields usually reserved for isolated drivers, thereby generating significant system cost benefits.
The key to make this possible is moving from the standard ground related to a true differential input with very
high common-mode rejection. The required symmetry of the input circuitry is achieved by on-chip trimming; it
finally allows to deal with peak common-mode voltages of up to ± 150 V between driver reference (GND) and
system ground (SGND). 1EDNx550 is not only ideally suited for any application with unwanted shiꢀs between
driver and system ground, but may also be utilized as a high-side driver within the allowed common-mode
range. Besides, switches requiring a bipolar driving voltage can be operated very easily as well.
3.1
Differential input
Figure 4 depicts the signal path from the controller’s PWM output to the logic gate driver signal as implemented
on 1EDNx550.
Controller
PWM
1EDNx550
VS
Rin1
2kW
0
IN+
15pF
15pF
1kW
1kW
Cp1
Cp2
12 MHz
2nd order
Lowpass
Differential
Schmitt
Trigger
Pulse
Extender
Av = 4.5
DVRin
DVRin / k
IN-
SGND
Rin2
2kW
GND
k = (Rin [kW] + 3) / 3
Figure 4
1EDNx550 input signal path
The controller output signal, switching between controller supply VS and zero, is applied at the one leg of a
differential voltage divider, while the other is connected to the controller ground SGND. The divider ratio has to
be adapted to VS to allow a fixed Schmitt-Trigger threshold voltage. For VS = 3.3 V, Rin1 and Rin2 are chosen to be
33 kΩ, resulting in a static divider ratio of k = 12 at the driver inputs and 36 at the internal voltage amplifier. With
VS other than 3.3 V, Rin has to fulfil the relation:
R
= R = 10.9 VS − 3 kΩ
in1
in2
Amplified by a factor of 4.5, the signal is filtered by a 2nd order low-pass filter. Taking into account the RC filter in
front of the amplifier, the overall input path exhibits the frequency behavior of a 3rd order low-pass filter with a
corner frequency around 12 MHz. The suppression of high frequencies is important for two reasons. Firstly,
common-mode ringing, being in the 100 MHz and above range for fast-switching power systems, can effectively
be damped. In addition, the high-frequency symmetry of the voltage divider is influenced by parasitic
capacitances, particularly Cp1 and Cp2, the parallel capacitances of Rin1 and Rin2. They are typically in the 50 to
100 fF range, rather independent of resistor size. Without filtering, any asymmetry would translate high-
frequency common-mode into differential signals.
The filtered signal is then applied to a differential Schmitt-Trigger with accurate trimmed threshold levels and
converted to the logic switch control signal. The subsequent pulse extender function guarantees that no pulses
shorter than 25 ns are transmitted to the output, thereby further improving noise immunity.
Due to the filtering requirements the input-to-output propagation delay is slightly increased to around 45 ns. By
means of on-chip trimming, however, the usually more relevant propagation delay variation can still be kept
low at +10 / -7 ns.
Datasheet
5
Rev. 2.2
2019-12-09
EiceDRIVER™ 1EDN7550 and 1EDN8550
™
Single-channel EiceDRIVER gate-drive IC with true differential inputs
Functional description
3.1.1
Common mode input range
There are two effects limiting the common-mode input range, i.e. the maximum allowed voltage difference
between controller outputs PWM/SGND and driver reference GND: the circuit and technology-related input
voltage restrictions and the finite common-mode rejection in the input signal path due to asymmetries.
The static voltage range at the input pins is limited to + 6 / - 7 V to guarantee accurate linear operation of the
input circuitry. Taking into account the proposed DC voltage divider ratio, this translates to a static common-
mode (CMR) range of + 72 / - 84 V. CMR is increased even further for high-frequency common-mode voltages
("ringing"). Then the maximum input voltage ratings ( ± 10 V) together with the frequency-dependence of the
voltage-divider ratio result in an extended dynamic CMR as high as ± 150 V.
The second limitation results from the fact that any imbalance in the signal path converts a common-mode to a
differential signal. To utilize the full CMR as calculated above, the high accuracy of the trimmed on-chip network
must not be affected by the external voltage divider resistors. This condition is easily fulfilled when choosing
Rin1 and Rin2 with 0.1% tolerance; resistors with only 1% accuracy, however, would reduce the common-mode
range significantly to ± 40 V.
3.2
Driver outputs
The rail-to-rail driver output stage realized with complementary MOS transistors is able to provide a typical 4 A
sourcing and 8 A sinking current. The low on-resistance coming together with high driving current is particularly
beneficial for fast switching of very large MOSFETs. With a Ron of 0.85 Ω for the sourcing pMOS and 0.35 Ω for
the sinking nMOS transistor the driver can in most applications be considered to behave like an ideal switch.
The p-channel sourcing transistor allows real rail-to-rail behavior without suffering from the source-follower’s
voltage drop typical for n-channel output stages.
In case of floating inputs or insufficient supply voltage the driver output is actively clamped to the “low” level
(GND).
3.3
Supply voltage and Undervoltage Lockout (UVLO)
The Undervoltage Lockout function ensures that the output can be switched only, if the supply voltage VDD
exceeds the UVLO threshold voltage. Thus it can be guaranteed that the switch transistor is not operated with a
driving voltage too low to achieve a complete and fast transition to the "on" state; this avoids excessive power
dissipation (see Table 3).
Table 3
Logic table
ΔVRin
x
L2)
UVLO
active1)
inactive 3)
inactive 3)
OUT_SRC
high impedance
high impedance
H
OUT_SNK
L
L
H4)
high impedance
EiceDRIVER™ 1EDNx550 is available in two different packages; the SOT23 version offers 2 UVLO threshold levels
to support switches with a broad range of threshold voltages
•
•
1EDN7550 with a typical UVLO threshold of 4.2 V (0.3 V hysteresis)
1EDN8550 with a typical UVLO threshold of 8 V (1 V hysteresis)
In addition, the high maximum VDD of 20 V makes the driver family well suited for a broad variety of power
switch types.
1
VDD < UVLOoff
ΔVRin < ΔVRinL
VDD > UVLOon
ΔVRin > ΔVRinH
2
3
4
Datasheet
6
Rev. 2.2
2019-12-09
EiceDRIVER™ 1EDN7550 and 1EDN8550
™
Single-channel EiceDRIVER gate-drive IC with true differential inputs
Electrical characteristics and parameters
4
Electrical characteristics and parameters
The absolute maximum ratings are listed in Table 4 . Stresses beyond these values may cause permanent
damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability.
4.1
Absolute maximum ratings
Table 4
Absolute Maximum Ratings
Parameter
Symbol
Min.
Values
Typ.
Unit Note or Test Condition
Max.
Supply voltage
VDD
-0.3
–
22
10
V
Voltage between VDD to
GND
Voltage at pins IN+ and IN-
Voltage at pin OUT_SRC
VIN
-10
–
–
V
V
–
VOUT_SRC -24
0.3
OUT = low; referred to
VDD pin, DC
-24
VOUT_SNK -0.3
-2
–
–
–
–
–
2
V
V
V
A
A
OUT = low; referred to
VDD pin < 200 ns
Voltage at pin OUT_SNK
24
24
–
OUT = high; referred to
GND pin, DC
OUT = high, referred to
GND pin < 200 ns
Peak reverse current at
OUT_SRC
ISRC_rev
ISRC_rev
-5
–
< 500 ns
Peak reverse current at
OUT_SRC
5
< 500 ns
Junction temperature
Storage temperature
ESD capability
Tj
-40
-55
–
–
–
–
150
150
2
°C
°C
kV
–
–
TS
VESD_HBM
Human Body Model
(HBM)5)
ESD capability
VESD_CDM
–
–
1
kV
Charged Device Model
(CDM)6)
5
According to ANSI/ESDA/JEDEC JS-001 (discharging 100 pF capacitor through 1.5 kΩ resistor)
According to ANSI/ESDA/JEDEC JS-002
6
Datasheet
7
Rev. 2.2
2019-12-09
EiceDRIVER™ 1EDN7550 and 1EDN8550
™
Single-channel EiceDRIVER gate-drive IC with true differential inputs
Electrical characteristics and parameters
4.2
Thermal characteristics
Table 5
Thermal characteristics SOT23 package
Parameter
Symbol
Values
Typ.
165.1
Unit
Note or Test Condition
Min.
Max.
Thermal resistance junction- RthJA25
–
–
–
–
–
–
–
–
–
–
K/W
K/W
K/W
K/W
K/W
–
–
–
–
–
ambient7)
Thermal resistance junction- RthJC25
79.9
65.2
14
case (top)8)
Thermal resistance junction- RthJB25
board9)
Characterization parameter ΨthJC25
junction-case (top)10)
Characterization parameter ΨthJB25
junction-board11)
51
Table 6
Thermal characteristics TSNP package
Symbol Values
Typ.
141
Parameter
Unit
Note or Test Condition
Min.
Max.
Thermal resistance junction- RthJA25
–
–
–
–
–
–
–
–
–
–
K/W
K/W
K/W
K/W
K/W
–
–
–
–
–
ambient 7)
Thermal resistance junction- RthJC25
81
36
80
36
case (top) 8)
Thermal resistance junction- RthJB25
board 9)
Characterization parameter ΨthJC25
junction-case (top) 10)
Characterization parameter ΨthJB25
junction-board 11)
7
Obtained in a simulation on a JEDEC-standard, high-K board, as specified in JESD51-7, in an environment
described in JESD51-2a
Obtained by simulating a cold plate test on the package top. No specific JEDEC standard test exists, but a
close description can be found in the ANSI SEMI standard G30-88
Obtained by simulation in an environment with a ring cold plate fixture to control the PCB temperature, as
described in JESD51-8
Estimates the junction temperature of a device in a real system and is extracted from the simulation data
for obtaining Rth, using a procedure described in JESD51-2a (sections 6 and 7)
Estimates the junction temperature of a device in a real system and is extracted from the simulation data
for obtaining Rth, using a procedure described in JESD51-2a (sections 6 and 7)
8
9
10
11
Datasheet
8
Rev. 2.2
2019-12-09
EiceDRIVER™ 1EDN7550 and 1EDN8550
™
Single-channel EiceDRIVER gate-drive IC with true differential inputs
Electrical characteristics and parameters
4.3
Operating range
Table 7
Operating Range
Symbol
Parameter
Values
Typ.
Unit Note or Test Condition
Min.
4.5
Max.
Supply voltage
VDD
–
–
–
20
6
V
Min defined by UVLO
Voltage at pins IN+ and IN-
Junction temperature
VIN
Tj
-7
V
–
12)
-40
150
°C
4.4
Electrical characteristics
Unless otherwise noted, min./max. values of characteristics are the lower and upper limits, respectively. They
are valid within the full operating range. The supply voltage is VDD= 12 V. Typical values are given at Tj=25°C.
Table 8
Power Supply
Parameter
Symbol
Values
Typ.
Unit Note or Test Condition
Min.
Max.
VDD quiescent current
VDD quiescent current
IVDDh
IVDDl
–
–
1.1
0.9
–
–
mA
mA
OUT = high
OUT = low
Table 9
Undervoltage Lockout 1EDN7550x (Logic level MOSFET)
Parameter
Symbol
Values
Typ.
Unit Note or Test Condition
Min.
3.9
Max.
4.5
Undervoltage Lockout (UVLO) UVLOon
turn on threshold
4.2
V
V
V
–
–
–
Undervoltage Lockout (UVLO) UVLOoff
turn off threshold
–
3.9
0.3
–
UVLO threshold hysteresis
UVLOhys 0.25
0.35
Table 10
Undervoltage Lockout 1EDN8550B (Standard MOSFET)
Parameter
Symbol
Values
Typ.
Unit Note or Test Condition
Min.
7.4
Max.
8.6
Undervoltage Lockout (UVLO) UVLOon
turn on threshold
8.0
V
V
V
–
–
–
Undervoltage Lockout (UVLO) UVLOoff
turn off threshold
–
7.0
1.0
–
UVLO threshold hysteresis
UVLOhys 0.8
1.2
12
Continuous operation above 125°C may reduce life time
Datasheet
9
Rev. 2.2
2019-12-09
EiceDRIVER™ 1EDN7550 and 1EDN8550
™
Single-channel EiceDRIVER gate-drive IC with true differential inputs
Electrical characteristics and parameters
Table 11
Inputs IN+, IN-
Parameter
Symbol
Values
Typ.
Unit Note or Test Condition
Min.
Max.
Differential input voltage
threshold for transition LH (at
input resistor)
∆VRinH
–
–
–
1.7
–
–
–
V
Independent of VDD
Rin1/Rin2 = 33 kΩ 13)
Differential input voltage
threshold for transition HL (at
input resistor)
∆VRinL
1.5
36
V
Independent of VDD
Rin1/Rin2 = 33 kΩ 13)
Total input resistance on each Rin1 / Rin2
leg
kΩ
Rin1/Rin2 = 33 kΩ 13)
Table 12
Static Output Characteristics
Parameter
Symbol
Min.
Values
Typ.
0.85
Unit Note or Test Condition
Max.
High-level (sourcing) output
resistance
Ron_SRC
–
–
Ω
ISRC = 50 mA
14)
Sourcing output current
ISRC_pk
–
–
4.0
A
–
Low-level (sinking) output
resistance
Ron_SNK
0.35
–
Ω
ISNK = 50 mA
15)
Sinking output current
ISNK_pk
–
-8.0
A
–
Table 13
Dynamic characteristics
Symbol
Parameter
Values
Typ.
Unit Note or Test Condition
Min.
Max.
Input-to-output propagation tPDon
38
38
45
55
55
ns
ns
CL = 200 pF
CL = 200 pF
delay turn-on
Input-to-output propagation tPDoff
delay turn-off
45
Rise time
Fall time
Rise time
Fall Time
trise
tfall
trise
tfall
tPW
—
—
—
—
—
6.5
4.5
1
1516)
1516)
516)
516)
—
ns
ns
ns
ns
ns
CL = 1.8 nF
CL = 1.8 nF
CL = 200 pF
CL = 200 pF
CL = 1.8 nF
1
Minimum input pulse width
that changes output state
2516)
For an illustration of the dynamic characteristics see Figure 6 and Figure 7
Figure 5 gives the circuit used for parameter testing
13
See Figure 1
14
Actively limited to approx. 5.2 Apk; not subject to production test - verified by design / characterization
Actively limited to approx. -10.4 Apk; not subject to production test - verified by design / characterization
Parameter verified by design, not 100% tested in production
15
16
Datasheet
10
Rev. 2.2
2019-12-09
EiceDRIVER™ 1EDN7550 and 1EDN8550
™
Single-channel EiceDRIVER gate-drive IC with true differential inputs
Electrical characteristics and parameters
Figure 5
Test circuit
4.5
Timing diagram
Figure 6 depicts rise, fall and delay times as given in the Chapter 4.
1.7
1.5
IN+ - IN-
50%
90%
10%
OUTx
tPDoff
tPDon
trise
tfall
Figure 6
Propagation delay, rise and fall time
Figure 7 illustrates the Undervoltage Lockout function.
UVLOon
UVLOoff
VDD
OUTx
Figure 7
UVLO behavior (output state high)
Datasheet
11
Rev. 2.2
2019-12-09
EiceDRIVER™ 1EDN7550 and 1EDN8550
™
Single-channel EiceDRIVER gate-drive IC with true differential inputs
Typical characteristics
5
Typical characteristics
1.
Undervoltage Lockout threshold (1EDN7550) 2.
vs temperature
Undervoltage Lockout threshold (1EDN8550)
vs temperature
4.5
8.8
UVLO on
UVLO off
UVLO on
UVLO off
8.4
8.0
7.6
7.2
6.8
6.4
4.3
4.1
3.9
3.7
-50
0
50
100
150
-50
0
50
100
150
T [ °C]
j
T [°C]
j
3.
Differential input voltage threshold vs
temperature
4.
Typical quiescent current vs temperature
2.5
1.4
ON threshold
OFF threshold
OUT High
OUT Low
2.3
2.1
1.9
1.7
1.5
1.3
1.1
1.2
1.0
0.8
0.6
VDD=12V
Vin=3.3V
-50
0
50
100
150
-50
0
50
100
150
T [ °C]
j
T [°C]
j
Datasheet
12
Rev. 2.2
2019-12-09
EiceDRIVER™ 1EDN7550 and 1EDN8550
™
Single-channel EiceDRIVER gate-drive IC with true differential inputs
Typical characteristics
5.
Typical quiescent current vs supply voltage 6.
Total operating current consumption with
capacitive load vs frequency
1.6
50
VDD 4.5V
VDD 12V
VDD 20V
OUT High
OUT Low
Duty Cycle 50%
CL = 1.8nF
1.5
1.4
1.3
1.2
1.1
1.0
0.9
0.8
0.7
0.6
40
30
20
10
0
0
200
400
600
800
1000
0
5
10
15
20
25
Frequency [kHz]
VDD [V]
7.
Typical propagation delay vs temperature
8.
Typical rise and fall time vs temperature
8
turn-on
turn-on
54
turn-off
turn-off
7
52
50
48
46
44
6
5
4
VDD=12V
CL=1.8nF
42
VDD=12V
Vin=3.3V
3
40
-50
0
50
100
150
-50
0
50
100
150
T [ °C]
j
T [ °C]
j
Datasheet
13
Rev. 2.2
2019-12-09
EiceDRIVER™ 1EDN7550 and 1EDN8550
™
Single-channel EiceDRIVER gate-drive IC with true differential inputs
Typical applications
6
Typical applications
6.1
Switches with Kelvin source connection (4-pin packages)
This is one of the key target applications of 1EDNx550. The 4-pin configuration depicted in Figure 8 is a very
effective measure to improve the switching performance of transistors in packages with high source inductance
LS as is typical for the widely used TO-packages. Although the Kelvin Source connection SS solves the problem
of the largely increased switching losses due to LS, it is evident, that the gate driver reference potential is
moving by the inductive voltage drop vLS with respect to the system ground SGND. In fast-switching
applications at high current, vLS can reach 100 V and above. This is why 4-pin systems so far either used isolated
drivers or external filters with relatively low corner frequency that add significant signal delay. Now, however,
1EDNx550 provides an optimum solution for this case.
Figure 8 also indicates that the usually SGND-related VDD cannot be used directly as the driver supply. But due
to the high frequency of vLS (> 100 MHz), a filter composed of impedance ZVDD together with the blocking cap
CVDD is well suited to generate a sufficiently stable driver supply. ZVDD can be either a resistor (e.g. 22 Ω with a
typical CVDD of 1 µF) or, even better, a proper ferrite bead.
MOSFET
VDD
ZVDD
Controller
1EDNx550
D
Rgoff
Rin1
IN- OUT_SNK
GND OUT_SRC
SGND
G
SGND
ΔVRin
Rgon
CVDD
VDD
IN+
PWM_Out
Rin2
SS
vLS
LS
S
Figure 8
1EDN driving 4-pin MOSFET
6.2
Applications with significant parasitic PCB-inductances
In fast switching power systems the unavoidable parasitic inductance associated with any electrical connection
may cause significant inductive voltage drops, particularly if the PCB-layout cannot be optimized, the most
common reasons being limitations in the number of PCB-layers, geometric restrictions or also the lack of
specific experience. In such situations the high robustness of 1EDNx550 with respect to “switching noise” (high-
frequency voltage between reference potential of driver and controller) is extremely valuable and allows good
performance even in systems with formerly critical layout. Figure 9 indicates a respective example, indicating
the most relevant parasitic PCB-inductances.
Datasheet
14
Rev. 2.2
2019-12-09
EiceDRIVER™ 1EDN7550 and 1EDN8550
™
Single-channel EiceDRIVER gate-drive IC with true differential inputs
Typical applications
MOSFET
1EDNx550
Controller
ZVDD
Rgoff
D
Rin1
IN-
GND OUT_SRC
VDD
OUT_SNK
SGND
VDD
G
DVRin
Rgon
IN+
PWM_Out
S
Rin2
CVDD
SGND
Figure 9
Application with significant PCB inductance
6.3
Switches with bipolar gate drive
Another application 1EDNx550 is tailored for, is driving power switches that require a negative gate-to-source
voltage to safely hold them in the “off” state. Although MOSFETs are usually operated at zero “off” voltage, in
certain situations a negative gate drive voltage can be very helpful. Particularly the fast switching “off” of high
current when using switches with large common source inductance (e.g. in 3-pin TO-packages) may become
critical in terms of losses and stability with a zero “off” level. In such cases a negative gate drive voltage is able
to significantly improve switching performance. As depicted in Figure 10, this kind of application is completely
uncritical and handled easily with 1EDNx550, while standard drivers cannot be applied directly without
adaptations.
MOSFET
Controller
1EDNx550
D
Rgoff
Rin1
SGND
ΔVRin
IN- OUT_SNK
GND OUT_SRC
SGND
G
Rgon
VDD
IN+
PWM_Out
Rin2
S
Figure 10
Bipolar gate drive for 3-pin MOSFET
Datasheet
15
Rev. 2.2
2019-12-09
EiceDRIVER™ 1EDN7550 and 1EDN8550
™
Single-channel EiceDRIVER gate-drive IC with true differential inputs
Typical applications
6.4
High-side switches
Due to the large static input common-mode range, even driving high-side switches is an interesting application
field for 1EDNx550. Although not providing galvanic isolation, 1EDNx550 can functionally be used as a high-side
driver, as long as the power-loop voltage VP does not cause a violation of the allowed common-mode range.
In high-side operation as depicted in Figure 11, the driver ground GND switches between zero (“off” ) and VP
(“on" state) with respect to SGND; the resulting common-mode voltage at the driver input pins is 0 and -VP/12,
respectively. The input voltage restriction to -7 V (Table 7) thus limits VP to 84 V. In many applications the driver
supply voltage can be generated by means of the well-known bootstrapping method also indicated in Figure 11.
Dboot
VDD
VP < 84V
1EDNx550
Rboot
Rgoff
D
Controller
Rin1
SGND
ΔVRin
IN- OUT_SNK
GND OUT_SRC
SGND
G
Rgon
VDD
IN+
PWM_Out
S
Rin2
Cboot
Vsw
D
G
S
Figure 11
1EDNx550 as a high-side driver
Datasheet
16
Rev. 2.2
2019-12-09
EiceDRIVER™ 1EDN7550 and 1EDN8550
™
Single-channel EiceDRIVER gate-drive IC with true differential inputs
Layout guidelines
7
Layout guidelines
It is well-known that the layout of a fast-switching power system is a critical task with strong influence on the
overall performance. This is why there exists a huge number of rules, recommendations, guidelines, tips and
tricks that should help to finally end up with a proper system layout.
With 1EDNx550 one of the central layout problems, namely the design of the grounding network, has become
much less critical due to the highly reduced sensitivity of the differential concept with respect to ground voltage
differences. So layout rules can be restricted to the following rather simple and evident ones:
•
place input resistors Rin close to the driver and make layout of input signal path as symmetric and as
compact as possible
•
•
use a low-ESR decoupling capacitance for the VDD supply and place it as close as possible to the driver
minimize power loop inductance as the most critical limitation of switching speed due to the resulting
unavoidable voltage overshoots
A layout recommendation for the input path of the SOT23 package version is given in Figure 12.
RGOFF
DRV_GND
RIN1
IN_N
IN_P
IN-
GND
IN+
OUT_SNK
OUT_SRC
VDD
OUT
RGON
CVDD
RVDD
RIN2
VIN
Figure 12
Layout recommendation for SOT23 package
As in the case of the TSNP package routing in a single PCB layer is not possible, the layout can be changed
according to Figure 13 . The chosen size of the input resistors (0603) allows to utilize the full dynamic common-
mode input range of ±150 V.
DRV_GND
RGOFF
RIN1
IN_N
IN_P
1EDN7550U
GND
OUT_SRC
OUT
RGON
CVDD
RIN2
VIN
RVDD
Figure 13
Layout recommendation for TSNP package with SMD resistor 0603
Datasheet
17
Rev. 2.2
2019-12-09
EiceDRIVER™ 1EDN7550 and 1EDN8550
™
Single-channel EiceDRIVER gate-drive IC with true differential inputs
Layout guidelines
For applications that do not require the maximum CMR an even more compact layout utilizing resistors of size
0402 is shown in Figure 14.
RGOFF
DRV_GND
RIN1
1EDN7550U
IN_N
IN_P
OUT
GND
OUT_SRC
RGON
CVDD
RIN2
RVDD
VIN
Figure 14
Layout recommendation for TSNP package with SMD resistor 0402
For futher layout recommendations for TSNP, see Recommendations for Printed Circuit Board Assembly of
Infineon TSLP/TSSLP/TSNP Packages.
Datasheet
18
Rev. 2.2
2019-12-09
EiceDRIVER™ 1EDN7550 and 1EDN8550
™
Single-channel EiceDRIVER gate-drive IC with true differential inputs
Package information
8
Package information
8.1
PG-SOT23-6 package
1)
1)
2.9
1.6
0.15 C A-B
2x
0.15 C D 2x
0.45±0.1
2.8
C
0.1 C
COPLANARITY
0.2 C
6x
SEATING
D
PLANE
0.4±0.1
0.2
C A B
6x
BOTTOM VIEW
A
6
4
6
4
1
3
3
1
INDEX
MARKING
B
0.95
1) DOES NOT INCLUDE PLASTIC OR METAL PROTRUSION OF 0.15 MAX. PER SIDE
ALL DIMENSIONS ARE IN UNITS MM
THE DRAWING IS IN COMPLIANCE WITH ISO 128 & PROJECTION METHOD 1 [
]
Figure 15
SOT23 outline
Datasheet
19
Rev. 2.2
2019-12-09
EiceDRIVER™ 1EDN7550 and 1EDN8550
™
Single-channel EiceDRIVER gate-drive IC with true differential inputs
Package information
0.95
0.5
0.95
0.5
copper
solder mask
stencil apertures
ALL DIMENSIONS ARE IN UNITS MM
Figure 16
SOT23 footprint
4
4
0.25
PIN 1
INDEX MARKING
3.3
1.55
ALL DIMENSIONS ARE IN UNITS MM
THE DRAWING IS IN COMPLIANCE WITH ISO 128 & PROJECTION METHOD 1 [
]
Figure 17
SOT23 packaging
Datasheet
20
Rev. 2.2
2019-12-09
EiceDRIVER™ 1EDN7550 and 1EDN8550
™
Single-channel EiceDRIVER gate-drive IC with true differential inputs
Package information
Type code
Pin 1 marking
Date code (YW)
Figure 18
Package marking (SOT23)
Note:
Date code digits Y and W in Table Table 14 and Table 15
Table 14
Year date code marking - digit "Y"
Year
2000
2001
2002
2003
2004
2005
2006
2007
2008
2009
Y
0
1
2
3
4
5
6
7
8
9
Year
2010
2011
2012
2013
2014
2015
2016
2017
2018
2019
Y
0
1
2
3
4
5
6
7
8
9
Year
2020
2021
2022
2023
2024
2025
2026
2027
2028
2029
Y
0
1
2
3
4
5
6
7
8
9
Table 15
Week date code marking - digit "W"
Week
W
A
B
C
D
E
Week
12
W
N
P
Q
R
S
Week
23
W
4
5
6
7
a
b
c
Week
W
h
j
Week
45
46
47
48
49
50
51
52
–
W
v
x
1
34
35
36
37
38
39
40
41
42
43
44
2
13
24
3
14
25
k
l
y
z
4
15
26
5
16
27
n
p
q
r
8
9
2
3
–
–
–
6
F
17
T
28
7
G
H
J
18
U
V
29
8
19
30
d
e
f
9
20
W
Y
31
s
10
11
K
L
21
32
t
–
22
Z
33
g
u
–
Datasheet
21
Rev. 2.2
2019-12-09
EiceDRIVER™ 1EDN7550 and 1EDN8550
™
Single-channel EiceDRIVER gate-drive IC with true differential inputs
Package information
8.2
PG-TSNP-6 package
1.1±0.05
0.375±0.025
0.3±0.05
A
0.1 A
6x
3
2
1
4
5
6
INDEX MARKING
(LASERED)
0.6
ALL DIMENSIONS ARE IN UNITS MM
THE DRAWING IS IN COMPLIANCE WITH ISO 128 & PROJECTION METHOD 1 [
]
Figure 19
TSNP-6 outline
Datasheet
22
Rev. 2.2
2019-12-09
EiceDRIVER™ 1EDN7550 and 1EDN8550
™
Single-channel EiceDRIVER gate-drive IC with true differential inputs
Package information
Optional solder mask dam
0.35
0.6
0.6
copper
solder mask
stencil apertures
ALL DIMENSIONS ARE IN UNITS MM
Figure 20
TSNP-6 footprint
4
PIN 1
INDEX MARKING
4
0.5
1.3
ALL DIMENSIONS ARE IN UNITS MM
THE DRAWING IS IN COMPLIANCE WITH ISO 128 & PROJECTION METHOD 1 [
]
Figure 21
TSNP-6 packaging
Datasheet
23
Rev. 2.2
2019-12-09
EiceDRIVER™ 1EDN7550 and 1EDN8550
™
Single-channel EiceDRIVER gate-drive IC with true differential inputs
Package information
Pin 1 marking
Date code (YW)
Type code
Figure 22
Package marking (TSNP-6)
Note:
Date code digits Y and W in Table and Table 14 and Table 15
Further information on packages: www.infineon.com/packages
Datasheet
24
Rev. 2.2
2019-12-09
EiceDRIVER™ 1EDN7550 and 1EDN8550
™
Single-channel EiceDRIVER gate-drive IC with true differential inputs
Device numbers and markings
9
Device numbers and markings
Table 16
Device numbers and markings
Part number
1EDN7550B
1EDN8550B
1EDN7550U
Orderable part number (OPN)
1EDN7550BXTSA1
Device marking
70
80
70
1EDN8550BXTSA1
1EDN7550UXTSA1
Datasheet
25
Rev. 2.2
2019-12-09
EiceDRIVER™ 1EDN7550 and 1EDN8550
™
Single-channel EiceDRIVER gate-drive IC with true differential inputs
Revision history
Revision history
Document
version
Date of
release
Description of changes
Rev.2.2
2019-12-09
•
•
Added new product 1EDN7550U with package TSNP-6
On front cover "Description", added reference to application note
(Applications of 1EDNx550 single-channel lowside EiceDRIVER™ with
truly differential inputs.) for input PWM signal voltage levels other than
3.3 V
•
•
•
•
•
•
•
Added Table 3, Logic table
Corrected footnote in Table 4 VESD_HDM
Updated Max. value in Table 4 VESD_CDM and added footnote
Updated Thermal characteristics in Table 5 and added Table 6
Updated Typ. values for Table 8 and added footnotes for Table 13
Added Figure 5 for Test circuit
Added layout recommendations for TSNP package Figure 13 and Figure
14
•
Added package marking for SOT23 Figure 18 and code marking tables
Table 14, Table 15
•
•
Added package marking for TSNP Figure 22
Added Chapter 9, Device numbers and markings
Rev. 2.1
2019-11-28
•
Parameter split in Table 4 Voltage at pins OUT_SRC and OUT_SNK →
Voltage at pin OUT_SRC and Voltage at pin OUT_SNK and specified min.
and max.
•
•
Corrected typo in Table 4 VESD_CDM
To match pin configurations in Figure 2 update of Figure 1 as well as in
Chapter 5 the Figure 8 to Figure 11.
•
•
•
Updated diagram according to number of OUT pins → OUTx, Figure 7
CLoad → CL for Fig 12 and Fig 14
Updated to latest package diagrams, Chapter 8
Rev. 2.0
2018-05-14
Final Datasheet created
Datasheet
26
Rev. 2.2
2019-12-09
Trademarks
All referenced product or service names and trademarks are the property of their respective owners.
Edition 2019-12-09
Published by
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The information given in this document shall in no
event be regarded as a guarantee of conditions or
characteristics (“Beschaffenheitsgarantie”) .
With respect to any examples, hints or any typical values
stated herein and/or any information regarding the
application of the product, Infineon Technologies
hereby disclaims any and all warranties and liabilities of
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Document reference
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