2ED21091S06F_技术文档

2ED2106 (4) S06F (J)

650 V high-side and low-side gate driver with integrated bootstrap diode

Features

Product summary

•

Unique Infineon Thin-Film-Silicon On Insulator (SOI)-technology

Negative VS transient immunity of 100 V

V_{S_OFFSET}= 650 V max

I_o+pk/ I_o-pk(typ.) = + 0.29 A/ - 0.7 A

V_CC= 10 V to 20 V

Delay matching = 35 ns max.

Propogation delay = 200 ns

t_ON/ t_OFF(typ.) = 200 ns/ 200 ns

Floating channel designed for bootstrap operation

Operating voltages (VS node) upto + 650 V

Maximum bootstrap voltage (VB node) of + 675 V

Integrated ultra-fast, low resistance bootstrap diode

Logic operational up to –11 V on VS Pin

Negative voltage tolerance on inputs of –5 V

Independent under voltage lockout for both channels

Schmitt trigger inputs with hysteresis

3.3 V, 5 V and 15 V input logic compatible

Maximum supply voltage of 25 V

Dual package options of DSO-8 and DSO-14

High and low voltage pins separated for maximum creepage and

clearance (2ED21064S06J version)

Packages

•

Separate logic and power ground with the 2ED21064S06J version

RoHS compliant

DSO-14

DSO-8

Potential applications

Driving IGBTs, enhancement mode N-Channel MOSFETs in various power electronic applications.

Typical Infineon recommendations are as below:

•

Motor drives, general purpose inverters having TRENCHSTOP™ IGBT6 or 600 V EasyPACK™ modules or its

equivalent power stages

Refrigeration compressors, induction cookers, other major home appliances having RCD series IGBTs or

TRENCHSTOP™ family IGBTs or their equivalent power stages

Battery operated small home appliances such as power tools, vaccum cleaners using low voltage OptiMOS™

MOSFETs or their equivalent power stages

Totem pole, half-bridge and full-bridge converters in offline AC-DC power supplies for industrial SMPS having

high voltage CoolMOS™ super junction MOSFETs or TRENCHSTOP™ H3 and WR5 IGBT series or their equivalent

High power LED and HID lighting having CoolMOS™ super junction MOSFETs

Electric vehicle (EV) charging stations and battery management systems

Driving 650 V SiC MOSFETs in above applications

•

Product validation

Qualified for industrial applications according to the relevant tests of JEDEC47/20/22

Ordering information

Standard pack

Base part number Package type

Orderable part number

Form

Quantity

2500

2ED2106S06F

2ED21064S06J

DSO - 8

DSO - 14

Tape and Reel

2ED2106S06FXUMA1

2ED21064S06JXUMA1

2500

Datasheet

www.infineon.com/soi

Please read the Important Notice and Warnings at the end of this document

Page 1 of 24

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2ED2106 (4) S06F (J)

650 V high-side and low-side gate driver with integrated bootstrap diode

Description

The 2ED2106(4)S06F(J) is a high voltage, high speed power MOSFET and IGBT driver with independent high and

low side referenced output channels. Based on Infineon’s SOI-technology there is an excellent ruggedness and

noise immunity with capability to maintain operational logic at negative voltages of up to - 11 V on VS pin (V_CC

=

15 V) on transient voltages. There are not any parasitic thyristor structures present in the device, hence no

parasitic latch up may occur at all temperature and voltage conditions. The logic input is compatible with

standard CMOS or LSTTL output, down to 3.3 V logic. The output drivers feature a high pulse current buffer stage

designed for minimum driver cross-conduction. The floating channel can be used to drive an N-channel power

MOSFET, SiC MOSFET or IGBT in the high side configuration, which operate up to 650 V.

Refer to lead assignments for

correct pin configuration. This

diagram shows electrical

connections only. Please refer to

our application notes and design

tips for proper circuit board

layout.

*Bootstrap diode is monolithically integrated

Figure 1

Typical application block diagram

Summary of feature comparison of the 2ED210x family:

Table 1

Cross

Input

logic

conduction

prevention

logic

Part No.

Deadtime

Ground pins t_ON/ t_OFFPackage

2ED2106S06F

2ED21064S06J

2ED2108S06F

COM

DSO - 8

DSO - 14

DSO - 8

HIN, LIN

No

None

VSS / COM

COM

200 ns /

200 ns

Internal 540 ns

Yes

HIN, LIN

Programmable

540 ns - 5000 ns

2ED21084S06J

2ED2109S06F

2ED21094S06J

VSS / COM

COM

DSO - 14

DSO - 8

Internal 540 ns

Yes

IN, SD

Programmable

540 ns - 5000 ns

VSS / COM

740 ns / DSO - 14

200 ns

Programmable

540 ns - 2700 ns

2ED21091S06F IN, DT/SD Yes

COM

DSO – 8

Datasheet

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2ED2106 (4) S06F (J)

650 V high-side and low-side gate driver with integrated bootstrap diode

1

Table of contents

1

Table of contents ................................................................................................................... 3

2

Block diagram........................................................................................................................ 4

3

3.1

3.2

Pin configuration and functionality.......................................................................................... 5

Pin configuration.....................................................................................................................................5

Pin functionality ......................................................................................................................................5

4

Electrical parameters ............................................................................................................. 6

Absolute maximum ratings.....................................................................................................................6

Recommended operating conditions.....................................................................................................6

Static electrical characteristics...............................................................................................................7

Dynamic electrical characteristics..........................................................................................................8

4.1

4.2

4.3

4.4

5

Application information and additional details.......................................................................... 9

IGBT / MOSFET gate drive .......................................................................................................................9

Switching and timing relationships........................................................................................................9

Matched propagation delays ................................................................................................................10

Input logic compatibility.......................................................................................................................10

Undervoltage lockout ...........................................................................................................................11

Bootstrap diode.....................................................................................................................................11

Calculating the bootstrap capacitance C_BS..........................................................................................12

Tolerant to negative tranisents on input pins......................................................................................13

Negative voltage transient tolerance of VS pin....................................................................................14

NTSOA – Negative Transient Safe Operating Area...............................................................................15

Higher headroom for input to output signal transmission with logic operation upto -11 V..............16

Maximum switching frequency.............................................................................................................17

PCB layout tips ......................................................................................................................................18

5.1

5.2

5.3

5.4

5.5

5.6

5.7

5.8

5.9

5.10

5.11

5.12

5.13

6

7

8

9

Qualification information.......................................................................................................19

Related products...................................................................................................................19

Package details.....................................................................................................................20

Part marking information ......................................................................................................21

10

10.1

Additional documentation and resources.................................................................................22

Infineon online forum resources ..........................................................................................................22

11

Revision history ....................................................................................................................23

Datasheet

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2ED2106 (4) S06F (J)

650 V high-side and low-side gate driver with integrated bootstrap diode

2

Block diagram

8

VB

UV

DETECT

R

S

2ED2106S06F

7

6

HO

VS

Q

Pulse

Filter

VSS/COM

LEVEL

SHIFT

2

HIN

LIN

Pulse

Generator

BS diode

1

VCC

UV

DETECT

VSS/COM

LEVEL

SHIFT

5

4

LO

Delay

Match

3

COM

13

VB

UV

DETECT

R

S

12

11

HO

VS

Q

Pulse

Filter

2ED21064S06J

VSS/COM

LEVEL

SHIFT

2

HIN

Pulse

Generator

BS diode

1

VCC

UV

DETECT

VSS/COM

LEVEL

SHIFT

7

6

LO

Delay

Match

3

LIN

VSS

COM

5

Figure 2

Block diagrams

Datasheet

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2ED2106 (4) S06F (J)

650 V high-side and low-side gate driver with integrated bootstrap diode

3

Pin configuration and functionality

3.1

Pin configuration

14

13

1

2

3

4

5

6

7

VCC

HIN

LIN

VB

8

VB

HO

VS

LO

1

2

3

4

VCC

HIN

HO 12

7

6

5

VS

11

10

9

LIN

VSS

COM

8

LO

8 - Lead DSO - 8 (150 mil)

2ED2106S06F

14 - Lead DSO -14 (150 mil)

2ED21064S06J

Figure 3

2ED2106(4)S06F(J) pin assignments (top view)

3.2

Pin functionality

Table 2

Symbol

Description

VCC

Low-side and logic supply voltage

Logic input for high-side gate driver output (HO), in phase. Schmitt trigger inputs

with hysteresis and pull down

HIN

Logic input for low-side gate driver output (LO), in phase. Schmitt trigger inputs

with hysteresis and pull down

LIN

VSS

COM

LO

Logic ground ( 2ED21064S06J only)

Low-side gate drive return

Low-side driver output

VS

High voltage floating supply return

High-side driver output

HO

VB

High-side gate drive floating supply

Datasheet

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2ED2106 (4) S06F (J)

650 V high-side and low-side gate driver with integrated bootstrap diode

4

Electrical parameters

4.1

Absolute maximum ratings

Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage

parameters are absolute voltages referenced to COM unless otherwise stated in the table. The thermal resistance

and power dissipation ratings are measured under board mounted and still air conditions.

Table 3

Absolute maximum ratings

Definition

High-side floating well supply voltage ^{Note 1}

High-side floating well supply return voltage

Floating gate drive output voltage

Floating gate drive voltage supply voltage

Low side supply voltage

Symbol

V_B

Min.

V_CC– 5

Max.

675

Units

V_S

V_HO

V_BS

V_CC– V_BS– 5

650

V_S– 0.5

V_B+ 0.5

25

-1

V

V_CC

-1

25

V_LO

V_IN

V_SS

Low-side output voltage

Logic input voltage (HIN & LIN)

Logic ground (2ED21064S06J only)

–0.5

-5/ (V_SS– 5)

V_CC– 25

—

V_CC+ 0.5

50

dV_S/dt Allowable V_Soffset supply transient relative to COM

V/ns

W

—

-55

—

0.625

1

200

120

150

8 - Lead DSO - 8

14 - Lead DSO -14

8 - Lead DSO - 8

14 - Lead DSO -14

P_D

Package power dissipation @ T_A≤+25ºC

Rth_JA

Thermal resistance, junction to ambient

ºC/W

ºC

T_J

T_S

T_L

Junction temperature

Storage temperature

Lead temperature (soldering, 10 seconds)

150

300

Note 1:

activated bootstrap diode.

In case V_CC> V_Bthere is an additional power dissipation in the internal bootstrap diode between pins V_CCand V_Bin case of

4.2

Recommended operating conditions

For proper operation, the device should be used within the recommended conditions. All voltage parameters

are absolute voltages referenced to COM unless otherwise stated in the table. The offset rating is tested with

supplies of (V_CC– COM) = (V_B– V_S) = 15 V.

Table 4

Recommended operating conditions

Symbol

V_B

Definition

Bootstrap voltage

High-side floating well supply voltage

High-side floating well supply offset voltage ^{Note 2}

Floating gate drive output voltage

Low-side supply voltage

Low-side output voltage

Logic input voltage(HIN & LIN)

Logic ground (2ED21064S06J only) with respect to COM

Ambient temperature

Min

V_S+ 10

10

Max

V_S+ 20

20

650

V_B

Units

V

V_BS

V_S

V_HO

V_CC

V_LO

V_IN

V_SS

T_A

V_CC– V_BS– 1

V_S

10

COM

20

V_CC

-4 / (V_SS– 4) 5 / (V_SS+ 5)

-5

-40

+5

125

ºC

Note 2: Logic operation for V_Sof – 11 V to +650 V.

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2ED2106 (4) S06F (J)

650 V high-side and low-side gate driver with integrated bootstrap diode

4.3

Static electrical characteristics

(V_CC– COM) = (V_B– V_S) = 15 V, V_SS= COM and T_A= 25 °C unless otherwise specified. The V_IL,V_IHand I_INparameters are

referenced to Vss / COM and are applicable to the respective input leads: HIN and LIN. The V_Oand I_Oparameters

are referenced to V_S/ COM and are applicable to the respective output leads HO or LO. The V_CCUVparameters are

referenced to COM. The V_BSUVparameters are referenced to V_S.

Table 5

Symbol

Static electrical characteristics

Definition

V_BSsupply undervoltage positive going

threshold

Min.

Typ.

Max.

Units Test Conditions

V_BSUV

7.6

8.2

8.9

+

V_BSsupply undervoltage negative going

threshold

V_BSsupply undervoltage hysteresis

V_CCsupply undervoltage positive going

threshold

V_BSUV

6.7

—

7.2

1.0

9.1

8.1

—

-

V

V_BSUVHY

V_CCUV

8.4

9.8

+

V_CCsupply undervoltage negative going

threshold

V_CCUV

7.5

8.2

8.9

-

V_CCUVHY

I_LK

I_QBS

I_QCC

V_CCsupply undervoltage hysteresis

High-side floating well offset supply leakage

Quiescent V_BSsupply current

Quiescent V_CCsupply current

—

180

—

450

—

1.7

0.7

—

0.9

1

—

12.5

—

600

0.2

0.1

—

V_B= V_S= 650 V

170

300

0.05

0.02

230

290

650

700

2.1

0.9

25

uA

V_IN= 0 V or 5 V

V_OHHigh level output voltage drop, V_cc- V_{LO ,}V_B- V_HO

V_OLLow level output voltage drop, V_O

I_o+meanMean output current from 3 V to 6 V

V

I_O= 2 mA

C_L= 22 nF

V_O= 0 V

C_L= 22 nF

V_O= 15 V

I_o+

Peak output current turn-on¹

mA

I_o-meanMean output current from 12 V to 9 V

I_o-

V_IH

V_IL

Peak output current turn-off¹

Logic “1” input voltage

Logic “0” input voltage

2.4

1.1

50

1

V

µA

V

Vcc = 10 V to 20 V

I_IN+Input bias current (Output = High)

I_IN-

V_IN= 5 V

V_IN= 0 V

Input bias current (Output = Low)

Bootstrap diode forward voltage between Vcc

and VB

—

V_FBSD

—

1

1.2

I_F= 0.3 mA

Bootstrap diode forward current between Vcc

and VB

R_BSDBootstrap diode resistance

I_FBSD

45

20

—

85

30

125

45

mA

Ω

V_CC- V_B= 4 V

V_F1= 4 V,V_F2= 5 V

Vcc = 15 V

Allowable Negative VS pin voltage for IN

Signal propagation to HO

V_S

-11

-10

V

¹Not subjected to production test, verified by characterization.

Datasheet

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2ED2106 (4) S06F (J)

650 V high-side and low-side gate driver with integrated bootstrap diode

4.4

Dynamic electrical characteristics

V_CC= V_BS= 15 V, V_SS= COM, T_A= 25 ^oC and C_L= 1000 pF unless otherwise specified.

Table 6 Dynamic electrical characteristics

Test

Conditions

Symbol Definition

Min.

—

Typ.

200

100

35

Max.

300

150

80

Units

t_ONTurn-on propagation delay

t_OFFTurn-off propagation delay

V_LIN/HIN= 0 V

or 5 V

V_S= 0 V

t_R

t_F

Turn-on rise time

Turn-off fall time

ns

MT Delay matching time (HS & LS turn-on/off)

—

35

Datasheet

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2ED2106 (4) S06F (J)

650 V high-side and low-side gate driver with integrated bootstrap diode

5

Application information and additional details

5.1

IGBT / MOSFET gate drive

The 2ED2106 (4) S06F (J) HVIC is designed to drive MOSFET or IGBT power devices. Figure 4 and Figure 5 illustrate

several parameters associated with the gate drive functionality of the HVIC. The output current of the HVIC, used

to drive the gate of the power switch, is defined as I_O. The voltage that drives the gate of the external power switch

is defined as V_HOfor the high-side power switch and V_LOfor the low-side power switch; this parameter is

sometimes generically called V_OUTand in this case does not differentiate between the high-side or low-side output

voltage.

Figure 4

HVIC Sourcing current

Figure 5

HVIC Sinking current

5.2

Switching and timing relationships

The relationships between the input and output signals of the 2ED2106 (4) S06F (J) are illustrated below in

Figure 6 and Figure 7. From these figures, we can see the definitions of several timing parameters (i.e. t_ON, t_OFF

t_R, and t_F) associated with this device.

,

Figure 6

Switching timing diagram

Figure 7

Input/output logic diagram

Datasheet

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2ED2106 (4) S06F (J)

650 V high-side and low-side gate driver with integrated bootstrap diode

5.3

Matched propagation delays

The 2ED2106 (4) S06F (J) is designed with propagation delay matching circuitry. With this feature, the IC’s

response at the output to a signal at the input requires approximately the same time duration (i.e., tON, tOFF) for

both the low-side channels and the high-side channels; the maximum difference is specified by the delay

matching parameter (MT). The propagation turn-on delay (t_ON) of the 2ED2106 (4) S06F (J) is matched to the

propagation turn-off delay (t_OFF).

Figure 8

Delay matching waveform definition

5.4

Input logic compatibility

The input pins are based on a TTL and CMOS compatible input-threshold logic that is independent of the Vcc

supply voltage. With typical high threshold (V_IH) of 2.1 V and typical low threshold (V_IL) of 0.9 V, along with very

little temperature variation as summarized in Figure 9, the input pins are conveniently driven with logic level

PWM control signals derived from 3.3 V and 5 V digital power-controller devices. Wider hysteresis (typically 0.9

V) offers enhanced noise immunity compared to traditional TTL logic implementations, where the hysteresis is

typically less than 0.5 V. 2ED2106 (4) S06F (J) also features tight control of the input pin threshold voltage levels

which eases system design considerations and ensures stable operation across temperature. The 2ED2106 (4)

S06F (J) features floating input protection wherein if any of the input pin is left floating, the output of the

corresponding stage is held in the low state. This is achieved using pull-down resistors on all the input pins (HIN,

LIN) as shown in the block diagram. The 2ED2106 (4) S06F (J) has input pins that are capable of sustaining

voltages higher than the bias voltage applied on the Vcc pin of the device.

Figure 9

HIN & LIN input thresholds

Datasheet

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2ED2106 (4) S06F (J)

650 V high-side and low-side gate driver with integrated bootstrap diode

5.5

Undervoltage lockout

This IC provides undervoltage lockout protection on both the V_CC(logic and low-side circuitry) power supply and

the V_BS(high-side circuitry) power supply. Figure 10 is used to illustrate this concept; V_CC(or V_BS) is plotted over

time and as the waveform crosses the UVLO threshold (V_CCUV+/-or V_BSUV+/-) the undervoltage protection is enabled

or disabled.

Upon power-up, should the V_CCvoltage fail to reach the V_CCUV+threshold, the IC won’t turn-on. Additionally, if the

V_CCvoltage decreases below the V_CCUV-threshold during operation, the undervoltage lockout circuitry will

recognize a fault condition and shutdown the high and low-side gate drive outputs.

Upon power-up, should the V_BSvoltage fail to reach the V_BSUV+threshold, the IC won’t turn-on. Additionally, if the

V_BSvoltage decreases below the V_BSUV-threshold during operation, the undervoltage lockout circuitry will

recognize a fault condition, and shutdown the high-side gate drive outputs of the IC.

The UVLO protection ensures that the IC drives the external power devices only when the gate supply voltage is

sufficient to fully enhance the power devices. Without this feature, the gates of the external power switch could

be driven with a low voltage, resulting in the power switch conducting current while the channel impedance is

high; this could result in very high conduction losses within the power device and could lead to power device

failure.

Figure 10

UVLO protection

5.6

Bootstrap diode

An ultra-fast bootstrap diode is monolithically integrated for establishing the high side supply. The differential

resistor of the diode helps to avoid extremely high inrush currents when initially charging the bootstrap

capacitor. The integrated diode with its resistrance helps save cost and improve reliability by reducing external

components as shown below Figure 11 and Figure 12.

Figure 11

2ED210x with integrated components Figure 12

Standard bootstrap gate driver

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2ED2106 (4) S06F (J)

650 V high-side and low-side gate driver with integrated bootstrap diode

The low ohmic current limiting resistor provides essential advantages over other competitor devices with high

ohmic bootstrap structures. A low ohmic resistor such as in the 2ED210x family allows faster recharching of the

bootstrap capacitor during periods of small duty cycles on the low side transistor. The bootstrap diode is a real

pn-diode which works with all control algorithms of modern power electronics, such as trapezoidal or sinusoidal

motor drives control.

5.7

Calculating the bootstrap capacitance C_BS

Bootstrapping is a common method of pumping charges from a low potential to a higher one. With this technique

a supply voltage for the floating high side sections of the gate drive can be easily established according to Figure

13. This method has the advantage of being simple and low cost but may force some limitations on duty-cycle

and on-time since they are limited by the requirement to refresh the charge in the bootstrap capacitor.Proper

capacitor choice can reduce drastically these limitations.

Figure 13

Half bridge bootstrap circuit in 2ED210x

When the low side MOSFET turns on, it will force the potential of pin V_Sto GND. The existing difference between

the voltage of the bootstrap capacitor V_CBSand V_CCresults in a charging current I_BSinto the capacitor C_BS. The

current I_BSis a pulse current and therefore the ESR of the capacitor C_BSmust be very small in order to avoid losses

in the capacitor that result in lower lifetime of the capacitor. This pin is on high potential again after low side is

turned off and high side is conducting current. But now the bootstrap diode D_BSblocks a reverse current, so that

the charges on the capacitor cannot flow back to the capacitor C_VCC. The bootstrap diode D_BSalso takes over the

blocking voltage between pin V_Band V_CC. The voltage of the bootstrap capacitor can now supply the high side

gate drive sections. It is a general design rule for the location of bootstrap capacitors C_BS, that they must be placed

as close as possible to the IC. Otherwise, parasitic resistors and inductances may lead to voltage spikes, which

may trigger the undervoltage lockout threshold of the individual high side driver section. However, all parts of

the 2ED210x family, which have the UVLO also contain a filter at each supply section in order to actively avoid

such undesired UVLO triggers.

The current limiting resistor R_BSaccording to Figure 13 reduces the peak of the pulse current during the low side

MOSFET turn-on. The pulse current will occur at each turn-on of the low side MOSFET, so that with increasing

switching frequency the capacitor C_BSis charged more frequently. Therefore a smaller capacitor is suitable at

higher switching frequencies. The bootstrap capacitor is mainly discharged by two effects: The high side

quiescent current and the gate charge of the high side MOSFET to be turned on.

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2ED2106 (4) S06F (J)

650 V high-side and low-side gate driver with integrated bootstrap diode

The minimum size of the bootstrap capacitor is given by

ꢃ_ꢄꢅꢆꢅ

ꢀ_ꢁꢂ

=

∆ꢇ_ꢁꢂ

∆V_BSis the maximum allowable voltage drop at the bootstrap capacitor within a switching period, typically 1 V.

It is recommended to keep the voltage drop below the undervoltage lockout (UVLO) of the high side and limit

∆V_BS≤ (V_CC– V_F– V_GSmin– V_DSon

)

V_GSmin> V_BSUV-, V_GSminis the minimum gate source voltage we want to maintain and V_BSUV-is the high-side supply

undervoltage negative threshold.

V_CCis the IC voltage supply, V_Fis bootstrapdiode forward voltage and V_DSonis drain-source voltage of low side

MOSFET

Please note, that the value Q_GTOTmay vary to a maximum value based on different factors as explained below and

the capacitor shows voltage dependent derating behavior of its capacitance.

The influencing factors contributing V_BSto decrease are:

- MOSFET turn on required Gate charge (Q_G)

- MOSFET gate-source leakage current (I_{LK_GS}

)

- Floating section quiescent current (I_QBS

- Floating section leakage current (I_LK)

- Bootstrap diode leakage current (I_{LK_DIODE}

- Charge required by the internal level shifters (ꢃ_ꢈꢂ): typical 1nC

- Bootstrap capacitor leakage current (I_{LK_CAP}

)

- High side on time (T_HON

)

Considering the above,

ꢃ_ꢄꢅꢆꢅ= ꢃ_ꢄ+ ꢃ_ꢈꢂ+ ꢉꢊ_ꢋꢁꢂ+ ꢊ_ꢈꢌ+ ꢊ_ꢈꢌ+ ꢊ_ꢈꢌ

+ ꢊ_ꢈꢌꢖ ∗ ꢗ_ꢘꢆꢙ

ꢓꢔꢕ

ꢍꢎ

ꢏꢐꢑꢏꢒ

ILK_CAP is only relevant when using an electrolytic capacitor and can be ignored if other types of capacitors are

used. It is strongly recommend using at least one low ESR ceramic capacitor (paralleling electrolytic capacitor

and low ESR ceramic capacitor may result in an efficient solution).

The above C_BSequation is valid for pulse by pulse considerations. It is easy to see, that higher capacitance values

are needed, when operating continuously at small duty cycles of low side. The recommended bootstrap

capacitance is therefore in the range up to 4.7 μF for most switching frequencies. The performance of the

integrated bootstrap diode supports the requirement for small bootstrap capacitances.

5.8

Tolerant to negative tranisents on input pins

Typically the driver's ground pin is connected close to the source pin of the MOSFET or IGBT. The microcontroller

which sends the HIN and LIN PWM signals refers to the same ground and in most cases there will be an offset

voltage between the microcontroller ground pin and driver ground because of ground bounce. The 2ED210x

family can handle negative voltage spikes up to 5 V. The recommended operating level is at negative 4 V with

absolute maximum of negative 5 V. Standard half bridge or high-side/low-side gate drivers only allow negative

voltage levels down to -0.3 V. The 2ED210x family has much better noise immunity capability on the input pins.

Datasheet

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2ED2106 (4) S06F (J)

650 V high-side and low-side gate driver with integrated bootstrap diode

Figure 14

Negative voltage tolerance on inputs of upto –5 V

5.9

Negative voltage transient tolerance of VS pin

A common problem in today’s high-power switching converters is the transient response of the switch node’s

voltage as the power switches transition on and off quickly while carrying a large current. A typical 3-phase

inverter circuit is shown in Figure 15, here we define the power switches and diodes of the inverter.

If the high-side switch (e.g., the IGBT Q1 in Figure 15 and Figure 16) switches from on to off, while the U phase

current is flowing to an inductive load, a current commutation occurs from high-side switch (Q1) to the diode

(D2) in parallel with the low-side switch of the same inverter leg. At the same instance, the voltage node V_S1,

swings from the positive DC bus voltage to the negative DC bus voltage.

Figure 15

Three phase inverter

Also when the V phase current flows from the inductive load back to the inverter (see Figure 16 C) and D)), and

Q4 IGBT switches on, the current commutation occurs from D3 to Q4. At the same instance, the voltage node, V_S2,

swings from the positive DC bus voltage to the negative DC bus voltage.

However, in a real inverter circuit, the VS voltage swing does not stop at the level of the negative DC bus, rather

it swings below the level of the negative DC bus. This undershoot voltage is called “negative V_Stransient”

Datasheet

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2ED2106 (4) S06F (J)

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A)

D)

B)

C)

Figure 16

A) Q1 conducting

B) D2 conducting

C) D3 conducting

D) Q4 conducting

The circuit shown in Figure 17-A depicts one leg of the three phase inverter; Figure 17-B and 17-C show a

simplified illustration of the commutation of the current between Q1 and D2. The parasitic inductances in the

power circuit from the die bonding to the PCB tracks are lumped together in L_Cand L_Efor each IGBT. When the

high-side switch is on, V_S1is below the DC+ voltage by the voltage drops associated with the power switch and

the parasitic elements of the circuit. When the high-side power switch turns off, the load current momentarily

flows in the low-side freewheeling diode due to the inductive load connected to V_S1(the load is not shown in

these figures). This current flows from the DC- BUS (which is connected to the COM pin of the HVIC) to the load

and a negative voltage between V_S1and the DC- BUS is induced (i.e., the COM pin of the HVIC is at a higher

potential than the V_Spin).

A

C

B

Figure 17

Figure A shows the parasitic elements. Figure B shows the generation of V_Spositive. Figure C shows

the generation of V_Snegative

5.10

NTSOA – Negative Transient Safe Operating Area

In a typical motor drive system, dV/dt is typically designed to be in the range of 3 – 5 V / ns. The negative VS

transient voltage can exceed this range during some events such as short circuit and over-current shutdown,

when di/dt is greater than in normal operation.

Infineon’s HVICs have been designed for the robustness required in many of today’s demanding applications. An

indication of the 2ED2106 (4) S06F (J)’s robustness can be seen in Figure 18, where the 2ED2106 (4) S06F (J)’s Safe

Operating Area is shown at V_BS=15 V based on repetitive negative VS spikes. A negative VS transient voltage falling

in the grey area (outside SOA) may lead to IC permanent damage; viceversa unwanted functional anomalies or

permanent damage to the IC do not appear if negative Vs transients fall inside the SOA.

Datasheet

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2ED2106 (4) S06F (J)

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Recommended safe operating area

Figure 18

Negative VS transient SOA for 2ED2106 (4) S06F (J) @ VBS = 15 V

Even though the 2ED2106 (4) S06F (J) has been shown able to handle these large negative VS transient

conditions, it is highly recommended that the circuit designer always limit the negative VS transients as much

as possible by careful PCB layout and component use.

5.11

Higher headroom for input to output signal transmission with logic

operation upto -11 V

If there is not enough voltage for the level shifter to transmit a valid signal to the high side. High side driver

doesn’t turn on. The level shifter circuit is with respect to COM (refer to Block Diagram on page 4), the voltage

from V_Bto COM is the supply voltage of level shifter. Under the condition of VS is negative voltage with respect to

COM, the voltage of VS - COM is decreased, as shown in Figure 19. There is a minimum operational supply voltage

of level shifter, if the supply voltage of level shifter is too low, the level shifter cannot pass through HIN signal to

HO. The specification of VS is –11 V as the internal structure allows a voltage difference of 15 V between Vcc and

COM pins. If V_B– V_Svoltage is different, the minimum VS voltage changes accordingly.

VS

COM

- 11 V

Figure 19

Headroom for HV level shifter data transmission

Datasheet

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5.12

Maximum switching frequency

The 2ED2106 (4) S06F (J) is capable of switching at higher frequencies as compared to standard half-bridge or

high side / low side gate drivers. They are available in two packages, the PG-DSO-8 and the PG-DSO-14. It is

essential to ensure that the component is not thermally overloaded when operating at higher frequencies. This

can be checked by means of the thermal resistance junction to ambient and the calculation or measurement of

the dissipated power. The thermal resistance is given in the datasheet (section 4) and refers to a specific layout.

Changes of this layout may lead to an increased thermal resistance, which will reduce the total dissipated power

of the driver IC. One should therefore do temperature measurements in order to avoid thermal overload under

application relevant conditions of ambient temperature and housing.

The maximum chip temperature T_Jcan be calculated with

ꢗ = Pd ∙ ꢛꢜℎ_ꢚꢝ+ ꢗ

, where T_{A_max}is the maximum ambient temperature.

ꢚ

ꢝ_ꢞꢟꢠ

The dissipated power Pd by the driver IC is a combination of several sources. These are explained in detail in the

application note “2ED2106 (4) S06F (J) (HVICs)”

Here is the example of the figures which estimates the gate driver IC junction temperature when switching a given

MOSFET at different switching frequencies.

150

125

100

75

150

125

100

75

Vbus = 400 V

Vbus = 200 V

Vbus = 400 V

Vbus = 200 V

50

25

125

225

325

425

525

25

125

225

325

425

525

Frequency (kHz)

*Assumptions for above curves: LLC topology, Power switch = IPP60R600P6, T_a= 25 °C, V_BUS= 400 V, V_CC= 12 V,

R_gon= 3.9 Ω, R_goff= 1 Ω

Figure 20 Estimated T_Jvs. Frequencies (Left: DSO - 8, Right: DSO - 14)

Datasheet

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5.13

PCB layout tips

Distance between high and low voltage components: It’s strongly recommended to place the components tied

to the floating voltage pins (V_Band V_S) near the respective high voltage portions of the device. Please see the

Case Outline information in this datasheet for the details.

Ground Plane: In order to minimize noise coupling, the ground plane should not be placed under or near the high

voltage floating side.

Gate Drive Loops: Current loops behave like antennas and are able to receive and transmit EM noise (see Figure

21). In order to reduce the EM coupling and improve the power switch turn on/off performance, the gate drive

loops must be reduced as much as possible. Moreover, current can be injected inside the gate drive loop via the

IGBT collector-to-gate parasitic capacitance. The parasitic auto-inductance of the gate loop contributes to

developing a voltage across the gate-emitter, thus increasing the possibility of a self turn-on effect.

Figure 21

Avoid antenna loops

Supply Capacitor: It is recommended to place a bypass capacitor (C_IN) between the V_CCand COM pins. A ceramic

1μF ceramic capacitor is suitable for most applications. This component should be placed as close as possible

to the pins in order to reduce parasitic elements.

Routing and Placement: Power stage PCB parasitic elements can contribute to large negative voltage transients

at the switch node; it is recommended to limit the phase voltage negative transients. In order to avoid such

conditions, it is recommended to 1) minimize the high-side emitter to low-side collector distance, and 2)

minimize the low-side emitter to negative bus rail stray inductance. However, where negative VS spikes remain

excessive, further steps may be taken to reduce the spike. This includes placing a resistor (5 Ω or less) between

the VS pin and the switch node (see Figure 22- A), and in some cases using a clamping diode between COM and

V_S(see Figure 22- B). See DT04-4 at www.infineon.com for more detailed explanations.

Figure 22

Resistor between the VS pin and the switch node and clamping diode between COM and VS

Datasheet

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2ED2106 (4) S06F (J)

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6

Qualification information¹

Table 7

Qualification information

Industrial²

Note: This family of ICs has passed JEDEC’s Industrial

qualification. Consumer qualification level is granted by

extension of the higher Industrial level.

Qualification level

MSL2, 260°C

DSO-8

(per IPC/JEDEC J-STD-020)

Moisture sensitivity level

ESD

MSL3³, 260°C

DSO-14

(per IPC/JEDEC J-STD-020)

Class C3 (1.0 kV)

(per JEDEC standard JS-002)

Class 1C (1.5 kV)

(per JEDEC standard JS-001)

Class II Level A

(per JESD78)

Yes

Charged device model

Human body model

IC latch-up test

RoHS compliant

7


型号：	2ED21091S06F
厂家：	Infineon
描述：	650 V high-side and low-side gate driver with integrated bootstrap diode
文件：	总24页 (文件大小：1615K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

2ED21091S06F [INFINEON]

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