2EDF7275K [INFINEON]
Fast, robust, dual-channel, functional and reinforced isolated MOSFET gate-driver;
| 型号： | 2EDF7275K |
| 厂家： | 
Infineon |
| 描述： | Fast, robust, dual-channel, functional and reinforced isolated MOSFET gate-driver 驱动 接口集成电路 |
| 文件： | 总38页 (文件大小：1494K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
EiceDRIVER™ 2EDi product family
Fast, robust, dual-channel, functional and reinforced isolated
MOSFET gate-driver with accurate and stable timing
Description
The EiceDRIVER™ 2EDi is a family of fast dual-channel isolated MOSFET gate-driver ICs providing functional
(2EDFx) or reinforced (2EDSx) input-to-output isolation by means of coreless transformer (CT) technology. Due
to high driving current, excellent common-mode rejection and fast signal propagation, 2EDi is particularly well
suited for driving medium- to high-voltage MOSFETs (CoolMOS™, OptiMOS™, CoolSIC™) in fast-switching power
systems.
Features
•
•
•
4 A / 8 A or 1 A / 2 A source / sink output current
Up to 10 MHz PWM switching frequency
PWM signal propagation delay typ. 37 ns with
–
–
3 ns channel-to-channel mismatch
+7/-6 ns propagation delay variance
•
•
•
•
•
•
•
Resistor-programmable Dead Time Control (DTC) ranging from 15 ns to 250 ns
Common Mode Transient Immunity CMTI >150 V/ns
Fast safety turn-off in case of input side Undervoltage Lockout (UVLO)
Output supply voltage from 4.5 V to 20 V with 4 V or 8 V UVLO threshold
Wide temperature operating range TJ = -40°C to +150°C
RoHS compliant wide /narrow-body (WB/NB) DSO16 and 5 mm x 5 mm LGA packages
Fully qualified according to JEDEC for Industrial Applications
Isolation and safety certificates
•
2EDSx with reinforced isolation:
–
–
–
–
DIN V VDE V 0884-10 (2006-12) compliant with VIOTM = 8 kVpk and VIOSM = 6.25 kVpk (tested at 10kVpk)
certified according to UL1577 (Ed. 5) opto-coupler component isolation standard with VISO = 5700 VRMS
certified according to DIN EN 62368-1 and DIN EN 60950-1 and corresponding CQC certificates
certified according to EN 61010-1 (reinforced isolation, 300 Vrms mains voltage, overvoltage category III)
•
2EDFx with functional isolation: Production test with 1.5 kVDC for 10 ms
VDD > 3.5V
VBus
RVDDI
VDDI
VDDA
OUTA
UVLO
VDD
UVLO
(3.3V)
CVDDI
SLDON
RX
TX
SLDO
Rg1
Controller
Logic
M1
INA
INB
CVDDA
PWM1
PWM2
GNDA
VDDB
Control
Logic
Vsw
Channel-to-Channel
Isolation
Dboot
Aux Power
(12V)
UVLO
DISABLE
GPIOx
TX
RX
OUTB
GNDB
Rg2
Logic
M2
RDTC
DTC
Dead Time
Control
GND
CVDDB
GNDI
PGND
Final datasheet
www.infineon.com
Please read the Important Notice and Warnings at the end of this document
Rev. 2.5
2020-03-17
EiceDRIVER™ 2EDi product family
2EDSx reinforced, 2EDFx functional isolated 4A/8A, 1A/2A gate drivers
Potential Applications
•
•
•
Server, telecom and industrial SMPS
Synchronous rectification, brick converters, UPS and battery storage
EV charging industry automation, motor drives and power tools
Final datasheet
2
Rev.2.5
2020-03-17
EiceDRIVER™ 2EDi product family
2EDSx reinforced, 2EDFx functional isolated 4A/8A, 1A/2A gate drivers
Table of Contents
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
EiceDRIVER™ 2EDi product family device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Input-to-output isolation testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Channel-to-channel isolation testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Application overview and system block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.1
1.2
1.3
1.4
2
2.1
2.2
Pin configurations by device type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Pin configuration for dual-channel input mode with (with DISABLE, SLDON) . . . . . . . . . . . . . . . . . . . . . . 6
Pin configuration for dual-channel input mode (with DISABLE, SLDOP, DTC) . . . . . . . . . . . . . . . . . . . . . . 8
3
3.1
3.2
3.2.1
3.3
3.3.1
3.3.2
3.4
3.5
3.6
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Input-to-output isolation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Typical applications by isolation type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Supply voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Input-side power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Output-side power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Input configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Driver outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Undervoltage Lockout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Input-side UVLO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Output-side UVLO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Data transmission input-side to output-side . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Dead Time Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.6.1
3.6.2
3.7
3.8
4
4.1
4.2
4.3
4.4
4.5
4.5.1
4.5.1.1
4.5.1.2
4.5.2
4.5.3
Device characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Operating range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Functional and reinforced isolation specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Functional isolation specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Functional isolation of devices in PG-TFLGA-13-1 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Functional isolation of devices in NB PG-DSO-16-11 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Reinforced isolation of devices in WB PG-DSO-16-30 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Safety-limiting values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5
6
Timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Typical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
7
Package outline dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Device numbers and markings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Package PG-DSO-16-11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Package PG-DSO-16-30 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Package PG-TFLGA-13-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
7.1
7.2
7.3
7.4
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Final datasheet
3
Rev.2.5
2020-03-17
EiceDRIVER™ 2EDi product family
2EDSx reinforced, 2EDFx functional isolated 4A/8A, 1A/2A gate drivers
Description
1
Description
The gate drivers of the EiceDRIVER™ 2EDi product family are designed for fast-switching, medium to high power
systems with MOSFET switches. They are optimized for high timing accuracy over temperature and production
spread. The reliable accurate timing simplifies system design and provides better power conversion efficiency.
The 2EDSx, 2EDFx dual-channel reinforced (safe) and functional isolated product variants are available with
different drive strengths: 4 A/8 A for low-ohmic power MOSFETs, 1 A/2 A for higher Ron MOSFETs or slower
switching transients (EMI). The 1 A/2 A reinforced isolation driver can also be used as a PWM Data Coupler in
combination with a non-isolated boost gate driver such as 1EDNx 4 A/8 A placed in closest proximity to the
Superjunction power switches.
Two independent and galvanically isolated gate driver channels ensure that all 2EDi versions can be used in any
possible configuration of low- and high-side switches.
Improved system robustness is supported by min. 150 V/ns Common Mode Transient Immunity (CMTI), PWM
inputs with 18 ns noise filter, UVLO on output side including a safety self-lock-down of driver outputs in case of
input UVLO (VDDI < 3 V), PWM outputs with up to 5 A peak reverse current capability and an intrinsically robust
gate driver design.
1.1
EiceDRIVER™ 2EDi product family device overview
Table 1
EiceDRIVER™ 2EDi product family device overview
Input-to-output isolation
Part
Package
Source/ UVLO
sink
current
DTC
Isolation
class
Safety
Surge testing certification2)
number1)
Rating
2EDF7275F
2EDF9275F
2EDF7175F
4 V
no
no
no
4 A/8 A
NB-DSO16
10mm x 6mm
13 V
1 A/ 2 A 4 V
Functional VIO = 1.5 kVDC
n.a
n.a
2EDF7275K
2EDF7235K
LGA13
5mm x 5mm
4 A/8 A 4 V
no
yes
VIOTM = 8 kVpk
VDE0884-10 3)
2EDS8265H WB-DSO16 4 A/8 A
8 V
13 V
8 V
(VDE0884-10 3)) VIOSM = 10 kVpk UL1577
no
no
no
10.3mm x
10.3mm
Reinforced
(IEC60065)
EN 60950-1,
EN 62368-1,
EN 61010-1
2EDS9265H
V
ISO = 5.7 kVrms
2EDS8165H
1 A/2 A
(UL1577)
1) for device ordering information and device marking see Chapter 7.1, Table 31
2) CSA Component Acceptance Notice 5A IEC60950 planned and CQC per GB4943.1-2011 pending. For 2EDS9265H, all
certifications are planned.
3) tested according to VDE0884-10 specifications with certification no longer available due to standard expiration
The 2EDi product table is provided as a first quick device selection guide; more detailed specifications are
provided in the product features, package dimension and testing chapters of this datasheet.
Find current information on configurations and application notes under www.infineon.com/2EDi
Final datasheet
4
Rev.2.5
2020-03-17
EiceDRIVER™ 2EDi product family
2EDSx reinforced, 2EDFx functional isolated 4A/8A, 1A/2A gate drivers
Description
1.2
Input-to-output isolation testing
•
2EDSx Reinforced isolation (2EDSx in WB PG-DSO-16-30 package), for details see Table 26 to Table 29.
–
–
8 kVpk transient isolation voltage applied according to DIN V VDE V 0884-10 (2006-12)
10 kVpk surge isolation tested with 25 positive and 25 negative pulses according to VDE-0884-10
•
Functional isolation (2EDFx in NB PG-DSO-16-11 and PG-TFLGA-13-1 packages), for details see Table 21 to
Table 23
–
Production test with 1.5 kVDC for 10 ms
1.3
Channel-to-channel isolation testing
•
The functional isolation between the two channels are verified by the following tests
–
–
sample test with 1.5 kVDC for 10 ms (NB PG-DSO-16-11, WB PG-DSO-16-30)
sample test with 0.65 kVDC for 10 ms (PG-TFLGA-13-1)
1.4
Application overview and system block diagram
2EDi gate drivers are perfectly suited to substitute bulky pulse transformers and drive power MOSFETs in half-
bridge configuration as depicted in Figure 1.
The input side is usually powered by the same power supply as the PWM controllers (VDDI = 3.3 V or VDDI > 3.5 V
if SLDO is activated). The output-side gate driver voltages VDDA, VDDB are generated by separate isolated
auxiliary supplies. In some topologies like LLC, the high side driver supply VDDA can be generated via a
bootstrapping circuitry.
For further application implementation guidance please refer to dedicated application notes.
VDD > 3.5V
RVDDI
VBus
VDDA
OUTA
VDDI
UVLO
VDD
UVLO
(3.3V)
CVDDI
SLDON
INA
RX
TX
SLDO
Rg1
Controller
Logic
M1
CVDDA
PWM1
PWM2
GNDA
VDDB
Control
Logic
Vsw
Channel-to-Channel
Isolation
Dboot
INB
Aux Power
(12V)
UVLO
DISABLE
8
GPIOx
TX
RX
OUTB
GNDB
Rg2
Logic
M2
RDTC
DTC
Dead Time
Control
GND
CVDDB
GNDI
PGND
Figure 1
Typical application with 5 V controller and bootstrapped high-side VDDA
Final datasheet
5
Rev.2.5
2020-03-17
EiceDRIVER™ 2EDi product family
2EDSx reinforced, 2EDFx functional isolated 4A/8A, 1A/2A gate drivers
Pin configurations by device type
2
Pin configurations by device type
Functional behavior and electrical characteristics are independent of package configuration
2.1
Pin configuration for dual-channel input mode with (with DISABLE, SLDON)
The pin configurations for the different package variants 2EDFxx75F, 2EDF7x75K and 2EDSxx65H are outlined in
Figure 2.
DSO-16
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VDDA
OUTA
GNDA
N.C.
INA
INB
narrow-body
2EDF7275F
2EDF9275F
2EDF7175F
VDDI
GNDI
wide-body
2EDS8265H
2EDS9265H
2EDS8165H
N.C.
DISABLE
N.C.
VDDB
OUTB
GNDB
N.C.
SLDON
LGA-13 (5 x 5 mm)
GNDI
INA
1
2
3
4
5
6
7
13 VDDA
12 OUTA
11 GNDA
INB
SLDON
DISABLE
N.C.
2EDF7275K
VDDB
OUTB
GNDB
10
9
VDDI
8
Figure 2
Pin configuration DSO-16 and LGA-13 packages (2EDF7x75F, 2EDF7x75K and 2EDF8x65H)
(Top view, figure is not to scale)
Final datasheet
6
Rev.2.5
2020-03-17
EiceDRIVER™ 2EDi product family
2EDSx reinforced, 2EDFx functional isolated 4A/8A, 1A/2A gate drivers
Pin configurations by device type
For package drawing details see Chapter 7 Package outline dimensions.
Table 2
Pin description for dual-channel input mode (with DISABLE, SLDON)
Pin# Pin# Symbol Description
DSO LGA
1
2
INA
Digital CMOS / TTL logic signal input for channel A with internal pull-down resistor to
GNDI
If channel is not used it is recommended to connect pin to GNDI (see Chapter 3.4)
2
3
INB
Digital CMOS / TTL logic signal input for channel B with internal pull-down resistor to
GNDI
If channel is not used it is recommended to connect pin to GNDI (see Chapter 3.4)
3
4
5
7
1
5
VDDI
GNDI
Supply voltage (input side) 3.3 V (Internal SLDO available)
It is recommended to place a bypass capacitor from VDDI to GNDI (see Chapter 3.3.1)
Ground input side (all signals on input side are referenced to this pin)
(see Chapter 3.3.1)
DISABLE Digital CMOS / TTL logic input for both channels A and B; logic input high disables both
output channels
Internal pull-down resistor (see Chapter 3.4)
6
7
8
6
-
N.C.
Not connected; keep pin floating
Not connected; keep pin floating
N.C.
4
SLDON
Default 3.3 V supply selected, if N.C. or connected to VDDI
If SLDON pin is connected to GNDI, SLDO is activated and a supply voltage higher than
3.5 V can be used (see Chapter 3.3.1)
Internal pull-up resistor to VDDI; hard-wired PCB connection recommended
9
8
9
GNDB
OUTB
Ground for output channel B
10
11
Output gate driver for channel B
10 VDDB
Supply voltage for output channel B
It is recommended to place a bypass capacitor from VDDB to GNDB (see Chapter 3.3.2)
12 N.P. N.C.
Not present; not connected; for channel-to-channel isolation
Not connected; for channel-to-channel isolation
Ground for output channel A
13
14
15
16
-
N.C.
11 GNDA
12 OUTA
13 VDDA
Output gate driver for channel A
Supply voltage for output channel A
It is recommended to place a bypass capacitor from VDDA to GNDA (see Chapter 3.3.2)
Final datasheet
7
Rev.2.5
2020-03-17
EiceDRIVER™ 2EDi product family
2EDSx reinforced, 2EDFx functional isolated 4A/8A, 1A/2A gate drivers
Pin configurations by device type
2.2
Pin configuration for dual-channel input mode (with DISABLE, SLDOP, DTC)
The pin configuration for the LGA-version with Dead Time Control (2EDF7235K) is outlined in Figure 3
LGA-13 (5 x 5 mm)
GNDI
INA
1
2
3
4
5
6
7
13
12
11
VDDA
OUTA
GNDA
INB
SLDOP
DISABLE
DTC
2EDF7235K
10
9
VDDB
OUTB
GNDB
VDDI
8
Figure 3
Pin configuration dual-channel input mode (with DISABLE, SLDOP, DTC) for 2EDF7235K
(Top view, Figure is not to scale)
Final datasheet
8
Rev.2.5
2020-03-17
EiceDRIVER™ 2EDi product family
2EDSx reinforced, 2EDFx functional isolated 4A/8A, 1A/2A gate drivers
Pin configurations by device type
For package drawing details see Chapter 7 Package outline dimensions.
Table 3
Pin description for dual-channel input mode (with DISABLE, SLDOP, DTC)
Pin# Symbol
LGA
Description
2
3
7
1
5
INA
Digital CMOS / TTL logic signal input for channel A with internal pull-down resistor to GNDI
If channel is not used it is recommended to connect pin to GNDI (see Chapter 3.4)
INB
Digital CMOS / TTL logic signal input for channel B with internal pull-down resistor to GNDI
If channel is not used it is recommended to connect pin to GNDI (see Chapter 3.4)
VDDI
GNDI
Supply voltage (input side) 3.3 V (Internal SLDO available)
It is recommended to place a bypass capacitor from VDDI to GNDI (see Chapter 3.3.1)
Ground input side (all signals on input side are referenced to this pin)
(see Chapter 3.3.1)
DISABLE Digital CMOS / TTL logic input for both channels A and B
Logic input high disables both output channels
Internal pull-down resistor (see Chapter 3.4)
6
4
DTC
Dead time control
Programmable from 15 ns to 350 ns via resistor to GNDI see Chapter 3.8 Dead Time Control
Internal pull-up resistor; no connection or connection to VDDI disables DTC functionality
SLDOP
Default mode: supply voltage > 3.5V (with external shunt resistor), if pin N.C. or connected to
VDDI
If SLDOP pin is connected to GNDI SLDO Operation is deactivated, for use with 3.3 V supply on
VDDI(see Chapter 3.3.1)
Internal pull-up resistor to VDDI; hard-wired PCB connection recommended
8
9
GNDB
OUTB
Ground for output channel B
Output gate driver for channel B
10 VDDB
Supply voltage for output channel B
It is recommended to place a bypass capacitor from VDDB to GNDB (see Chapter 3.3.2)
-
N.P.
Not present; for channel-to-channel isolation creepage requirements
Ground for output channel A
11 GNDA
12 OUTA
13 VDDA
Output gate driver for channel A
Supply voltage for output channel A
It is recommended to place a bypass capacitor from VDDA to GNDA (see Chapter 3.3.2)
Final datasheet
9
Rev.2.5
2020-03-17
EiceDRIVER™ 2EDi product family
2EDSx reinforced, 2EDFx functional isolated 4A/8A, 1A/2A gate drivers
Functional description
3
Functional description
3.1
Block diagram
A simplified functional block diagram for the the EiceDRIVER™ 2EDi gate-driver family is given in Figure 4.
UVLO
UVLO
VDDI
VDDA
SLDON
SLDOP
SLDO
Tx
Rx
Logic
OUTA
GNDA
INA
INB
Control
Logic
Channel-to-Channel
Isolation
UVLO
VDDB
DISABLE
ENABLE
Tx
Rx
Logic
Dead Time
Control
OUTB
GNDB
NC
DTC
GNDI
Figure 4
EiceDRIVER™ 2EDi product family block diagram
3.2
Input-to-output isolation
All EiceDRIVER™ 2EDi dual-channel isolated products are tested in accordance with their respective isolation
class.
•
2EDFx for functional isolation, typically used as primary-side controlled galvanically isolated driver.
Device part numbers: 2EDFxxxxK (2EDF7275K, 2EDF7235K) and 2EDFxxxxF (2EDF7275F, 2EDF9275F,
2EDF7175F)
•
2EDSx for reinforced safe isolation, typically used as secondary-side controlled isolated gate driver.
Device part numbers: 2EDSxxxxH (2EDS8165H, 2EDS9265H, 2EDS8265H)
In combination with the different package dimensions and material characteristics, e.g. WB DSO-16 wide-body
(PG-DSO-16-30), NB DSO-16 narrow-body (PG-DSO-16-11) or LGA - 13 at 5mm x 5mm (PG-TFLGA-13-1) the
maximum input-to-output and channel-to-channel creepage and clearance distances and the possible working
voltages of the IC as a semiconductor component are defined (see Table 18 to Table 29)
Note:
The achievable system isolation depends on PCB design, materials, manufacturing- and working
environment. It is the customer’s obligation to verify that the outlined semiconductor component
isolation of the 2EDSx, 2EDFx device fits to application, manufacturing, working environment and end
system saftey requirement standards.
Final datasheet
10
Rev.2.5
2020-03-17
EiceDRIVER™ 2EDi product family
2EDSx reinforced, 2EDFx functional isolated 4A/8A, 1A/2A gate drivers
Functional description
3.2.1
Typical applications by isolation type
Isolated gate drivers are typically deployed in the following applications.
Table 4
Isolation type Potential applications
•
High-power hard-switching high-voltage PFC, Vienna Rectifier, Totem Pole PFC or
Synchronous Rectification
Driving switches with Kelvin source connection (4-pin package)
Secondary-side control in low voltage isolated DC/DC topologies and brick converters
Secondary-side control of high voltage SJ-MOSFETs in LLC or PS-ZVS
Primary-side controlled synchronous rectification
1 A / 2 A PWM data- / signal-coupler for local boost gate drivers
Functional
Reinforced
3.3
•
•
•
•
•
Supply voltages
Three different power domains with independent internal power management are utilized to supply the input
chip and the two output drivers. An undervoltage lockout functionality (UVLO) in each domain enables a defined
startup and ensures a robust operation under all conditions.
3.3.1
Input-side power supply
The input side is powered via VDDI with nominal 3.3 V. For using the device with a supply voltage > 3.5 V the on-
chip switched low-dropout regulator (SLDO) must be activated and an external shunt resistor RVDDI has to be
connected to VDDI.
It is recommended to use a ceramic bypass capacitor (10 nF - 22 nF) between VDDI and GNDI.
The SLDO is activated, if the pin SLDON is connected to GNDI. In devices with the inverted pin SLDOP (e.g.
2EDF7235K) the SLDO is active by default and will be deactivated if connected to GNDI. A hard-wired connection
is recommended.
The SLDO regulates the current through an external resistor RVDDI connected between the external supply voltage
V
DD and pin VDDI as depicted in Figure 1 to generate the required voltage drop. For proper operation it has to be
ensured that the current through RVDDI always exceeds the maximum supply current IVDD of the input chip (see
Figure 8).
Thus, RVDDI has to fulfill:
R
VDDI < (VDD - 3.3) / IVDD, max
A typical choice for VDD = 12 V is RVDDI = 3 kΩ, resulting in sufficient margin between resistor current and VDDI
operating current. Dynamic current peaks are eliminated by a blocking cap (10 to 22 nF) between VDDI and GNDI.
The total power consumption of 2EDi is dominated by the output side and depends on switching frequency, gate
resistor and gate charge, while for typical switching frequencies the input supply current stays relatively constant
(see Figure 7 to Figure 8)
3.3.2
Output-side power supply
Each gate driver channel has to be powered separately. It is recommended to use a ceramic bypass capacitor
(minimum value 20 x Ciss of MOSFET) from VDDA to GNDA and from VDDB to GNDB in close proximity to the
device.
The operating supply voltage can range from 4.5 V to 20 V for each gate drive channel.
The minimum gate driver turn-on voltage is set by the device Undervoltage Lockout (UVLO) to protect the power
MOSFETs from operating in the saturation region.
Devices with 4 V, 8 V and 13 V UVLO thresholds for the output supply are currently available (see Chapter 1.1.)
Final datasheet
11
Rev.2.5
2020-03-17
EiceDRIVER™ 2EDi product family
2EDSx reinforced, 2EDFx functional isolated 4A/8A, 1A/2A gate drivers
Functional description
3.4
Input configurations
The inputs INA and INB control two independent PWM channels. The input signal is transferred non-inverted to
the corresponding gate driver outputs OUTA and OUTB. All inputs are compatible with LV-TTL threshold levels
and provide a hysteresis of typ. 0.8 V. The hysteresis is independent of the supply voltage VDDI.
The PWM inputs are internally pulled down to a logic low voltage level (GNDI). In case the PWM-controller signals
have an undefined state during the power-up sequence, the gate driver outputs are forced to the "off"-state
(low).
If the DISABLE input is “high”, this unconditionally drives both channel outputs to “low” regardless of the state of
INA or INB.
Table 5
Logic table
Inputs
Gate Drive Output
OUTA OUTB
DISABLE INA INB UVLO
input side1)
active
UVLO
output side1)
x
x
x
x
x
x
x
L
L
x
ch A/B active
L
L
L
L
H
L
L
L
H
L
L
L
L
L
L
H
L
L
L
x
L
H
x
inactive
inactive
inactive
inactive
inactive
inactive
inactive
inactive
ch A activ, ch B inactive
ch A active, ch B inactive
ch A inactive, ch B active
ch A inactive, ch B active
ch A/B inactive
x
H
L
L
H
x
x
L
x
L
L
L
H
L
H
H
ch A/B inactive
L
ch A/B inactive
H
H
ch A/B inactive
1) “inactive” means that VDD is above UVLO threshold voltage (normal operation)
“active” means that UVLO disables the gate driver output stages
3.5
Driver outputs
The two rail-to-rail output stages, realized with complementary PMOS, NMOS transistors, are able to provide the
necessary sourcing and sinking current and shoot-through protection and active current limitation have been
implemented with a very low on-resistance (see Table 15). The use of a p-channel sourcing transistor PMOS is
crucial for achieving true rail-to-rail behavior without any source follower voltage drop.
Gate Drive Outputs OUTA, OUTB are held actively low in case of floating inputs or during startup or power down
as long as the UVLO thresholds are not exceeded.
Final datasheet
12
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2020-03-17
EiceDRIVER™ 2EDi product family
2EDSx reinforced, 2EDFx functional isolated 4A/8A, 1A/2A gate drivers
Functional description
3.6
Undervoltage Lockout
3.6.1
Input-side UVLO
During startup (rise of the input-side supply), as long as VDDI is below UVLO, no data is transferred to the output
side. All gate driver outputs are held low (Safety Lock-down at startup).
When VDDI exceeds the UVLO level, the PWM input signal is transferred to the output side. If the output side is
ready (not in UVLO condition), the output reacts according to the logic input. At any time, if the VDDI voltage
drops below the UVLO threshold, an immediate “switch-to-low” command is sent to all output channels. The
gate driver outputs are held low (Safety Lock-down is active at missing VDDI supply).
3.6.2
Output-side UVLO
The Undervoltage Lockout function (UVLO) ensures that the output can be switched to its high level only if the
gate driver supply voltage exceeds the UVLO threshold voltage. Thus it can be guaranteed, that the power switch
transistors always stay within their Safe Operating Area (SOA). Otherwise a too low driving voltage could cause
the power MOSFET to enter its saturation (ohmic) region with potentially destructive power dissipation.
The UVLO of each channel VDDA/VDDB is controlled independently. There is no feedback to the input side.
3.7
Data transmission input-side to output-side
Coreless Transformer (CT) based communication modules situated on the input die are used for signal transfer
between input and output devices. A proven high-resolution pulse repetition scheme in the transmitter
combined with a watchdog time-out at the receiver side enables recovery from communication fails and ensures
safe system shutdown in failure cases.
3.8
Dead Time Control
Dead Time Control function (DTC) increases the propagation delay of the rising output voltage by a time tDT. This
feature is used in half-bridge applications to prevent the switches from a shoot-through current due to
overlapping or jitter on the PWM signals.
If the DTC feature is available, it can be enabled by connecting a resistor from DTC to GND. If this pin is not
connected or set to VDDI, DTC is disabled.
Recommended DTC resistor (RDTC) values are between 4.7 kΩ and 150 kΩ .
R
DTC is related to tDT by the formula: RDTC [kΩ] = (tDT[ns] - 3) / 1.8
The resistor values and dead time delays are shown in Table 17 and Figure 15.
Final datasheet
13
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2020-03-17
EiceDRIVER™ 2EDi product family
2EDSx reinforced, 2EDFx functional isolated 4A/8A, 1A/2A gate drivers
Device characteristics
4
Device characteristics
The absolute maximum ratings are listed in Table 6. Stresses beyond these values may cause permanent damage
to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
4.1
Absolute maximum ratings
Table 6
Absolute maximum ratings
Symbol
Parameter
Values
Typ.
–
Unit Note or Test Condition
Min.
Max.
Input supply voltage
Output supply voltage
VDDI
-0.3
4.0
V
SLDO inactive (N.C. or
connected to VDDI)
VDDO
VIN
-0.3
-0.3
-5
–
–
–
–
22
V
V
V
V
–
Voltage at pins PWM and
DISABLE
17
–
–
< 50 ns for transient 1)
Voltage at pins DTC and
TEST/SLDO
VDTC
VTEST/SLDO
/
-0.3
VDDI + 0.3
–
Voltage at pins OUTA, OUTB
VOUTA/B
-0.3
-2
–
–
–
–
–
VDDO + 0.3
V
–
VDDO+ 1.5
V
< 200 ns 1)
< 500 ns 1)
Reverse current peak at pins
OUTA, OUTB
ISRC_rev
ISNK_rev
CMTI
-5
–
5
–
Apk
Apk
–
Non-destructive Common
Mode Transient Immunity
400
V/ns input to each output
channel
Junction temperature
Storage temperature
Soldering temperature
ESD capability
TJ
TSTG
-40
-65
–
–
–
–
–
150
150
260
0.5
°C
–
°C
°C
kV
–
TSOL
reflow / wave soldering 2)
VESD_CDM
–
Charged Device Model
(CDM) 3)
ESD capability
VESD_HBM
–
–
2
kV
Human Body Model
(HBM) 4)
1) parameter verified by design, not tested in production
2) according to JESD22A111
3) according to JESD22-002
4) according to JESD22-A114-B (discharging 100 pF capacitor through 1.5 kΩ resistor)
Final datasheet
14
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EiceDRIVER™ 2EDi product family
2EDSx reinforced, 2EDFx functional isolated 4A/8A, 1A/2A gate drivers
Device characteristics
4.2
Thermal characteristics
Table 7
Thermal characteristics at Tamb= 25°C
Parameter
Symbol
Values
Typ.
Unit Note or
Test Condition
Min.
Max.
PG-TFLGA-13-1
Thermal resistance junction-
ambient 1)
RthJA25
RthJC25
–
–
112
44
–
–
K/W
K/W
–
Thermal resistance junction-case
–
(top) 2)
Thermal resistance junction-board 3) RthJB25
–
–
66
–
–
K/W
K/W
–
–
Characterization parameter
junction-top 4)
ΨthJT25
7.7
Characterization parameter
junction-board 4)
ΨthJB25
–
5.6
–
K/W
–
PG-DSO-16-11
Thermal resistance junction-
ambient 1)
RthJA25
RthJC25
–
–
51
25
–
–
K/W
K/W
–
–
Thermal resistance junction-case
(top) 2)
Thermal resistance junction-board 3) RthJB25
–
–
36
–
–
K/W
K/W
–
–
Characterization parameter
junction-top 4)
ΨthJT25
4.4
Characterization parameter
junction-board 4)
ΨthJB25
–
5.4
–
K/W
–
PG-DSO-16-30
Thermal resistance junction-
ambient 1)
RthJA25
RthJC25
–
–
59
32
–
–
K/W
K/W
–
–
Thermal resistance junction-case
(top) 2)
Thermal resistance junction-board 3) RthJB25
–
–
33
–
–
K/W
K/W
–
–
Characterization parameter
junction-top 4)
ΨthJT25
8.9
Characterization parameter
ΨthJB25
–
7.7
–
K/W
–
junction-board 4)
1) obtained in a simulation on a JEDEC-standard, high-K board, as specified in JESD51-7, in an environment described in
JESD51-2a.
2) obtained by simulating a cold plate test on the package top. No specific JEDEC standard test exists, but a close
description can be found in the ANSI SEMI standard G30-88.
3) obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in
JESD51-8.
4) estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining
Rth, using a procedure described in JESD51-2a (sections 6 and 7).
Final datasheet
15
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2020-03-17
EiceDRIVER™ 2EDi product family
2EDSx reinforced, 2EDFx functional isolated 4A/8A, 1A/2A gate drivers
Device characteristics
4.3
Operating range
Table 8
Operating range
Parameter
Symbol
Values
Unit Note or Test Condition
Min.
3.0
Typ.
Max.
3.5
Input supply voltage
Output supply voltage
VDDI
–
–
V
V
Min. defined by UVLO
Min. defined by UVLO
VDDA
/
4.5
20
VDDB
Logic input voltage at pins INA,
INB, DISABLE
VIN
0
0
–
–
15
V
V
–
–
Voltage at pins DTC and SLDO
VDTC
/
3.5
VTEST/SLDO
1)
Junction temperature
Ambient temperature
TJ
-40
-40
–
–
150
125
°C
°C
Tamb
–
1) continuous operation above 125°C may reduce lifetime.
4.4
Electrical characteristics
Unless otherwise noted, min./max. values of characteristics are the lower and upper limits, respectively. They are
valid within the full operating range. The supply voltage is VDDA, VDDB= 12 V and VDDI= 3.3 V. Typical values are given
at TJ = 25°C.
Table 9
Power supply (see Figure 7, Figure 8 and Figure 9)
Parameter
Symbol
Values
Typ.
1.4
Unit Note or Test Condition
Min.
Max.
IVDDI quiescent current
IVDDIqu1
–
–
–
–
mA no switching
IVDDA , IVDDB quiescent current
IVDDAqu2
/
0.6
mA Outx = low, no switching
(4 V, 8 V UVLO options)
IVDDBqu2
–
0.7
–
mA Outx = low, no
switching, VDDA/B= 15 V >
UVLO_ CMon (13 V UVLO
options)
Table 10 Undervoltage Lockout VDDI (See Figure 11)
Parameter
Symbol
Values
Typ.
Unit Note or Test Condition
Min.
Max.
Undervoltage Lockout (UVLO)
turn-on threshold VDDI
UVLOon
UVLOoff
2.75
2.85
2.95
V
V
V
–
–
–
Undervoltage Lockout (UVLO)
turn-off threshold VVDDI
–
2.70
0.15
–
UVLO threshold hysteresis VDDI UVLOhys
0.1
0.2
Final datasheet
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EiceDRIVER™ 2EDi product family
2EDSx reinforced, 2EDFx functional isolated 4A/8A, 1A/2A gate drivers
Device characteristics
Table 11 Undervoltage Lockout VDDA, VDDB 13 V-versions for SiC MOSFETs (see Figure 13)
Parameter
Symbol
Values
Typ.
Unit Note or
Test Condition
Min.
Max.
Undervoltage Lockout (UVLO) turn-on UVLO_
threshold VDDA, VDDB CMon
Undervoltage Lockout (UVLO) turn-off UVLO_
13.0
13.7
14.2
V
V
V
–
–
12.9
0.8
–
–
–
threshold VDDA , VDDB
CMoff
UVLO threshold hysteresis VDDA, VDDB
UVLO_
CMhys
0.4
1.2
Table 12 Undervoltage Lockout VDDA, VDDB 8 V-versions for standard MOSFETs (see Figure 12)
Parameter
Symbol
Values
Typ.
8.0
Unit Note or
Test Condition
Min.
Max.
Undervoltage Lockout (UVLO) turn-on UVLO_
threshold VDDA, VDDB CMon
Undervoltage Lockout (UVLO) turn-off UVLO_
7.6
8.4
V
V
V
–
–
7.0
1
–
–
–
threshold VDDA , VDDB
CMoff
UVLO threshold hysteresis VDDA,
VDDB
UVLO_
CMhys
0.7
1.3
Table 13 Undervoltage Lockout VDDA, VDDB 4 V-versions for logic-level MOSFETs (see Figure 12)
Parameter
Symbol
Values
Typ.
4.2
Unit Note or
Test Condition
Min.
Max.
Undervoltage Lockout (UVLO) turn on UVLO_
threshold VDDA , VDDB CMon
Undervoltage Lockout (UVLO) turn off UVLO_
4.0
4.4
V
V
V
–
–
3.9
0.3
–
–
–
threshold VDDA, VDDB
CMoff
UVLO threshold hysteresis
VDDA , VDDB
UVLO_
CMhys
0.2
0.4
Table 14 Logic inputs INA, INB and DISABLE (see Figure 11)
Parameter
Symbol
Values
Typ.
2.0
Unit Note or
Test Condition
Min.
Max.
Input voltage threshold for transition
LH
VINH
VINL
1.7
2.3
V
–
Input voltage threshold for transition
HL
–
1.2
–
V
–
Input voltage threshold hysteresis
Input pull-down resistor
VIN_hys
RIN
0.4
–
0.8
1.2
–
V
–
–
150
kΩ
Final datasheet
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EiceDRIVER™ 2EDi product family
2EDSx reinforced, 2EDFx functional isolated 4A/8A, 1A/2A gate drivers
Device characteristics
Table 15 Static output characteristics 4 A/8 A devices (see Figure 10)
Parameter
Symbol
Values
Typ.
Unit Note or
Test Condition
Min.
Max.
High-level (Sourcing) Output
Resistance
Ron_SRC
ISRC_pk
0.42
0.85
1.6
Ω
ISNK = 50 mA
1)
Peak Sourcing Output Current
–
4
0.35
-8
A
Ω
A
–
Low-level (Sinking) Output Resistance Ron_SNK
Peak Sinking Output Current ISNK_pk
0.18
2)
0.75
–
ISRC = 50 mA
–
1) actively limited by design at approx. 5.2 Apk, parameter is not subject to production test - verified by design /
characterization
2) actively limited by design at approx. -10.2 Apk, parameter is not subject to production test - verified by design /
characterization
Table 16 Static output characteristics 1 A / 2 A devices (see Figure 10)
Parameter
Symbol
Values
Typ.
3.1
Unit Note or Test Condition
Min.
Max.
High-level (Sourcing) Output
Resistance
Ron_SRC
1.4
5.8
Ω
ISNK = 50 mA
1)
Peak Sourcing Output Current
ISRC_pk
–
1
A
–
Low-level (Sinking) Output
Resistance
Ron_SNK
0.6
1.2
2.5
Ω
ISRC = 50 mA
2)
Peak Sinking Output Current
ISNK_pk
-2
–
A
–
1) actively limited by design at approx. 1.3 Apk, parameter is not subject to production test - verified by design /
characterization
2) actively limited by design at approx. -2.6 Apk, parameter is not subject to production test - verified by design /
characterization
Table 17 Dynamic characteristics (see Figure 5 and Figure 14)
TJ,max = 125°C, CLOAD = 1.8 nF for 4 A / 8 A version, CLOAD = 0.47 nF for 1 A / 2 A version
Parameter
Symbol
Values
Typ.
37
Unit Note or Test Condition
Min.
Max.
INA- /INB-to-output turn-on /
turn-off propagation delay
tPDon
tPDoff
tPDon
,
31
44
ns 4 A/8 A version
ns 1 A/2 A version
ns 1 A/2 A version
INA- /INB-to-output turn-on
propagation delay
31
29
–
37
35
–
44
44
100
3
INA- /INB-to-output turn-off
propagation delay
tPDoff
DISABLE-to-output turn-on/
-off propagation delay
tPDDISoff
,
ns
–
tPDDISoff
Output turn-on propagation
delay mismatch between
channels
∆tPDon
–
–
ns INA, INB shorted
Rise time
trise
–
6.5
121)
ns
–
Final datasheet
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EiceDRIVER™ 2EDi product family
2EDSx reinforced, 2EDFx functional isolated 4A/8A, 1A/2A gate drivers
Device characteristics
Table 17 Dynamic characteristics (see Figure 5 and Figure 14) (cont’d)
TJ,max = 125°C, CLOAD = 1.8 nF for 4 A / 8 A version, CLOAD = 0.47 nF for 1 A / 2 A version
Parameter
Symbol
Values
Typ.
4.5
Unit Note or Test Condition
Min.
Max.
81)
Fall time
tfall
tPW
–
–
ns
ns
–
–
Minimum input pulse width
that changes output state
18
–
Programmable dead time
tDT
–
115
–
ns with RDTC = 62 kΩ
1) parameter verified by design, not tested in production
Final datasheet
19
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2020-03-17
EiceDRIVER™ 2EDi product family
2EDSx reinforced, 2EDFx functional isolated 4A/8A, 1A/2A gate drivers
Device characteristics
4.5
Functional and reinforced isolation specifications
Each individual part number and package variant has its own safety isolation characteristic due to package
dimension and respective isolation test voltages and methods applied. The table heading references each unique
part number.
For reinforced safety, the regulatory tests described in the component and system standards are applied by
Infineon. For functional isolation, the outlined in-house test methods have been applied.
As soon as the regulatory certificates are available, the reference and or documents will become available for
public download on the Infineon website www.infineon.com/2EDi
Note:
Final creepage and clearance of component, must be verified in conjunction with PCB design layout
and manufacturing choice like PCB material (CTI), stubs, graves, lacquer which might increase or
reduce safety distances. Meeting the isolation requirements on system level is therefore the
responsibility of the application owner.
4.5.1
Functional isolation specifications
4.5.1.1 Functional isolation of devices in PG-TFLGA-13-1 package
The PG-TFLGA-13-1 package is available for 2EDF7275K and 2EDF7235K. The isolation related parameters are
shown in Table 18, Table 19 and Table 20; for a component with basic or reinforced safety approval, choose a
different part number (e.g. Chapter 4.5.2: 2EDS8265H, 2EDS9265H and 2EDS8165H)
Table 18 Functional isolation input-to-output (PG-TFLGA-13-1)
Parameter
Symbol
Values
Typ.
–
Unit Note or Test Condition
Min.
Max.
Functional isolation test
voltage
VIO
VIOWM
CLR
1500
–
VDC Impulse test >10 ms,
production tested
Maximum isolation working
voltage
460
–
–
–
–
VRMS according to IEC 60664-1
(PD 2; MG II)
Package clearance
3.4
mm Shortest distance over
air, from any input pin to
any output pin
Package creepage
CPG
–
3.4
–
–
–
mm Shortest distance over
surface, from any input
pin to any output pin
Common Mode Transient
Immunity
CMTI
150
V/ns according to DIN V VDE
V0884-10, static and
dynamic test
1)
Capacitance input-to-output
Resistance input-to-output
CIO
RIO
–
–
2
–
–
pF
1)
>1000
MΩ
1) parameter verified by design, not tested in production
Final datasheet
20
Rev.2.5
2020-03-17
EiceDRIVER™ 2EDi product family
2EDSx reinforced, 2EDFx functional isolated 4A/8A, 1A/2A gate drivers
Device characteristics
Table 19 Package characteristics (PG-TFLGA-13-1)
Parameter
Symbol
Values
Typ.
–
Unit Note or Test Condition
Min.
Max.
Comparative Tracking Index of
package mold
CTI
–
400
600
V
–
according to DIN EN
60112 (VDE 0303-11)
Material group
–
II
–
according to IEC 60112
Table 20 Functional isolation channel-to-channel (PG-TFLGA-13-1)
Parameter
Symbol
Values
Typ.
–
Unit Note or Test Condition
Min.
Max.
Functional isolation test
voltage
VCh2Ch-DC-
650
–
VDC Impulse Test > 10 ms;
sample tested
Test
Package creepage
CPG
–
1.0
–
mm Shortest distance over
surface, from output pin
Ch1-GND to output pin
Ch2-VDD
4.5.1.2 Functional isolation of devices in NB PG-DSO-16-11 package
The PG-DSO-16-11 package is available for 2EDF7175F, 2EDF9275Fand 2EDF7275F. The isolation related
parameters are shown in Table 21, Table 22 and Table 23
Table 21 Input-to-output isolation specification (NB PG-DSO-16-11)
Parameter
Symbol
Values
Typ.
Unit Note or Test Condition
Min.
Max.
Functional isolation test
voltage
VIO
1500
–
–
–
VDC Impulse test > 10 ms,
sample tested
Maximum isolation working
voltage
VIOWM
CLR
510
–
–
–
VRMS according to IEC 60664-1
(PD2; MG II)
Package clearance
4.0
4.0
–
mm Shortest distance over air,
from any input pin to any
output pin
Package creepage
CPG
–
–
mm Shortest distance over
surface, from any input
pin to any output pin
Common Mode Transient
Immunity
CMTI
150
–
V/ns according to DIN V VDE
V0884-10, static and
dynamic test
1)
Capacitance input-to-output
Resistance input-to-output
CIO
RIO
–
–
2
–
–
pF
1)
>1000
MΩ
1) parameter verified by design, not tested in production
Final datasheet
21
Rev.2.5
2020-03-17
EiceDRIVER™ 2EDi product family
2EDSx reinforced, 2EDFx functional isolated 4A/8A, 1A/2A gate drivers
Device characteristics
Table 22 Package characteristics (NB PG-DSO-16-11)
Parameter
Symbol
Values
Typ.
–
Unit Note or Test Condition
Min.
Max.
Comparative Tracking Index
of package mold
CTI
–
400
600
V
–
according to DIN EN 60112
(VDE 0303-11)
Material group
–
II
–
according to IEC 60112
Table 23 Channel-to-channel isolation (NB PG-DSO-16-11)
Parameter
Symbol
Values
Typ.
–
Unit Note or Test Condition
Min.
Max.
Functional isolation test
voltage
VCh2Ch-DC-
1500
–
VDC Impulse Test >10 ms;
sample tested
Test
Package Creepage
CPG
–
2.5
–
mm Shortest distance over
surface, from Output pin
Ch1-GND to output pin
Ch2-VDD
4.5.2
Reinforced isolation of devices in WB PG-DSO-16-30 package
The PG-DSO-16-30 package is available for 2EDS8265H, 2EDS9265H and 2EDS8165H. The safety related
certifications are listed in Table 24, Table 25 and the isolation related parameters are shown in Table 26 to
Table 30
Table 24 Component safety-related certificates for WB PG-DSO-16-301)
Certification
DIN V VDE V 0884-10
UL 1577
Issuing certification body
Certification status
Certified 2)
Certification number
40043864
VDE
UL
Certified
E311313
1) certifications planned for 2EDS9265H
2) certification no longer available due to standard expiration
Table 25 Sistem safety-related certifications for WB PG-DSO-16-30 1)
Certification
Issuing certification body
Certification status
Certification number
DIN EN 62368-1 (VDE 0868-1),
DIN 60950-1 (VDE 0805-1)
VDE
Certified
40050289
EN 61010-1
VDE
VDE
CQC
CSA
Certified
40051533
EN 60601-1
Certification pending
Certification pending
Certification planned
–
–
–
GB 4943.1-2011
CSA C22.2 No. 62368-1
1) certifications planned for 2EDS9265H
Final datasheet
22
Rev.2.5
2020-03-17
EiceDRIVER™ 2EDi product family
2EDSx reinforced, 2EDFx functional isolated 4A/8A, 1A/2A gate drivers
Device characteristics
Table 26 Input-to-output isolation specification according to DIN V, VDE0884-10 (2016-06)1)
in WB PG-DSO-16-30
Parameter
Symbol
Values
Typ.
–
Unit Note or Test Condition
Min.
Max.
Maximum transient isolation
voltage
VIOTM
8000
–
Vpk qualification for t = 60 s;
production test with
V
IOTM > 10 kVpk for t =1 s
Maximum repetitive peak
isolation voltage
VIORM
VIOWM
1420
–
–
Vpk Time Dependent Dielectric
Breakdown test method
Maximum isolation working
voltage
1420
1000
4500
–
–
–
–
–
–
VDC
VRMS
Partial discharge voltage
VPD
Vpk Test sequence: 10.2 kVpk for
t = 1 s followed by partial
discharge 4.5 kVpk > 1.875 x
V
IOWM , QPD < 5 pC; production
test
Maximum surge isolation
voltage
VIOSM
CLR
CPG
–
6250
–
–
–
Vpk VIOSM_test = 1.6 x VIOSM >10 kVpk;
sample tested 2)
Package clearance
–
–
I
8.0
8.0
–
mm from any input pin to any
output pin
Package creepage
–
mm from any input pin to any
output pin
Overvoltage category per
IEC 60664-1 table F.1
IV
Rated mains voltage
≤ 150 VRMS
I
I
–
III
II
–
≤ 300 VRMS
≤ 600 VRMS
–
Capacitance input-to-output
Resistance input-to-output
CIO
RIO
–
2
>1000
–
pF
–
–
–
–
MΩ
Common Mode Transient
Immunity
CMTI
150
–
V/ns input to each output channel;
static & dynamic; sample test
1) VDE encompasses former VDE0884-10, IEC60747-5-5 (opto-coupler standard)
2) Surge pulse tests applied according to IEC60065-10.1 (Ed 8.0 2014), 61000-4-5, 60060-1; waveforms (1.2 µs slope,
50 µs decay)
Table 27 Reinforced isolation package characteristics (in WB PG-DSO-16-30)
Parameter
Symbol
Values
Typ.
–
Unit Note or Test Condition
Min.
Max.
Comparative Tracking Index
of package mold
CTI
400
600
V
according to DIN EN 60112
(VDE 0303-11)
Material group
–
–
–
–
–
–
II
2
–
–
–
–
–
–
according to IEC 60112
Pollution degree
Climatic category
–
–
40/125/
21
Final datasheet
23
Rev.2.5
2020-03-17
EiceDRIVER™ 2EDi product family
2EDSx reinforced, 2EDFx functional isolated 4A/8A, 1A/2A gate drivers
Device characteristics
Table 28 Reinforced input-to-output isolation according to UL1577 Ed 5 (in WB PG-DSO-16-30)
Parameter
Symbol
Values
Typ.
–
Unit Note or Test Condition
Min.
Max.
Withstand isolation voltage
VISO
5700
–
VRMS
VISO= 5700 VRMS for
t = 60 s (qualification);
V
ISO > 1.2 x VRMS = 6840 V for
t = 1 s
Table 29 Functional isolation channel-to-channel (in WB PG-DSO-16-30)
Parameter
Symbol
Values
Typ.
–
Unit Note or Test Condition
Min.
Max.
Functional isolation VCh2Ch-DC-
1500
–
VDC Impulse Test >10 ms; sample tested
test voltage
test
Package creepage
CPG
2.4
2.5
2.7
mm Shortestdistanceoversurface, from
Output pin Ch1-GND to output pin
Ch2-VDD
4.5.3
Safety-limiting values
Table 30 Reinforced isolation safety-limiting values as outlined in VDE-0884-10 (WB PG-DSO-16-30)
Parameter
Side
Values
Unit
Note or Test Condition
Min.
Typ.
Max.
20.0
1050
1050
2120
87.5
87.5
Safety supply power Input chip
–
–
–
–
–
–
–
–
–
–
–
–
mW RthJA = 59 K/W1),
T
amb = 25°C,
Output A
Output B
Total
mW
mW
mW
mA
TJ = 150°C
Safety supply
currents
Output A
Output B
R
thJA = 59 K/W1),
VDDA/VDDB = 12 V,
amb = 25°C, TJ = 150°C
mA
T
Output A
Output B
–
–
–
–
53.5
53.5
mA
mA
R
thJA = 59 K/W,
VDDA/VDDB = 20 V,
amb = 25°C, TJ = 150°C
T
Safety temperature
Ts
–
–
150
°C
Ts = TJ,max
1) calculated with the Rth of WB PG-DSO-16-30 package (see Table 7)
According to VDE0884-10 and UL1577, safety-limiting values define the operating conditions under which the
isolation barrier can be guaranteed to stay unaffected. This corresponds with the maximum allowed junction
temperature, as temperature-induced failures might cause significant overheating and eventually damage the
isolation barrier.
Final datasheet
24
Rev.2.5
2020-03-17
EiceDRIVER™ 2EDi product family
2EDSx reinforced, 2EDFx functional isolated 4A/8A, 1A/2A gate drivers
Timing diagrams
5
Timing diagrams
Figure 5 depicts rise, fall and delay times for 2EDi 4 A/8 A. Besides, the effect of an activated dead time control
(resistor connected to pin DTC) is indicated.
VINH
VINL
INA/B
90%
10%
90%
10%
OUTA/B
tPDon
tPDoff
trise
tfall
tdt
Figure 5
Propagation delays, rise, fall and dead time
Figure 6 illustrates the Undervoltage Lockout function for the output supplies.
UVLOon
UVLOoff
VDDA/B - GNDA/B
OUTA/B - GNDA/B
Figure 6
Output UVLO behavior (output state high)
Final datasheet
25
Rev.2.5
2020-03-17
Timing_diag.fm
EiceDRIVER™ 2EDi product family
2EDSx reinforced, 2EDFx functional isolated 4A/8A, 1A/2A gate drivers
Typical characteristics
6
Typical characteristics
VDDA = VDDB = 12 V, VDDI = 3.3 V, Tamb = 25°C, 2EDF7235K (PG-TFLGA-13-1) and no load unless otherwise noted.
6.0
5.0
4.0
3.0
2.0
1.0
1.6
1.4
1.2
1.0
100kHz
1MHz
3MHz
0
-50
0
50
TJ[°C]
100
150
-50
0
50
TJ[°C]
100
150
Typical VDDI quiescent
current vs. temperature
Typical VDDI current vs.
temperature and frequency
Figure 7
Supply current VDDI
1.0
0.9
0.8
0.7
0.6
0.5
0.4
1.0
0.8
0.6
0.4
OUT High
OUT Low
OUT High
OUT Low
0
5
10
VDDA/B [V]
Typical VDDA/B quiescent
currents vs. supply voltage
15
20
25
-50
0
50
TJ[°C]
100
150
Typical VDDA/B quiescent
currents vs. temperature
Figure 8
Supply current VDDA, VDDB
Final datasheet
26
Rev.2.5
2020-03-17
EiceDRIVER™ 2EDi product family
2EDSx reinforced, 2EDFx functional isolated 4A/8A, 1A/2A gate drivers
Typical characteristics
14
12
10
8
50
40
30
20
10
0
50kHz
1MHz
3MHz
Duty Cycle 50%
CLoad = 1.8nF
VDD 4.5V
VDD 12V
VDD 20V
6
4
2
0
0
200
400
600
800
1000
-50
0
50
100
150
TJ[°C]
frequency [kHz]
Typical VDDA/B current consumption with
capacitive load vs frequency
Typical VDDA/B current vs.
temperature and frequency, no load
Figure 9
Supply current VDDA, VDDB (with / without load)
6
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
Ron_src
Ron_snk
Ron_src
Ron_snk
5
4
3
2
1
0
-50
0
50
100
150
-50
0
50
100
150
TJ[°C]
TJ[°C]
Typical output resistance vs.
temperature (4A/8A version)
Typical output resistance vs.
temperature (1A/2A version)
Figure 10 Output resistance
Final datasheet
27
Rev.2.5
2020-03-17
EiceDRIVER™ 2EDi product family
2EDSx reinforced, 2EDFx functional isolated 4A/8A, 1A/2A gate drivers
Typical characteristics
2.5
ON threshold
OFF threshold
UVLO on
UVLO off
2.9
2.7
2.5
2.0
1.5
1.0
0.5
-50
0
50
100
150
-50
0
50
TJ[°C]
100
150
TJ[°C]
Typical input voltage
thresholds vs. temperature
Typical Undervoltage Lockout
threshold VDDI vs. temperature
Figure 11 Logic input thresholds and VDDI UVLO
4.5
8.8
8.4
8.0
7.6
7.2
6.8
6.4
UVLO on
UVLO off
UVLO on
UVLO off
4.3
4.1
3.9
3.7
-50
0
50
TJ[°C]
100
150
-50
0
50
TJ[°C]
100
150
Typical Undervoltage Lockout threshold
VDDA/B vs. temperature (4V-versions)
Typical Undervoltage Lockout threshold
VDDA/B vs. temperature (8V-versions)
Figure 12 VDDA/B UVLO (4 V and 8 V)
Final datasheet
28
Rev.2.5
2020-03-17
EiceDRIVER™ 2EDi product family
2EDSx reinforced, 2EDFx functional isolated 4A/8A, 1A/2A gate drivers
Typical characteristics
14.0
UVLO on
UVLO off
13.6
13.2
12.8
12.4
-50
0
50
100
150
Tj [°C]
Typical Under Voltage Lockout threshold
VDDA/B vs. temperature (13V-version)
Figure 13 VDDA/B UVLO (13 V)
8
45
turn-on
turn-off
7
6
5
4
3
40
35
30
VDD=12V
Cload=1.8n
-50
0
50
100
150
-50
0
50
100
150
TJ[°C]
TJ[°C]
Typical propagation
delay vs. temperature
Typical rise and fall time
vs. temperature
Figure 14 Propagation delay and rise / fall time
Final datasheet
29
Rev.2.5
2020-03-17
EiceDRIVER™ 2EDi product family
2EDSx reinforced, 2EDFx functional isolated 4A/8A, 1A/2A gate drivers
Typical characteristics
300
250
200
150
100
50
0
0
50
100
150
200
R
DTC [kΩ]
Figure 15 Dead time control: rising edge delay vs RDTC
2500
2000
1500
1000
500
100
I_VDDA, VDDB for VDD=12 V
I_VDDA, VDDB for VDD=20 V
75
50
25
VDDI = 3.3 V
VDDI = 3.3 V
(Current in each channel with both
channels running simultaneously)
(Current in each channel with both
channels running simultaneously)
0
0
-50
0
50
amb [°C]
100
150
-50
0
50
amb [°C]
100
150
T
T
Thermal derating for safety-
related limiting current
Thermal derating for safety-
related limiting power
Figure 16 Thermal derating curves
Final datasheet
30
Rev.2.5
2020-03-17
EiceDRIVER™ 2EDi product family
2EDSx reinforced, 2EDFx functional isolated 4A/8A, 1A/2A gate drivers
Package outline dimensions
7
Package outline dimensions
The following package versions are available.
•
•
•
an NB PG-DSO-16-11 package with typ. 4 mm creepage input to output
an area optimized 5 x 5 mm2 PG-TFLGA-13-1
a WB PG-DSO-16-30 package with typ. 8 mm creepage input to output
Note:
For further information on package types, recommendation for board assembly, please go to:
www.infineon.com/2EDi
7.1
Device numbers and markings
Table 31 Device numbers and markings
Part number
2EDF7275F
2EDF9275F
2EDF7175F
2EDF7275K
2EDF7235K
Orderable part number (OPN)
Device marking
2F7275B
2EDF7275FXUMA2
2EDF9275FXUMA1
2EDF7175FXUMA2
2EDF7275KXUMA2
2F9275B
2F7175B
2F7275B
2F7235A
2EDF7235KXUMA1
2EDS8265HXUMA2
2EDS9265HXUMA1
2EDS8165HXUMA2
2EDS8265H
2EDS9265H
2EDS8165H
2S8265B
2S9265B
2S8165B
7.2
Package PG-DSO-16-11
1)
4-00..02
1)
10-00..02
0.33+-00..0187
x 45°
D
0.64 0.25
C
0.1 C 16x
SEATING COPLANARITY
6
0.2
PLANE
0.41+-00..0068
0.25
D
C 16x
BOTTOM VIEW
16
9
9
8
16
1
1
8
1.27
INDEX
MARKING
1) DOES NOT INCLUDE PLASTIC OR METAL PROTRUSION OF 0.25 MAX. PER SIDE
ALL DIMENSIONS ARE IN UNITS MM
THE DRAWING IS IN COMPLIANCE WITH ISO 128 & PROJECTION METHOD 1 [
]
Figure 17 PG-DSO-16-11 outline
Final datasheet
31
Rev.2.5
2020-03-17
EiceDRIVER™ 2EDi product family
2EDSx reinforced, 2EDFx functional isolated 4A/8A, 1A/2A gate drivers
Package outline dimensions
Figure 18 PG-DSO-16-11 footprint
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3,1 ꢀ
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@
Figure 19 PG-DSO-16-11 packaging
Final datasheet
32
Rev.2.5
2020-03-17
EiceDRIVER™ 2EDi product family
2EDSx reinforced, 2EDFx functional isolated 4A/8A, 1A/2A gate drivers
Package outline dimensions
7.3
Package PG-DSO-16-30
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Figure 20 PG-DSO-16-30 outline
Figure 21 PG-DSO-16-30 footprint
Final datasheet
33
Rev.2.5
2020-03-17
EiceDRIVER™ 2EDi product family
2EDSx reinforced, 2EDFx functional isolated 4A/8A, 1A/2A gate drivers
Package outline dimensions
16
0.3
PIN 1
INDEX MARKING
4
10.8
2.7
3.2
All dimensions are in units mm
The drawing is in compliance with ISO 128-30, Projection Method 1 [
]
Figure 22 PG-DSO-16-30 packaging
7.4
Package PG-TFLGA-13-1
Figure 23 PG-TFLGA-13-1 outline
Final datasheet
34
Rev.2.5
2020-03-17
EiceDRIVER™ 2EDi product family
2EDSx reinforced, 2EDFx functional isolated 4A/8A, 1A/2A gate drivers
Package outline dimensions
Figure 24 PG-TFLGA-13-1 footprint
Figure 25 PG-TFLGA-13-1 packaging
Final datasheet
35
Rev.2.5
2020-03-17
EiceDRIVER™ 2EDi product family
2EDSx reinforced, 2EDFx functional isolated 4A/8A, 1A/2A gate drivers
Revision history
Page or Item
Subjects (major changes since previous revision)
Rev. 2.5 Datasheet, 2020-03-17
Page 1
“certified according to DIN V VDE V0884-10” changed in “DIN V VDE V0884-10
compliant” due to standard expiration on 2019.12.31
Whole document
added references to 2EDF9275F and 2EDS9265H (13 V UVLO options for SiC
MOSFETs driving)
Page 1, Table 1
Page 1
added reference to EN 61010-1 certification
update of term DIN EN 62368-1 and DIN EN 60950-1
CQC removed from Table 1 due to presence of footnote 2)
added footnote 3) due to expiration of VDE0884-10 certification
added 2EDF9275F and 2EDS9265H products
Table 1
Table 1
Table 1, Table 31
Table 1
removed OPN for better readability; OPN shown in Table 31
Table 13
Table 9
VIN max. value 6.5 V→ 15 V
added IVDDA, IVDDBquiescient current for 2EDF9275F and 2EDS9265H
Table 11
Table 13
added VDDA, VDDB Undervoltage Lockout table for 2EDF9275F and 2EDS9265H
added “UVLO threshold vs temperature” for the 13 V UVLO options
(2EDF9275F, 2EDS9265H)
Table 24, Table 25
Table 26
added tables for overview on safety-related certifications of PG-DSO-16-30
“see VDE certificate” footnote removed due to certification expiration
fixed typo in the test condition: 5700 kVRMS → 5700 VRMS
Table 28
Table 31
new OPN and “B” marking: improved secondary-side clamping performance
Rev 2.4 Datasheet, 2019-02-08
Table 6
max. VDDI: 3.7 V → 4.0 V
Rev. 2.3 Datasheet, 2019-01-31
Whole document
removed “certification pending” because certification has been issued (see
Table 1)
Chapter 7
latest footprints, outlines and packaging for PG-DSO-16-11 and
PG-DSO-16-30
Figure 7
adjusted values
Page 1
propagation delay variance in “Features” updated
OPN inserted for 2EDF7235K
Table 1 and Table 31
Table 6
reference to max. value → VDDO for voltage at pins OUTA and OUTB
Table 6
removed footnote 1 from parameter “Non-destructive Common Mode
Transient Immunity”
Table 8
Tamb max. value 85°C → 125°C
Table 17
CLOAD in "Note or test condition" moved to table description
Table 18, Table 21 and Table 26 Non-destructive Common Mode Transient Immunity transferred to Table 6,
Absolute maximum ratings
Table 18
added footnote to “Capacitance” and “Resistance” parameters
Final datasheet
36
Rev.2.5
2020-03-17
EiceDRIVER™ 2EDi product family
2EDSx reinforced, 2EDFx functional isolated 4A/8A, 1A/2A gate drivers
Page or Item
Subjects (major changes since previous revision)
Table 21
footnotes assignation patched
Rev. 2.2 Datasheet, 2018-11-07
Chapter 3.2
Update device part numbers
Update of term “DIN V, VDE V0884-10”
Update product validation in “Features”
Update of OPN
Chapter 4
Page 1
Table 1, Table 31
Table 6
Removed typos
Rev. 2.1 Datasheet, 2018-10-24
Table 1, Table 6, Table 31
Rev. 2.0 Datasheet, 2018-06-04
Updates
Initial data sheet available
Final datasheet
37
Rev.2.5
2020-03-17
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Document reference
EiceDRIVER™ 2EDi Rev.2.4
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