6ED2230S12T [INFINEON]

EiceDRIVER™ 1200 V three-phase gate driver with typical 0.35 A source and 0.65 A sink currents in DSO-24 lead package for IGBT discretes and IGBT modules.;


型号：	6ED2230S12T
厂家：	Infineon
描述：	EiceDRIVER™ 1200 V three-phase gate driver with typical 0.35 A source and 0.65 A sink currents in DSO-24 lead package for IGBT discretes and IGBT modules. 驱动双极性晶体管
文件：	总23页 (文件大小：824K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

2ED2142S02M

6ED2230S12T

1200 V Three Phase Gate Driver with Integrated Bootstrap Diode and OCP

Features

Product summary

•

Infineon Thin-Film-SOI technology

V_{S_OFFSET}

V_CC

= ≤ 1200 V

Fully operational to +1200 V

= 13 V – 20 V

Integrated Ultra‐fast Bootstrap Diode

Floating channel designed for bootstrap operation

Output source/sink current capability +0.35 A/‐0.65 A

Tolerant to negative transient voltage up to -100 V

(Pulse width is up 700 ns) given by SOI-technology

Undervoltage lockout for both channels

Shoot-through protection

3.3 V, 5 V, and 15 V input logic compatible

Over current protection with ±5% ITRIP threshold

Fault reporting, automatic Fault clear and

Enable function on the same pin (RFE)

Matched propagation delay for all channels

Integrated 460 ns deadtime protection

VCC support up to 25 V

I_O+/ I_O-(typ) = + 0.35 A / - 0.65 A

t_ON/ t_OFF(typ.) = 700 ns/ 650 ns

Deadtime (typ.) = 460 ns

•

Package

•

DSO-24 (DSO-28 with 4 pins removed)

2 kV HBM ESD

Typical applications

•

Commercial and Lite Commercial Air Conditioning; CAC, HVAC

•

Industrial Drives, Servo Drives

Embedded inverters for Motor Control in Pumps, Fans

Heatpumps

Product validation

Qualified for industrial applications according to the relevant tests of JEDEC78/20/22

Ordering information

Standard pack

Form

Base part number Package type

6ED2230S12T ¹⁾

DSO-24

Orderable part number

6ED2230S12TXUMA1

Quantity

Tape and Reel

1000

Also available for die sales as ‘Sawn Wafer on Film’ with part number 6ED2230S12C. Please contact Infineon for more

information.

Datasheet

www.infineon.com/soi

Please read the Important Notice and Warnings at the end of this document

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6ED2230S12T

1200 V Three Phase Gate Driver with Integrated Bootstrap Diode and OCP

Description

The 6ED2230S12T is a high voltage, high speed IGBT with three independent high side and low side referenced

output channels for three phase applications. Proprietary HVIC and latch immune CMOS technologies enable

ruggedized monolithic construction. The logic input is compatible with standard CMOS or TTL outputs, down

to 3.3 V logic. An over-current protection (OCP) function which terminates all six outputs can also be derived

from this resistor. An open drain FAULT signal is provided to indicate that an over-current or undervoltage

shutdown has occurred. Fault conditions are cleared automatically after a delay programmed externally via

an RC network. The output drivers feature a high-pulse current buffer stage designed for minimum driver

cross-conduction. The floating channel can be used to drive N-channel power MOSFETs or IGBTs in the high

side configuration which operates up to 1200 V. Propagation delays are matched to simplify the HVIC’s use in

high frequency applications.

DC + BUS

VCC

(x3)

HIN

LIN

HIN(x3)

(x3)

LIN

V_DD

6ED2230S12T

R_RFE

(x3)

Load

RFE

C_RFE

ITRIP

VSS

COM

DC - BUS

*(Refer to Lead Assignments for correct pin configuration). This diagram shows electrical connections only. Please refer to Application

Notes & Design Tips for proper circuit board layout.

Figure 1

Typical application block diagram

Datasheet

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6ED2230S12T

1200 V Three Phase Gate Driver with Integrated Bootstrap Diode and OCP

Table of contents

Product validation .......................................................................................................................................................1

Description

Table of contents............................................................................................................................ 3

Block diagram........................................................................................................................ 4

2.1

2.2

Pin configuration and functionality.......................................................................................... 5

Pin configuration.....................................................................................................................................5

Pin functionality ......................................................................................................................................5

Electrical parameters ............................................................................................................. 6

Absolute maximum ratings.....................................................................................................................6

Recommended operating conditions.....................................................................................................6

Static electrical characteristics...............................................................................................................7

Dynamic electrical characteristics..........................................................................................................8

3.1

3.2

3.3

3.4

Application information and additional details.......................................................................... 9

IGBT/MOSFET gate drive.........................................................................................................................9

Switching and timing relationships........................................................................................................9

Deadtime and matched propagation delays........................................................................................10

Input logic compatibility.......................................................................................................................11

Undervoltage lockout ...........................................................................................................................11

Shoot-through protection.....................................................................................................................12

Enable, Fault reporting and programmable fault clear timer .............................................................12

Over-current protection........................................................................................................................13

Truth table: Undervoltage lockout, ITRIP and enable .........................................................................13

Advanced input filter.............................................................................................................................14

Short-Pulse / Noise Rejection ...............................................................................................................14

Integrated bootstrap diode...................................................................................................................15

Tolerance to negative VS transient.......................................................................................................15

PCB layout tips ......................................................................................................................................17

4.1

4.2

4.3

4.4

4.5

4.6

4.7

4.8

4.9

4.10

4.11

4.12

4.13

4.14

Qualification information........................................................................................................18

Related products...................................................................................................................19

Packaging information ..........................................................................................................20

Additional documentation and resources.................................................................................21

8.1

Infineon online forum resources ..........................................................................................................21

Revision history ....................................................................................................................22

Datasheet

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6ED2230S12T

1200 V Three Phase Gate Driver with Integrated Bootstrap Diode and OCP

Block diagram

VB1

Input

Noise

filter

VSS/COM

Level

Shifter

Latch

UV Detect

HV Level

Shifter

HIN1

LIN1

Driver

HO1

VS1

Deadtime &

Shoot-Through

Prevention

Input

Noise

filter

VB2

HO2

VS2

Input

Noise

filter

VSS/COM

Level

Shifter

Latch

UV Detect

HIN2

LIN2

HV Level

Shifter

Driver

Deadtime &

Shoot-Through

Prevention

Input

Noise

filter

VB3

HO3

VS3

Input

Noise

filter

VSS/COM

Level

Shifter

Latch

UV Detect

HV Level

Shifter

HIN3

Driver

Deadtime &

Shoot-Through

Prevention

Input

Noise

filter

LIN3

VSS

Detect

VCC

LO1

ITRIP

RFE

ITRIP

Noise

filter

VSS/COM

Level

Shifter

Delay

Driver

Noise

filter

VSS/COM

Level

Shifter

Delay

Driver

LO2

VSS/COM

Level

Shifter

Driver

Delay

LO3

COM

Figure 2

Functional block diagram

Datasheet

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6ED2230S12T

1200 V Three Phase Gate Driver with Integrated Bootstrap Diode and OCP

Pin configuration and functionality

2.1

Pin configuration

VB1

HO1

VS1

HIN1

HIN2

HIN3

LIN1

LIN2

LIN3

VB2

HO2

VS2

ITRIP

RFE

VCC

VSS

VB3

HO3

VS3

COM

LO1

LO2

LO3

Figure 3

6ED2230S12T pin assignments (top view)

2.2

Pin functionality

Table 1

Symbol

Description

HIN1,2,3

LIN1,2,3

VB1,2,3

HO1,2,3

VS1,2,3

VCC

Logic input for high side gate driver output (HO), in phase

Logic input for low side gate driver output (LO), in phase

High side floating supply

High side gate drive output

High side floating supply return

Low side and logic fixed supply

Low side gate drive output

LO1,2,3

COM

Low side return

VSS

Logic ground

Analog input for over-current shutdown. When active, ITRIP shuts down outputs

and activates RFE low. When ITRIP becomes inactive, RFE stays active low for an

externally set time t_FLTCLR, then automatically becomes inactive (open-drain high

impedance).

ITRIP

RFE

Integrated fault reporting function like over-current (ITRIP), or low-side

undervoltage lockout and the fault clear timer. This pin has negative logic and an

open-drain output. The use of over-current protection requires the use of

external components.

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6ED2230S12T

1200 V Three Phase Gate Driver with Integrated Bootstrap Diode and OCP

Electrical parameters

3.1

Absolute maximum ratings

Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage

parameters are absolute voltages referenced to COM unless otherwise stated in the table. The thermal resistance

and power dissipation ratings are measured under board mounted and still air conditions.

Table 2

Absolute maximum ratings

Symbol

V_CC

Definition

Low-side supply voltage

Min.

-0.3

Max.

Units

V_IN

Logic input voltage (LIN, HIN, RFE, ITRIP)

High-side floating well supply voltage (Note 1)

High-side floating well supply return voltage

Floating gate drive output voltage

Low-side output voltage

V_SS– 5

-0.3

V_CC+ 0.3

1225

V_{B 1,2,3}

V_{S 1,2,3}

V_{HO 1,2,3}

V_{LO 1,2,3}

V_SS

dV_S/dt

P_D

Rth_JA

T_J

V_{B 1,2,3}– 25

V_{S 1,2,3}– 0.3

–0.3

V_CC-25

—

V_{B 1,2,3}+ 0.3

V_CC+ 0.3

Logic ground

V / ns

ºC/W

Allowable V_Soffset supply transient relative to COM

Package power dissipation @ T_A+25ºC

Thermal resistance, junction to ambient

Junction temperature

—

1.3

150

T_S

Storage temperature

-55

150

ºC

T_L

Lead temperature (soldering, 10 seconds)

—

300

3.2

Recommended operating conditions

For proper operation, the device should be used within the recommended conditions. All voltage parameters are

absolute voltages referenced to COM unless otherwise stated in the table. Recommended operating conditions

Table 3

Symbol

V_CC

Recommended operating conditions

Definition

Min

Max

Units

Low-side supply voltage

V_IN

V_RFE

Logic input voltage (LIN, HIN, ITRIP)

RFE logic input voltage

V_SS

V_SS+ 5

V_CC

V_B1,2,3

V_S1,2,3

V_St

V_HO1,2,3

V_LO1,2,3

V_SS

High-side floating well supply voltage

High-side floating well supply offset voltage

V_S1,2,3+ 12

COM – 8

- 100

V_S1,2,3

V_S1,2,3+ 20

1200

V_B1,2,3

V_CC

Transient High-side floating well supply offset voltage²⁾

Floating gate drive output voltage

Low-side output voltage

Logic ground

- 5

T_A

Ambient temperature

-40

125

ºC

1: Logic operation for V_Sof -8V to +1200 V. Logic state held for V_Sof -8V to -V_BS

2: In case V_CC> V_Bthere is an additional power dissipation in the internal bootstrap diode between pins V_CCand V_Bx. Insensitivity of bridge

output to negative transient voltage up to –100 V is not subject to production test – verified by design / characterization.

Datasheet

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6ED2230S12T

1200 V Three Phase Gate Driver with Integrated Bootstrap Diode and OCP

3.3

Static electrical characteristics

(V_CC- COM) = (V_B- V_S) = 15 V. T_A= 25 °C unless otherwise specified. The V_INand I_INparameters are referenced to COM.

The V_Oand I_Oparameters are referenced to respective V_Sand COM and are applicable to the respective output leads

H_Oor L_O. The V_CCUVparameters are referenced to COM. The V_BSUVparameters are referenced to V_S.

Table 4

Symbol

VBSUV+

Static electrical characteristic

Definition

Min.

Typ.

Max.

Units

Test Conditions

9.2

10.4

11.6

VBS supply under voltage positive threshold

VBSUV-

8.3

9.4

10.5

VBS supply under voltage negative threshold

—

VBSUVHY

VCCUV+

VBS supply under voltage hysteresis

10.2

11.4

12.6

VCC supply under voltage positive threshold

VCCUV-

9.3

10.4

11.5

VCC supply under voltage negative threshold

—

VCCUVHY

VOH

VCC supply under voltage hysteresis

High level output voltage drops, VBIAS^-VO

0.35

I_o= 20 mA

—

2.3

—

VOL

VIH

0.15

—

Low level output voltage drops, VO

Logic “1” input voltage

VIL

—

0.7

2.3

1.1

0.525

0.475

—

Logic “0” input voltage

1.7

0.7

0.47

1.9

VRFE+

VRFE-

RFE positive going threshold

RFE negative going threshold

ITRIP positive going threshold

ITRIP negative going threshold

ITRIP hysteresis

0.9

0.500

0.450

0.050

—

VITRIP+

VITRIP-

VITRIP HYS

ILK

0.42

—

VB = VS = 1200 V

High-side floating well offset supply leakage

—

175

250

1500

—

IQBS

VIN = 0 V or 5 V

C = 22 nF

Quiescent VBS supply current

Quiescent VCC supply current

1000

IQCC

IO+ mean

200

300

Meanoutput currentfor loadcapacitycharging

from3 V(20%) to 6 V(40%)

IO- mean

IO+

400

600

350

—

C = 22 nF

Mean output current for load capacity

discharging from 10.5 V (70%) to 7.5 V (50%)

VO = 0 V

PW ≤ 1 us

—

Output high short circuit pulsed current

Output low short circuit pulsed current

IO-

—

650

—

VO = 15 V

PW ≤ 1 us

VRFE = 3.3 V

VRFE = 0 V

VIN = 5 V

—

IRFE+

IRFE-

IIN+

Logic “1” Input bias current (RFE)

Logic “0” Input bias current (RFE)

Logic “1” Input bias current (LIN, HIN)

—

1000

1250

IIN-

—

VIN = 0 V

Logic “0” Input bias current (LIN, HIN)

—

IITRIP+

IITRIP-

RBS

VIN = 1 V

VIN = 0 V

—

Logic “1” Input bias current (ITRIP)

Logic “0” Input bias current (ITRIP)

Bootstrap diode on resistance

120

0.9

150

—

VFBSD

I_o= 300 mA

Bootstrap diode forward voltage drops

RON, RFE

—

RFE mos resistance

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6ED2230S12T

1200 V Three Phase Gate Driver with Integrated Bootstrap Diode and OCP

3.4

Dynamic electrical characteristics

V_CC= V_BS= 15 V, V_S= COM, T_A= 25 ^oC and C_L= 1000 pF unless otherwise specified.

Table 5 Dynamic electrical characteristics

Symbol Definition

Min.

500

450

—

Typ.

700

650

Max.

900

850

—

Units

Test Conditions

t_ONTurn-on propagation delay

t_OFFTurn-off propagation delay

t_R

t_F

Turn-on rise time

Turn-off fall time

—

MT Delay matching time (HS & LS turn-on/off)

—

130

Deadtime: LO Turn-off to HO Turn-on & HO

Turn-off to LO turn-on

t_FIL,INInput noise filter time

300

200

—

460

350

600

700

500

—

Enable low to output shutdown propagation

delay

t_EN

V_ITRIP= 1 V

t_ITRIPITRIP to output shutdown propagation delay

—

1250

750

t_BLITRIP blanking time

t_FLTITRIP to FAULT propagation delay

—

450

500

650

—

900

FAULT clear time

(R = 2 MΩ, C = 1 nF)

VDD = 3.3 V

t_FLTCLR

—

1.9

—

Datasheet

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6ED2230S12T

1200 V Three Phase Gate Driver with Integrated Bootstrap Diode and OCP

Application information and additional details

Information regarding the following topics are included as subsections within this section of the datasheet.

•

IGBT/MOSFET gate drive

Switching and timing relationships

Deadtime

Matched propagation delays

Input logic compatibility

Undervoltage lockout protection

Shoot-Through protection

Enable input

Fault reporting and programmable fault clear timer

Over-Current protection

Truth table: Undervoltage lockout, ITRIP, and ENABLE

Advanced input filter

Short-Pulse / Noise rejection

Ultra fast, Integrated bootstrap diodes

Negative VS transient SOA

PCB layout tips

Additional documentation

4.1

IGBT/MOSFET gate drive

The 6ED2230S12T HVICs are designed to drive IGBT power devices. Figure 4 and Figure 5 illustrate several

parameters associated with the gate drive functionality of the HVIC. The output current of the HVIC, used to drive the

gate of the power switch, is defined as IO. The voltage that drives the gate of the external power switch is defined as

VOUT.

Figure 4

HVIC Sourcing current

Figure 5

HVIC Sinking current

4.2

Switching and timing relationships

The relationships between the input and output signals of the 6ED2230S12T are illustrated below in

Figure 6. From these figures, we can see the definitions of several timing parameters (i.e., PW_IN, PW_OUT

t_ON, t_OFF, t_R, and t_F) associated with this device.

PW_IN

50%

t_ON

50%

LIN, HIN

LO, HO

t_OFF

t_R

PW_OUT

90%

10%

90%

10%

Figure 6

Switching timing waveforms _ Input/output timing diagram

Datasheet

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6ED2230S12T

1200 V Three Phase Gate Driver with Integrated Bootstrap Diode and OCP

Figure 7 and Figure 8 illustrate the timing relationships of some of the functionality of the 6ED2230S12T; this

functionality is described in further detail later in this document. During interval A of Figure 7, the HVIC has received

the command to turn-on both the high- and low-side switches at the same time; as a result, the shoot-through

protection of the HVIC has. HVIC is keeping on output channel that is already on ignoring the 2^ndinput signal.

Interval B of Figure 7 and Figure 8 shows that the signal on the ITRIP input pin has gone from a low to a high state;

as a result, all of the gate drive outputs have been disabled (i.e., see that HO has returned to the low state; LO is also

held low), and a fault condition is reported on the RFE pin, which goes 0V. Once the ITRIP input has returned to the

low state, the output will remain disabled and the fault condition reported until the voltage on the RFE pin charges

up to VRFE+ threshold; the charging characteristics are dictated by the RC network attached to the RFE pin. After

fault clear time HVIC is waiting for a new input signal on LIN/HIN before activate the output stage (LO/HO).

During interval C of Figure 7 and Figure 9, we can see that the RFE pin has been pulled low (as is the case when the

driver IC has received a command from the control IC to shutdown); these results in the outputs (HO and LO) being

held in the low state until the RFE pin is pulled high. After an enable event HVIC will wait for a new input signal on

LIN/HIN before activate the output stage (LO/HO).

RFE

Figure 7

Input/output timing diagram

VITRIP+

VITRIP-

VEN-

tEN

ITRIP

VRFE+

RFE

50%

t_FLT

t_FLTCLR

t_ITRIP

90%

LO, HO

90%

HO, LO

Figure 8

Detailed view of B interval

Figure 9

Detailed view of C interval

4.3

Deadtime and matched propagation delays

The 6ED2230S12T features integrated deadtime protection circuitry. The deadtime feature inserts a time period (a

minimum deadtime) in which both the high- and low-side power switches are held off; this is done to ensure that the

power switch being turned off has fully turned off before the second power switch is turned on. This minimum

deadtime is automatically inserter whenever the external deadtime is shorter than DT; external deadtimes larger

than DT are not modified by the gate driver. Figure 10 illustrates the deadtime period and the relationship between

the output gate signals.

The deadtime circuitry of 6ED2230S12T is matched with respect to the high- and low-side outputs. Figure 11 defines

the two deadtime parameters (i.e., DT_LO-HOand DT_HO-LO);the deadtime matching parameter (MDT) associated with the

6ED2230S12T specifies the maximum difference between DT_LO-HOand DT_HO-LO

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6ED2230S12T

1200 V Three Phase Gate Driver with Integrated Bootstrap Diode and OCP

LIN

50%

HIN

90%

10%

DT_LO-HO

DT_HO-LO

90%

10%

Figure 10 Dead Time Definitions

Figure 11 Delay Matching Waveform Definitions

The 6ED2230S12T is designed with propagation delay matching circuitry. With this feature, the IC’s response at the

output to a signal at the input requires approximately the same time duration (i.e., tON, tOFF) for both the low-side

channels and the high-side channels; the maximum difference is specified by the delay matching parameter (MT).

The propagation turn-on delay (t_ON) of the 6ED2230S12T is matched to the propagation turn-on delay (t_OFF).

4.4

Input logic compatibility

The inputs of this IC are compatible with standard CMOS and TTL outputs. The 6ED2230S12T has been designed to

be compatible with 3.3V and 5V logic-level signals. Figure 12 illustares an inputsignal to the 6ED2230S12T, its input

threshold values, and the logic state of the IC as a result of the input signals.

V_IH

V_IL

High

Low

Figure 12 HIN & LIN input thresholds

4.5

Undervoltage lockout

This HVIC provides undervoltage lockout protection on both the VCC (logic and low-side circuitry) power supply and

the VBS (high-side circuitry) power supply. Figure 13 is used to illustrate this concept; VCC (or VBS) is plotted over

time and as the waveform crosses the UVLO threshold (VCCUV+/- or VBSUV+/-) the undervoltage protection is

enabled or disabled.

Upon power-up, should the VCC voltage fail to reach the VCCUV+ threshold, the IC will not turn-on. Additionally, if the

VCC voltage decreases below the VCCUV- threshold during operation, the undervoltage lockout circuitry will

recognize a fault condition and shutdown the high- and low-side gate drive outputs, and the FAULT pin will transition

to the low state to inform the controller of the fault condition.

Upon power-up, should the VBS voltage fail to reach the VBSUV threshold, the IC will not turn-on. Additionally, if the

VBS voltage decreases below the VBSUV threshold during operation, the undervoltage lockout circuitry will

recognize a fault condition, and shutdown the high-side gate drive outputs of the IC.

The UVLO protection ensures that the IC drives the external power devices only when the gate supply voltage is

sufficient to fully enhance the power devices. Without this feature, the gates of the external power switch could be

driven with a low voltage, resulting in the power switch conducting current while the channel impedance is high; this

could result in very high conduction losses within the power device and could lead to power device failure.

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6ED2230S12T

1200 V Three Phase Gate Driver with Integrated Bootstrap Diode and OCP

VCCUV+

(or VBSUV+)

VCC (or

VBS)

VCCUV-

(or VBSUV-)

Time

UVLO protection

(Gate drive

outputs disabled)

Normal operation

Figure 13 UVLO protection

4.6

Shoot-through protection

The 6ED2230S12T is equipped with shoot-through protection circuitry (also known as cross-conduction prevention

circuitry). Figure 14 shows how this protection circuitry prevents both the high- and low-side switches from

conducting at the same time.

Figure 14 Illustration of shoot-through protection circuitry

4.7

Enable, Fault reporting and programmable fault clear timer

The 6ED2230S12T provides an enable functionality that allows it to shutdown or enable the HVIC and also provides

an integrated fault reporting output along with an adjustable fault clear timer. There are two situations that would

cause the IC to report a fault via the RFE pin. The first is an undervoltage condition of VCC and the second is if the

over-current feature has recognized a fault. Once the fault condition occurs, the RFE pin is internally pulled to VSS

and the fault clear timer is activated. The RFE output stays in the low state until the fault condition has been removed

and the fault clear timer expires; once the fault clear timer expires, the voltage on the RFE pin will return to its

external pull-up voltage.

The length of the fault clear time period (t_FLTCLR) is determined by exponential charging characteristics of the

capacitor where the time constant is set by R_RFEand C_RFE. Figure 15 shows that R_RFEis connected between the external

supply (V_DD)¹⁾and the RFE pin, while C_RFEis placed between the RFE and VSS pins.

DC + BUS

VCC

(x3)

HIN

LIN

(x3)

HIN

LIN

(x3)

V_DD

6ED2230S12T

R_RFE

(x3)

Load

RFE

C_RFE

ITRIP

VSS

COM

DC - BUS

Figure 15 Programming the fault clear timer

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6ED2230S12T

1200 V Three Phase Gate Driver with Integrated Bootstrap Diode and OCP

The design guidelines for this network are shown in Table 6

Table 6

Design guidelines

≤1 nF

C_RFE

Ceramic

0.5 MΩ to 2 MΩ

>> R_{ON, RCIN}

R_RFE

The length of the fault clear time period can be determined by using the formula below.

v_C(t) = V_f*(1-e^-t/RC

)

t_FLTCLR= - (R_RFE*C_RFE) *ln (1-V_RFE+/V_DD) + 160us

The voltage on the RF pin should not exceed the VDD of the uC power supply.

¹⁾In case VDD is higher than 5V, the R_RFEresistor needs to be at least 200 kΩ in order to limit the IC power dissipation.

4.8

Over-current protection

The 6ED2230S12T is equipped with an over-current feature (ITRIP input pin). This functionality can sense over-

current events in the DC- bus. Once the HVIC detects an over-current event, the outputs are shutdown, and RFE is

pulled to VSS.

The level of current at which the over-current protection is initiated is determined by the resistor network (i.e., R0,

R₁, and R2) connected to ITRIP as shown in Figure 16, and the ITRIP threshold (VITRIP+). The circuit designer will need

to determine the maximum allowable level of current in the DC- bus and select R0, R₁, and R2 such that the voltage

at node VX reaches the over-current threshold _(VITRIP+)at that current level.

VITRIP+ = R0*IDC-(R1/ (R1+R2))

DC + BUS

VCC

(x3)

HIN

LIN

(x3)

HIN

LIN

(x3)

V_DD

6ED2230S12T

R_RFE

(x3)

Load

RFE

C_RFE

ITRIP

VSS

COM

IDC-

DC - BUS

Figure 16 Programming the over-current protection

For example, a typical value for resistor R0 could be 50 mΩ. The voltage of the ITRIP pin should not be

allowed to exceed 5 V; if necessary, an external voltage clamp may be used.

4.9

Truth table: Undervoltage lockout, ITRIP and enable

Table 7 provides the truth table for the 6ED2231S12T. The first line shows that the UVLO for VCC has been tripped;

the RFE output has gone low and the gate drive outputs have been disabled. VCCUV is not latched in this case and

when VCC is greater than VCCUV, the FAULT output returns the driver is functional.

The second case shows that the UVLO for VBS has been tripped and that the high-side gate drive outputs have been

disabled. After VBS exceeds the VBSUV threshold, HO will stay low until the HVIC input receives a new rising transition

of HIN. The third case shows the normal operation of the HVIC. The fourth case illustrates that the ITRIP trip threshold

has been reached and that the gate drive outputs have been disabled. This condition is stored in the external RC

network waiting for fault clear time. The last case shows when the HVIC has received an enable command through the

RFE input to shutdown; as a result, the gate drive outputs have been disabled.

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6ED2230S12T

1200 V Three Phase Gate Driver with Integrated Bootstrap Diode and OCP

Table 7

6ED2230S12T UVLO, ITRIP, FLT/EN/RCIN

VCC

VBS

—

ITRIP

—

RFE

UVLO V_CC

UVLO V_BS

V_CCUV

15 V

0 V

HIGH

LIN

V_BSUV

Normal

operation

15 V

0 V

HIGH

LIN

HIN

ITRIP fault

>V_ITRIP+

0 V

Enable

command

HIGH

Disable

0 V

4.10

Advanced input filter

The advanced input filter allows an improvement in the input/output pulse symmetry of the HVIC and helps to reject

noise spikes and short pulses. This input filter has been applied to the HIN and LIN inputs. The working principle of

the new filter is shown in Figures 17.

Figure 17 shows a typical input filter and the asymmetry of the input and output. The upper pair of waveforms

(Example 1) show an input signal with a duration much longer then t_FIL,IN; the resulting output is approximately the

difference between the input signal and t_FIL,IN. The lower pair of waveforms (Example 2) show an input signal with a

duration slightly longer then t_FIL,IN; the resulting output is approximately the difference between the input signal and

t_FIL,IN

Figure 18 shows the advanced input filter and the symmetry between the input and output. The upper pair of

waveforms (Example 1) show an input signal with a duration much longer then t_FIL,IN; the resulting output is

approximately the same duration as the input signal. The lower pair of waveforms (Example 2) show an input signal

with a duration slightly longer then t_FIL,IN; the resulting output is approximately the same duration as the input signal.

t_FIL,IN

OUT

t_FIL,IN

OUT

Figure 17

Typical input filter

Figure 18

Advanced input filter

4.11

Short-Pulse / Noise Rejection

This device’s input filter provides protection against short-pulses (e.g., noise) on the input lines. If the duration of

the input signal is less than t_FIL,IN, the output will not change states. Example 1 of Figure 19 shows the input and

output in the low state with positive noise spikes of durations less than t_FIL,IN; the output does not change states.

Example 2 of Figure 19 shows the input and output in the high state with negative noise spikes of durations less than

t_FIL,IN; the output does not change states.

t_FIL,IN

OUT

t_FIL,IN

OUT

Figure 19 Noise rejecting input filters

Datasheet

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6ED2230S12T

1200 V Three Phase Gate Driver with Integrated Bootstrap Diode and OCP

4.12

Integrated bootstrap diode

An ultra-fast bootstrap diode is monolithically integrated for establishing the high side supply. The differential

resistor of the diode helps to avoid extremely high inrush currents when initially charging the bootstrap capacitor.

The integrated diode with its resistrance helps save cost and improve reliability by reducing external components as

shown below Figure 20.

Figure 20 6ED2230S12T with integrated components

The low ohmic current limiting resistor provides essential advantages over other competitor devices with high ohmic

bootstrap structures. A low ohmic resistor such as in the 6ED2230S12T allows faster recharching of the bootstrap

capacitor during periods of small duty cycles on the low side transistor. The bootstrap diode is usable for all kind

power electronic converters. The bootstrap diode is a real pn-diode and is temperature robust. It can be used at high

temperatures with a low duty cycle of the low side transistor.

The bootstrap diode of the 6ED2230S12T works with all control algorithms of modern power electronics, such as

trapezoidal or sinusoidal motor drives control.

4.13

Tolerance to negative VS transient

A common problem in today’s high-power switching converters is the transient response of the switch node’s voltage

as the power switches transition on and off quickly while carrying a large current. A typical 3-phase inverter circuit

is shown in Figure 21, here we define the power switches and diodes of the inverter.

If the high-side switch (e.g., the IGBT Q1 in Figures 22-A and 22-B) switches from on to off, while the U phase current

is flowing to an inductive load, a current commutation occurs from high-side switch (Q1) to the diode (D2) in parallel

with the low-side switch of the same inverter leg. At the same instance, the voltage node V_S1, swings from the positive

DC bus voltage to the negative DC bus voltage.

DC+ BUS

V_S3

Input

Voltage

V_S2

Load

V_S1

DC- BUS

Figure 21 Three phase inverter

Also, when the V phase current flows from the inductive load back to the inverter (see Figures 22-C and 22-D)), and

Q4 IGBT switches on, the current commutation occurs from D3 to Q4. At the same instance, the voltage node, V_S2,

swings from the positive DC bus voltage to the negative DC bus voltage.

However, in a real inverter circuit, the VS voltage swing does not stop at the level of the negative DC bus, rather it

swings below the level of the negative DC bus. This undershoot voltage is called “negative V_Stransient”

DC+ BUS

OFF

I_U

I_V

V_S1

V_S2

V_S1

V_S2

I_V

I_U

OFF

DC- BUS

Figure 22 A) Q1 conducting B) D2 conducting C) D3 conducting D) Q4 conducting

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6ED2230S12T

1200 V Three Phase Gate Driver with Integrated Bootstrap Diode and OCP

The circuit shown in Figure 23-A depicts one leg of the three phase inverter; Figures 23-B and 23-C show a simplified

illustration of the commutation of the current between Q1 and D2. The parasitic inductances in the power circuit

from the die bonding to the PCB tracks are lumped together in L_Cand L_Efor each IGBT. When the high-side switch is

on, V_S1is below the DC+ voltage by the voltage drops associated with the power switch and the parasitic elements of

the circuit. When the high-side power switch turns off, the load current momentarily flows in the low-side

freewheeling diode due to the inductive load connected to V_S1(the load is not shown in these figures). This current

flows from the DC- bus (which is connected to the COM pin of the HVIC) to the load and a negative voltage between

V_S1and the DC- Bus is induced (i.e., the COM pin of the HVIC is at a higher potential than the V_Spin).

DC+ BUS

L_C1

DC+ BUS

V_LC1

OFF

L_E1

L_C2

I_U

V_LE1

V_S1

I_U

V_LC2

OFF

V_D2

L_E2

DC- BUS

V_LE2

DC- BUS

Figure 23 Figure A shows the Parasitic Elements. Figure B shows the generation of V_Spositive. Figure C shows the

generation of V_Snegative

In a typical motor drive system, dV/dt is typically designed to be in the range of 3-5 V/ns. The negative VS transient

voltage can exceed this range during some events such as short circuit and over-current shutdown, when di/dt is

greater than in normal operation.

Infineon’s HVICs have been designed for the robustness required in many of today’s demanding applications. An

indication of the 6ED2231S12T’s robustness can be seen in Figure 24, where the 6ED2230S12T Safe Operating Area is

shown at VBS=15V based on repetitive negative VS spikes. A negative VS transient voltage falling in the grey area

(outside SOA) may lead to IC permanent damage; viceversa unwanted functional anomalies or permanent damage

to the IC do not appear if negative Vs transients fall inside the SOA.

Figure 24 Negative VS transient SOA for 6ED2230S12T @ VBS=15V

Even though the 6ED2230S12T has been shown to be able to handle these large negative VS transient conditions, it

is highly recommended that the circuit designer always limit the negative VS transients as much as possible by

careful PCB layout and component use.

Datasheet

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6ED2230S12T

1200 V Three Phase Gate Driver with Integrated Bootstrap Diode and OCP

4.14

PCB layout tips

Distance between high and low voltage components: It’s strongly recommended to place the components tied to

the floating voltage pins (V_Band V_S) near the respective high voltage portions of the device. Please see the Case

Outline information in this datasheet for the details.

Ground Plane: In order to minimize noise coupling, the ground plane should not be placed under or near the high

voltage floating side.

Gate Drive Loops: Current loops behave like antennas and are able to receive and transmit EM noise (see Figure 25).

In order to reduce the EM coupling and improve the power switch turn on/off performance, the gate drive loops must

be reduced as much as possible. Moreover, current can be injected inside the gate drive loop via the IGBT collector-

to-gate parasitic capacitance. The parasitic auto-inductance of the gate loop contributes to developing a voltage

across the gate-emitter, thus increasing the possibility of a self turn-on effect.

Figure 25 Avoid antenna loops

Supply Capacitor: It is recommended to place a bypass capacitor (C_IN) between the VCC and COM pins. A ceramic

1μF ceramic capacitor is suitable for most applications. This component should be placed as close as possible to

the pins in order to reduce parasitic elements.

Routing and Placement: Power stage PCB parasitic elements can contribute to large negative voltage transients at

the switch node; it is recommended to limit the phase voltage negative transients. In order to avoid such conditions,

it is recommended to 1) minimize the high-side emitter to low-side collector distance, and 2) minimize the low-side

emitter to negative bus rail stray inductance. However, where negative VS spikes remain excessive, further steps

may be taken to reduce the spike. This includes placing a resistor (5 Ω or less) between the VS pin and the switch

node (see Figure 26), and in some cases using a clamping diode between COM and V_S(see Figure 27). See the design

tip of DT04-4 for more detailed explanations.

Figure 26 Resistor between the VS pin and

the switch node

Figure 27 Clamping diode between COM and V_S

Datasheet

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6ED2230S12T

1200 V Three Phase Gate Driver with Integrated Bootstrap Diode and OCP

Qualification information

Table 8

Qualification information 1)

Industrial 2)

Qualification Level

Note:

This family of ICs has passed JEDEC’s

Industrial qualification. Consumer

qualification level is granted by

extension of the higher Industrial level.

MSL3 ³⁾, 260 °C

(per IPC/JEDEC J-STD-020)

Moisture Sensitivity Level

ESD

DSO-24

Class 2

Human Body Model

(per JEDEC standard JESD22-A114)

Class C4

Charged Device Model

(per JEDEC standard JS-022-2014)

Class II Level A

(per JESD78)

IC Latch-Up Test

RoHS Compliant

Yes

Qualification standards can be found at Infineon’s web site www.infineon.com

Higher qualification ratings may be available should the user have such requirements. Please

contact your Infineon sales representative for further information.

Higher MSL ratings may be available for the specific package types listed here. Please

contact your Infineon sales representative for further information.

Datasheet

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6ED2230S12T

1200 V Three Phase Gate Driver with Integrated Bootstrap Diode and OCP

6ED2230S12T [INFINEON]

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