ARM2812TCK [INFINEON]
HYBRID - HIGH RELIABILITY 1 MEGA-RAD HARDENED DC/DC CONVERTER; 混合 - 高可靠性1 MEGA - RAD淬硬DC / DC转换器
| 型号： | ARM2812TCK |
| 厂家： | 
Infineon |
| 描述： | HYBRID - HIGH RELIABILITY 1 MEGA-RAD HARDENED DC/DC CONVERTER |
| 文件： | 总13页 (文件大小：128K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PD - 94530B
ARM28XXT SERIES
28V Input, Triple Output
HYBRID - HIGH RELIABILITY
1 MEGA-RAD HARDENED
DC/DC CONVERTER
Description
The ARM Series of three output DC/DC converters are
designed specifically for use in the high-dose radiation
environments encountered during deep space planetary
missions. The extremely high level of radiation tolerance
inherent in the ARM design is assured as a result of
extensive research, thorough analysis and testing,
careful selection of components and lot verification
testing of finished hybrids. Many of the best circuit
design features characterizing earlier International
Rectifier products have been incorporated into the ARM
topology. Capable of uniformly high performance
through long term exposures in radiation intense
environments, this series sets the standard for distributed
power systems demanding high performance and
reliability.
ARM
Features
n Total Dose > 1MRad (Si)
n SEE Hardened to LET up to 83 Mev.cm2/mg
n Derated per MIL-STD-975 & MIL-STD-1547
n Output Power Range 3 to 30 Watts
n 19 to 50 Volt Input Range
The ARM converters are hermetically sealed in a
rugged, low profile package utilizing copper core pins
to minimize resistive DC losses. Long-term hermeticity
is assured through use of parallel seam welded lid
attachment along with International Rectifier’s rugged
ceramic pin-to-package seal. Axial lead orientation
facilitates preferred bulkhead mounting to the principal
heat-dissipating surface.
n Input Undervoltage Lockout
n High Electrical Efficiency > 80%
n Full Performance from -55°C to +125°C
n Continuous Short Circuit Protection
n 12.8 W / in3 Output Power Density
n True Hermetic Package
n External Inhibit Port
n Externally Synchronizable
n Fault Tolerant Design
n 5V, ±12V or 5V, ±15V Outputs Available
Manufactured in a facility fully qualified to MIL-PRF-
38534, these converters are fabricated utilizing DSCC
qualified processes. For available screening options
refer to device screening table in the data sheet.
Variations in electrical, mechanical and screening
specifications may be accommodated. Contact IR Santa
Clara for special requirements.
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1
08/11/06
ARM28XXT Series
Specifications
Absolute Maximum Ratings
Recommended Operating Conditions
+19V to +60VDC
Input Voltage range
-0.5V to +80VDC
Input Voltage range
+19V to +50V for full derating to MIL-STD-975
3.0W to 30W
5% Maximum rated
current, any Output
300°C for 10 seconds
Minimum Output Current
Soldering temperature
Output Power
-55°C to +125°C
Operating case
temperature
-55°C to +85°C for full derating to MIL-STD-975
Storage case temperature -65°C to +135°C
Electrical Performance -55°C < TCASE < +125°C, VIN=28V, CL=0 unless otherwise specified.
Parameter
Symbol
Conditions
IOUT = 1.5Adc, TC = +25°C
Min
4.95
Max
5.05
Units
(main)
Output voltage accuracy
VOUT
Vdc
±11.50
±14.50
±12.50
±15.15
°
OUT = ±250mAdc, TC = +25 C ARM2812(dual)
IOUT = ±250mAdc, TC = +25°C ARM2815(dual)
I
Output power Note 5
Output current Note 5
POUT
IOUT
19 Vdc< VIN < 50Vdc
3.0
30
W
(main)
150
3000
19 Vdc< VIN < 50Vdc
mAdc
75
750
+15
(dual)
-15
150 mAdc < IOUT < 3000 mAdc
19 Vdc< VIN < 50Vdc
(main)
Line regulation Note 3
Load regulation Note 4
Cross regulation Note 8
Total regulation
VRLINE
VRLOAD
VRCROSS
VR
mV
mV
mV
V
-60
+60
±75 mAdc < IOUT < ±750 mAdc
(dual)
(main)
-180
+180
150 mAdc < IOUT < 3000 mAdc
19 Vdc< VIN < 50Vdc
-300
-10
+300
+10
±75 mAdc < IOUT < ±750 mAdc
(dual)
(main)
19 Vdc< VIN < 50Vdc
-500
4.8
+500
5.2
(dual)
(main)
All conditions of Line, Load,
Cross Regulation, Aging,
Temperature and Radiation ARM2812(dual)
ARM2815(dual)
±11.1
±13.9
±12.9
±16.0
IOUT = minimum rated, Pin 3 open
250
Input current
IIN
VRIP
IRIP
mA
Pin 3 shorted to pin 2 (disabled)
19 Vdc< VIN < 50Vdc
8.0
Output ripple voltage Note 6
Input ripple current Note 6
100
mVp.p
mAp.p
IOUT = 3000 mAdc (main), ±500 mAdc (dual)
19 Vdc< VIN < 50Vdc
150
275
IOUT = 3000 mAdc (main), ±500 mAdc (dual)
Switching frequency
Efficiency
FS
Sychronization input open. (pin 6)
225
80
KHz
%
Eff
IOUT = 3000 mAdc (main), ±500 mAdc (dual)
For Notes to Specifications, refer to page 3
2
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ARM28XXT Series
Electrical Performance (Continued)
Parameter
Enable Input
Symbol
Conditions
19 Vdc< VIN < 50Vdc
Min
Max
Units
open circuit voltage
drive current (sink)
voltage range
3.0
0.1
-0.5
5.0
V
mA
V
50.0
External clock signal on Sync. input (pin 4)
Synchronization Input
frequency range
pulse high level
pulse low level
225
4.5
-0.5
40
310
10.0
0.25
KHz
V
V
V/µs
%
pulse rise time
pulse duty cycle
20
80
7.5
200
Power dissipation, load fault
PD
Short circuit, any output
W
Output response to step load
changes Notes 7, 11
10% Load to/from 50% load
-200
-200
VTLD
mVPK
50% Load to/from 100% load
10% Load to/from 50% load
200
200
Recovery time from step load
µ
s
changes Notes 11, 12
TTLD
VTLN
TTLN
50% Load to/from 100% load
200
350
Output response to step line
changes Notes 10, 11
IOUT = 3000 mAdc
IN = 19 V to/from 50 V
IOUT = ±500 mAdc
(main)
-350
V
mVPK
(dual)
-1050
1050
500
Recovery time from step line
changes Notes 10, 11,13
IOUT = 3000 mAdc
(main)
VIN = 19 V to/from 50 V
OUT = ±500 mAdc
µs
I
(dual)
500
500
(main)
Turn on overshoot
Turn on delay Note 14
Capacitive load Notes 9, 10
Isolation
VOS
TDLY
CL
IOUT = minimum and full rated
IOUT = minimum and full rated
No effect on DC performance
mV
ms
µF
(dual)
1500
20
5.0
(main)
(dual)
500
100
ISO
500VDC Input to Output or any pin to case
(except pin 12)
100
MΩ
Notes to Specifications Table
1.
Operation outside absolute maximum/minimum limits may cause permanent damage to the device. Extended operation at the limits may permanently
degrade performance and affect reliability.
2.
Device performance specified in Electrical Performance table is guaranteed when operated within recommended limits. Operation outside
recommended limits is not specified.
3.
4.
5.
6.
7.
8.
9.
Parameter measured from 28V to 19 V or to 50V while loads remain fixed.
Parameter measured from nominal to minimum or maximum load conditions while line remains fixed.
Up to 750 mA is available from the dual outputs provided the total output power does not exceed 30W.
Guaranteed for a bandwidth of DC to 20MHz. Tested using a 20KHz to 2MHz bandwidth.
Load current is stepped for output under test while other outputs are fixed at half rated load.
Load current is fixed for output under test while other output loads are varied for any combination of minimum to maximum.
A capacitive load of any value from 0 to the specified maximum is permitted without comprise to DC performance. A capacitive load in excess of the
maximum limit may interfere with the proper operation of the converter’s short circuit protection, causing erratic behavior during turn on.
10. Parameter is tested as part of design characterization or after design or process changes. Thereafter, parameters shall be guaranteed to the limits
specified in the table.
≤ 2A/µs.
11. Load transient rate of change, di/dt
12. Recovery time is measured from the initiation of the transient to where VOUT has returned to within ±1% of its steady state value.
13. Line transient rate of change, dv/dt ≤ 50V/µs.
14. Turn on delay time is for either a step application of input power or a logical low to high transition on the enable pin (pin 3) while power is present at the
input.
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3
ARM28XXT Series
Group A Tests VIN= 28Volts, CL =0 unless otherwise specified.
Group A
Test
Symbol Conditions unless otherwise specified
Subgroups
Min
Max
Units
IOUT = 1.5 Adc
(main)
1, 2, 3
4.95
5.05
Output voltage accuracy
VOUT
V
I
I
OUT = ±250mAdc
OUT = ±250mAdc
ARM2812(dual)
ARM2815(dual)
1, 2, 3
1, 2, 3
±11.70
±14.50
±12.30
±15.15
Output power Note 1
POUT
IOUT
VIN = 19 V, 28V, 50 V
1, 2, 3
1, 2, 3
3.0
30
W
(main)
(dual)
150
3000
Output current
Note 1
VIN 19 V, 28V, 50 V
mA
1, 2, 3
1, 2, 3
75
500
5.2
IOUT = 150, 1500, 3000mAdc
VIN = 19 V, 28V, 50 V
(main)
4.8
Output regulation Note 4
VR
V
I
I
OUT = ±75, ±310, ±625mAdc 2812(dual)
OUT = ±75, ±250, ±500mAdc 2815(dual)
1, 2, 3
1, 2, 3
±11.1
±14.0
±12.9
±15.8
IOUT = minimum rated, Pin 3 open
1, 2, 3
250
Input current
IIN
VRIP
IRIP
mA
Pin 3 shorted to pin 2 (disabled)
VIN = 19 V, 28V, 50 V
1, 2, 3
1, 2, 3
8.0
Output ripple Note 2
Input ripple Note 2
100
mVP-P
mAP-P
I
OUT = 3000mA main, ±500mA dual
VIN = 19 V, 28V, 50 V
1, 2, 3
4, 5, 6
150
275
I
OUT = 3000mA main, ±500mA dual
Switching frequency
Efficiency
FS
Synchronization pin (pin 6) open
IOUT = 800mA main, ±500mA dual
225
KHz
%
Eff
1
2, 3
80
78
Power dissipation,
load fault
PD
VTL
TTL
VOS
Short circuit, any output
1, 2, 3
4, 5, 6
7.5
W
mVPK
µs
Output response to step
load changes Notes 3, 5
10% Load to/from 50% load
-200
-200
200
50% Load to/from 100% load
10% Load to/from 50% load
4, 5, 6
4, 5, 6
200
200
Recovery time from step
load changes Notes 5, 6
50% Load to/from 100% load
IOUT = minimum and full rated
IOUT = minimum and full rated
4, 5, 6
4, 5, 6
200
500
(main)
(dual)
Turn on overshoot
mV
4, 5, 6
4, 5, 6
1
1500
20
Turn on delay Note 7
TDLY
ISO
5.0
ms
Isolation
500VDC Input to output or any pin to case
(except pin 12)
100
MΩ
Notes to Group A Test Table
1. Parameter verified during dynamic load regulation tests
2. Guaranteed for DC to 20 MHz bandwidth. Test conducted using a 20KHz to 2MHz bandwidth.
3. Load current is stepped for output under test while other outputs are fixed at half rated load.
4. Each output is measured for all combinations of line and load. Only the minimum and maximum readings for each output are recorded.
5. Load step transition time ≥ 10µS.
6. Recovery time is measured from the initiation of the transient to where VOUT has returned to within ±1% of its steady state value.
7. Turn on delay time is tested by application of a logical low to high transition on the enable pin (pin 3) with power present at the input.
8. Subgroups 1 and 4 are performed at +25°C, subgroups 2 and 5 at -55°C and subgroups 3 and 6 at +125°C.
4
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ARM28XXT Series
Radiation Performance
radiation performance variations. Radiation tests on
random ART2800T manufacturing lots provide continued
confirmation of the soundness of the design goals as well
as justification for the element selection criteria.
The radiation tolerance characteristics inherent in the
ARM28XXT converter are based on the results of the
ground-up design effort on the ART2800T program and
started with specific radiation design goals. By imposing
sufficiently large margins on those electrical parameters
subject to the degrading effects of radiation, appropriate
elements were selected for incorporation into the
ART2800T circuit. Known radiation data was utilized for
input to PSPICE and RadSPICE in the generation of circuit
performance verification analyses. Thus, electrical
performance capability under all environmental conditions
including radiation was well understood before first
application of power to the inputs.
To achieve the radiation levels specified for the ARM28XXT,
the ART2800T topology is utilized as the basis but lot
assurance testing is utilized as part of the screening
process to assure the specified level. Each ARM28XXT
converter is delivered with lot test data at the hybrid level
supporting the minimum TID specification. Other radiation
specifications are assured by design and generic data are
available on request.
The principal ART2800T design goal was a converter
topology, which because of large design margins, had
radiation performance essentially independent of wafer-lot
The following table specifies guaranteed minimum radiation
exposure levels tolerated while maintaining specification limits.
Radiation Specification T
Test
= 25°C
case
Conditions
Min
Unit
Total Ionizing Dose
MIL-STD-883, Method 1019.4
Operating bias applied during exposure
1,000
KRads
(Si)
Dose Rate
MIL-STD-883, Method 1021
Temporary Saturation
1E8
Rads
Survival
1E11
(Si)/sec
Neutron Fluence
MIL-STD-883, Method 1017.2
3E12
83
Neutron
/cm²
Heavy Ions
BNL Tandem Van de Graaff Generator
MeV•
(Single event effects)
cm²/mg
International Rectifier currently does not have a DSCC certified Radiation Hardness Assurance Program.
Standard Quality Conformance Inspections on ARM28XXT Series (Flight Screened)
Inspection
Application
Samples
Group A
Group B
Group C
Part of Screening on Each Unit
Each Inspection Lot
100%
* 5 units
10 units
First Inspection Lot or
Following Class 1 Change
Group D
In Line (Part of Element Evaluation)
3 units
* Group B quantity for Option 2 End of Line QCI. No Group B samples reuired for Option 1, In-line.
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5
ARM28XXT Series
Figure I. Block Diagram
EMI
Filter
+15 Vout
Dual
1
11
10
+Input
Output
Return
Under-Voltage
Detector
-15 Vout
Dual
9
Primary Bias
& Reference
3
13
+5 Vdc
Output
Enable
Short
Circuit
Output
Return
14
Sample
Hold
Pulse Width
Modulator
4
Sync In
Input
Return
2
Operating Guidelines
Circuit Description and Application Information
The circuit topology used for regulating output voltages in
the ARM28XXT series of converters was selected for a
number of reasons. Significant among these is the ability
to simultaneously provide adequate regulation to three
output voltages while maintaining modest circuit complexity.
These attributes were fundamental in retaining the high
reliability and insensitivity to radiation that characterizes
device performance. Use of this topology dictates that the
user maintain the minimum load specified in the electrical
tables on each output. Attempts to operate the converter
without a load on any output will result in peak charging to
an output voltage well above the specified voltage regulation
limits, potentially in excess of ratings, and should be
avoided. Output loads that are less than specification
minimums will result in regulation performance outside the
limits presented in the tables. In most practical applications,
this lower bound on the load range does not present a
serious constraint; however the user should be mindfull of
the results. Characteristic curves illustrating typical
regulation performance are shown in Figures VII, VIII and IX.
The ARM28XXT series of converters have been designed
using a single ended forward switched mode converter
topology. (refer to Figure I.) Single ended topologies enjoy
some advantage in radiation hardened designs in that they
eliminate the possibility of simultaneous turn on of both
switching elements during a radiation induced upset; in
addition, single ended topologies are not subject to
transformer saturation problems often associated with
double ended implementations.
The design incorporates an LC input filter to attenuate
input ripple current. A low overhead linear bias regulator
is used to provide bias voltage for the converter primary
control logic and a stable, well regulated reference for the
error amplifier. Output control is realized using a wide band
discrete pulse width modulator control circuit incorporating
a unique non-linear ramp generator circuit. This circuit
helps stabilize loop gain over variations in line voltage for
superior output transient response. Nominal conversion
frequency has been selected as 250 KHz to maximize
efficiency and minimize magnetic element size.
Thermal Considerations
Output voltages are sensed using a coupled inductor and
a patented magnetic feedback circuit. This circuit is
relatively insensitive to variations in temperature, aging,
radiation and manufacturing tolerances making it
particularly well suited to radiation hardened designs. The
control logic has been designed to use only radiation
tolerant components, and all current paths are limited with
series resistance to limit photo currents.
The ARM series of converters is capable of providing
relatively high output power from a package of modest
volume. The power density exhibited by these devices is
obtained by combining high circuit efficiency with effective
methods of heat removal from the die junctions. Good
design practices have effectively addressed this
requirement inside the device. However when operating
at maximum loads, significant heat generated at the die
junctions must be carried away by conduction from the
base. To maintain case temperature at or below the
specified maximum of 125°C, this heat can be transferred
by attachment to an appropriate heat dissipater held in
intimate contact with the converter base-plate.
Other key circuit design features include short circuit
protection, undervoltage lockout and an external
synchronization port permitting operation at an externally
set clock rate.
6
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ARM28XXT Series
Thus, a total heat sink surface area (including fins, if any)
of approximately 32 in in this example, would limit case
Effectiveness of this heat transfer is dependent on the
intimacy of the baseplate-heatsink interface. It is therefore
suggested that a heat transferring medium possessing
good thermal conductivity is inserted between the
baseplate and heatsink. A material utilized at the factory
during testing and burn-in processes is sold under the
trade name of Sil-Pad 400 . This particular product is an
insulator but electrically conductive versions are also
available. Use of these materials assures optimum surface
contact with the heat dissipater by compensating for minor
surface variations. While other available types of heat
conducting materials and thermal compounds provide
similar effectiveness, these alternatives are often less
convenient and are frequently messy to use.
2
rise to 35°C above ambient. A flat aluminum plate, 0.25"
2
thick and of approximate dimension 4" by 4" (16 in per
side) would suffice for this application in a still air
environment. Note that to meet the criteria, both sides of
the plate require unrestricted exposure to the ambient air.
®
1
Inhibiting Converter Output
As an alternative to application and removal of the DC
voltage to the input, the user can control the converter
output by providing an input referenced, TTL compatible,
logic signal to the enable pin 3. This port is internally pulled
“high” so that when not used, an open connection on the
pin permits normal converter operation. When inhibited
outputs are desired, a logical “low” on this port will shut the
converter down. An open collector device capable of
sinking at least 100 µA connected to enable pin 3 will work
well in this application.
A conservative aid to estimating the total heat sink surface
area (A
) required to set the maximum case
HEAT SINK
temperature rise (∆T) above ambient temperature is given
by the following expression:
−1.43
A benefit of utilization of the enable input is that following
initial charge of the input capacitor, subsequent turn-on
commands will induce no uncontrolled current inrush.
∆T
⎧
⎨
⎩
⎫
⎬
⎭
A
HEAT SINK
≈
−5.94
80P0.85
where
Figure II. Enable Input Equivalent Circuit
∆T = Case temperature rise above ambient
Vin
⎧
⎨
⎩
⎫
1
5K
P = Device dissipation in Watts = POUT
−1
⎬
Eff
⎭
2N2907A
As an example, assume that it is desired to maintain the
case temperature of an ARM2815T at +65°C or less while
operating in an open area whose ambient temperature
does not exceed +35°C; then
64K
150K
150K
Enable
Input
5.6 V
2N2222A
2N2222A
186K
150K
∆T = 65 - 35 = 35°C
Input
Return
Converter inhibit is initiated when
this transistor is turned off
From the Specification Table, the worst case full load
efficiency for this device is 80%; therefore the maximum
power dissipation at full load is given by
1
⎧
⎨
⎩
⎫
⎭
P = 30•
−1 = 30• 0.25 = 7.5W
(
)
⎬
.80
and the required heat sink area is
−1.43
35
⎧
⎨
⎩
⎫
⎬
⎭
A
HEAT SINK
=
− 5.94 = 31.8 in2
80• 7.50.85
1
Sil-Pad is a registered Trade Mark of Bergquist, Minneapolis, MN
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7
ARM28XXT Series
Synchronization
Parallel Operation
When using multiple converters, system requirements may
dictate operating several converters at a common system
frequency. To accommodate this requirement, the
ARM28XXT type converter provides a synchronization
input port (pin 4). Circuit topology is as illustrated in Figure III.
Although no special provision for forced current sharing
has been incorporated in the ARM28XXT series, multiple
units may be operated in parallel for increased output power
applications. The 5 volt outputs will typically share to within
approximately 10% of their full load capability and the dual
(±15 volt) outputs will typically share to within 50% of their
full load. Load sharing is a function of the individual
impedance of each output and the converter with the highest
nominal set voltage will furnish the predominant load current.
The sync input port permits synchronization of an ARM
converter to any compatible external frequency source
operating in the band of 225 to 310 KHz. The synchronization
input is edge triggered with synchronization initiated on
the negative transition. This input signal should be a
negative going pulse referenced to the input return and
have a 20% to 80% duty cycle. Compatibility requires the
negative transition time to be less than 100 ns with a
minimum pulse amplitude of +4.25 volts referred to the
input return. In the event of failure of an external
synchronization source, the converter will revert to its
own internally set frequency. When external synchronization
is not desired, the sync in port may be left open
(unconnected) permitting the converter to operate at its’
own internally set frequency.
Input Undervoltage Protection
A minimum voltage is required at the input of the converter
to initiate operation. This voltage is set to a nominal value
of 16.8 volts. To preclude the possibility of noise or other
variations at the input falsely initiating and halting converter
operation, a hysteresis of approximately 1.0 volts is
incorporated in this circuit. The converter is guaranteed to
operate at 19 Volts input under all specified conditions.
Input Filter
To attenuate input ripple current, the ARM28XXT series
converters incorporate a single stage LC input filter. The
elements of this filter comprise the dominant input load
impedance characteristic, and therefore determine the
nature of the current inrush at turn-on. The input filter
circuit elements are as shown in Figure IV.
Figure III. Synchronization Input Equivalent Circuit
+10V
5K
Figure IV. Input Filter Circuit
Sync
Input
2N2907A
47pf
10 Ω
5K
+ Input
3.6 µH
Input
Return
5.4 µfd
Output Short Circuit Protection
Input
Return
Protection against accidental short circuits on any output
is provided in the ARM28XXT converters. This protection
is implemented by sensing primary switching current and,
when an over-current condition is detected, switching action
is terminated and a restart cycle is initiated. If the short
circuit condition has not been cleared by the time the restart
cycle has completed, another restart cycle is initiated. The
sequence will repeat until the short circuit condition is
cleared at which time the converter will resume normal
operation. The effect is that during a shorted condition, a
series of narrow pulses are generated at approximately
5% duty cycle which periodically sample the state of the
load. Thus device power dissipation is greatly reduced
during this mode of operation.
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ARM28XXT Series
Additional Filtering
It is important to be aware that when filtering high frequency
noise, parasitic circuit elements can easily dominate filter
performance. Therefore, it is incumbent onthe designer to
exercise care when preparing a circuit layout for such
devices. Wire runs and lengths should be minimized, high
frequency loops should be avoided and careful attention
paid to the construction details of magnetic circuit elements.
Tight magnetic coupling will improve overall magnetic
performance and reduce stray magnetic fields.
Although internal filtering is provided at both the input and
output terminals of the ARM2800 series, additional filtering
may be desirable in some applications to accommodate
more stringent system requirements.
While the internal input filter of Figure IV keeps input ripple
current below 100 mAp-p, an external filter is available that
will further attenuate this ripple content to a level below the
CE03 limits imposed by MIL-STD-461B. Figure V is a
general diagram of the Advanced Analog ARF461 filter
module designed to operate in conjunction with the
ARM2800 series converters to provide that attenuation.
Figure VI. External Output Filter
L1
+5 V
+5V Out
L3
C1
C2
C6
Figure V. ARF461 Input EMI Filter
5V
+5V
Return
Return
+15V
Out
L2
L4
+15V
C3
C7
C8
15V
Return
15V
Return
C4
C5
This circuit as shown in Figure V is constructed using the
same quality materials and processes as those employed
in the ARM2800 series converters and is intended for use
in the same environments. This filter is fabricated in a
complementary package style whose output pin configuration
allows pin to pin connection between the filter and the
converter. More complete information on this filter can be
-15V
Out
-15V
obtained from the ARF461 data sheet.
An external filter may also be added to the output where
circuit requirements dictate extremely low output ripple
noise. The output filter described by Figure VI has been
characterized with the ARM2815T using the values shown
in the associated material list.
Measurement techniques can impose a significant influence
on results. All noise measurements should be measured
with test leads as close to the device output pins and as
short as physically possible. Probe ground leads should
be kept to a minimum length.
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9
ARM28XXT Series
Performance Characteristics (Typical @ 25°C)
Figure VII. Efficiency vs Output Power
for Three Line Voltages.
85
80
75
70
65
60
55
50
18V
28V
50V
0
5
10
15
20
25
30
35
Output Power (Watts)
Figure VIII. 5 V Output Regulation Limits
Including all conditions of Line, Load and Cross Regulation.
5.2
5.1
5.0
4.9
4.8
4.7
Upper Limit
Lower Limit
0.0
0.5
1.0
1.5
2.0
2.5
3.0
Output Current (Amps)
10
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ARM28XXT Series
Performance Characteristics (Typical @ 25°C) (Continued)
Figure IX. ±15 V Regulation Curves
For Three conditions of Load on the 5 Volt Output.
17.0
16.0
15.0
14.0
5V Load = 3.0A
5V Load = 1.5A
5V Load = 150 mA
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
Output Current (Each Output)
Figure X. Cross Regulation Curves
5 Volt Output as a function of 15 Volt Load Current for Three 5 Volt Loads.
5.2
5.1
5.0
4.9
4.8
4.7
4.6
4.5
5V Load = 150mA
5V Load = 1.5A
5V Load = 3.0A
0
0.1
0.2
0.3
0.4
0.5
0.6
±15 Volt Load Current
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11
ARM28XXT Series
Mechanical Outline
Ø 0.136 - 6 Holes
0.040
Pin Dia.
6 x 0.200
= 1.200
1.675 2.200
1.950
0.375
0.263
0.138
0.300
1.400
0.150
2.400
2.700
0.275
0.240
3.25 Ref.
Max
Mounting
Plane
0.050
Flange
0.500
Max
Note:
1. Dimensions are in inches.
2. Base Plate Mounting Plane Flatness 0.003 maximum.
3. Unless otherwise specified, tolerances are
4. Device Weight - 120 grams maximum.
5. Materials:
Case: Cold rolled steel
Cover: Kovar
Pins: Copper cored Alloy 42 with ceramic insulators
∠
.XX
.XXX
= ± 2°
= ± .01
= ± .005
Pin Designation
Pin #
Designation
1
2
+ Input
Input Return
Enable
3
4
Sync In
5
NC
8
NC
9
-15Vdc Output
15Vdc Output return
+15Vdc Output
Chassis
10
11
12
13
14
+5Vdc Output
+5Vdc Output return
12
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ARM28XXT Series
Device Screening
Requirement
MIL-STD-883 Method
No Suffix
CK
EM
Temperature Range
Element Evaluation
Non-Destructive Bond Pull
Internal Visual
-55°C to +85°C
Class K
Yes
-55°C to +85°C
Class K
Yes
-55°C to +85°C
MIL-PRF-38534
2023
N/A
N/A
2017
Yes
Yes
Temperature Cycle
Constant Acceleration
PIND
1010
Cond C
Cond C
3000 Gs
Cond A
Cond C
3000 Gs
N/A
2001, Y1 Axis
2020
3000 Gs
Cond A
320 hrs @ 125°C
( 2 x 160 hrs )
-55°C, +25°C,
+85°C
320 hrs @ 125°C 48 hrs @ 125°C
( 2 x 160 hrs )
Burn-In
1015
Final Electrical
( Group A )
MIL-PRF-38534
& Specification
MIL-PRF-38534
1014
-55°C, +25°C,
+85°C
2%
-55°C, +25°C,
+85°C
PDA
2%
N/A
Seal, Fine and Gross
Radiographic
External Visual
Cond A, C
Yes
Cond A, C
Yes
Cond A
N/A
2012
2009
Yes
Yes
Notes:
Best commercial practice.
CK is DSCC class K compliant without radiation performance. No Suffix is a radiation rated device but
not available as a DSCC qualified SMD per MIL-PRF-38534.
International Rectifier currently does not have a DSCC certified Radiation Hardness Assurance Program.
Part Numbering
ARM 28 15 T /EM
Model
Screening Level
(Please refer to Screening Table)
Input Voltage
No Suffix, CK, EM
28 = 28V
Output
T = Triple
Output Voltage
15 = 5V, ± 15V
12 = 5V, ± 12V
WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, Tel: (310) 252-7105
IR SANTA CLARA: 2270 Martin Av., Santa Clara, California 95050, Tel: (408) 727-0500
Visit us at www.irf.com for sales contact information.
Data and specifications subject to change without notice. 08/2006
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13
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