ART2812T/EMPBF [INFINEON]
DC-DC Regulated Power Supply Module, 3 Output, 30W, Hybrid, HERMETIC SEALED PACKAGE-12;
| 型号： | ART2812T/EMPBF |
| 厂家： | 
Infineon |
| 描述： | DC-DC Regulated Power Supply Module, 3 Output, 30W, Hybrid, HERMETIC SEALED PACKAGE-12 输出元件 |
| 文件： | 总12页 (文件大小：213K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PD-94529B
ART28XXT SERIES
28V Input, Triple Output
HYBRID - HIGH RELIABILITY
RADIATION HARDENED
DC/DC CONVERTER
Description
The ART Series of three output DC/DC converters are
designed specifically for use in the hostile radiation
environments characteristic of space and weapon
systems. The extremely high level of radiation tolerance
inherent in the ART design is the culmination of
extensive research, thorough analysis and testing and
of careful component specification. Many of the best
circuit design features characterizing the International
Rectifier standard product line were adapted for
incorporation into the ART topology. Capable of
uniformly high performance over long term exposures
in radiation intense environments, this series sets the
standard for distributed power systems demanding high
performance and reliability.
ART
Features
n Total Dose > 100 krad (Si), 2:1margin
n No SEE to LET > 83 Mev.cm2 /mg
n Derated per MIL-STD-975 & MIL-STD-1547
n Output Power Range 3 to 30 Watts
n 19 to 50 Volt Input Range
The ART converters are hermetically sealed in a
rugged, low profile package utilizing copper core pins
to minimize resistive DC losses. Long-term hermeticity
is assured through use of parallel seam welded lid
attachment along with International Rectifier’s rugged
ceramic pin-to-package seal. Axial orientation of the
leads facilitates preferred bulkhead mounting to the
principal heat-dissipating surface.
n Input Undervoltage Lockout
n High Electrical Efficiency > 83%
n Full Performance from -55°C to +125°C
n Continuous Short Circuit and Overload
Protection
n 12.8 W/in3 Output Power Density
n True Hermetic Package
n External Inhibit Port
n Externally Synchronizable
n Fault Tolerant Design
Manufactured in a facility fully qualified to MIL-PRF-38534,
class K, these converters are fabricated utilizing DSCC
qualified processes and are fully compliant to Class K.
The complete suite of PI tests has been completed
including Group C life test. Variations in electrical,
mechanical and screening specifications can be
accommodated. Contact IR Santa Clara for special
requirements.
n 5V, ±12V or ±15 V Outputs Available
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1
08/12/04
ART28XXT Series
SPECIFICATIONS
Absolute Maximum/Minimum Ratings Note1 Recommended Operating Conditions Note 2
Input Voltage
-0.5V to 80V
Input Voltage Range
19V to 60V
Minimum Output Current
5% maximum rated
current, any output
300°C for 10 seconds
-65°C to +135°C
19V to 50V for full derating
to MIL-STD-975
3W to 30 W
Soldering Temperature
Storage Temperature
Output Power Range
Operating Temperature -55°C to +125°C
-55°C to +85°C for full
derating to MIL-STD-975
Electrical Performance -55°C < TCASE < +125°C, VIN=28V, CL=0 unless otherwise specified.
Parameter
Symbol
Conditions
IOUT = 1.5Adc, TC = +25 C
Min
4.95
Max
Units
5.05
(main)
°
Output voltage accuracy
VOUT
Vdc
±11.50
±14.50
±12.50
±15.15
IOUT = ±250mAdc, T = +25 C ART2812(dual)
°
C
IOUT = ±250mAdc, T = +25 C ART2815(dual)
°
C
Output power Note 5
Output current Note 5
POUT
IOUT
19 Vdc< VIN < 50Vdc
3.0
30
W
(main)
150
3000
19 Vdc< VIN < 50Vdc
(dual)
mAdc
75
750
+15
-15
150 mAdc < IOUT < 3000 mAdc
19 Vdc< VIN < 50Vdc
(main)
Line regulation
VRLINE
mV
mV
Note 3
-60
+60
±75 mAdc < IOUT < ±750 mAdc
(dual)
-180
+180
150 mAdc < IOUT < 3000 mAdc
19 Vdc< VIN < 50Vdc
(main)
Load regulation Note 4
VRLOAD
-300
-10
+300
+10
±75 mAdc < IOUT < ±750 mAdc
(dual)
(main)
Cross regulation Note 8
VRCROSS
mV
V
19 Vdc< VIN < 50Vdc
-500
4.8
+500
5.2
(dual)
All conditions of Line, Load,
Cross Regulation, Aging,
(main)
Total regulation
VR
Temperature and Radiation ART2812(dual)
ART2815(dual)
±11.1
±13.9
±12.9
±16.0
IOUT = minimum rated, Pin 3 open
250
Input current
IIN
mA
Pin 3 shorted to pin 2 (disabled)
19 Vdc< VIN < 50Vdc
8.0
70
Output ripple voltage Note 6
Input ripple current Note 6
VRIP
IRIP
mVp.p
mAp.p
IOUT = 3000 mAdc (main), ±500 mAdc (dual)
19 Vdc< VIN < 50Vdc
100
275
IOUT = 3000 mAdc (main), ±500 mAdc (dual)
Switching frequency
Efficiency
FS
Sychronization input open. (pin 6)
225
83
kHz
%
Eff
IOUT = 3000 mAdc (main), ±500 mAdc (dual)
For Notes to SPECIFICATIONS, refer to page 3
2
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ART28XXT Series
Electrical Performance (Continued)
Parameter
Enable Input
Symbol
Conditions
MIN
MAX
Units
open circuit voltage
drive current (sink)
voltage range
3.0
0.1
-0.5
5.0
V
mA
V
50.0
Synchronization Input
frequency range
pulse high level
pulse low level
External clock signal on Sync. input (pin 4)
225
4.5
-0.5
40
310
10.0
0.25
Khz
V
V
V/µS
%
pulse rise time
pulse duty cycle
20
80
Synchronization Output
pulse high level
Signal compatible with synchronization input
Short circuit, any output
3.7
0.0
4.3
0.25
V
pulse low level
Power dissipation, load fault
PD
16
W
Output response to step load
changes Notes 7, 11
10% Load to/from 50% load
50% Load to/from 100% load
-200
-200
200
200
VTLD
TTLD
VTLN
mVPK
µS
Recovery time from step load
changes Notes 11, 12
10% Load to/from 50% load
50% Load to/from 100% load
200
200
Output response to step line
changes Notes 10, 11
I
OUT = 3000 mAdc
(main)
-350
350
VIN = 19 V to/from 50 V
IOUT = ±500 mAdc
mVPK
(dual)
-1050
1050
500
Recovery time from step line
IOUT = 3000 mAdc
(main)
changes Notes 10, 11,13
TTLN
V
IN = 19 V to/from 50 V
µS
IOUT = ±500 mAdc
(dual)
500
Turn on overshoot
(main)
(dual)
100
500
VOS
IOUT = minimum and full rated
IOUT = minimum and full rated
mV
mS
Turn on delay Note 14
TDLY
5.0
20
(main)
(dual)
500
100
Capacitive load Notes 9, 10
CL
No effect on DC performance
µF
Isolation
ISO
500VDC Input to Output or any pin to case
(except pin 12)
100
MΩ
Notes to SPECIFICATIONS
1.
Operation outside absolute maximum/minimum limits may cause permanent damage to the device. Extended operation at the limits may permanently
degrade performance and affect reliability.
2.
Device performance specified in Electrical Performance table is guaranteed when operated within recommended limits. Operation outside
recommended limits is not specified.
3.
4.
5.
6.
7.
8.
9.
Parameter measured from 28V to 19 V or to 50V while loads remain fixed.
Parameter measured from nominal to minimum or maximum load conditions while line remains fixed.
Up to 750 mA is available from the dual outputs provided the total output power does not exceed 30W.
Guaranteed for a bandwidth of DC to 20MHz. Tested using a 20KHz to 2MHz bandwidth.
Load current is stepped for output under test while other outputs are fixed at half rated load.
Load current is fixed for output under test while other output loads are varied for any combination of minimum to maximum.
A capacitive load of any value from 0 to the specified maximum is permitted without comprise to DC performance. A capacitive load in excess of the
maximum limit may interfere with the proper operation of the converter’s short circuit protection, causing erratic behavior during turn on.
10. Parameter is tested as part of design characterization or after design or process changes. Thereafter, parameters shall be guaranteed to the limits
specified in the table.
≤
11. Load transient rate of change, di/dt 2 A/µSec.
12. Recovery time is measured from the initiation of the transient to where VOUT has returned to within ±1% of its steady state value.
13. Line transient rate of change, dv/dt ≤ 50 V/µSec.
14. Turn on delay time is for either a step application of input power or a logical low to high transition on the enable pin (pin 3) while power is present at the
input.
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3
ART28XXT Series
Group A Tests VIN= 28Volts, CL =0 unless otherwise specified.
Group A
Subgroups
MIN
MAX
Units
Test
Symbol
Conditions unless otherwise specified
IOUT = 1.5 Adc
(main)
1, 2, 3
4.95
5.05
Output voltage accuracy
VOUT
V
IOUT = ±250mAdc
IOUT = ±250mAdc
ART2812(dual)
ART2815(dual)
1, 2, 3
1, 2, 3
±11.70
±14.50
±12.30
±15.15
Output power Note 1
POUT
IOUT
VIN = 19 V, 28V, 50 V
1, 2, 3
1, 2, 3
3.0
30
W
(main)
(dual)
150
3000
Output current
Note 1
VIN 19 V, 28V, 50 V
mA
1, 2, 3
1, 2, 3
75
500
5.2
IOUT = 150, 1500, 3000mAdc
VIN = 19 V, 28V, 50 V
(main)
4.8
Output regulation Note 4
VR
V
IOUT = ±75, ±310, ±625mAdc
IOUT = ±75, ±250, ±500mAdc
2812(dual)
2815(dual)
1, 2, 3
1, 2, 3
±11.1
±14.0
±12.9
±15.8
IOUT = minimum rated, Pin 3 open
Pin 3 shorted to pin 2 (disabled)
1, 2, 3
250
Input current
IIN
mA
1, 2, 3
1, 2, 3
8.0
70
Output ripple Note 2
Input ripple Note 2
VRIP
IRIP
VIN = 19 V, 28V, 50 V
IOUT = 3000mA main, ±500mA dual
mVP-P
mAP-P
VIN = 19 V, 28V, 50 V
IOUT = 3000mA main, ±500mA dual
1, 2, 3
4, 5, 6
100
275
Switching frequency
Efficiency
FS
Synchronization pin (pin 6) open
IOUT = 3000mA main, ±500mA dual
225
KHz
%
Eff
1
2, 3
83
81
Power dissipation,
load fault
PD
VTL
TTL
VOS
Short circuit, any output
1, 2, 3
16
W
mVPK
µS
Output response to step
load changes Notes 3, 5
10% Load to/from 50% load
4, 5, 6
-200
-200
200
50% Load to/from 100% load
10% Load to/from 50% load
4, 5, 6
4, 5, 6
200
200
Recovery time from step
load changes Notes 5, 6
50% Load to/from 100% load
IOUT = minimum and full rated
IOUT = minimum and full rated
4, 5, 6
4, 5, 6
200
100
(main)
(dual)
Turn on overshoot
mV
4, 5, 6
4, 5, 6
1
500
20
Turn on delay Note 7
TDLY
ISO
5.0
mS
Isolation
500VDC Input to output or any pin to case
(except pin 12)
100
MΩ
Notes to Group A Test Table
1.
2.
3.
4.
5.
6.
7.
8.
Parameter verified during dynamic load regulation tests.
Guaranteed for DC to 20 MHz bandwidth. Test conducted using a 20KHz to 2MHz bandwidth.
Load current is stepped for output under test while other outputs are fixed at half rated load.
Each output is measured for all combinations of line and load. Only the minimum and maximum readings for each output are recorded.
Load step transition time ≥ 10µS.
Recovery time is measured from the initiation of the transient to where VOUT has returned to within ±1% of its steady state value.
Turn on delay time is tested by application of a logical low to high transition on the enable pin (pin 3) with power present at the input.
Subgroups 1 and 4 are performed at +25ºC, subgroups 2 and 5 at -55ºC and subgroups 3 and 6 at +125ºC.
4
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ART28XXT Series
Radiation Performance
The radiation tolerance characteristics inherent in the
ART28XXT converter are the direct result of a carefully
planned ground-up design program with specific radiation
design goals. After identification of the general circuit
topology, a primary task of the design effort was selection
of appropriate elements from the list of devices for which
extensive radiation effects data was available. By imposing
sufficiently large margins on those electrical parameters
subject to the degrading effects of radiation, designers
were able to select appropriate elements for incorporation
into the circuit. Known radiation data was utilized for input
to PSPICE and RadSPICE in the generation of circuit
performance verification analyses. Thus, electrical
performance capability under all environmental conditions
including radiation was well understood before first
application of power to the inputs.
performance variations. In the few instances where such
margins were not assured, element lots were selected
from which die were fabricated (and characterized) as
radiation hard devices so that realization of the design
goals could be assured.
Completion of first article fabrication, screening and
standard environmental testing was followed by radiation
testing to confirm design goals. All design goals were met
handily and in most cases exceeded by large margin.
These test samples were built with elements that, with the
foregoing exceptions, were not screened for radiation
characteristics. Additional radiation tests on subsequent
ART28XXT manufacturing lots provide continued
confirmation of the soundness of the design goals as well
as justification for the element selection criteria.
The following table specifies guaranteed minimum radiation
exposure levels tolerated while maintaining specification
limits.
A principal design goal was a converter topology that,
because of large design margins, had radiation performance
essentially independent of normal elemental lot radiation
Radiation Specification T
Test
= 25°C
case
Conditions
Min
Unit
Total Ionizing Dose
(2:1 Margin)
MIL-STD-883, Method 1019.4
Operating bias applied during exposure
200
krad
(Si)
Dose Rate
MIL-STD-883, Method 1021
Temporary Saturation
Survival
1E8
1E11
Rads
(Si)/sec
Heavy Ions
BNL Dual Van de Graf Generator
83
MeV•
cm²/mg
(Single event effects)
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5
ART28XXT Series
ART28XXT Circuit Description
Figure I. ART Block Diagram
EMI
Filter
+15
+Input
Under-Voltage
Detector
Return
-15
+5
Primary Bias
& Reference
Enable
Sync In
Short
Circuit
Return
Sample
Hold
Pulse Width
Modulator
Sync Out
Input
Return
Circuit Description and Application Information
Operating Guidelines
The ART28XXT series of converters have been designed
using a single ended forward switched mode converter
topology. (refer to Figure I.) Single ended topologies enjoy
some advantage in radiation hardened designs in that they
eliminate the possibility of simultaneous turn on of both
switching elements during a radiation induced upset; in
addition, single ended topologies are not subject to
transformer saturation problems often associated with
double ended implementations.
The circuit topology used for regulating output voltages in
the ART28XXT series of converters was selected for a
number of reasons. Significant among these is the ability
to simultaneously provide adequate regulation to three
output voltages while maintaining modest circuit complexity.
These attributes were fundamental in retaining the high
reliability and insensitivity to radiation that characterizes
device performance. Use of this topology dictates
maintaining the minimum load specified in the electrical
tables on each output. Operating the converter without a
load on any output will result in peak charging to an output
voltage well above the specified voltage regulation limits,
potentially in excess of ratings, and should be avoided.
Output load currents less than specification minimums will
result in regulation performance that exceeds the limits
presented in the tables. In most practical applications, this
lower bound on the load range does not present a serious
constraint; however the user should be mindfull of device
performance when operated outside specified limits.
The design incorporates a two-stage LC input filter to
attenuate input ripple current. A low overhead linear bias
regulator is used to provide bias voltage for the converter
primary control logic and a stable, well regulated reference
for the error amplifier. Output control is realized using a
wide band discrete pulse width modulator control circuit
incorporating a unique non-linear ramp generator circuit.
This circuit helps stabilize loop gain over variations in line
voltage for superior output transient response. Nominal
conversion frequency has been selected as 250 KHz to
maximize efficiency and minimize magnetic element size.
Thermal Considerations
Output voltages are sensed using a coupled inductor and
a patented magnetic feedback circuit. This circuit is
relatively insensitive to variations in temperature, aging,
radiation and manufacturing tolerances making it
particularly well suited to radiation hardened designs. The
control logic has been designed to use only radiation
tolerant components, and all current paths are limited with
series resistance to limit photo currents.
The ART series of converters is capable of providing
relatively high output power from a package of modest
volume. The power density exhibited by these devices is
obtained by combining high circuit efficiency with effective
methods of heat removal from the die junctions. Good
design practices have effectively addressed this
requirement inside the device. However when operating
at maximum loads, significant heat generated at the die
junctions must be carried away by conduction from the
base. To maintain case temperature at or below the
specified maximum of 125°C, this heat can be transferred
by attachment to an appropriate heat dissipater held in
intimate contact with the converter base-plate.
Other key circuit design features include short circuit
protection, undervoltage lockout and an external
synchronization port permitting operation at an externally
set clock rate.
6
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ART28XXT Series
Thus, a total heat sink surface area (including fins, if any)
of approximately 32 in in this example, would limit case
Effectiveness of this heat transfer is dependent on the
intimacy of the baseplate-heatsink interface. It is therefore
suggested that a heat transferring medium possessing
good thermal conductivity is inserted between the
baseplate and heatsink. A material utilized at the factory
during testing and burn-in processes is sold under the
trade name of Sil-Pad 400 . This particular product is an
insulator but electrically conductive versions are also
available. Use of these materials assures optimum surface
contact with the heat dissipater by compensating for minor
surface variations. While other available types of heat
conducting materials and thermal compounds provide
similar effectiveness, these alternatives are often less
convenient and are frequently messy to use.
2
rise to 35°C above ambient. A flat aluminum plate, 0.25"
2
thick and of approximate dimension 4" by 4" (16 in per
side) would suffice for this application in a still air
environment. Note that to meet the criteria, both sides of
the plate require unrestricted exposure to the ambient air.
®
1
Inhibiting Converter Output
As an alternative to application and removal of the DC
voltage to the input, the user can control the converter
output by providing an input referenced, TTL compatible,
logic signal to the enable pin 3. This port is internally pulled
“high” so that when not used, an open connection on the
pin permits normal converter operation. When inhibited
outputs are desired, a logical “low” on this port will shut the
converter down. An open collector device capable of
sinking at least 100 µA connected to enable pin 3 will work
well in this application.
A conservative aid to estimating the total heat sink surface
area (A
) required to set the maximum case
HEAT SINK
temperature rise (∆T) above ambient temperature is given
by the following expression:
−1.43
∆T
⎧
⎨
⎩
⎫
⎬
⎭
A benefit of utilization of the enable input is that following
initial charge of the input capacitor, subsequent turn-on
commands will induce no uncontrolled current inrush.
A
HEAT SINK
≈
−5.94
80P0.85
where
Figure II. Enable Input Equivalent Circuit
∆T = Case temperature rise above ambient
Vin
⎧
⎨
⎩
⎫
1
P = Device dissipation in Watts = POUT
−1
⎬
118K
Eff
⎭
As an example, assume that it is desired to maintain the
case temperature of an ART2815T at +65°C or less while
operating in an open area whose ambient temperature
does not exceed +35°C; then
2N2907A
64K
150K
Enable
Input
5.6 V
CR2
2N2222A
186K
150K
65K
2N2222A
∆T = 65 - 35 = 35°C
150K
Input
Return
From the Specification Table, the worst case full load
efficiency for this device is 80%; therefore the maximum
power dissipation at full load is given by
Converter inhibit is initiated when
this transistor is turned off
1
⎧
⎨
⎩
⎫
⎭
P = 30•
−1 = 30• 0.25 = 7.5W
(
)
⎬
.80
and the required heat sink area is
−1.43
35
⎧
⎨
⎩
⎫
⎬
⎭
A
HEAT SINK
=
− 5.94 = 31.8 in2
80• 7.50.85
1
Sil-Pad is a registered Trade Mark of Bergquist, Minneapolis, MN
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7
ART28XXT Series
Synchronization
Output Load Fault Protection
An additional feature is a synchronization output (pin 5)
permitting multiple Protection against overload or short
circuit on any output is provided in the ART28XXT converter
series. This protection is implemented by sensing primary
switching current and, when a load fault condition is
detected, pulse width is limited by the protection circuitry.
The converter is able to operate continuously with a load
fault witout damage or exceeding derating limits.
Systems using multiple convertors may dictate operating
the group at a common switching frequency. To
accomodate this requirement, the ART28XXT converters
include a synchronization input (pin 4). Topology is
illustrated in Figure III.
An additional feature is a synchronization output (pin 5)
permitting multiple ART28XX converters in a system to be
synchronized to one of the converters in the set. See
Figure IV.
Parallel Operation
Figure III. Synchronization Input Equivalent Circuit
Although no special provision for forced current sharing
has been incorporated in the ART28XXT series, multiple
units may be operated in parallel for increased output power
applications. The 5.0 volt outputs will typically share to
within approximately 10% of their full load capability and
the dual (±15 volt) outputs will typically share to within
50% of their full load. Load sharing is a function of the
individual impedance of each output and the converter
with the highest nominal set voltage will furnish the
predominant load current.
+10V
5K
Sync
Input
2N2907A
47pf
10K
Input Undervoltage Protection
Input
Return
A minimum voltage is required at the input of the converter
to initiate operation. This voltage is set to a nominal value
of 16.8 volts. To preclude the possibility of noise or other
variations at the input falsely initiating and halting converter
operation, a hysteresis of approximately 1.0 volts is
incorporated in this circuit. The converter is guaranteed to
operate at 19 Volts input under all specified conditions.
Figure IV. Synchronization Output Equivalent Circuit
+10V
To Internal
Clock
6K
10pf
10K
Sync
Output
5
Input Filter
To attenuate input ripple current, the ART28XXT series
converters incorporate a two-stage LC input filter. The
elements of this filter comprise the dominant input load
impedance characteristic, and therefore determine the
nature of the current inrush at turn-on. The input filter
4K
2N2222
Input
Return
2
circuit elements are as shown in Figure V.
The sync input port permits synchronization of an ART
converter to any compatible external frequency source
operating in the band of 225 to 310 KHz. The synchronization
input is edge triggered with synchronization initiated on
the negative transition. This input signal should be a
negative going pulse referenced to the input return and
have a 20% to 80% duty cycle. Compatibility requires the
negative transition time to be less than 100 ns with minimum
pulse amplitude of +4.25 volts referred to the input return.
In the absence of an external source, the converter will
revert to its own internally set frequency. If external
synchronization is not desired, the sync in pin may be left
open (unconnected) permitting the converter to operate at
Figure V. Input Filter Circuit
4.7 µH
1.35Ω
Pin 1
Pin 2
34 µH
5.4 µfd
its’ own internally set frequency.
8
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ART28XXT Series
Additional Filtering
It is important to be aware that when filtering high frequency
noise, parasitic circuit elements can easily dominate filter
performance. Therefore, it is incumbent on the designer to
exercise care when preparing a circuit layout for such
devices. Wire runs and lengths should be minimized, high
frequency loops should be avoided and careful attention
paid to the construction details of magnetic circuit elements.
Tight magnetic coupling will improve overall magnetic
performance and reduce stray magnetic fields.
Although internal filtering is provided at both the input and
output terminals of the ART28XX series, additional filtering
may be desirable in some applications to accommodate
more stringent system requirements.
While the internal input filter of Figure V keeps input ripple
current below 100 mAp-p, an external filter may be applied
to further attenuate this ripple to a level below the CE03
limits imposed by MIL-STD-461B. Figure VI is a general
diagram of the International Rectifier filter module designed
to operate in conjunction with the ART28XX series
Figure VII. External Output Filter
converters to provide that attenuation.
L1
+5 V
+5V Out
L3
C1
C2
Figure VI. External Input EMI Filter
C6
5V
+5V
Return
Return
+15V
Out
L2
L4
+15V
C3
C7
C8
15V
Return
15V
Return
This circuit as shown in Figure VI is constructed using the
same quality materials and processes as those employed
in the ART28XX series converters and is intended for use
in the same environments. This filter is fabricated in a
complementary package style whose output pin configuration
allows pin to pin connection between the filter and the
converter. More complete information on this filter can be
obtained from the ARF461 data sheet.
C4
C5
-15V
Out
-15V
An external filter may also be added to the output where
circuit requirements dictate extremely low output ripple
noise. The output filter described by Figure VII has been
characterized with the ART2815T using the values shown
in the associated material list.
Measurement techniques can impose a significant influ-
ence on results. All noise measurements should be mea-
sured with test leads as close to the device output pins as
physically possible. Probe ground leads should be kept to
a minimum length.
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9
ART28XXT Series
Performance Characteristics (Typical @ 25°C)
Figure VIII. Efficiency vs Output Power
for Three Line Voltages.
Figure IX. 5.0 V Output Regulation Limits
0.3 A load on ±15 V outputs
5.20
5.10
5.00
4.90
4.80
0.0
0.5
1.0
1.5
2.0
2.5
3.0
5V Load Current, Amps
10
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ART28XXT Series
ART28XXT Case Outline
Ø 0.136 - 6 Holes
0.040
Pin Dia.
6 x 0.200
= 1.200
1.675 2.200
1.950
0.375
0.263
0.138
0.300
1.400
0.150
2.400
2.700
0.275
0.240
3.25 Ref.
Max
Mounting
Plane
0.050
Flange
0.500
Max
Note:
1. Dimensions are in inches.
2. Base Plate Mounting Plane Flatness 0.003 maximum.
3. Unless otherwise specified, tolerances are
∠
.XX
.XXX
= ± 2°
= ± .01
= ± .005
4. Device Weight - 120 grams maximum.
Part Numbering
Pin Designation
ART 28 15 T / EM
Pin #
1
2
Designation
+ V input
Input return
Model
Screening Level
No Suffix = Flight
/EM = Engineering
3
4
5
8
Enable
Sync In
Sync Out
Input Voltage
28 = 28V
100 = 100V
Outputs
T = Triple
No connection
- 15 Vdc output
15 Vdc output return
+ 15 Vdc output
Chassis
Output Voltages
9
15 = 5V, ± 15V
12 = 5V, ± 12V
10
11
12
13
14
Note:
+ 5 Vdc output
5 Vdc output return
Radiation performance not specified for /EM screened device type.
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11
ART28XXT Series
Standard Process Screening for ART28XXT Series
MIL-STD-883
Method
/EM Limits
No Suffix Limits
(Class K)
Requirement
Temperature Range
Element Evaluation
Non-destructive Bond Pull
Internal Visual
-55°C to +125°C
-55°C to +125°C
MIL-PRF-38534
100%
N/A
N/A
2023
2017
1010
2001,
2020
1015
Temperature Cycle
Constant Acceleration
PIND
Cond C
Cond A
Cond A
500 g
N/A
Burn-in
160 hrs @ 125°C
320 hrs @ 125°C
(2 × 160 hrs)
Interim Electrical @ 160 hrs
Final Electrical (Group A)
Read & Record Data
MIL-PRF-38534
& Specification
-55, +25, +125°C
-55, +25, +125°C
PDA (25°C, interim to final)
Radiographic Inspection
Seal, Fine & Gross
N/A
N/A
2%
2012
1014
2009
Cond A, C
External Visual
Standard Periodic Inspections on ART28XXT Series
As prescribed by MIL-PRF-38534 for Option 2
Inspection
Application
Quantity
Group A
Group B
Group C
Part of Screening on Each Unit
Each Inspection Lot
100%
5 units
First Inspection Lot or
10 Units
Following Class 1 Change
Group D
In Line (Part of Element Evaluation)
WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, Tel: (310) 252-7105
IR SANTA CLARA: 2270 Martin Av., Santa Clara, California 95050, Tel: (408) 727-0500
Visit us at www.irf.com for sales contact information.
Data and specifications subject to change without notice. 08/2004
12
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