AUIRLS3114ZTRR [INFINEON]

Power Field-Effect Transistor, N-Channel, Metal-oxide Semiconductor FET;
AUIRLS3114ZTRR
型号: AUIRLS3114ZTRR
厂家: Infineon    Infineon
描述:

Power Field-Effect Transistor, N-Channel, Metal-oxide Semiconductor FET

文件: 总13页 (文件大小:240K)
中文:  中文翻译
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AUTOMOTIVE GRADE  
AUIRLS3114Z  
HEXFET® Power MOSFET  
Features  
l
l
l
l
l
l
l
l
l
Advanced Process Technology  
VDSS  
RDS(on) typ.  
max.  
40V  
D
Ultra Low On-Resistance  
Logic Level Gate Drive  
EnhanceddV/dTanddI/dTcapability  
175°COperatingTemperature  
Fast Switching  
Repetitive Avalanche Allowed up to Tjmax  
Lead-Free,RoHSCompliant  
AutomotiveQualified*  
3.8m  
4.9m  
122A  
Ω
Ω
G
ID  
(Silicon Limited)  
S
ID  
56A  
(Wirebond Limited)  
Description  
Specifically designed for Automotive applications, this HEXFET®  
PowerMOSFETutilizesthelatestprocessingtechniquestoachieve  
extremelylowon-resistancepersiliconarea. Additionalfeaturesof  
thisdesign area175°Cjunctionoperatingtemperature,fastswitch-  
ingspeedandimprovedrepetitiveavalancherating.Thesefeatures  
combine to make this design an extremely efficient and reliable  
deviceforuseinAutomotiveapplicationsandawidevarietyofother  
applications.  
S
D
G
D2Pak  
AUIRLS3114Z  
G
Gate  
D
S
Drain  
Source  
Standard Pack  
Form  
Base Part Number  
Package Type  
Orderable Part Number  
Quantity  
Tube  
50  
800  
800  
AUIRLS3114Z  
AUIRLS3114ZTRL  
AUIRLS3114ZTRR  
AUIRLS3114Z  
D2-Pak  
Tape and Reel Left  
Tape and Reel Right  
AbsoluteMaximumRatings  
StressesbeyondthoselistedunderAbsoluteMaximumRatingsmaycausepermanentdamagetothedevice. Thesearestressratingsonly;andfunctional  
operation of the device at these or any other condition beyond those indicated in the specifications is not implied. Exposure to absolute-maximum-rated  
conditionsforextendedperiodsmayaffectdevicereliability.Thethermalresistanceandpowerdissipationratingsaremeasuredunderboardmountedand  
still air conditions. Ambient temperature (TA) is 25°C, unless otherwise specified.  
Parameter  
Max.  
122  
86  
Units  
ID @ TC = 25°C  
Continuous Drain Current, VGS @ 10V (Silicon Limited)  
ID @ TC = 100°C Continuous Drain Current, VGS @ 10V (Silicon Limited)  
A
ID @ TC = 25°C  
IDM  
Continuous Drain Current, VGS @ 10V (Wirebond Limited)  
Pulsed Drain Current  
56  
488  
143  
0.95  
± 20  
168  
518  
PD @TC = 25°C  
W
Maximum Power Dissipation  
Linear Derating Factor  
W/°C  
V
VGS  
Gate-to-Source Voltage  
EAS (Thermally Limited)  
Single Pulse Avalanche Energy  
Single Pulse Avalanche Energy  
Avalanche Current  
mJ  
EAS (Tested)  
IAR  
A
See Fig. 12a, 12b, 15, 16  
EAR  
mJ  
Repetitive Avalanche Energy  
Peak Diode Recovery  
2.3  
dv/dt  
TJ  
V/ns  
-55 to + 175  
Operating Junction and  
TSTG  
°C  
Storage Temperature Range  
Soldering Temperature, for 10 seconds (1.6mm from case)  
300  
Thermal Resistance  
Parameter  
Typ.  
–––  
Max.  
1.05  
40  
Units  
Rθ  
Junction-to-Case  
JC  
°C/W  
Rθ  
–––  
Junction-to-Ambient (PCB Mount)  
JA  
HEXFET® is a registered trademark of International Rectifier.  
*Qualification standards can be found at http://www.irf.com/  
1
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March 03, 2014  
AUIRLS3114Z  
Static Electrical Characteristics @ TJ = 25°C (unless otherwise specified)  
Parameter  
Drain-to-Source Breakdown Voltage  
Breakdown Voltage Temp. Coefficient  
Static Drain-to-Source On-Resistance  
Gate Threshold Voltage  
Min. Typ. Max. Units  
Conditions  
VGS = 0V, ID = 250μA  
V(BR)DSS  
ΔV(BR)DSS/ΔTJ  
RDS(on)  
40  
–––  
0.03  
3.8  
–––  
–––  
4.9  
V
–––  
–––  
1
V/°C Reference to 25°C, ID = 1mA  
VGS = 10V, ID = 56A  
VDS = VGS, ID = 100μA  
VDS = 10V, ID = 56A  
Ω
m
VGS(th)  
1.7  
2.5  
V
Δ
VGS(th)  
Gate Threshold Voltage Coefficient  
Forward Transconductance  
–––  
103  
–––  
–––  
–––  
–––  
–––  
-6.6  
–––  
0.8  
––– mV/°C  
gfs  
RG  
–––  
–––  
20  
S
Ω
Internal Gate Resistance  
IDSS  
Drain-to-Source Leakage Current  
–––  
–––  
–––  
–––  
VDS = 40V, VGS = 0V  
VDS = 40V, VGS = 0V, TJ = 125°C  
VGS = 16V  
μA  
250  
100  
-100  
IGSS  
Gate-to-Source Forward Leakage  
Gate-to-Source Reverse Leakage  
nA  
VGS = -16V  
Dynamic Electrical Characteristics @ TJ = 25°C (unless otherwise specified)  
Parameter  
Total Gate Charge  
Min. Typ. Max. Units  
Conditions  
Qg  
–––  
–––  
–––  
–––  
–––  
–––  
–––  
–––  
–––  
–––  
–––  
–––  
–––  
35  
53  
ID = 56A  
Qgs  
Qgd  
td(on)  
tr  
Gate-to-Source Charge  
Gate-to-Drain ("Miller") Charge  
Turn-On Delay Time  
Rise Time  
11  
–––  
VDS =20V  
VGS = 4.5V  
VDD = 20V  
nC  
ns  
16  
28  
–––  
–––  
–––  
–––  
–––  
–––  
–––  
–––  
–––  
–––  
271  
43  
ID = 56A  
td(off)  
tf  
Ω
RG = 3.7  
VGS = 4.5V  
VGS = 0V  
Turn-Off Delay Time  
Fall Time  
60  
Ciss  
Coss  
Crss  
Coss  
Coss  
Coss eff.  
Input Capacitance  
3617  
633  
345  
2378  
570  
875  
Output Capacitance  
Reverse Transfer Capacitance  
Output Capacitance  
Output Capacitance  
Effective Output Capacitance  
V
DS = 25V  
ƒ = 1.0 MHz, See Fig. 5  
GS = 0V, VDS = 1.0V, ƒ = 1.0MHz  
pF  
V
VGS = 0V, VDS = 32V, ƒ = 1.0MHz  
VGS = 0V, VDS = 0V to 32V  
Diode Characteristics  
Parameter  
Continuous Source Current  
Min. Typ. Max. Units  
Conditions  
MOSFET symbol  
IS  
D
–––  
––– 122  
(Body Diode)  
showing the  
A
G
ISM  
Pulsed Source Current  
integral reverse  
–––  
–––  
488  
S
(Body Diode)  
p-n junction diode.  
VSD  
trr  
Diode Forward Voltage  
–––  
–––  
–––  
–––  
33  
1.3  
50  
48  
V
TJ = 25°C, IS = 56A, VGS = 0V  
TJ = 25°C, IF = 56A, VDD = 20V,  
di/dt = 100A/μs  
Reverse Recovery Time  
Reverse Recovery Charge  
Forward Turn-On Time  
ns  
nC  
Qrr  
ton  
32  
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)  
Notes:  
„ ISD 56A, di/dt 263A/μs, VDD V(BR)DSS, TJ 175°C.  
Pulse width 1.0ms; duty cycle 2%.  
† Coss eff. is a fixed capacitance that gives the same charging  
 Calculated continuous current based on maximum  
allowable junction temperature. Bond wire current limit is  
56A. Note that current limitations arising from heating of  
the device leads may occur with some lead mounting  
time as Coss while VDS is rising from 0 to 80% VDSS  
.
‡ When mounted on 1" square PCB (FR-4 or G-10 Material).  
For recommended footprint and soldering techniques refer  
to application note #AN-994.  
arrangements. (Refer to AN-1140)  
‚ Repetitive rating; pulse width limited by max. junction  
temperature.  
ƒ Limited by TJmax, starting TJ = 25°C, L = 0.107mH,  
RG = 50Ω, IAS = 56A, VGS =10V. Part not recommended  
for use above this value.  
ˆ Rθ is measured at TJ approximately 90°C  
2
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AUIRLS3114Z  
1000  
100  
10  
1000  
100  
10  
VGS  
15V  
10V  
8.0V  
4.5V  
3.5V  
3.0V  
2.8V  
2.5V  
VGS  
15V  
10V  
8.0V  
4.5V  
3.5V  
3.0V  
2.8V  
2.5V  
TOP  
TOP  
BOTTOM  
BOTTOM  
2.5V  
2.5V  
1
60μs PULSE WIDTH  
Tj = 175°C  
60μs PULSE WIDTH  
Tj = 25°C  
0.1  
1
0.1  
1
10  
100  
1000  
0.1  
1
10  
100  
1000  
V
, Drain-to-Source Voltage (V)  
DS  
V
, Drain-to-Source Voltage (V)  
DS  
Fig 1. Typical Output Characteristics  
Fig 2. Typical Output Characteristics  
175  
150  
125  
100  
75  
1000  
100  
10  
T
= 25°C  
J
T = 175°C  
J
T
= 175°C  
J
T
= 25°C  
J
50  
1
V
= 25V  
25  
DS  
V
= 10V  
DS  
60μs PULSE WIDTH  
0
0.1  
0
20  
40  
60  
80  
1
2
3
4
5
6
I ,Drain-to-Source Current (A)  
D
V
, Gate-to-Source Voltage (V)  
GS  
Fig 4. Typical Forward Transconductance  
Fig 3. Typical Transfer Characteristics  
vs. Drain Current  
3
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AUIRLS3114Z  
100000  
10000  
1000  
14.0  
12.0  
10.0  
8.0  
V
= 0V,  
= C  
f = 1 MHZ  
GS  
I = 56A  
D
C
C
C
+ C , C  
SHORTED  
iss  
gs  
gd  
ds  
= C  
rss  
oss  
gd  
V
V
= 32V  
= C + C  
DS  
ds  
gd  
= 20V  
DS  
VDS= 8V  
C
iss  
6.0  
C
oss  
4.0  
C
rss  
2.0  
100  
0.0  
1
10  
, Drain-to-Source Voltage (V)  
100  
0
10 20 30 40 50 60 70 80 90  
V
Q , Total Gate Charge (nC)  
G
DS  
Fig 6. Typical Gate Charge vs.  
Fig 5. Typical Capacitance vs.  
Gate-to-Source Voltage  
Drain-to-Source Voltage  
10000  
1000  
100  
10  
1000  
100  
10  
OPERATION IN THIS AREA  
LIMITED BY R  
(on)  
DS  
T
= 175°C  
J
100μsec  
1msec  
10msec  
T
= 25°C  
J
1
Tc = 25°C  
Tj = 175°C  
Single Pulse  
DC  
V
= 0V  
GS  
0.1  
1.0  
0.1  
1
10  
100  
0.0  
0.5  
1.0  
1.5  
2.0  
2.5  
V
, Drain-to-Source Voltage (V)  
DS  
V
, Source-to-Drain Voltage (V)  
SD  
Fig 7. Typical Source-Drain Diode  
Fig 8. Maximum Safe Operating Area  
Forward Voltage  
4
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AUIRLS3114Z  
140  
120  
100  
80  
2.2  
2.0  
1.8  
1.6  
1.4  
1.2  
1.0  
0.8  
0.6  
0.4  
I
= 56A  
D
Wirebond Limitation  
V
= 10V  
GS  
60  
40  
20  
0
25  
50  
75  
100  
125  
150  
175  
-60 -40 -20 0 20 40 60 80 100120140160180  
, Junction Temperature (°C)  
T
, Case Temperature (°C)  
T
J
C
Fig 9. Maximum Drain Current vs.  
Fig 10. Normalized On-Resistance  
Case Temperature  
vs. Temperature  
10  
1
D = 0.50  
0.20  
0.10  
0.05  
0.1  
0.01  
0.02  
0.01  
SINGLE PULSE  
( THERMAL RESPONSE )  
Notes:  
1. Duty Factor D = t1/t2  
2. Peak Tj = P dm x Zthjc + Tc  
0.001  
1E-006  
1E-005  
0.0001  
0.001  
0.01  
0.1  
t
, Rectangular Pulse Duration (sec)  
1
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case  
5
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AUIRLS3114Z  
15V  
700  
600  
500  
400  
300  
200  
100  
0
I
D
DRIVER  
+
L
V
DS  
TOP  
9.6A  
20A  
BOTTOM 56A  
D.U.T  
AS  
R
G
V
DD  
-
I
A
2
V0GVS  
Ω
0.01  
t
p
Fig 12a. Unclamped Inductive Test Circuit  
V
(BR)DSS  
t
p
25  
50  
75  
100  
125  
150  
175  
Starting T , Junction Temperature (°C)  
J
Fig 12c. Maximum Avalanche Energy  
I
AS  
vs. Drain Current  
Fig 12b. Unclamped Inductive Waveforms  
Q
G
2.6  
2.4  
2.2  
2.0  
1.8  
1.6  
1.4  
10 V  
Q
Q
GD  
GS  
V
G
Charge  
I
= 100μA  
D
1.2  
1.0  
0.8  
0.6  
0.4  
ID = 250μA  
= 1.0mA  
I
Fig 13a. Basic Gate Charge Waveform  
D
ID = 10mA  
I
= 1.0A  
D
-75 -50 -25  
0
25 50 75 100 125 150 175  
T , Temperature ( °C )  
J
L
VCC  
Fig 14. Threshold Voltage vs. Temperature  
DUT  
0
1K  
Fig 13b. Gate Charge Test Circuit  
6
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AUIRLS3114Z  
1000  
100  
10  
Allowed avalanche Current vs avalanche  
pulsewidth, tav, assuming ΔTj = 150°C and  
Tstart =25°C (Single Pulse)  
Duty Cycle = Single Pulse  
0.01  
0.05  
0.10  
1
Allowed avalanche Current vs avalanche  
pulsewidth, tav, assuming ΔΤ j = 25°C and  
Tstart = 150°C.  
0.1  
1.0E-06  
1.0E-05  
1.0E-04  
1.0E-03  
1.0E-02  
1.0E-01  
tav (sec)  
Fig 15. Typical Avalanche Current vs.Pulsewidth  
180  
160  
140  
120  
100  
80  
Notes on Repetitive Avalanche Curves , Figures 15, 16:  
(For further info, see AN-1005 at www.irf.com)  
1. Avalanche failures assumption:  
Purely a thermal phenomenon and failure occurs at a  
temperature far in excess of Tjmax. This is validated for  
every part type.  
2. Safe operation in Avalanche is allowed as long asTjmax is  
not exceeded.  
3. Equation below based on circuit and waveforms shown in  
Figures 12a, 12b.  
TOP  
BOTTOM 1.0% Duty Cycle  
= 56A  
Single Pulse  
I
D
4. PD (ave) = Average power dissipation per single  
avalanche pulse.  
5. BV = Rated breakdown voltage (1.3 factor accounts for  
voltage increase during avalanche).  
60  
40  
6. Iav = Allowable avalanche current.  
20  
7. ΔT = Allowable rise in junction temperature, not to exceed  
Tjmax (assumed as 25°C in Figure 15, 16).  
tav = Average time in avalanche.  
0
25  
50  
75  
100  
125  
150  
175  
D = Duty cycle in avalanche = tav ·f  
ZthJC(D, tav) = Transient thermal resistance, see figure 11)  
Starting T , Junction Temperature (°C)  
J
PD (ave) = 1/2 ( 1.3·BV·Iav) = DT/ ZthJC  
Fig 16. Maximum Avalanche Energy  
Iav = 2DT/ [1.3·BV·Zth]  
EAS (AR) = PD (ave)·tav  
vs. Temperature  
7
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AUIRLS3114Z  
Driver Gate Drive  
P.W.  
P.W.  
Period  
D.U.T  
Period  
D =  
+
ƒ
-
*
=10V  
V
GS  
Circuit Layout Considerations  
Low Stray Inductance  
Ground Plane  
Low Leakage Inductance  
Current Transformer  
D.U.T. I Waveform  
SD  
+
‚
-
Reverse  
Recovery  
Current  
Body Diode Forward  
„
Current  
di/dt  
-
+
D.U.T. V Waveform  
DS  
Diode Recovery  
dv/dt  

V
DD  
VDD  
Re-Applied  
Voltage  
dv/dt controlled by RG  
Driver same type as D.U.T.  
RG  
+
-
Body Diode  
Forward Drop  
ISD controlled by Duty Factor "D"  
D.U.T. - Device Under Test  
Inductor Curent  
I
SD  
Ripple  
5%  
* VGS = 5V for Logic Level Devices  
Fig 17. Peak Diode Recovery dv/dt Test Circuit for N-Channel  
HEXFET® Power MOSFETs  
RD  
VDS  
VGS  
D.U.T.  
RG  
+VDD  
-
10V  
Pulse Width ≤ 1 µs  
Duty Factor ≤ 0.1 %  
Fig 18a. Switching Time Test Circuit  
V
DS  
90%  
10%  
V
GS  
t
t
r
t
t
f
d(on)  
d(off)  
Fig 18b. Switching Time Waveforms  
8
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AUIRLS3114Z  
D2Pak Package Outline (Dimensions are shown in millimeters (inches))  
D2Pak Part Marking Information  
PartNumber  
AULS3114Z  
Date Code  
Y= Year  
WW= Work Week  
A= Automotive, Lead Free  
IR Logo  
YWWA  
XX or XX  
Lot Code  
Note: For the most current drawing please refer to IR website at http://www.irf.com/package/  
9
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March 03, 2014  
AUIRLS3114Z  
D2Pak (TO-263AB) Tape & Reel Information  
Dimensions are shown in millimeters (inches)  
TRR  
1.60 (.063)  
1.50 (.059)  
1.60 (.063)  
1.50 (.059)  
4.10 (.161)  
3.90 (.153)  
0.368 (.0145)  
0.342 (.0135)  
FEED DIRECTION  
TRL  
11.60 (.457)  
11.40 (.449)  
1.85 (.073)  
1.65 (.065)  
24.30 (.957)  
23.90 (.941)  
15.42 (.609)  
15.22 (.601)  
1.75 (.069)  
1.25 (.049)  
10.90 (.429)  
10.70 (.421)  
4.72 (.136)  
4.52 (.178)  
16.10 (.634)  
15.90 (.626)  
FEED DIRECTION  
13.50 (.532)  
12.80 (.504)  
27.40 (1.079)  
23.90 (.941)  
4
330.00  
(14.173)  
MAX.  
60.00 (2.362)  
MIN.  
30.40 (1.197)  
MAX.  
NOTES :  
1. COMFORMS TO EIA-418.  
2. CONTROLLING DIMENSION: MILLIMETER.  
3. DIMENSION MEASURED @ HUB.  
4. INCLUDES FLANGE DISTORTION @ OUTER EDGE.  
26.40 (1.039)  
24.40 (.961)  
4
3
Note: For the most current drawing please refer to IR website at http://www.irf.com/package/  
10  
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AUIRLS3114Z  
Qualification Information†  
Automotive  
††  
(per AEC-Q101)  
Comments:  
This part  
number(s) passed  
Qualification Level  
Automotive qualification. IR’s Industrial and  
Consumer qualification level is granted by  
extension of the higher Automotive level.  
Moisture Sensitivity Level  
MSL1  
Class M4(+/- 600V )†††  
3L-D2 PAK  
Machine Model  
(per AEC-Q101-002)  
Class H1C(+/- 2000V )†††  
(per AEC-Q101-001)  
ESD  
Human Body Model  
Class C5(+/- 2000V )†††  
(per AEC-Q101-005)  
Charged Device Model  
RoHS Compliant  
Yes  
Qualification standards can be found at International Rectifier’s web site: http//www.irf.com/  
†† Exceptions (if any) to AEC-Q101 requirements are noted in the qualification report.  
††† Highest passing voltage  
11  
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AUIRLS3114Z  
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of sale supplied at the time of order acknowledgment.  
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withIR’sstandardwarranty. TestingandotherqualitycontroltechniquesareusedtotheextentIRdeemsnecessary  
to support this warranty. Except where mandated by government requirements, testing of all parameters of each  
product is not necessarily performed.  
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customers should provide adequate design and operating safeguards.  
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Submit Datasheet Feedback  
March 03, 2014  
AUIRLS3114Z  
Revision History  
Date  
Comments  
Added "Logic Level Gate Drive" bullet in the features section on page 1  
Updated data sheet with new IR corporate template  
3/3/2014  
13  
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March 03, 2014  

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