AUIRLS4030TRR [INFINEON]
Power Field-Effect Transistor, 180A I(D), 100V, 0.0043ohm, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, TO-263AB, ROHS COMPLIANT, PLASTIC, D2PAK-3;![AUIRLS4030TRR](http://pdffile.icpdf.com/pdf2/p00212/img/icpdf/AUIRLS_1197611_icpdf.jpg)
型号: | AUIRLS4030TRR |
厂家: | ![]() |
描述: | Power Field-Effect Transistor, 180A I(D), 100V, 0.0043ohm, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, TO-263AB, ROHS COMPLIANT, PLASTIC, D2PAK-3 晶体 晶体管 开关 脉冲 局域网 |
文件: | 总13页 (文件大小:274K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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PD - 96406B
AUTOMOTIVE GRADE
AUIRLS4030
Features
AUIRLSL4030
l
Optimized for Logic Level Drive
Advanced Process Technology
UltraLowOn-Resistance
HEXFET® Power MOSFET
l
l
l
l
l
l
l
D
S
VDSS
RDS(on) typ.
max.
100V
175°COperatingTemperature
Fast Switching
3.4m
4.3m
Ω
Repetitive Avalanche Allowed up to Tjmax
Lead-Free,RoHSCompliant
Automotive Qualified *
G
ID
180A
Description
Specifically designed for Automotive applications, this
HEXFET® Power MOSFET utilizes the latest processing
techniques to achieve extremely low on-resistance per
siliconarea. Additionalfeaturesofthisdesign area175°C
junctionoperatingtemperature, fastswitchingspeedand
improved repetitive avalanche rating . These features
combine to make this design an extremely efficient and
reliable device for use in Automotive applications and a
wide variety of other applications.
S
S
D
D
G
G
D2Pak
AUIRLS4030
TO-262
AUIRLSL4030
G
D
S
Gate
Drain
Source
Absolute Maximum Ratings
StressesbeyondthoselistedunderAbsoluteMaximumRatingsmaycausepermanentdamagetothedevice.Thesearestress
ratings only; and functional operation of the device at these or any other condition beyond those indicated in the specifications
is not implied.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability. Thethermal
resistanceandpowerdissipationratingsaremeasuredunderboardmountedandstillairconditions.Ambienttemperature(TA)
is 25°C, unless otherwise specified.
Parameter
Continuous Drain Current, VGS @ 10V
Continuous Drain Current, VGS @ 10V
Pulsed Drain Current
Max.
180
130
730
Units
A
ID @ TC = 25°C
ID @ TC = 100°C
IDM
PD @TC = 25°C
W
370
2.5
± 16
305
Maximum Power Dissipation
Linear Derating Factor
Gate-to-Source Voltage
Single Pulse Avalanche Energy (Thermally limited)
Avalanche Current
W/°C
V
mJ
A
VGS
EAS
IAR
See Fig. 14, 15, 22a, 22b,
Repetitive Avalanche Energy
EAR
mJ
21
dv/dt
TJ
V/ns
Peak Diode Recovery
Operating Junction and
-55 to + 175
TSTG
Storage Temperature Range
Soldering Temperature, for 10 seconds
(1.6mm from case)
°C
300
Thermal Resistance
Parameter
Typ.
–––
–––
Max.
0.40
40
Units
°C/W
Rθ
Junction-to-Case
JC
Junction-to-Ambient (PCB Mount) , D2Pak
RθJA
HEXFET® is a registered trademark of International Rectifier.
*Qualification standards can be found at http://www.irf.com/
www.irf.com
1
11/17/11
AUIRLS/SL4030
Static Electrical Characteristics @ TJ = 25°C (unless otherwise specified)
Parameter
Min. Typ. Max. Units
100 ––– –––
––– 0.10 ––– V/°C Reference to 25°C, ID = 5mA
Conditions
VGS = 0V, ID = 250μA
V(BR)DSS
Drain-to-Source Breakdown Voltage
Breakdown Voltage Temp. Coefficient
Static Drain-to-Source On-Resistance
V
V
/ T
(BR)DSS Δ
Δ
J
RDS(on)
–––
–––
1.0
3.4
3.6
4.3
4.5
2.5
VGS = 10V, ID = 110A
VGS = 4.5V, ID = 92A
VDS = VGS, ID = 250μA
VDS = 25V, ID = 110A
VDS = 100V, VGS = 0V
VDS = 100V, VGS = 0V, TJ = 125°C
VGS = 16V
m
Ω
VGS(th)
Gate Threshold Voltage
–––
V
gfs
IDSS
Forward Transconductance
Drain-to-Source Leakage Current
320 ––– –––
––– ––– 20
S
μA
––– ––– 250
––– ––– 100
––– ––– -100
IGSS
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Internal Gate Resistance
nA
VGS = -16V
RG(int)
–––
2.1
–––
Ω
Dynamic Electrical Characteristics @ TJ = 25°C (unless otherwise specified)
Parameter
Total Gate Charge
Min. Typ. Max. Units
Conditions
Qg
–––
–––
–––
–––
–––
87
27
45
42
74
130
–––
–––
–––
–––
ID = 110A
Qgs
Gate-to-Source Charge
Gate-to-Drain ("Miller") Charge
Total Gate Charge Sync. (Qg - Qgd)
Turn-On Delay Time
Rise Time
VDS = 50V
nC
ns
Qgd
VGS = 4.5V
Qsync
ID = 110A, VDS =0V, VGS = 4.5V
VDD = 65V
td(on)
tr
––– 330 –––
––– 110 –––
––– 170 –––
––– 11360 –––
––– 670 –––
––– 290 –––
––– 760 –––
––– 1140 –––
ID = 110A
td(off)
tf
Turn-Off Delay Time
Fall Time
R = 2.7
Ω
G
VGS = 4.5V
Ciss
Input Capacitance
VGS = 0V
Coss
Output Capacitance
Reverse Transfer Capacitance
VDS = 50V
Crss
ƒ = 1.0MHz
pF
Coss eff. (ER)
Coss eff. (TR)
VGS = 0V, VDS = 0V to 80V
VGS = 0V, VDS = 0V to 80V
Effective Output Capacitance (Energy Related)
Effective Output Capacitance (Time Related)
Diode Characteristics
Parameter
Min. Typ. Max. Units
Conditions
D
S
IS
Continuous Source Current
MOSFET symbol
––– ––– 180
A
(Body Diode)
Pulsed Source Current
(Body Diode)
showing the
integral reverse
G
ISM
––– ––– 730
p-n junction diode.
VSD
trr
Diode Forward Voltage
Reverse Recovery Time
––– –––
1.3
–––
–––
–––
V
TJ = 25°C, IS = 110A, VGS = 0V
TJ = 25°C
TJ = 125°C
TJ = 25°C
TJ = 125°C
TJ = 25°C
VR = 85V,
IF = 110A
di/dt = 100A/μs
–––
–––
–––
50
60
88
ns
Qrr
Reverse Recovery Charge
nC
A
––– 130 –––
––– 3.3 –––
IRRM
ton
Reverse Recovery Current
Forward Turn-On Time
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
Notes:
Repetitive rating; pulse width limited by max. junction temperature.
Limited by TJmax, starting TJ = 25°C, L = 0.05mH, RG = 25Ω,
IAS = 110A, VGS =10V. Part not recommended for use above
this value .
ꢀ Coss eff. (TR) is a fixed capacitance that gives the same
charging time as Coss while VDS is rising from 0 to 80% VDSS
Coss eff. (ER) is a fixed capacitance that gives the same energy as
Coss while VDS is rising from 0 to 80% VDSS
.
ISD ≤ 110A, di/dt ≤ 1330A/μs, VDD ≤ V(BR)DSS, TJ ≤ 175°C.
Pulse width ≤ 400μs; duty cycle ≤ 2%.
Rθ is measured at TJ approximately 90°C.
When mounted on 1" square PCB (FR-4 or G-10 Material). For
recommended footprint and soldering techniquea refer to applocation
note # AN- 994 echniques refer to application note #AN-994.
RθJC value shown is at time zero.
2
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AUIRLS/SL4030
Qualification Information†
Automotive
††
(per AEC-Q101)
Comments: This part number(s) passed Automotive
qualification. IR’s Industrial and Consumer
Qualification Level
qualification level is granted by extension of the
higher Automotive level.
MSL1
N/A
3L-D2 PAK
3L-TO-262
Moisture Sensitivity Level
Class M4(+/- 800V )†††
Machine Model
(per AEC-Q101-002)
Class H3A(+/- 6000V )†††
(per AEC-Q101-001)
Human Body Model
ESD
Class C5(+/- 2000V )†††
(per AEC-Q101-005)
Charged Device Model
Yes
RoHS Compliant
†
Qualification standards can be found at International Rectifier’s web site: http//www.irf.com/
Exceptions (if any) to AEC-Q101 requirements are noted in the qualification report.
††
††† Highest passing voltage
www.irf.com
3
AUIRLS/SL4030
1000
1000
100
10
VGS
15V
10V
8.0V
4.5V
3.5V
3.0V
2.7V
2.5V
VGS
15V
10V
8.0V
4.5V
3.5V
3.0V
2.7V
2.5V
TOP
TOP
100
BOTTOM
BOTTOM
10
2.5V
2.5V
60μs PULSE WIDTH
60μs PULSE WIDTH
≤
≤
Tj = 175°C
Tj = 25°C
1
0.1
1
10
100
1000
0.1
1
10
100
1000
V
, Drain-to-Source Voltage (V)
DS
V
, Drain-to-Source Voltage (V)
DS
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
1000
100
10
2.5
2.0
1.5
1.0
0.5
0.0
I
= 110A
D
V
= 10V
GS
T = 175°C
J
T = 25°C
J
V
= 50V
DS
60μs PULSE WIDTH
≤
1.0
1
2
3
4
5
-60 -40 -20 0 20 40 60 80 100120140160180
T , Junction Temperature (°C)
J
V
, Gate-to-Source Voltage (V)
GS
Fig 4. Normalized On-Resistance vs. Temperature
Fig 3. Typical Transfer Characteristics
100000
10000
1000
5.0
V
= 0V,
= C
f = 1 MHZ
GS
I = 110A
D
C
C
C
+ C , C
SHORTED
V
V
= 80V
= 50V
iss
gs
gd
ds
DS
DS
= C
rss
oss
gd
4.0
3.0
2.0
1.0
0.0
= C + C
ds
gd
C
iss
C
oss
C
rss
100
1
10
, Drain-to-Source Voltage (V)
100
0
20
40
60
80
100
V
Q , Total Gate Charge (nC)
DS
G
Fig 5. Typical Capacitance vs. Drain-to-Source Voltage
Fig 6. Typical Gate Charge vs. Gate-to-Source Voltage
4
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AUIRLS/SL4030
1000
100
10
10000
1000
100
10
OPERATION IN THIS AREA
LIMITED BY R (on)
T = 175°C
J
DS
100μsec
T = 25°C
J
10msec
DC
1msec
1
Tc = 25°C
Tj = 175°C
Single Pulse
V
= 0V
GS
2.0
0.1
1
0.0
0.5
1.0
1.5
2.5
0
1
10
100
1000
V
, Source-to-Drain Voltage (V)
SD
V
, Drain-to-Source Voltage (V)
DS
Fig 8. Maximum Safe Operating Area
Fig 7. Typical Source-Drain Diode
Forward Voltage
200
125
120
115
110
105
100
95
Id = 5mA
180
160
140
120
100
80
60
40
20
0
90
25
50
75
100
125
150
175
-60 -40 -20 0 20 40 60 80 100120140160180
T
, Case Temperature (°C)
T , Temperature ( °C )
J
C
Fig 9. Maximum Drain Current vs.
Fig 10. Drain-to-Source Breakdown Voltage
Case Temperature
4.5
1400
I
D
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
1200
1000
800
600
400
200
0
TOP
17A
40A
BOTTOM 110A
-20
0
20
40
60
80
100 120
25
50
75
100
125
150
175
Starting T , Junction Temperature (°C)
J
V
Drain-to-Source Voltage (V)
DS,
Fig 11. Typical COSS Stored Energy
Fig 12. Maximum Avalanche Energy vs. DrainCurrent
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5
AUIRLS/SL4030
1
D = 0.50
0.1
0.01
0.20
0.10
0.05
R1
R1
R2
R2
R3
R3
Ri (°C/W) τi (sec)
0.0477 0.000071
0.02
0.01
τ
J τJ
τ
τ
Cτ
τ
1τ1
τ
2τ2
3τ3
0.1631 0.000881
0.1893 0.007457
Ci= τi/Ri
0.001
SINGLE PULSE
( THERMAL RESPONSE )
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
0.0001
1E-006
1E-005
0.0001
0.001
0.01
0.1
t
, Rectangular Pulse Duration (sec)
1
Fig 13. Maximum Effective Transient Thermal Impedance, Junction-to-Case
1000
100
10
Duty Cycle = Single Pulse
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming ΔTj = 150°C and
Tstart =25°C (Single Pulse)
0.01
0.05
0.10
1
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming ΔΤj = 25°C and
Tstart = 150°C.
0.1
1.0E-06
1.0E-05
1.0E-04
1.0E-03
1.0E-02
1.0E-01
tav (sec)
Fig 14. Typical Avalanche Current vs.Pulsewidth
350
300
250
200
150
100
50
Notes on Repetitive Avalanche Curves , Figures 14, 15:
(For further info, see AN-1005 at www.irf.com)
1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a temperature far in
excess of Tjmax. This is validated for every part type.
2. Safe operation in Avalanche is allowed as long asTjmax is not exceeded.
3. Equation below based on circuit and waveforms shown in Figures 22a, 22b.
4. PD (ave) = Average power dissipation per single avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase
during avalanche).
6. Iav = Allowable avalanche current.
7. ΔT = Allowable rise in junction temperature, not to exceed Tjmax (assumed as
25°C in Figure 14, 15).
tav = Average time in avalanche.
D = Duty cycle in avalanche = tav ·f
TOP
BOTTOM 1.0% Duty Cycle
= 110A
Single Pulse
I
D
ZthJC(D, tav) = Transient thermal resistance, see Figures 13)
0
PD (ave) = 1/2 ( 1.3·BV·Iav) = DT/ ZthJC
25
50
75
100
125
150
175
Iav = 2DT/ [1.3·BV·Zth]
Starting T , Junction Temperature (°C)
EAS (AR) = PD (ave)·tav
J
Fig 15. Maximum Avalanche Energy vs. Temperature
6
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AUIRLS/SL4030
2.5
2.0
1.5
1.0
0.5
0.0
40
35
30
25
20
15
10
5
I = 73A
F
V
= 85V
R
T = 25°C
J
T = 125°C
J
I
I
I
= 250μA
= 1.0mA
= 1.0A
D
D
D
0
0
200
400
600
800
1000
-75 -50 -25
0
25 50 75 100 125 150 175
T , Temperature ( °C )
di /dt (A/μs)
F
J
Fig. 17 - Typical Recovery Current vs. dif/dt
Fig 16. Threshold Voltage vs. Temperature
35
800
I = 110A
F
I = 73A
F
720
640
560
480
400
320
240
160
80
30
25
20
15
10
5
V
= 85V
V
= 85V
R
R
T = 25°C
T = 25°C
J
J
T = 125°C
J
T = 125°C
J
0
0
200
400
600
800
1000
0
200
400
600
800
1000
di /dt (A/μs)
di /dt (A/μs)
F
F
Fig. 18 - Typical Recovery Current vs. dif/dt
Fig. 19 - Typical Stored Charge vs. dif/dt
880
I = 110A
F
800
V
= 85V
R
720
640
560
480
400
320
240
160
80
T = 25°C
J
T = 125°C
J
0
200
400
600
800
1000
di /dt (A/μs)
F
Fig. 20 - Typical Stored Charge vs. dif/dt
www.irf.com
7
AUIRLS/SL4030
Driver Gate Drive
P.W.
P.W.
Period
D.U.T
Period
D =
+
*
=10V
V
GS
CircuitLayoutConsiderations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
-
D.U.T. I Waveform
SD
+
-
Reverse
Recovery
Current
Body Diode Forward
Current
di/dt
-
+
D.U.T. V Waveform
DS
Diode Recovery
dv/dt
V
DD
VDD
Re-Applied
Voltage
• dv/dtcontrolledbyRG
RG
+
-
Body Diode
Forward Drop
• Driver same type as D.U.T.
• ISD controlled by Duty Factor "D"
• D.U.T. - Device Under Test
InductorCurrent
I
SD
Ripple ≤ 5%
* VGS = 5V for Logic Level Devices
Fig 21. Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET® Power MOSFETs
V
(BR)DSS
15V
t
p
DRIVER
+
L
V
DS
D.U.T
AS
R
G
V
DD
-
I
A
V
2
GS
Ω
0.01
t
p
I
AS
Fig 22b. Unclamped Inductive Waveforms
Fig 22a. Unclamped Inductive Test Circuit
RD
VDS
V
DS
90%
VGS
D.U.T.
RG
+
VDD
-
VGS
10%
PulseWidth ≤ 1 µs
Duty Factor ≤ 0.1 %
V
GS
t
t
r
t
t
f
d(on)
d(off)
Fig 23a. Switching Time Test Circuit
Fig 23b. Switching Time Waveforms
Id
Current Regulator
Same Type as D.U.T.
Vds
Vgs
50KΩ
.2μF
12V
.3μF
+
V
DS
D.U.T.
-
Vgs(th)
V
GS
3mA
I
I
D
G
Qgs1
Qgs2
Qgd
Qgodr
Current Sampling Resistors
Fig 24a. Gate Charge Test Circuit
Fig 24b. Gate Charge Waveform
8
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AUIRLS/SL4030
D2Pak Package Outline (Dimensions are shown in millimeters (inches))
D2Pak Part Marking Information
PartNumber
AULS4030
DateCode
Y= Year
WW= Work Week
A= Automotive, Lead Free
IRLogo
YWWA
XX or XX
LotCode
Note: For the most current drawing please refer to IR website at http://www.irf.com/package/
www.irf.com
9
AUIRLS/SL4030
TO-262 Package Outline ( Dimensions are shown in millimeters (inches))
TO-262 Part Marking Information
PartNumber
AULSL4030
DateCode
Y= Year
WW= Work Week
A= Automotive, Lead Free
IRLogo
YWWA
XX or XX
LotCode
Note: For the most current drawing please refer to IR website at http://www.irf.com/package/
10
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AUIRLS/SL4030
D2Pak (TO-263AB) Tape & Reel Information
Dimensions are shown in millimeters (inches)
TRR
1.60 (.063)
1.50 (.059)
1.60 (.063)
1.50 (.059)
4.10 (.161)
3.90 (.153)
0.368 (.0145)
0.342 (.0135)
FEED DIRECTION
1.85 (.073)
11.60 (.457)
11.40 (.449)
1.65 (.065)
24.30 (.957)
23.90 (.941)
15.42 (.609)
15.22 (.601)
TRL
1.75 (.069)
1.25 (.049)
10.90 (.429)
10.70 (.421)
4.72 (.136)
4.52 (.178)
16.10 (.634)
15.90 (.626)
FEED DIRECTION
13.50 (.532)
12.80 (.504)
27.40 (1.079)
23.90 (.941)
4
330.00
(14.173)
MAX.
60.00 (2.362)
MIN.
30.40 (1.197)
MAX.
NOTES :
1. COMFORMS TO EIA-418.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION MEASURED @ HUB.
4. INCLUDES FLANGE DISTORTION @ OUTER EDGE.
26.40 (1.039)
24.40 (.961)
4
3
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11
AUIRLS/SL4030
Ordering Information
Base part
Package Type
Standard Pack
Form
Complete Part Number
Quantity
AUIRLSL4030
AUIRLS4030
TO-262
D2Pak
Tube
Tube
50
50
AUIRLSL4030
AUIRLS4030
Tape and Reel Left
Tape and Reel Right
800
800
AUIRLS4030TRL
AUIRLS4030TRR
12
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AUIRLS/SL4030
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the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services
at any time and to discontinue any product or services without notice. Part numbers designated with the “AU” prefix follow
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standard warranty. Testing and other quality control techniques are used to the extent IR deems necessary to support this
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IR products are neither designed nor intended for use in automotive applications or environments unless the specific IR
productsaredesignatedbyIRascompliantwithISO/TS16949requirementsandbearapartnumberincludingthedesignation
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be responsible for any failure to meet such requirements.
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13
相关型号:
![](http://pdffile.icpdf.com/pdf2/p00303/img/page/AUIRLSL4030_1829125_files/AUIRLSL4030_1829125_1.jpg)
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AUIRLSL4030
Power Field-Effect Transistor, 180A I(D), 100V, 0.0043ohm, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, TO-262AA, ROHS COMPLIANT, PLASTIC, TO-262, 3 PIN
INFINEON
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AUIRLU024Z
Power Field-Effect Transistor, 16A I(D), 55V, 0.058ohm, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, TO-251AA, ROHS COMPLIANT, PLASTIC, IPAK-3
INFINEON
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AUIRLU2905
Power Field-Effect Transistor, 42A I(D), 55V, 0.03ohm, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, ROHS COMPLIANT, IPAK-3
INFINEON
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AUIRS1170S
AUIRS1170S 是一款通过汽车认证的智能次级侧驱动器 IC,该产品设计用于驱动在隔离谐振、反激和正向转换器中用作同步整流器的 N 通道功率 MOSFET。该 IC 可以控制一个或多个并联 N 通道 MOSFET,模拟肖特基二极管整流器行为。AUIRS1170S 可在 DCM 和 CCM 工作模式下运行。SYNC 引脚应在 CCM 模式下使用,通过次级或主控制器信号直接关断 MOSFET。该 IC 设计使用简单电容器耦合接口连接主控制器。除 SYNC 控制外,漏极到源极电压通过差分感测,确定电流极性并开关电源开关,近乎零电流转换。使用先进的消隐方案和双脉冲抑制实现稳健性和抗噪声能力,可在各种工作模式下可靠运行。
INFINEON
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