BSC146N10LS5 [INFINEON]

逻辑电平 OptiMOS™ 5 100V 功率 MOSFET提供低栅极电荷,可在不影响导通损耗的情况下减少开关损耗。采用 SuperS08 封装的 OptiMOS™ 5(BSC146N10LS5)功率 MOSFET 可在高开关频率下运作,并且其栅极阈值电压低,因此 MOSFET 可直接由微控制器驱动。它可用于 充电器、 适配器 和 电信等应用;
BSC146N10LS5
型号: BSC146N10LS5
厂家: Infineon    Infineon
描述:

逻辑电平 OptiMOS™ 5 100V 功率 MOSFET提供低栅极电荷,可在不影响导通损耗的情况下减少开关损耗。采用 SuperS08 封装的 OptiMOS™ 5(BSC146N10LS5)功率 MOSFET 可在高开关频率下运作,并且其栅极阈值电压低,因此 MOSFET 可直接由微控制器驱动。它可用于 充电器、 适配器 和 电信等应用

开关 栅 驱动 控制器 电信 微控制器 栅极
文件: 总12页 (文件大小:1202K)
中文:  中文翻译
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BSC146N10LS5  
MOSFET  
OptiMOSTMꢀ5ꢀPower-Transistor,ꢀ100ꢀV  
SuperSO8  
5
8
6
7
7
Features  
6
5
8
•ꢀOptimizedꢀforꢀhighꢀperformanceꢀSMPS,ꢀe.g.ꢀsync.ꢀRec.  
•ꢀ100%ꢀavalancheꢀtested  
•ꢀSuperiorꢀthermalꢀresistance  
•ꢀN-channel,ꢀlogicꢀlevel  
•ꢀPb-freeꢀleadꢀplating;ꢀRoHSꢀcompliant  
•ꢀHalogen-freeꢀaccordingꢀtoꢀIEC61249-2-21  
4
3
1
2
2
3
1
4
Productꢀvalidation  
FullyꢀqualifiedꢀaccordingꢀtoꢀJEDECꢀforꢀIndustrialꢀApplications  
S 1  
8 D  
7 D  
Tableꢀ1ꢀꢀꢀꢀꢀKeyꢀPerformanceꢀParameters  
S 2  
S 3  
G 4  
Parameter  
Value  
100  
14.6  
44  
Unit  
6 D  
5 D  
VDS  
V
RDS(on),max  
ID  
m  
A
Qoss  
20  
nC  
nC  
QG(0V..4.5V)  
7.6  
Typeꢀ/ꢀOrderingꢀCode  
Package  
Marking  
RelatedꢀLinks  
BSC146N10LS5  
PG-TDSON-8  
146N10LS  
-
Final Data Sheet  
1
Rev.ꢀ2.3,ꢀꢀ2020-08-06  
OptiMOSTMꢀ5ꢀPower-Transistor,ꢀ100ꢀV  
BSC146N10LS5  
TableꢀofꢀContents  
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1  
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3  
Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3  
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4  
Electrical characteristics diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6  
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10  
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12  
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12  
Disclaimer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12  
Final Data Sheet  
2
Rev.ꢀ2.3,ꢀꢀ2020-08-06  
OptiMOSTMꢀ5ꢀPower-Transistor,ꢀ100ꢀV  
BSC146N10LS5  
1ꢀꢀꢀꢀꢀMaximumꢀratings  
atꢀTA=25ꢀ°C,ꢀunlessꢀotherwiseꢀspecified  
Tableꢀ2ꢀꢀꢀꢀꢀMaximumꢀratings  
Values  
Typ.  
Parameter  
Symbol  
Unit Noteꢀ/ꢀTestꢀCondition  
Min.  
Max.  
VGS=10ꢀV,ꢀTC=25ꢀ°C  
VGS=10ꢀV,ꢀTC=100ꢀ°C  
-
-
-
-
-
-
44  
28  
10  
Continuous drain current1)  
ID  
A
VGS=10ꢀV,ꢀTA=25ꢀ°C,  
RTHJA=50ꢀ°C/W2)  
Pulsed drain current3)  
Avalanche energy, single pulse4)  
ID,pulse  
EAS  
-
-
-
-
176  
30  
A
TA=25ꢀ°C  
-
mJ  
V
ID=20ꢀA,ꢀRGS=25ꢀΩ  
Gate source voltage  
VGS  
-20  
20  
-
-
-
-
-
52  
2.5  
TC=25ꢀ°C  
Power dissipation  
Ptot  
W
TA=25ꢀ°C,ꢀRTHJA=50ꢀ°C/W3)  
IEC climatic category; DIN IEC 68-1:  
55/150/56  
Operating and storage temperature  
Tj,ꢀTstg  
-55  
-
150  
°C  
2ꢀꢀꢀꢀꢀThermalꢀcharacteristics  
Tableꢀ3ꢀꢀꢀꢀꢀThermalꢀcharacteristics  
Values  
Typ.  
1.4  
Parameter  
Symbol  
Unit Noteꢀ/ꢀTestꢀCondition  
Min.  
Max.  
Thermal resistance, junction - case  
RthJC  
RthJA  
-
2.4  
°C/W -  
°C/W -  
Device on PCB,  
-
-
50  
6 cm² cooling area2)  
1) Rating refers to the product only with datasheet specified absolute maximum values, maintaining case temperature  
at 25°C. For higher case temperature please refer to Diagram 2. De-rating will be required based on the actual  
environmental conditions.  
2) Device on 40 mm x 40 mm x 1.5 mm epoxy PCB FR4 with 6 cm2 (one layer, 70 µm thick) copper area for drain  
connection. PCB is vertical in still air.  
3) See Diagram 3 for more detailed information  
4) See Diagram 13 for more detailed information  
Final Data Sheet  
3
Rev.ꢀ2.3,ꢀꢀ2020-08-06  
OptiMOSTMꢀ5ꢀPower-Transistor,ꢀ100ꢀV  
BSC146N10LS5  
3ꢀꢀꢀꢀꢀElectricalꢀcharacteristics  
atꢀTj=25ꢀ°C,ꢀunlessꢀotherwiseꢀspecified  
Tableꢀ4ꢀꢀꢀꢀꢀStaticꢀcharacteristics  
Values  
Typ.  
-
Parameter  
Symbol  
Unit Noteꢀ/ꢀTestꢀCondition  
Min.  
100  
1.1  
Max.  
-
Drain-source breakdown voltage  
Gate threshold voltage  
V(BR)DSS  
VGS(th)  
V
V
VGS=0ꢀV,ꢀID=1ꢀmA  
VDS=VGS,ꢀID=23ꢀµA  
1.7  
2.3  
-
-
0.1  
10  
1
100  
VDS=100ꢀV,ꢀVGS=0ꢀV,ꢀTj=25ꢀ°C  
VDS=100ꢀV,ꢀVGS=0ꢀV,ꢀTj=125ꢀ°C  
Zero gate voltage drain current  
Gate-source leakage current  
Drain-source on-state resistance  
IDSS  
µA  
nA  
IGSS  
-
10  
100  
VGS=20ꢀV,ꢀVDS=0ꢀV  
-
-
12.2  
15.8  
14.6  
20.8  
VGS=10ꢀV,ꢀID=22ꢀA  
VGS=4.5ꢀV,ꢀID=11ꢀA  
RDS(on)  
mΩ  
Gate resistance1)  
Transconductance  
RG  
gfs  
-
1
1.5  
-
-
19  
38  
S
|VDS|2|ID|RDS(on)max,ꢀID=22ꢀA  
Tableꢀ5ꢀꢀꢀꢀꢀDynamicꢀcharacteristics  
Values  
Typ.  
Parameter  
Symbol  
Unit Noteꢀ/ꢀTestꢀCondition  
Min.  
Max.  
Input capacitance1)  
Output capacitance1)  
Reverse transfer capacitance1)  
Ciss  
Coss  
Crss  
-
-
-
1000 1300 pF  
VGS=0ꢀV,ꢀVDS=50ꢀV,ꢀf=1ꢀMHz  
VGS=0ꢀV,ꢀVDS=50ꢀV,ꢀf=1ꢀMHz  
VGS=0ꢀV,ꢀVDS=50ꢀV,ꢀf=1ꢀMHz  
170  
9
220  
15  
pF  
pF  
VDD=50ꢀV,ꢀVGS=10ꢀV,ꢀID=22ꢀA,  
RG,ext=3ꢀΩ  
Turn-on delay time  
Rise time  
td(on)  
tr  
td(off)  
tf  
-
-
-
-
5
-
-
-
-
ns  
ns  
ns  
ns  
VDD=50ꢀV,ꢀVGS=10ꢀV,ꢀID=22ꢀA,  
RG,ext=3ꢀΩ  
3
VDD=50ꢀV,ꢀVGS=10ꢀV,ꢀID=22ꢀA,  
RG,ext=3ꢀΩ  
Turn-off delay time  
Fall time  
14  
3
VDD=50ꢀV,ꢀVGS=10ꢀV,ꢀID=22ꢀA,  
RG,ext=3ꢀΩ  
Tableꢀ6ꢀꢀꢀꢀꢀGateꢀchargeꢀcharacteristics2)ꢀ  
Values  
Typ.  
3.3  
Parameter  
Symbol  
Unit Noteꢀ/ꢀTestꢀCondition  
Min.  
Max.  
Gate to source charge  
Gate charge at threshold  
Gate to drain charge1)  
Switching charge  
Qgs  
-
-
-
-
-
-
-
-
-
nC  
nC  
nC  
nC  
nC  
V
VDD=50ꢀV,ꢀID=22ꢀA,ꢀVGS=0ꢀtoꢀ4.5ꢀV  
VDD=50ꢀV,ꢀID=22ꢀA,ꢀVGS=0ꢀtoꢀ4.5ꢀV  
VDD=50ꢀV,ꢀID=22ꢀA,ꢀVGS=0ꢀtoꢀ4.5ꢀV  
VDD=50ꢀV,ꢀID=22ꢀA,ꢀVGS=0ꢀtoꢀ4.5ꢀV  
VDD=50ꢀV,ꢀID=22ꢀA,ꢀVGS=0ꢀtoꢀ4.5ꢀV  
VDD=50ꢀV,ꢀID=22ꢀA,ꢀVGS=0ꢀtoꢀ4.5ꢀV  
VDS=0.1ꢀV,ꢀVGS=0ꢀtoꢀ10ꢀV  
Qg(th)  
Qgd  
1.7  
-
2.8  
4.2  
-
Qsw  
4.4  
Gate charge total1)  
Qg  
7.6  
10  
-
Gate plateau voltage  
Gate charge total, sync. FET  
Output charge1)  
Vplateau  
Qg(sync)  
Qoss  
3.3  
13  
-
nC  
nC  
20  
27  
VDS=50ꢀV,ꢀVGS=0ꢀV  
1) Defined by design. Not subject to production test.  
2) See Gate charge waveformsfor parameter definition  
Final Data Sheet  
4
Rev.ꢀ2.3,ꢀꢀ2020-08-06  
OptiMOSTMꢀ5ꢀPower-Transistor,ꢀ100ꢀV  
BSC146N10LS5  
Tableꢀ7ꢀꢀꢀꢀꢀReverseꢀdiode  
Values  
Parameter  
Symbol  
Unit Noteꢀ/ꢀTestꢀCondition  
Min.  
Typ.  
-
Max.  
44  
Diode continuous forward current  
Diode pulse current  
IS  
-
-
-
-
-
A
TC=25ꢀ°C  
IS,pulse  
VSD  
trr  
-
176  
1.1  
52  
A
TC=25ꢀ°C  
Diode forward voltage  
0.9  
26  
19  
V
VGS=0ꢀV,ꢀIF=22ꢀA,ꢀTj=25ꢀ°C  
VR=50ꢀV,ꢀIF=22ꢀA,ꢀdiF/dt=100ꢀA/µs  
VR=50ꢀV,ꢀIF=22ꢀA,ꢀdiF/dt=100ꢀA/µs  
Reverse recovery time1)  
Reverse recovery charge1)  
ns  
nC  
Qrr  
38  
1) Defined by design. Not subject to production test.  
Final Data Sheet  
5
Rev.ꢀ2.3,ꢀꢀ2020-08-06  
OptiMOSTMꢀ5ꢀPower-Transistor,ꢀ100ꢀV  
BSC146N10LS5  
4ꢀꢀꢀꢀꢀElectricalꢀcharacteristicsꢀdiagrams  
Diagramꢀ1:ꢀPowerꢀdissipation  
Diagramꢀ2:ꢀDrainꢀcurrent  
60  
50  
50  
40  
30  
20  
10  
0
40  
30  
20  
10  
0
0
20  
40  
60  
80  
100  
120  
140  
160  
0
20  
40  
60  
80  
100  
120  
140  
160  
TCꢀ[°C]  
TCꢀ[°C]  
Ptot=f(TC)  
ID=f(TC);ꢀVGS10ꢀV  
Diagramꢀ3:ꢀSafeꢀoperatingꢀarea  
Diagramꢀ4:ꢀMax.ꢀtransientꢀthermalꢀimpedance  
103  
102  
single pulse  
0.01  
0.02  
0.05  
0.1  
0.2  
0.5  
1 µs  
102  
10 µs  
101  
100 µs  
1 ms  
101  
100  
10 ms  
100  
10-1  
10-2  
DC  
10-1  
10-2  
10-1  
100  
101  
102  
103  
10-5  
10-4  
10-3  
10-2  
10-1  
100  
VDSꢀ[V]  
tpꢀ[s]  
ID=f(VDS);ꢀTC=25ꢀ°C;ꢀD=0;ꢀparameter:ꢀtp  
ZthJC=f(tp);ꢀparameter:ꢀD=tp/T  
Final Data Sheet  
6
Rev.ꢀ2.3,ꢀꢀ2020-08-06  
OptiMOSTMꢀ5ꢀPower-Transistor,ꢀ100ꢀV  
BSC146N10LS5  
Diagramꢀ5:ꢀTyp.ꢀoutputꢀcharacteristics  
Diagramꢀ6:ꢀTyp.ꢀdrain-sourceꢀonꢀresistance  
175  
40  
7 V  
10 V  
35  
150  
3 V  
30  
25  
20  
15  
10  
5
5 V  
125  
100  
75  
50  
25  
0
3.2 V  
3.5 V  
4 V  
4.5 V  
4.5 V  
4 V  
5 V  
7 V  
10 V  
3.5 V  
3.2 V  
2.8 V  
3 V  
0
0
1
2
3
4
5
0
20  
40  
60  
80  
100  
VDSꢀ[V]  
IDꢀ[A]  
ID=f(VDS),ꢀTj=25ꢀ°C;ꢀparameter:ꢀVGS  
RDS(on)=f(ID),ꢀTj=25ꢀ°C;ꢀparameter:ꢀVGS  
Diagramꢀ7:ꢀTyp.ꢀtransferꢀcharacteristics  
Diagramꢀ8:ꢀTyp.ꢀdrain-sourceꢀonꢀresistance  
80  
40  
35  
30  
25  
20  
60  
25 °C  
150 °C  
150 °C  
40  
20  
0
15  
25 °C  
10  
5
0
0
1
2
3
4
5
6
0
2
4
6
8
10  
VGSꢀ[V]  
VGSꢀ[V]  
ID=f(VGS),ꢀ|VDS|>2|ID|RDS(on)max;ꢀparameter:ꢀTj  
RDS(on)=f(VGS),ꢀID=22ꢀA;ꢀparameter:ꢀTj  
Final Data Sheet  
7
Rev.ꢀ2.3,ꢀꢀ2020-08-06  
OptiMOSTMꢀ5ꢀPower-Transistor,ꢀ100ꢀV  
BSC146N10LS5  
Diagramꢀ9:ꢀNormalizedꢀdrain-sourceꢀonꢀresistance  
Diagramꢀ10:ꢀTyp.ꢀgateꢀthresholdꢀvoltage  
2.0  
2.4  
2.0  
1.6  
1.2  
0.8  
0.4  
0.0  
1.6  
1.2  
0.8  
0.4  
0.0  
230 µA  
23 µA  
-80  
-40  
0
40  
80  
120  
160  
-80  
-40  
0
40  
80  
120  
160  
Tjꢀ[°C]  
Tjꢀ[°C]  
RDS(on)=f(Tj),ꢀID=22ꢀA,ꢀVGS=10ꢀV  
VGS(th=f(Tj),ꢀVGS=VDS;ꢀparameter:ꢀID  
Diagramꢀ11:ꢀTyp.ꢀcapacitances  
Diagramꢀ12:ꢀForwardꢀcharacteristicsꢀofꢀreverseꢀdiode  
104  
103  
25 °C  
25 °C, max  
150 °C  
150 °C, max  
103  
102  
101  
100  
Ciss  
102  
101  
100  
Coss  
Crss  
0
20  
40  
60  
80  
100  
0.00  
0.25  
0.50  
0.75  
1.00  
1.25  
1.50  
VDSꢀ[V]  
VSDꢀ[V]  
C=f(VDS);ꢀVGS=0ꢀV;ꢀf=1ꢀMHz  
IF=f(VSD);ꢀparameter:ꢀTj  
Final Data Sheet  
8
Rev.ꢀ2.3,ꢀꢀ2020-08-06  
OptiMOSTMꢀ5ꢀPower-Transistor,ꢀ100ꢀV  
BSC146N10LS5  
Diagramꢀ13:ꢀAvalancheꢀcharacteristics  
Diagramꢀ14:ꢀTyp.ꢀgateꢀcharge  
102  
10  
20 V  
50 V  
80 V  
8
6
4
2
0
101  
25 °C  
100 °C  
125 °C  
100  
10-1  
100  
101  
102  
103  
0.0  
2.5  
5.0  
7.5  
10.0  
12.5  
15.0  
tAVꢀ[µs]  
Qgateꢀ[nC]  
IAS=f(tAV);ꢀRGS=25ꢀ;ꢀparameter:ꢀTj,start  
VGS=f(Qgate),ꢀID=22ꢀAꢀpulsed,ꢀTj=25ꢀ°C;ꢀparameter:ꢀVDD  
Diagramꢀ15:ꢀDrain-sourceꢀbreakdownꢀvoltage  
Diagram Gate charge waveforms  
108  
106  
104  
102  
100  
98  
96  
94  
-60  
-20  
20  
60  
100  
140  
180  
Tjꢀ[°C]  
VBR(DSS)=f(Tj);ꢀID=1ꢀmA  
Final Data Sheet  
9
Rev.ꢀ2.3,ꢀꢀ2020-08-06  
OptiMOSTMꢀ5ꢀPower-Transistor,ꢀ100ꢀV  
BSC146N10LS5  
5ꢀꢀꢀꢀꢀPackageꢀOutlines  
Figureꢀ1ꢀꢀꢀꢀꢀOutlineꢀPG-TDSON-8,ꢀdimensionsꢀinꢀmm  
Final Data Sheet  
10  
Rev.ꢀ2.3,ꢀꢀ2020-08-06  
OptiMOSTMꢀ5ꢀPower-Transistor,ꢀ100ꢀV  
BSC146N10LS5  
PG-TDSON-8: Recommended Boardpads & Apertures  
1.905  
1.905  
1.27  
3x  
0.6  
1.27  
3x  
0.5  
1.6  
0.2  
1.5  
0.5  
1.27  
3x  
1.27  
3x  
0.4  
1.905  
1.905  
copper  
solder mask  
stencil apertures  
all dimensions in mm  
Figure 2 Outline Boardpads (TDSON-8), dimensions in mm  
Final Data Sheet  
11  
Rev.ꢀ2.3,ꢀꢀ2020-08-06  
OptiMOSTM 5 Power-Transistor , 100 V  
BSC146N10LS5  
Revision History  
BSC146N10LS5  
Revision: 2020-08-06, Rev. 2.3  
Previous Revision  
Revision Date  
Subjects (major changes since last revision)  
2.0  
2.1  
2.2  
2.3  
Release of final version  
2016-09-30  
2019-05-10  
2019-05-20  
2020-08-06  
Update Rg, trr, Qrr, Diagrams 5, 8 and 9  
Update Id pulse, Diagrams 2, 3, 12  
Update Max Current Rating  
Trademarks  
All referenced product or service names and trademarks are the property of their respective owners.  
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Published by  
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Final Data Sheet  
12  
Rev. 2.3, 2020-08-06  

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