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BTS7002-1EPP [INFINEON]

PROFET™+2 12V | Automotive Smart High-Side Switch;
BTS7002-1EPP
型号： BTS7002-1EPP
厂家： Infineon    Infineon
描述：

PROFET™+2 12V | Automotive Smart High-Side Switch
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BTS7002-1EPP  
PROFET™ +2 12V  
1x 2.6 mΩ  
Smart High-Side Power Switch  
Package  
Marking  
PG-TSDSO-14  
7002-1P  
1
Overview  
Potential Applications  
•
•
•
Suitable for driving 21 A resistive, inductive and capacitive loads  
Replaces electromechanical relays, fuses and discrete circuits  
Suitable for driving glow plug, heating loads, DC motor and for power  
distribution  
VBAT  
ZWIRE  
Optional  
Optional  
CVS  
RGND  
CVSGND  
T1  
Logic Supply  
VDD  
GND  
VS  
GPIO  
RIN  
IN  
OUT  
GPIO  
RDEN  
DEN  
COUT0  
PROFET™ +2  
12V  
Microcontroller  
DZ2  
CVS2  
ADC  
VSS  
RADC  
RIS_PROT  
IS  
CSENSE  
DZ1  
Logic GND  
Power GND  
Optional  
Chassis GND  
*See Chapter 1 „Potential Applications“  
App_1CH_INTDIO_CVG.emf  
Figure 1  
BTS7002-1EPP Application Diagram. Further information in Chapter 10  
Data Sheet  
www.infineon.com  
Rev. 1.10  
2020-12-14  
1
BTS7002-1EPP  
PROFET™ +2 12V  
Overview  
Basic Features  
•
•
•
•
•
High-Side Switch with Diagnosis and Embedded Protection  
Part of PROFET™ +2 12V Family  
ReverseON for low power dissipation in Reverse Polarity  
Switch ON capability while Inverse Current condition (InverseON)  
Green Product (RoHS compliant)  
Protection Features  
•
•
•
•
Absolute and dynamic temperature limitation with controlled reactivation  
Overcurrent protection (tripping) with Intelligent Latch  
Undervoltage shutdown  
Overvoltage protection with external components (as shown in Figure 37)  
Diagnostic Features  
•
•
•
Proportional load current sense  
Open Load in ON and OFF state  
Short circuit to ground and battery  
Product Validation  
Qualified for automotive applications. Product validation according to AEC-Q100 Grade 1.  
Description  
The BTS7002-1EPP is a Smart High-Side Power Switch, providing protection functions and diagnosis.  
Table 1  
Product Summary  
Parameter  
Symbol  
VS(OP)  
Values  
4.1 V  
Minimum Operating voltage  
Minimum Operating voltage (cranking)  
Maximum Operating voltage  
VS(UV)  
3.1 V  
VS  
28 V  
Minimum Overvoltage protection (TJ ≥ 25 °C)  
Maximum current in OFF mode (TJ ≤ 85 °C)  
Maximum operative current  
VDS(CLAMP)_25  
IVS(OFF)_85  
IGND(ON_D)  
RDS(ON)_25  
RDS(ON)_150  
IL(NOM)  
35 V  
0.9 µA  
3 mA  
2.6 mΩ  
4.8 mΩ  
21 A  
Typical ON-state resistance (TJ = 25 °C)  
Maximum ON-state resistance (TJ = 150 °C)  
Nominal load current (TA = 85 °C)  
Minimum overload detection current  
Typical current sense ratio at IL = IL(NOM)  
IL(OVL0)_-40  
kILIS  
120 A  
22700  
Data Sheet  
2
Rev.1.10  
2020-12-14  
BTS7002-1EPP  
PROFET™ +2 12V  
Block Diagram and Terms  
2
Block Diagram and Terms  
2.1  
Block Diagram  
VS  
Supply Voltage  
Monitoring  
Overvoltage  
Protection  
Channel  
Internal Power Supply  
Voltage Sensor  
Intelligent Restart  
Control  
T
Overtemperature  
Overvoltage  
Clamping  
IS  
IN  
SENSE Output  
Gate Control  
+
Overcurrent  
Protection  
Driver  
Logic  
Chargepump  
ReverseON  
InverseON  
OUT  
ESD  
Protection  
+
DEN  
Load Current Sense  
Output Voltage Limitation  
Input Logic  
Internal Reverse  
PolarityProtection  
GND Circuitry  
GND  
Block_HEAT1ch.emf  
Figure 2  
Block Diagram of BTS7002-1EPP  
Data Sheet  
3
Rev. 1.10  
2020-12-14  
BTS7002-1EPP  
PROFET™ +2 12V  
Block Diagram and Terms  
2.2  
Terms  
Figure 3 shows all terms used in this data sheet, with associated convention for positive values.  
IVS  
VSIS  
VS  
IIN  
VDS  
IN  
IDEN  
DEN  
IL  
VS  
OUT  
VIN  
IIS  
VDEN  
IS  
VOUT  
GND  
VIS  
IGND  
Terms_1CH.emf  
Figure 3  
Voltage and Current Convention  
Data Sheet  
4
Rev. 1.10  
2020-12-14  
BTS7002-1EPP  
PROFET™ +2 12V  
Pin Configuration  
3
Pin Configuration  
3.1  
Pin Assignment  
GND  
1
2
3
4
5
6
14  
13  
12  
11  
10  
9
OUT  
OUT  
OUT  
n.c.  
IN  
DEN  
IS  
n.c.  
n.c.  
n.c.  
VS  
OUT  
OUT  
OUT  
7 exposed pad (bottom)  
8
PinOut_PROFET1ch_PDH.emf  
Figure 4  
Pin Configuration  
Data Sheet  
5
Rev. 1.10  
2020-12-14  
BTS7002-1EPP  
PROFET™ +2 12V  
Pin Configuration  
3.2  
Pin Definitions and Functions  
Table 2  
Pin  
Pin Definition  
Symbol  
Function  
EP  
VS  
Supply Voltage  
(exposed pad)  
Battery voltage  
1
2
GND  
Ground  
Signal ground  
IN  
Input Channel  
Digital signal to switch ON the channel (“high” active)  
If not used: connect to GND pin or to module ground with resistor RIN = 4.7 kΩ  
3
DEN  
Diagnostic Enable  
Digital signal to enable device diagnosis (“high” active) and to clear the  
protection latch of channel  
If not used: connect to GND pin or to module ground with resistor RDEN = 4.7 kΩ  
4
IS  
SENSE current output  
Analog/digital signal for diagnosis  
If not used: left open  
5-7, 11  
n.c.  
Not connected, internally not bonded  
8-10, 12- OUT  
14  
Output  
Protected high-side power output channel1)  
1) All output pins of the channel must be connected together on the PCB. All pins of the output are internally connected  
together. PCB traces have to be designed to withstand the maximum current which can flow.  
Data Sheet  
6
Rev. 1.10  
2020-12-14  
BTS7002-1EPP  
PROFET™ +2 12V  
General Product Characteristics  
4
General Product Characteristics  
4.1  
Absolute Maximum Ratings - General  
Table 3  
Absolute Maximum Ratings1)  
TJ = -40 °C to +150 °C; all voltages with respect to ground, positive current flowing into pin  
(unless otherwise specified)  
Parameter  
Symbol  
Values  
Typ.  
Unit Note or  
Test Condition  
Number  
Min.  
Max.  
Supply pins  
Power Supply Voltage  
Load Dump Voltage  
VS  
-0.3  
–
–
–
28  
35  
V
V
–
P_4.1.0.1  
P_4.1.0.3  
VBAT(LD)  
suppressed  
Load Dump  
acc. to  
ISO16750-2  
(2010).  
Ri = 2 Ω  
Supply Voltage for Short Circuit VBAT(SC)  
Protection  
0
–
–
–
24  
16  
V
V
Setup acc. to  
AEC-Q100-012  
P_4.1.0.25  
P_4.1.0.5  
Reverse Polarity Voltage  
-VBAT(REV)  
t ≤ 2 min  
TA = +25 °C  
Setup as  
described in  
Chapter 10  
Current through GND Pin  
IGND  
-50  
–
50  
mA  
RGND according P_4.1.0.9  
to Chapter 10  
Logic & control pins (Digital Input = DI)  
DI = IN, DEN  
2)  
Current through DI Pin  
IDI  
-1  
-1  
–
–
2
mA  
mA  
P_4.1.0.14  
2)  
Current through DI Pin  
IDI(REV)  
10  
P_4.1.0.36  
Reverse Battery Condition  
t ≤ 2 min  
IS pin  
Voltage at IS Pin  
Current through IS Pin  
VIS  
IIS  
-1.5  
-25  
–
–
VS  
V
IIS = 10 μA  
P_4.1.0.16  
P_4.1.0.18  
IIS(SAT),M mA  
–
AX  
Temperatures  
Junction Temperature  
Storage Temperature  
TJ  
-40  
-55  
–
–
150  
150  
°C  
°C  
–
–
P_4.1.0.19  
P_4.1.0.20  
TSTG  
Data Sheet  
7
Rev. 1.10  
2020-12-14  
BTS7002-1EPP  
PROFET™ +2 12V  
General Product Characteristics  
Table 3  
Absolute Maximum Ratings1) (continued)  
TJ = -40 °C to +150 °C; all voltages with respect to ground, positive current flowing into pin  
(unless otherwise specified)  
Parameter  
Symbol  
Values  
Typ.  
Unit Note or  
Test Condition  
Number  
Min.  
Max.  
ESD Susceptibility  
ESD Susceptibility all Pins  
(HBM)  
VESD(HBM)  
-2  
–
–
–
–
2
kV  
kV  
V
HBM3)  
P_4.1.0.21  
P_4.1.0.22  
P_4.1.0.23  
P_4.1.0.24  
ESD Susceptibility OUT vs GND VESD(HBM)_OU -4  
and VS connected (HBM)  
4
HBM3)  
CDM4)  
CDM4)  
T
ESD Susceptibility all Pins  
(CDM)  
VESD(CDM)  
-500  
500  
750  
ESD Susceptibility Corner Pins VESD(CDM)_CR -750  
V
(CDM)  
N
(pins 1, 7, 8, 14)  
1) Not subject to production test - specified by design.  
2) Maximum VDI to be considered for Latch-Up tests: 5.5 V.  
3) ESD susceptibility, Human Body Model “HBM”, according to AEC Q100-002.  
4) ESD susceptibility, Charged Device Model “CDM”, according to AEC Q100-011.  
Notes  
1. Stresses above the ones listed here may cause permanent damage to the device. Exposure to absolute  
maximum rating conditions for extended periods may affect device reliability.  
2. Integrated protection functions are designed to prevent IC destruction under fault conditions described in the  
data sheet. Fault conditions are considered as “outside” normal operating range. Protection functions are  
not designed for continuous repetitive operation.  
Data Sheet  
8
Rev. 1.10  
2020-12-14  
BTS7002-1EPP  
PROFET™ +2 12V  
General Product Characteristics  
4.2  
Absolute Maximum Ratings - Power Stages  
4.2.1  
Power Stage - 2 mΩ  
Table 4  
Absolute Maximum Ratings1)  
TJ = -40 °C to +150 °C; all voltages with respect to ground, positive current flowing into pin  
(unless otherwise specified)  
Parameter  
Symbol  
Values  
Typ.  
–
Unit Note or  
Test Condition  
Number  
Min.  
Max.  
Maximum Energy Dissipation  
Single Pulse  
EAS  
–
315  
mJ  
IL = 2*IL(NOM)  
TJ(0) = 150 °C  
VS = 28 V  
P_4.2.10.1  
Maximum Energy Dissipation  
Repetitive Pulse  
EAR  
–
–
–
74  
mJ  
IL = IL(NOM)  
TJ(0) = 85 °C  
VS = 13.5 V  
1M cycles  
P_4.2.10.2  
P_4.2.10.3  
Load Current  
|IL|  
–
IL(OVL0),  
A
–
MAX  
1) Not subject to production test - specified by design.  
4.3  
Functional Range  
Table 5  
Functional Range - Supply Voltage and Temperature1)  
Parameter  
Symbol  
Values  
Unit Note or  
Test Condition  
Number  
Min. Typ. Max.  
Supply Voltage Range for  
Normal Operation  
VS(NOR)  
6
13.5  
18  
V
–
P_4.3.0.1  
P_4.3.0.2  
2)3)  
Lower Extended Supply  
VS(EXT,LOW)  
3.1  
–
6
V
Voltage Range for Operation  
(parameter  
deviations possible)  
Supply Voltage Range  
reached after Overload  
Protection activation  
leading to“Undervoltage on  
VS” condition  
VS(EXT,CVG)  
–
–
3.1  
V
CVSGND is required  
when the Overload  
Protection is  
triggered (see  
Chapter 8.2) and  
the observed  
P_4.3.0.7  
number of retries is  
different from what  
specified in  
Chapter 8.3.1  
Data Sheet  
9
Rev. 1.10  
2020-12-14  
BTS7002-1EPP  
PROFET™ +2 12V  
General Product Characteristics  
Table 5  
Functional Range - Supply Voltage and Temperature1) (continued)  
Parameter  
Symbol  
Values  
Unit Note or  
Test Condition  
Number  
Min. Typ. Max.  
3)  
Upper Extended Supply  
VS(EXT,UP)  
18  
–
28  
V
P_4.3.0.3  
Voltage Range for Operation  
(parameter  
deviations possible)  
Junction Temperature  
TJ  
-40  
–
150 °C  
–
P_4.3.0.5  
1) Not subject to production test - specified by design.  
2) In case of VS voltage decreasing: VS(EXT,LOW),MIN = 3.1 V. In case of VS voltage increasing: VS(EXT,LOW),MIN = 4.1 V.  
3) Protection functions still operative.  
Note:  
Within the functional or operating range, the IC operates as described in the circuit description. The  
electrical characteristics are specified within the conditions given in the Electrical Characteristics  
tables.  
4.4  
Thermal Resistance  
Note:  
This thermal data was generated in accordance with JEDEC JESD51 standards. For more  
information, go to www.jedec.org.  
Table 6  
Thermal Resistance1)  
Parameter  
Symbol  
Values  
Typ.  
3
Unit Note or  
Test Condition  
Number  
Min.  
Max.  
2)  
Thermal Characterization  
Parameter Junction-Top  
ΨJTOP  
–
5
K/W  
P_4.4.0.1  
P_4.4.0.2  
2)  
Thermal Resistance  
Junction-to-Case  
RthJC  
–
–
0.78  
30.7  
1.3  
–
K/W  
simulated at  
exposed pad  
2)  
Thermal Resistance  
Junction-to-Ambient  
RthJA  
K/W  
P_4.4.0.3  
1) Not subject to production test - specified by design.  
2) According to Jedec JESD51-2,-5,-7 at natural convection on FR4 2s2p board; the Product (Chip + Package) was  
simulated on a 76.2 × 114.3 × 1.5 mm board with 2 inner copper layers (2 × 70 µm Cu, 2 × 35 µm Cu). Where applicable  
a thermal via array under the exposed pad contacted the first inner copper layer. Simulation done at TA = 105°C,  
P
DISSIPATION = 1 W.  
Data Sheet  
10  
Rev. 1.10  
2020-12-14  
BTS7002-1EPP  
PROFET™ +2 12V  
General Product Characteristics  
4.4.1  
PCB Setup  
70 µm modeled (traces, cooling area)  
70 µm, 5% metalization*  
*: means percentual Cu metalization on each layer  
PCB_Zth_1s0p.emf  
Figure 5  
1s0p PCB Cross Section  
70 µm modeled (traces)  
35 µm, 90% metalization*  
35 µm, 90% metalization*  
70 µm, 5% metalization*  
*: means percentual Cu metalization on each layer  
PCB_Zth_2s2p.emf  
Figure 6  
2s2p PCB Cross Section  
PCB 1s0p + 600 mm2 cooling  
PCB 2s2p / 1s0p footprint  
PCB_sim_setup_TSDSO14.emf  
Figure 7  
PCB setup for thermal simulations  
PCB_ 2s2p_vias_TSDSO14.emf  
Figure 8  
Thermal vias on PCB for 2s2p PCB setup  
Data Sheet  
11  
Rev. 1.10  
2020-12-14  
BTS7002-1EPP  
PROFET™ +2 12V  
General Product Characteristics  
4.4.2  
Thermal Impedance  
BTS7002-1EPx  
100  
10  
1
2s2p  
1s0p - 600 mm²  
1s0p - 300 mm²  
1s0p - footprint  
0,1  
0,0001  
0,001  
0,01  
0,1  
1
10  
100  
1000  
Time (s)  
Figure 9  
Typical Thermal Impedance. PCB setup according Chapter 4.4.1  
BTS7002-1EPx  
120  
110  
100  
90  
1s0p - Ta = 105°C  
80  
70  
60  
50  
40  
30  
0
100  
200  
300  
400  
500  
600  
Cooling area (mm²)  
Figure 10 Thermal Resistance on 1s0p PCB with various cooling surfaces  
Data Sheet  
12  
Rev. 1.10  
2020-12-14  
BTS7002-1EPP  
PROFET™ +2 12V  
Logic Pins  
5
Logic Pins  
The device has 2 digital pins.  
5.1  
Input Pin (IN)  
The input pin IN activates the output channel. The input circuitry is compatible with 3.3V and 5V  
microcontroller (see Chapter 10 for the complete application setup overview). The electrical equivalent of the  
input circuitry is shown in Figure 11. In case the pin is not used, it should be pulled to module GND or device  
GND pin via RIN = 4.7 kΩ.  
VS  
IN  
VS(CLAMP)  
IDI  
IDI  
ESD  
VDI(CLAMP)  
VDI  
GND  
IGND  
Input_IN_INTDIO.emf  
Figure 11 Input circuitry  
The logic thresholds for “low” and “high” states are defined by parameters VDI(TH) and VDI(HYS). The relationship  
between these two values is shown in Figure 12. The voltage VIN needed to ensure a “high” state is always  
higher than the voltage needed to ensure a “low” state.  
VDI  
VDI(TH ),MAX  
VDI(TH)  
VDI(HYS)  
VDI(TH ),MIN  
t
Internal channel  
activation signal  
0
x
1
x
0
t
Input_VDITH_2.emf  
Figure 12 Input Threshold voltages and hysteresis  
Data Sheet  
13  
Rev. 1.10  
2020-12-14  
BTS7002-1EPP  
PROFET™ +2 12V  
Logic Pins  
5.2  
Diagnosis Pin  
The Diagnosis Enable (DEN) pin controls the diagnosis circuitry and can be used to reset the latched protection  
(Protection circuitry not disabled by DEN). When DEN pin is set to “high”, the diagnosis is enabled (see  
Chapter 9.2 for more details). When it is set to “low”, the diagnosis is disabled (IS pin is set to high  
impedance).  
The transition from “high” to “low” of DEN pin clears the protection latch of the channel depending on the  
logic state of IN pin and DEN pulse length (see Chapter 8.3 for more details). The internal structure of  
diagnosis pins is the same as the one of input pins. See Figure 11 for more details.  
5.3  
Electrical Characteristics Logic Pins  
VS = 6 V to 18 V, TJ = -40 °C to +150 °C  
Typical values: VS = 13.5 V, TJ = 25 °C  
Digital Input (DI) pins = IN, DEN  
Table 7  
Electrical Characteristics: Logic Pins - General  
Parameter  
Symbol  
Values  
Typ.  
1.3  
Unit Note or  
Test Condition  
Number  
Min.  
Max.  
Digital Input Voltage  
Threshold  
VDI(TH)  
0.8  
2
V
See Figure 11 and P_5.4.0.1  
Figure 12  
1)  
Digital Input Clamping  
Voltage  
VDI(CLAMP1)  
–
7
–
V
P_5.4.0.2  
IDI = 1 mA  
See Figure 11 and  
Figure 12  
Digital Input Clamping  
Voltage  
VDI(CLAMP2)  
VDI(HYS)  
IDI(H)  
6.5  
–
7.5  
0.25  
10  
8.5  
–
V
IDI = 2 mA  
See Figure 11 and  
Figure 12  
1)  
P_5.4.0.3  
P_5.4.0.4  
P_5.4.0.5  
P_5.4.0.6  
Digital Input Hysteresis  
V
See Figure 11 and  
Figure 12  
Digital Input Current  
(“high”)  
2
25  
25  
µA  
µA  
VDI = 2 V  
See Figure 11 and  
Figure 12  
Digital Input Current (“low”) IDI(L)  
2
10  
VDI = 0.8 V  
See Figure 11 and  
Figure 12  
1) Not subject to production test - specified by design.  
Data Sheet  
14  
Rev. 1.10  
2020-12-14  
BTS7002-1EPP  
PROFET™ +2 12V  
Power Supply  
6
Power Supply  
The BTS7002-1EPP is supplied by VS, which is used for the internal logic as well as supply for the power output  
stage. VS has an undervoltage detection circuit, which prevents the activation of the power output stage and  
diagnosis in case the applied voltage is below the undervoltage threshold (VS < VS(OP)). During power up, the  
internal power on signal is set when supply voltage (VS) exceeds the minimum operating voltage (VS > VS(OP)).  
6.1  
Operation Modes  
BTS7002-1EPP has the following operation modes in case of VS > VS(OP)  
:
•
•
•
•
•
OFF mode  
ON mode  
Diagnosis in ON mode  
Diagnosis in OFF mode  
Fault  
The transition between operation modes is determined according to these variables:  
•
•
•
Logic level at IN pin  
Logic level at DEN pin  
Internal latch  
The truth table in case of VS > VS(OP) is shown in Table 8. The behavior of BTS7002-1EPP as well as some  
parameters may change in dependence on the operation mode of the device.  
There are three parameters describing each operation mode of BTS7002-1EPP:  
•
•
•
Status of the output channel  
Status of the diagnosis  
Current consumption at VS pin (measured by IVS in OFF mode, IGND in all other operative modes)  
Table 8  
IN  
Operation Mode truth table  
DEN  
Internal IIS  
Operative Mode Comment  
latch  
L
L
L
L
L
leakage  
OFF  
DMOS channel is OFF  
L
H
L
leakage  
leakage  
open load  
fault  
OFF  
DMOS channel is OFF  
H
OFF_DIAG  
Diagnostic in OFF-mode  
Diagnostic in OFF-mode  
Diagnostic in OFF-mode  
DMOS channel is ON, no diagnostic  
L
H
L
H
L
H
H
leakage  
leakage  
ON  
L
H
fault  
DMOS channel is switched OFF due to  
failure  
H
H
H
H
L
IIS  
ON_DIAG  
fault  
DMOS channel is ON and diagnostic  
H
fault  
DMOS channel is switched OFF due to  
failure  
Data Sheet  
15  
Rev. 1.10  
2020-12-14  
BTS7002-1EPP  
PROFET™ +2 12V  
Power Supply  
6.1.1  
OFF mode  
When BTS7002-1EPP is in OFF mode, the output channel is OFF. The current consumption is minimum (see  
parameter IVS(OFF)). No Overtemperature, Overload protection mechanism and no diagnosis function is active  
when the device is in OFF mode.  
6.1.2  
ON mode  
ON (IN = High; DEN = Low) mode is the normal operation mode of BTS7002-1EPP. Device current consumption  
is specified with IGND(ON_D) + IIS(OFF) (measured at GND pin because the current at VS pin includes the load  
current). Overcurrent and Overtemperature protections are active. No diagnosis function is active.  
6.1.3  
OFF_Diag mode  
The device is in OFF_Diag mode as long as DEN pin is set to “high” and IN pin is set to “low”. The output  
channel is OFF. Depending on the load condition, either a fault current IIS(FAULT) or an Open Load in OFF current  
(IIS(OLOFF)) may be present at IS pin. In such situation, the current consumption of the device is increased.  
6.1.4  
ON_Diag mode  
The device is in ON_Diag mode with current sense function enabled. IIS is present at IS pin. Device current  
consumption is specified with IGND(ON_D). Depending on the load condition, either a fault current IIS(FAULT) or IIS  
current may be present at IS pin.  
6.1.5  
Fault mode  
The device is in Fault mode as soon as a protection event happens which affects that the device switches off  
due to its protection function. In Fault mode, a IIS(FAULT) signal is presenting at IS pin during the DEN signal is  
"high".  
Data Sheet  
16  
Rev. 1.10  
2020-12-14  
BTS7002-1EPP  
PROFET™ +2 12V  
Power Supply  
6.2  
Undervoltage on VS  
Between VS(OP) and VS(UV) the undervoltage mechanism is triggered. If the device is operative (in ON mode) and  
the supply voltage drops below the undervoltage threshold VS(UV), the internal logic switches OFF the output  
channel.  
As soon as the supply voltage VS is above the operative threshold VS(OP), the channel is switched ON again. The  
restart is delayed with a time tDELAY(UV) which protects the device in case the undervoltage condition is caused  
by a short circuit event (according to AEC-Q100-012), as shown in Figure 13.  
If the device is in OFF mode and the input is set to “high”, the channel will be switched ON if VS > VS(OP) without  
waiting for tDELAY(UV)  
.
VS  
VS(OP)  
VS(UV)  
VS(HYS)  
t
t
Channel  
activation signal  
VOUT  
tDELAY(UV)  
t
PowerSupply_UVRVS.emf  
Figure 13 VS undervoltage behavior  
Data Sheet  
17  
Rev. 1.10  
2020-12-14  
BTS7002-1EPP  
PROFET™ +2 12V  
Power Supply  
6.3  
Electrical Characteristics Power Supply  
VS = 6 V to 18 V, TJ = -40 °C to +150 °C  
Typical values: VS = 13.5 V, TJ = 25 °C  
Typical resistive load connected to the output for testing (unless otherwise specified):  
RL = 2.1 Ω  
Table 9  
Electrical Characteristics: Power Supply - General  
Parameter  
Symbol  
Values  
Typ.  
Unit Note or  
Test Condition  
Number  
Min.  
Max.  
VS pin  
Power Supply Undervoltage VS(UV)  
Shutdown  
1.8  
2.3  
3.0  
3.1  
V
VS decreasing  
IN = “high”  
From VDS ≤ 0.5 V to  
P_6.4.0.1  
V
DS = VS  
See Figure 13  
Power Supply Minimum  
Operating Voltage  
VS(OP)  
2.0  
4.1  
V
VS increasing  
IN = “high”  
P_6.4.0.3  
From VDS = VS to  
V
DS ≤ 0.5 V  
See Figure 13  
1)  
Power Supply Undervoltage VS(HYS)  
Shutdown Hysteresis  
–
0.7  
5
–
V
P_6.4.0.6  
P_6.4.0.7  
P_6.4.0.9  
VS(OP) - VS(UV)  
See Figure 13  
Power Supply Undervoltage tDELAY(UV)  
Recovery Time  
2.5  
16  
7.5  
30  
ms  
V
dVS/dt ≤ 0.5 V/µs  
VS ≥ -1 V  
See Figure 13  
1)  
Breakdown Voltage  
between GND and VS Pins in  
Reverse Battery  
-VS(REV)  
–
IGND(REV) = 7 mA  
TJ = 150 °C  
1) Not subject to production test - specified by design.  
Data Sheet  
18  
Rev. 1.10  
2020-12-14  
BTS7002-1EPP  
PROFET™ +2 12V  
Power Supply  
6.4  
Electrical Characteristics Power Supply - Product Specific  
VS = 6 V to 18 V, TJ = -40 °C to +150 °C  
Typical values: VS = 13.5 V, TJ = 25 °C  
Typical resistive load connected to the output for testing (unless otherwise specified):  
RL = 2.1 Ω  
6.4.1  
BTS7002-1EPP  
Table 10 Electrical Characteristics: Power Supply BTS7002-1EPP  
Parameter  
Symbol  
Values  
Typ.  
0.1  
Unit Note or  
Test Condition  
Number  
Min.  
Max.  
1)  
Supply Current  
IVS(OFF)_85  
–
0.9  
µA  
P_6.5.20.1  
Consumption in OFF Mode  
with Loads  
VS = 18 V  
VOUT = 0 V  
IN = DEN = “low”  
TJ ≤ 85 °C  
Supply Current  
IVS(OFF)_150  
–
1
27  
µA  
VS = 18 V  
P_6.5.20.2  
Consumption in OFF Mode  
with Loads  
VOUT = 0 V  
IN = DEN = “low”  
TJ = 150 °C  
Operating Current in  
ON_Diag Mode (Channel  
ON)  
IGND(ON_D)  
–
–
2
3
mA  
mA  
VS = 18 V  
IN = DEN = “high”  
P_6.5.20.3  
P_6.5.20.5  
Operating Current in  
OFF_Diag Mode  
IGND(OFF_D)  
1.2  
1.8  
VS = 18 V  
IN = “low”;  
DEN = “high”  
1) Not subject to production test - specified by design.  
Data Sheet  
19  
Rev. 1.10  
2020-12-14  
BTS7002-1EPP  
PROFET™ +2 12V  
Power Stages  
7
Power Stages  
The high-side power stage is built using a N-channel vertical Power MOSFET with charge pump.  
7.1  
Output ON-State Resistance  
The ON-state resistance RDS(ON) depends mainly on junction temperature TJ. Figure 14 shows the variation of  
RDS(ON) across the whole TJ range. The value “2” on the y-axis corresponds to the maximum RDS(ON) measured  
at TJ = 150 °C.  
RDS(ON) variation over TJ  
2.20  
Reference value:  
"2" = RDS(ON),MAX @ 150 °C  
2.00  
1.80  
1.60  
1.40  
1.20  
1.00  
0.80  
0.60  
0.40  
Typical  
0.20  
0.00  
-40  
-30  
-20  
-10  
0
10  
20  
30  
40  
50  
60  
70  
80  
90  
100  
110  
120  
130  
140  
150  
160  
Junction Temperature (°C)  
Figure 14  
RDS(ON) variation factor  
The behavior in Reverse Polarity is described in Chapter 8.4.1.  
Data Sheet  
20  
Rev. 1.10  
2020-12-14  
BTS7002-1EPP  
PROFET™ +2 12V  
Power Stages  
7.2  
Switching loads  
7.2.1  
Switching Resistive Loads  
When switching resistive loads, the switching times and slew rates shown in Figure 15 can be considered. The  
switch energy values EON and EOFF are proportional to load resistance and times tON and tOFF  
.
IN  
VIN(TH)  
VIN(HYS)  
t
VOUT  
tON  
90% of VS  
tOFF(DELAY)  
70% of VS  
70% of VS  
30% of VS  
-(dV/dt)OFF  
(dV/dt)ON  
30% of VS  
10% of VS  
tON(DELAY)  
tOFF  
t
PDMOS  
EON  
EOFF  
t
Power St age_SwitchRes.emf  
Figure 15 Switching a Resistive Load  
Data Sheet  
21  
Rev. 1.10  
2020-12-14  
BTS7002-1EPP  
PROFET™ +2 12V  
Power Stages  
7.2.2  
Switching Inductive Loads  
When switching OFF inductive loads with high-side switches, the voltage VOUT drops below ground potential,  
because the inductance intends to continue driving the current. To prevent the destruction of the device due  
to overvoltage, a voltage clamp mechanism is implemented. The clamping structure limits the negative  
output voltage so that VDS = VDS(CLAMP). Figure 16 shows a concept drawing of the implementation. The  
clamping structure is available in all operation modes listed in Chapter 6.1.  
VS  
High-side  
Channel  
VS  
VDS  
VSIS(CLAMP)  
VDS(CLAMP)  
IS  
IL  
VOUT  
VS(CLAMP)  
OUT  
GND  
L,  
RL  
IL  
PowerStage_Clamp_INTDIO_1CH.emf  
Figure 16 Output Clamp concept  
During demagnetization of inductive loads, energy has to be dissipated in BTS7002-1EPP. The energy can be  
calculated with Equation (7.1):  
RL IL  
ln 1 – ------------------------------------------- + IL  
VS – VDS(CLAMP)  
-------------------------------------------  
RL  
L
RL  
æ
ö
------  
E = VDS(CLAMP)  
(7.1)  
è
ø
VS – VDS(CLAMP)  
The maximum energy, therefore the maximum inductance for a given current, is limited by the thermal design  
of the component. Please refer to Chapter 4.2 for the maximum allowed values of EAS (single pulse energy)  
and EAR (repetitive energy).  
Data Sheet  
22  
Rev. 1.10  
2020-12-14  
BTS7002-1EPP  
PROFET™ +2 12V  
Power Stages  
7.2.3  
Output Voltage Limitation  
To increase the current sense accuracy, VDS voltage is monitored. When the output current IL decreases while  
the channel is diagnosed (DEN pin set to “high” - see Figure 17) bringing VDS equal or lower than VDS(SLC), the  
output DMOS gate is partially discharged. This increases the output resistance so that VDS = VDS(SLC) even for  
very small output currents. The VDS increase allows the current sensing circuitry to work more efficiently,  
providing better kILIS accuracy for output current in the low range.  
IN  
t
DEN  
t
IL  
t
t
VDS  
VDS(SLC)  
Figure 17 Output Voltage Limitation activation during diagnosis  
7.3  
Advanced Switching Characteristics  
7.3.1  
Inverse Current behavior  
When VOUT > VS, a current IINV flows into the power output transistor (see Figure 18). This condition is known  
as “Inverse Current”.  
If the channel is in OFF state, the current flows through the intrinsic body diode generating high power losses  
therefore an increase of overall device temperature. If the channel is in ON state, RDS(INV) can be expected and  
power dissipation in the output stage is comparable to normal operation in RDS(ON)  
.
During Inverse Current condition, the channel remains in ON or OFF state as long as |-IL| < |-IL(INV)|.  
With InverseON, it is possible to switch ON the channel during Inverse Current condition as long as |-IL| < |-IL(INV)  
(see Figure 19).  
|
Data Sheet  
23  
Rev. 1.10  
2020-12-14  
BTS7002-1EPP  
PROFET™ +2 12V  
Power Stages  
VBAT  
VS  
Gate  
Driver  
VOUT > VS  
-IL  
Device  
Logic  
INV  
Comp.  
OUT  
GND  
PowerStage_Inverse_HEAT.emf  
Figure 18 Inverse Current Circuitry  
IN  
IN  
CASE 1 : Switch is ON  
CASE 2 : Switch is OFF  
OFF  
ON  
t
t
t
IL  
IL  
NORMAL  
NORMAL  
NORMAL  
NORMAL  
t
INVERSE  
OFF  
INVERSE  
ON  
DMOS state  
DMOS state  
t
t
CASE 3 : Switch ON into Inverse Current  
CASE 4 : Switch OFF into Inverse Current  
IN  
IN  
OFF  
ON  
OFF  
ON  
t
t
IL  
IL  
NORMAL  
NORMAL  
NORMAL  
NORMAL  
t
t
t
t
INVERSE  
INVERSE  
DMOS state  
DMOS state  
ON  
OFF  
OFF  
ON  
PowerStage_InvCurr_INVON.emf  
Figure 19 InverseON - Channel behavior in case of applied Inverse Current  
Note:  
No protection mechanism like Overtemperature or Overload protection is active during applied  
Inverse Currents.  
Data Sheet  
24  
Rev. 1.10  
2020-12-14  
BTS7002-1EPP  
PROFET™ +2 12V  
Power Stages  
7.3.2  
Cross Current robustness with H-Bridge configuration  
When BTS7002-1EPP is used as high-side switch e.g. in a bridge configuration (therefore paired with a low-side  
switch as shown in Figure 20), the maximum slew rate applied to the output by the low-side switch must be  
lower than | dVOUT / dt |. Otherwise the output stage may turn ON in linear mode (not in RDS(ON)) while the low-  
side switch is commutating. This creates an unprotected overheating for the DMOS due to the cross-  
conduction current.  
VBAT  
R/L cable  
HSS1  
HSS 2  
VS  
VS  
T
T
IN  
OFF  
ON(DC) IN  
OUT  
OUT  
| dVOUT /dt |  
Cross  
Current  
Current through Motor  
M
ON( PWM)  
OFF  
PowerStag_e PassiveSlew_ PROFET1Ch.emf  
Figure 20 High-Side switch used in Bridge configuration  
Data Sheet  
25  
Rev. 1.10  
2020-12-14  
BTS7002-1EPP  
PROFET™ +2 12V  
Power Stages  
7.4  
Electrical Characteristics Power Stages  
VS = 6 V to 18 V, TJ = -40 °C to +150 °C  
Typical values: VS = 13.5 V, TJ = 25 °C  
Typical resistive load connected to the output for testing (unless otherwise specified):  
RL = 2.1 Ω  
Table 11 Electrical Characteristics: Power Stages - General  
Parameter  
Symbol  
Values  
Typ.  
Unit Note or  
Test Condition  
Number  
Min.  
Max.  
Voltages  
Drain to Source Clamping VDS(CLAMP)_-40 33  
Voltage at TJ = -40 °C  
36.5  
38  
42  
V
V
IL = 5 mA  
P_7.4.0.1  
P_7.4.0.2  
TJ = -40°C  
See Figure 16  
1)  
Drain to Source Clamping VDS(CLAMP)_25 35  
Voltage at TJ ≥ 25 °C  
44  
IL = 5 mA  
TJ ≥ 25°C  
See Figure 16  
1) Tested at TJ = 150°C.  
7.4.1  
Electrical Characteristics Power Stages  
Table 12 Electrical Characteristics: Power Stages  
Parameter  
Symbol  
Values  
Typ.  
Unit Note or  
Number  
Test Condition  
Min.  
Max.  
Timings  
Switch-ON Delay  
tON(DELAY)  
tOFF(DELAY)  
tON  
10  
70  
130  
μs  
μs  
μs  
μs  
μs  
VS = 13.5 V  
P_7.4.5.1  
P_7.4.5.2  
P_7.4.5.3  
P_7.4.5.4  
P_7.4.5.5  
V
OUT = 10% VS  
See Figure 15  
Switch-OFF Delay  
Switch-ON Time  
Switch-OFF Time  
10  
50  
30  
-60  
50  
160  
210  
220  
90  
VS = 13.5 V  
VOUT = 90% VS  
See Figure 15  
130  
100  
25  
VS = 13.5 V  
V
OUT = 90% VS  
See Figure 15  
tOFF  
VS = 13.5 V  
V
OUT = 10% VS  
See Figure 15  
Switch-ON/OFF Matching  
ΔtSW  
VS = 13.5 V  
tON - tOFF  
Data Sheet  
26  
Rev. 1.10  
2020-12-14  
BTS7002-1EPP  
PROFET™ +2 12V  
Power Stages  
Table 12 Electrical Characteristics: Power Stages (continued)  
Parameter  
Symbol  
Values  
Typ.  
Unit Note or  
Test Condition  
Number  
Min.  
Max.  
Voltage Slope  
Switch-ON Slew Rate  
(dV/dt)ON  
0.16  
0.27  
0.39  
V/μs VS = 13.5 V  
P_7.4.5.6  
V
OUT = 30% to 70%  
of VS  
See Figure 15  
Switch-OFF Slew Rate  
-(dV/dt)OFF  
0.16  
0.27  
0.39  
V/μs VS = 13.5 V  
P_7.4.5.7  
VOUT = 70% to 30%  
of VS  
See Figure 15  
Slew Rate Matching  
(dV/dt)ON - (dV/dt)OFF  
Δ(dV/dt)SW  
-0.15  
2
0
+0.15 V/μs VS = 13.5 V  
P_7.4.5.8  
P_7.4.5.9  
Voltages  
1)  
Output Voltage Drop  
Limitation at Small Load  
Currents  
VDS(SLC)  
10  
20  
mV  
IOUT = IOUT(OL) = 20  
mA  
1) Not subject to production test - specified by design  
7.5  
Electrical Characteristics - Power Output Stages  
VS = 6 V to 18 V, TJ = -40 °C to +150 °C  
Typical values: VS = 13.5 V, TJ = 25 °C  
Typical resistive load connected to the output for testing (unless otherwise specified):  
RL = 2.1 Ω  
7.5.1  
Power Output Stage - 2 mΩ  
Table 13 Electrical Characteristics: Power Stages - 2 mΩ  
Parameter  
Symbol  
Values  
Typ.  
Unit Note or  
Test Condition  
Number  
Min.  
Max.  
Output characteristics  
1)  
ON-State Resistance at  
TJ = 25 °C  
RDS(ON)_25  
RDS(ON)_150  
–
–
–
2.6  
–
–
mΩ  
mΩ  
mΩ  
P_7.5.10.1  
P_7.5.10.2  
P_7.5.10.3  
TJ = 25 °C  
TJ = 150 °C  
ON-State Resistance at  
TJ = 150 °C  
4.8  
6
ON-State Resistance in  
Cranking  
RDS(ON)_CRAN  
–
TJ = 150 °C  
VS = 3.1 V  
K
Data Sheet  
27  
Rev. 1.10  
2020-12-14  
BTS7002-1EPP  
PROFET™ +2 12V  
Power Stages  
Table 13 Electrical Characteristics: Power Stages - 2 mΩ (continued)  
Parameter  
Symbol  
Values  
Typ.  
2.7  
Unit Note or  
Test Condition  
Number  
Min.  
Max.  
1)  
ON-State Resistance in  
RDS(INV)_25  
–
–
mΩ  
P_7.5.10.4  
Inverse Current at TJ = 25 °C  
TJ = 25 °C  
VS = 13.5 V  
IL = -4 A  
DEN = “low”  
see Figure 18  
ON-State Resistance in  
Inverse Current at TJ = 150 °C  
RDS(INV)_150  
–
–
–
6
–
mΩ  
mΩ  
TJ = 150 °C  
VS = 13.5 V  
IL = -4 A  
DEN = “low”  
see Figure 18  
1)  
P_7.5.10.5  
P_7.5.10.6  
ON-State Resistance in  
RDS(REV)_25  
5.7  
Reverse Polarity at TJ = 25 °C  
TJ = 25 °C  
VS = -13.5 V  
IL = -4 A  
see Figure 29  
ON-State Resistance in  
Reverse Polarity at  
TJ = 150 °C  
RDS(REV)_150  
–
–
–
–
9.6  
–
mΩ  
A
TJ = 150 °C  
VS = -13.5 V  
IL = -4 A  
1)  
P_7.5.10.7  
P_7.5.10.8  
P_7.5.10.9  
Nominal Load Current  
IL(NOM)  
21  
0.1  
TA = 85 °C  
TJ ≤ 150 °C  
1)  
Output Leakage Current at IL(OFF)_85  
TJ ≤ 85 °C  
0.9  
μA  
VOUT = 0 V  
VIN = “low”  
TA ≤ 85 °C  
Output Leakage Current at IL(OFF)_150  
TJ = 150 °C  
–
–
–
27  
–
μA  
VOUT = 0 V  
P_7.5.10.10  
P_7.5.10.11  
V
IN = “low”  
TA = 150 °C  
1)  
Inverse Current Capability  
IL(INV)  
-21  
A
VS < VOUT  
IN = “high”  
see Figure 18  
Voltage Slope  
1)  
Passive Slew Rate (e.g. for  
Half Bridge Configuration)  
|dVOUT / dt|  
–
–
–
10  
V/μs  
P_7.5.10.12  
P_7.5.10.13  
VS = 13.5 V  
see Figure 20  
Voltages  
Drain Source Diode Voltage |VDS(DIODE)  
|
550  
700  
mV  
IL = -190 mA  
TJ = 150 °C  
Data Sheet  
28  
Rev. 1.10  
2020-12-14  
BTS7002-1EPP  
PROFET™ +2 12V  
Power Stages  
Table 13 Electrical Characteristics: Power Stages - 2 mΩ (continued)  
Parameter  
Symbol  
Values  
Typ.  
Unit Note or  
Test Condition  
Number  
Min.  
Max.  
Switching Energy  
1)  
Switch-ON Energy  
EON  
–
1.5  
–
mJ  
mJ  
P_7.5.10.14  
P_7.5.10.15  
VS = 18 V  
see Figure 15  
1)  
Switch-OFF Energy  
EOFF  
–
1.65  
–
VS = 18 V  
see Figure 15  
1) Not subject to production test - specified by design.  
Data Sheet  
29  
Rev. 1.10  
2020-12-14  
BTS7002-1EPP  
PROFET™ +2 12V  
Protection  
8
Protection  
The BTS7002-1EPP is protected against Overtemperature, Overload, Reverse Battery (with ReverseON) and  
Overvoltage. Overtemperature and Overload protections are working when the device is in ON or ON_Diag  
mode but not during InverseON and ReverseON function. Overvoltage protection works in all operation  
modes. Reverse Battery protection works when the GND and VS pins are reverse supplied.  
8.1  
Overtemperature Protection  
The device incorporates both an absolute (TJ(ABS)) and a dynamic (TJ(DYN)) temperature protection circuitry for  
the channel. An increase of junction temperature TJ above either one of the two thresholds (TJ(ABS) or TJ(DYN)  
)
switches OFF the overheated channel to prevent destruction. The channel remains switched OFF until  
junction temperature has reached the “Reactivation” condition described in Table 14. The behavior is shown  
in Figure 21 (absolute Overtemperature Protection) and Figure 22 (dynamic Overtemperature Protection).  
TJ(REF) is the reference temperature used for dynamic temperature protection.  
IN  
t
t
DEN  
IL  
IL(OVL0)  
IL(NOM)  
t
TJ  
TJ(ABS)  
t
t
IIS  
IIS( FAULT)  
I
IS = IL  
kILIS  
Internal  
latch  
0
1
t
Over_Temperature_Behavior.emf  
Figure 21 Overtemperature Protection (Absolute)  
Data Sheet  
30  
Rev. 1.10  
2020-12-14  
BTS7002-1EPP  
PROFET™ +2 12V  
Protection  
IN  
t
t
DEN  
IL  
IL( OVL)  
t
TJ  
TJ( ABS)  
T
J
(REF)  
t
I
IS  
IL  
k
/
ILIS  
I
IS( FAULT)  
t
t
Internal  
Latch  
0
1
Figure 22 Overtemperature Protection (Dynamic)  
When the Overtemperature protection circuitry allows the channel to be switched ON again, the Intelligent  
Latch strategy described in Chapter 8.3 is followed.  
Data Sheet  
31  
Rev. 1.10  
2020-12-14  
BTS7002-1EPP  
PROFET™ +2 12V  
Protection  
8.2  
Overload Protection  
The BTS7002-1EPP is protected in case of Overload or short circuit to ground. Two Overload thresholds are  
defined (see Figure 23) and selected automatically depending on the voltage VDS across the power DMOS:  
•
•
I
L(OVL0) when VDS < 13 V  
IL(OVL1) when VDS > 22 V  
Figure 23 Overload Current Thresholds  
In order to allow a higher load inrush at low ambient temperature, Overload threshold is maximum at low  
temperature and decreases when TJ increases (see Figure 24). IL(OVL0) typical value remains approximately  
constant up to a junction temperature of +75 °C.  
Data Sheet  
32  
Rev. 1.10  
2020-12-14  
BTS7002-1EPP  
PROFET™ +2 12V  
Protection  
Figure 24 Overload Current Thresholds variation with TJ  
Power supply voltage VS can increase above 18 V for short time, for instance in Load Dump or in Jump Start  
condition. Whenever VS ≥ VS(JS), the overload detection current is set to IL(OVL_JS) as shown in Figure 25.  
IL(OVL)  
IL(OVL0)  
IL(OVL_JS)  
VS  
VS(JS),min VS(JS),max  
Protection_JS.emf  
Figure 25 Overload Detection Current variation with VS voltage  
When IL ≥ IL(OVL) (either IL(OVL0), IL(OVL1) or IL(OVL_JS)) the channel is switched OFF. The channel is allowed to be  
reactivated according to the intelligent latch strategy described in Chapter 8.3.  
Data Sheet  
33  
Rev. 1.10  
2020-12-14  
BTS7002-1EPP  
PROFET™ +2 12V  
Protection  
8.3  
Protection and Diagnosis in case of Fault  
Any event that triggers a protection mechanism (either Overtemperature or Overload) has 2 consequences:  
•
•
The channel switches OFF and the internal latch is set to “1”  
If the diagnosis is active for the channel, a current IIS(FAULT) is provided by IS pin (see Chapter 9.2.2 for  
further details)  
The channel can be switched ON again if all the protection mechanisms fulfill the ”reactivation” conditions  
described in Table 14. Furthermore, the device has the intelligent latch to protect itself against unwanted  
repetitive reactivation in fault condition.  
Table 14 Protection “Reactivation” Condition  
Fault condition  
Switch OFF event  
“Reactivation” condition  
Overtemperature  
TJ ≥ TJ(ABS) or (TJ - TJ(REF)) ≥ TJ(DYN)  
TJ < TJ(ABS) and (TJ - TJ(REF)) < TJ(DYN)  
(including hysteresis)  
Overload  
IL ≥ IL(OVL)  
Device is OFF  
8.3.1  
Intelligent Latch Strategy  
At normal condition, when IN is set to “high”, the channel is switched ON. In case of fault condition the output  
stage latches OFF. There are two ways to de-latch the switch.  
With IN pin:  
It is necessary to set the input pin to “low” for a time longer than tDELAY(LR) (“latch reset delay” time) to de-latch  
the channel. The channel can be allowed to restart only if the “latch” conditions for the protection  
mechanisms are fulfilled (see Table 14 ).  
During the “latch reset delay” time, if the input is set to “high” the channel remains switched OFF and the timer  
tDELAY(LR) is reset. The timer tDELAY(LR) restarts as soon as the input pin is set to “low” again.  
The intelligent latch strategy is shown in Figure 28 (flowchart) and Figure 26 (timing diagram).  
With DEN pin:  
It is possible to “force” a reset of the internal latch without waiting for tDELAY(LR) by applying a pulse (rising edge  
followed by a falling edge) to the DEN pin while IN pin is “low”. The pulse applied to DEN pin must have a  
duration longer than tDEN(LR) to ensure a reset of the internal latch.  
The timing is shown in Figure 27.  
Data Sheet  
34  
Rev. 1.10  
2020-12-14  
BTS7002-1EPP  
PROFET™ +2 12V  
Protection  
tDELAY(LR)  
IN  
t
Short circuit  
to ground  
t
IL  
t
Internal  
latch  
0
1
0
1
t
DEN  
t
tsIS(DIAG )  
tON  
IIS (FAULT)  
IIS (FAULT)  
IIS  
t
Protection_Latch_Timing.emf  
Figure 26 Intelligent Latch Timing Diagram  
IN  
t
t
Short circuit  
to ground  
IL  
t
Internal  
0
1
0
1
latch  
t
t > tDEN(LR)  
t < tDEN(LR)  
DEN  
t
tsIS(DIAG)  
IIS (FAULT)  
tsIS(DIAG )  
IIS (FAULT )  
tsIS(DIAG)  
IIS (FAULT)  
IIS  
t
Protection_Latch_DENforce.emf  
Figure 27 Intelligent Latch Timing Diagram with Forced Reset  
Data Sheet  
35  
Rev. 1.10  
2020-12-14  
BTS7002-1EPP  
PROFET™ +2 12V  
Protection  
START  
no  
IN is "high"  
yes  
yes  
Latch = 1  
no  
Reactivation  
condition fulfilled  
(TJ and / or ΔT / and / or  
Overload)  
no  
yes  
Latch = 0  
Yes  
Switch channel ON  
Fault  
DEN pulse > tDEN(LR)  
(Overtemperature  
or Overload)  
no  
no  
yes  
Switch channel OFF  
Wait until  
DEN pulse > tDEN(LR)  
Latch = 1  
Wait until IN is "low"  
then start counting for  
tDELAY(LR)  
Set DEN to „high“  
no  
IN is "low"  
yes  
yes  
De-latching with  
DEN  
no  
Continue latching for  
tDELAY(LR)  
tDELAY(LR) elapsed  
no  
yes  
Latch = 0  
Protection_PROFET_Flow_PDH.emf  
Figure 28 Intelligent Latch Flowchart  
Data Sheet  
36  
Rev. 1.10  
2020-12-14  
BTS7002-1EPP  
PROFET™ +2 12V  
Protection  
8.4  
Additional protections  
8.4.1  
Reverse Polarity Protection  
In Reverse Polarity condition (also known as Reverse Battery), the output stage is switched ON (see parameter  
RDS(REV)) because of ReverseON feature which limits the power dissipation in the output stage. Each ESD diode  
of the logic contributes to total power dissipation. The reverse current through the output stage must be  
limited by the connected load. The current through Digital Input pins has to be limited as well by an external  
resistor (please refer to the Absolute Maximum Ratings listed in Chapter 4.1 and to Application Information in  
Chapter 10).  
Figure 29 shows a typical application including a device with ReverseON. A current flowing into GND pin (-IGND  
)
during Reverse Polarity condition is necessary to activate ReverseON, therefore a resistive path between  
module ground and device GND pin must be present.  
-VBA T(REV)  
High-side  
Channel  
VS  
IDI  
Microcontroller  
DO  
DI  
RDI  
ReverseON  
OUT  
-IL  
GND  
IS  
GND  
L, C, R  
-IIS  
-IGND  
Protection_RevBatt_HEAT.emf  
Figure 29 Reverse Battery Protection (application example)  
8.4.2  
Overvoltage Protection  
In the case of supply voltages between VS(EXT,UP) and VBAT(LD), the output transistor is still operational and  
follows the input pin. In addition to the output clamp for inductive loads as described in Chapter 7.2.2, there  
is a clamp mechanism available for Overvoltage protection for the logic circuit and the output channel,  
monitoring the voltage between VS and GND pins (VS(CLAMP)).  
Data Sheet  
37  
Rev. 1.10  
2020-12-14  
BTS7002-1EPP  
PROFET™ +2 12V  
Protection  
8.5  
Protection against loss of connection  
8.5.1  
Loss of Battery and Loss of Load  
The loss of connection to battery or to the load has no influence on device robustness when load and wire  
harness are purely resistive. In case of driving an inductive load, the energy stored in the inductance must be  
handled. PROFET™ +2 12V devices can handle the inductivity of the wire harness up to 10 µH with IL(NOM). In  
case of applications where currents and/or the aforementioned inductivity are exceeded, an external  
suppressor diode (like diode DZ2 shown in Chapter 10) is recommended to handle the energy and to provide  
a well-defined path to the load current.  
8.5.2  
Loss of Ground  
In case of loss of device ground, it is recommended to have a resistor connected between any Digital Input pin  
and the microcontroller to ensure a channel switch OFF (as described in Chapter 10).  
Note:  
In case any Digital Input pin is pulled to ground (either by a resistor or active) a parasitic ground  
path is available, which could keep the device operational during loss of device ground.  
Data Sheet  
38  
Rev. 1.10  
2020-12-14  
BTS7002-1EPP  
PROFET™ +2 12V  
Protection  
8.6  
Electrical Characteristics Protection  
VS = 6 V to 18 V, TJ = -40 °C to +150 °C  
Typical values: VS = 13.5 V, TJ = 25 °C  
Typical resistive load connected to the output for testing (unless otherwise specified):  
RL = 2.1 Ω  
Table 15 Electrical Characteristics: Protection - General  
Parameter  
Symbol  
Values  
Typ.  
175  
Unit Note or  
Test Condition  
Number  
Min.  
Max.  
1)2)  
Thermal Shutdown  
Temperature (Absolute)  
TJ(ABS)  
150  
200  
°C  
P_8.6.0.1  
P_8.6.0.2  
P_8.6.0.3  
P_8.6.0.6  
See Figure 21  
3)  
Thermal Shutdown  
Hysteresis (Absolute)  
THYS(ABS)  
TJ(DYN)  
–
–
30  
–
K
See Figure 21  
3)  
Thermal Shutdown  
Temperature (Dynamic)  
80  
–
K
See Figure 22  
Power Supply Clamping  
Voltage at TJ = -40 °C  
VS(CLAMP)_-40 33  
36.5  
42  
V
IVS = 5 mA  
TJ = -40 °C  
See Figure 16  
2)  
Power Supply Clamping  
Voltage at TJ ≥ 25 °C  
VS(CLAMP)_25 35  
38  
44  
V
V
P_8.6.0.7  
P_8.6.0.8  
IVS = 5 mA  
TJ ≥ 25 °C  
See Figure 16  
3)  
Power Supply Voltage  
Threshold for Overcurrent  
Threshold Reduction in case  
of Short Circuit  
VS(JS)  
20.5  
22.5  
24.5  
Setup acc. to AEC-  
Q100-012  
1) Functional test only.  
2) Tested at TJ = 150°C only.  
3) Not subject to production test - specified by design.  
8.6.1  
Electrical Characteristics Protection  
Table 16 Electrical Characteristics: Protection  
Parameter Symbol  
Values  
Typ.  
70  
Unit Note or  
Test Condition  
Number  
Min.  
Max.  
1)  
Latch Reset Delay Time after tDELAY(LR)  
40  
100  
ms  
P_8.6.4.1  
P_8.6.4.2  
Fault Condition  
See Figure 26  
2)  
Minimum DEN Pulse  
Duration for Latch Reset  
1) Functional test only.  
tDEN(LR)  
50  
100  
150  
µs  
See Figure 27  
2) Not subject to production test - specified by design.  
Data Sheet  
39  
Rev. 1.10  
2020-12-14  
BTS7002-1EPP  
PROFET™ +2 12V  
Protection  
8.7  
Electrical Characteristics Protection - Power Output Stages  
VS = 6 V to 18 V, TJ = -40 °C to +150 °C  
Typical values: VS = 13.5 V, TJ = 25 °C  
Typical resistive load connected to the output for testing (unless otherwise specified):  
RL = 2.1 Ω  
8.7.1  
Protection Power Output Stage - 2 mΩ  
Table 17 Electrical Characteristics: Protection - 2 mΩ  
Parameter  
Symbol  
Values  
Typ.  
135  
Unit Note or  
Test Condition  
Number  
Min.  
Max.  
1)  
Overload Detection Current IL(OVL0)_-40  
at TJ = -40 °C  
120  
158  
A
A
A
P_8.7.10.1  
TJ = -40 °C  
dI/dt = 0.4 A/µs  
see Figure 23 and  
Figure 24  
2)  
Overload Detection Current IL(OVL0)_25  
at TJ = 25 °C  
116  
100  
133  
115  
150  
130  
P_8.7.10.7  
P_8.7.10.8  
TJ = 25 °C  
dI/dt = 0.4 A/µs  
see Figure 23 and  
Figure 24  
2)  
Overload Detection Current IL(OVL0)_150  
at TJ = 150 °C  
TJ = 150 °C  
dI/dt = 0.4 A/µs  
see Figure 23 and  
Figure 24  
2)  
Overload Detection Current IL(OVL1)  
at High VDS  
–
–
81  
81  
–
–
A
A
P_8.7.10.5  
P_8.7.10.6  
dI/dt = 0.4 A/µs  
see Figure 23  
2)  
Overload Detection Current IL(OVL_JS)  
Jump Start Condition  
VS > VS(JS)  
dI/dt = 0.4 A/µs  
see Figure 25  
1) Functional test only.  
2) Not subject to production test - specified by design.  
Data Sheet  
40  
Rev. 1.10  
2020-12-14  
BTS7002-1EPP  
PROFET™ +2 12V  
Diagnosis  
9
Diagnosis  
For diagnosis purpose, the BTS7002-1EPP provides a sense current signal (IIS) at pin IS. In case of disabled  
diagnostic (DEN pin set to “low”), IS pin becomes high impedance.  
A sense resistor RSENSE must be connected between IS pin and module ground if the current sense diagnosis is  
used. RSENSE value has to be higher than 820 Ω (or 400 Ω when a central Reverse Battery protection is present  
on the battery feed) to limit the power losses in the sense circuitry. A typical value is RSENSE = 1.2 kΩ.  
Due to the internal connection between IS pin and VS supply voltage, it is not recommended to connect the IS  
pin to the sense current output of other devices, if they are supplied by a different battery feed.  
See Figure 30 for details as an overview.  
VS  
Output  
Channel  
T
Overtemperature  
IS Pin Control  
Logic  
Latch  
OUT  
IN  
IL / kILIS  
DEN  
+
IIS(FAULT)  
VDS(OLOFF)  
IIS(OLOFF)  
MUX  
IS  
Diagnosis_HEAT_1CH.emf  
Figure 30 Diagnosis Block Diagram  
Data Sheet  
41  
Rev. 1.10  
2020-12-14  
BTS7002-1EPP  
PROFET™ +2 12V  
Diagnosis  
9.1  
Overview  
Table 18 gives a quick reference to the state of the IS pin during BTS7002-1EPP operation.  
Table 18 SENSE Signal, Function of Application Condition  
Application Condition  
Input level DEN level VOUT  
Diagnostic Output  
Normal operation  
“low”  
“high”  
~ GND  
Z
IIS(FAULT) if latch ≠ 0  
Short circuit to GND  
~ GND  
Z
IIS(FAULT) if latch ≠ 0  
Overtemperature  
Z
IIS(FAULT)  
Short circuit to VS  
VS  
IIS(OLOFF)  
(IIS(FAULT) if latch ≠ 0)  
Open Load  
< VS - VDS(OLOFF)  
> VS - VDS(OLOFF)  
Z
1)  
IIS(OLOFF)  
(in both cases IIS(FAULT) if  
latch ≠ 0)  
Inverse current  
VOUT > VS  
IIS(OLOFF)  
(IIS(FAULT) if latch ≠ 0)  
Normal operation  
Overload  
“high”  
~ VS  
< VS  
~ GND  
Z
IIS = IL / kILIS  
IIS(FAULT)  
Short circuit to GND  
Overtemperature  
Short circuit to VS  
Open Load  
IIS(FAULT)  
IIS(FAULT)  
VS  
IIS < IL / kILIS  
IIS = IIS(EN)  
2)  
~ VS  
3)  
Under load (e.g. Output Voltage  
Limitation condition)  
~ VS  
IIS(EN) < IIS < IL(NOM) / kILIS  
Inverse current  
VOUT > VS  
IIS = IIS(EN)  
All conditions  
n.a.  
“low”  
n.a.  
Z
1) With additional pull-up resistor.  
2) The output current has to be smaller than IL(OL)  
3) The output current has to be higher than IL(OL)  
.
.
9.2  
Diagnosis in ON state  
A current proportional to the load current (ratio kILIS = IL / IIS) is provided at pin IS when the following conditions  
are fulfilled:  
•
•
•
The power output stage is switched ON with VDS < VDS(OLOFF)  
The diagnosis is enabled  
No fault (as described in Chapter 8.3) is present or was present and not cleared yet (see Chapter 9.2.2 for  
further details)  
If a “hard” failure mode is present or was present and not cleared yet a current IIS(FAULT) is provided at IS pin.  
Data Sheet  
42  
Rev. 1.10  
2020-12-14  
BTS7002-1EPP  
PROFET™ +2 12V  
Diagnosis  
9.2.1  
Current Sense (kILIS)  
The accuracy of the sense current depends on temperature and load current. IIS increases linearly with IL  
output current until it reaches the saturation current IIS(SAT). In case of Open Load at the output stage (IL close  
to 0 A), the maximum sense current IIS(EN) (no load, diagnosis enabled) is specified. This condition is shown in  
Figure 32. The blue line represents the ideal kILIS line, while the red lines show the behavior of a typical  
product.  
An external RC filter between IS pin and microcontroller ADC input pin is recommended to reduce signal ripple  
and oscillations (a minimum time constant of 1 µs for the RC filter is recommended).  
The kILIS factor is specified with limits that take into account effects due to temperature, supply voltage and  
manufacturing process. Tighter limits are possible (within a defined current window) with calibration:  
•
•
•
A well-defined and precise current (IL(CAL)) is applied at the output during End of Line test at customer side  
The corresponding current at IS pin is measured and the kILIS is calculated (kILIS @ IL(CAL)  
)
Within the current range going from IL(CAL)_L to IL(CAL)_H the kILIS is equal to kILIS @ IL(CAL) with limits defined by  
ΔkILIS  
The derating of kILIS after calibration is calculated using the formulas in Figure 31 and it is specified by ΔkILIS  
Diagnosis_dKILIS.emf  
Figure 31 ΔkILIS calculation formulas  
The calibration is intended to be performed at TA(CAL) = 25°C. The parameter ΔkILIS includes the drift  
overtemperature as well as the drift over the current range from IL(CAL)_L to IL(CAL)_H  
.
IIS  
IIS(OL)  
IIS(EN)  
IL  
IL(OL)  
Diagnosis_ OLON _adv .emf  
Figure 32 Current Sense Ratio in Open Load at ON condition  
Data Sheet  
43  
Rev. 1.10  
2020-12-14  
BTS7002-1EPP  
PROFET™ +2 12V  
Diagnosis  
9.2.2  
Fault Current (IIS(FAULT))  
As soon as a protection event occurs, the value of the internal latch (see Chapter 8.3 for more details) is  
changed from 0 to 1, a current IIS(FAULT) is provided by pin IS when DEN is set to “high”.  
If internal latch is 1, and it is not reset, the current IIS(FAULT) is provided each time the device diagnosis is  
activated by DEN=High.  
Figure 33 shows the relation between IIS = IL / kILIS, IIS(SAT) and IIS(FAULT)  
.
IIS  
IIS (SA T).max  
IIS (SA T)  
IIS (FA ULT).max  
IIS (FA ULT )  
IIS (SA T).min  
IIS (FA ULT).min  
IL / kILI S  
IL(OVL).min  
IL  
IL(OVL).max  
Diagnosis_HEAT_IISFAULT_IISSAT.emf  
Figure 33 SENSE behavior - overview  
9.3  
Diagnosis in OFF state  
When a power output stage is in OFF state, the BTS7002-1EPP can measure the drain-source voltage and  
compare it with a threshold voltage. In this way, using some additional external components (a pull-down  
resistor and a switchable pull-up current source), it is possible to detect if the load is missing or if there is a  
short circuit to battery. If a Fault condition was detected by the device (if internal latch is 1, fault current is  
provided by IS pin independent of drain-source or output voltage, as long as DEN=High) a current IIS(FAULT) is  
provided by IS pin each time the channel diagnosis is checked also in OFF state. See Chapter 9.2.2 for further  
details.  
9.3.1  
Open Load current (IIS(OLOFF))  
In OFF state, when DEN pin is set to “high”, the VDS voltage is compared with a threshold voltage VDS(OLOFF). If  
the load is properly connected and there is no short circuit to battery, VDS ~ VS therefore VDS > VDS(OLOFF). When  
the diagnosis is active and VDS ≤ VDS(OLOFF), a current IIS(OLOFF) is provided by IS pin. Figure 34 shows the  
relationship between IIS(OLOFF) and IIS(FAULT) as functions of VDS. The two currents do not overlap making it always  
possible to differentiate between Open Load in OFF and Fault condition.  
Data Sheet  
44  
Rev. 1.10  
2020-12-14  
BTS7002-1EPP  
PROFET™ +2 12V  
Diagnosis  
IIS  
IIS(FAULT)  
IIS(OLOFF)  
VDS(OLOFF)  
VDS  
Figure 34  
IIS in OFF State  
It is necessary to wait a time tIS(OLOFF)_D between the falling edge of the input pin and the sensing at pin IS for  
Open Load in OFF diagnosis to allow the internal comparator to settle. In Figure 35 the timings for an Open  
Load detection are shown - the load is always disconnected.  
IN  
t
DEN  
tIS(OLOFF)_D  
t
VOUT  
VDS(OLOFF)  
~ VS  
Load  
conn ect ed  
t
t
IIS  
IIS(OLOFF)  
IIS(OL)  
Diagnosis_PROFET_OLOFF_time.emf  
Figure 35 Open Load in OFF Timings - load disconnected  
Data Sheet  
45  
Rev. 1.10  
2020-12-14  
BTS7002-1EPP  
PROFET™ +2 12V  
Diagnosis  
9.4  
SENSE Timings  
Figure 36 shows the timing during settling tsIS(ON) and disabling tsIS(OFF) of the SENSE (including the case of load  
change). As a proper signal cannot be established before the load current is stable (therefore before tON),  
tsIS(DIAG) ≤ 3 × ( tON_max + tsIS(ON)_max ).  
IN  
OFF  
OFF  
ON  
t
t
DEN  
IL  
t
t
tsIS(LC)  
tsIS(O FF)  
tsIS(ON)  
tsIS(O FF)  
tsIS(DI AG)  
IIS  
Diagnose_PROFET_SENSE_timings_Heat.emf  
Figure 36 SENSE Settling / Disabling Timing  
Data Sheet  
46  
Rev. 1.10  
2020-12-14  
BTS7002-1EPP  
PROFET™ +2 12V  
Diagnosis  
9.5  
Electrical Characteristics Diagnosis  
VS = 6 V to 18 V, TJ = -40 °C to +150 °C  
Typical values: VS = 13.5 V, TJ = 25 °C  
Typical resistive load connected to the output for testing (unless otherwise specified):  
RL = 2.1 Ω  
Table 19 Electrical Characteristics: Diagnosis - General  
Parameter  
Symbol  
Values  
Typ.  
–
Unit Note or  
Test Condition  
Number  
Min.  
Max.  
1)  
SENSE Saturation Current  
IIS(SAT)  
4.4  
15  
mA  
P_9.6.0.1  
VSIS = VS - VIS ≥ 2 V  
See Figure 33  
SENSE Leakage Current  
when Disabled  
IIS(OFF)  
–
–
0.01  
0.2  
0.5  
1
µA  
µA  
DEN = “low”  
VIS = 0 V  
1)  
P_9.6.0.2  
P_9.6.0.3  
SENSE Leakage Current  
IIS(EN)_85  
when Enabled at TJ ≤ 85 °C  
TJ ≤ 85 °C  
DEN = “high”  
IL = 0 A  
See Figure 32  
SENSE Leakage Current  
when Enabled at TJ = 150 °C  
IIS(EN)_150  
–
–
–
–
0.2  
0.5  
0.5  
0.5  
1
1
1
1
µA  
V
TJ = 150 °C  
DEN = “high”  
IL = 0 A  
See Figure 32  
1)  
P_9.6.0.4  
P_9.6.0.6  
P_9.6.0.7  
P_9.6.0.8  
Saturation Voltage in kILIS  
Operation  
(VS - VIS)  
VSIS_k  
VS = 6 V  
IN = DEN = “high”  
IL ≤ 2 * IL(NOM)  
1)  
Saturation Voltage in Open VSIS_OL  
Load at OFF Diagnosis  
(VS - VIS)  
V
VS = 6 V  
IN = “low”  
DEN = “high”  
1)  
Saturation Voltage in Fault VSIS_F  
V
Diagnosis  
VS = 6 V  
(VS - VIS)  
IN = “low”  
DEN = “high”  
latch ≠ 0  
Power Supply to IS Pin  
Clamping Voltage at  
TJ = -40 °C  
VSIS(CLAMP)_- 33  
36.5  
38  
42  
44  
V
V
IIS = 1 mA  
TJ = -40 °C  
See Figure 16  
2)  
P_9.6.0.9  
40  
Power Supply to IS Pin  
Clamping Voltage at  
TJ ≥ 25 °C  
VSIS(CLAMP)_25 35  
P_9.6.0.10  
IIS = 1 mA  
TJ ≥ 25 °C  
See Figure 16  
1) Not subject to production test - specified by design.  
2) Tested at TJ = 150°C.  
Data Sheet  
47  
Rev. 1.10  
2020-12-14  
BTS7002-1EPP  
PROFET™ +2 12V  
Diagnosis  
9.5.1  
Electrical Characteristics Diagnosis  
Table 20 Electrical Characteristics: Diagnosis  
Parameter  
Symbol  
Values  
Typ.  
5.5  
Unit Note or  
Test Condition  
Number  
Min.  
4.4  
Max.  
10  
SENSE Fault Current  
IIS(FAULT)  
IIS(OLOFF)  
mA  
mA  
–
P_9.6.4.1  
P_9.6.4.2  
SENSE Open Load in OFF  
Current  
1.8  
2.5  
3.5  
–
SENSE Open Load in OFF  
Delay Time  
tIS(OLOFF)_D 70  
185  
300  
µs  
VDS < VOL(OFF)  
P_9.6.4.4  
from IN falling  
edge to VIS = RSENSE  
* 0.9 * IIS(OLOFF),MIN  
DEN = “high”  
Open Load VDS Detection  
Threshold in OFF State  
VDS(OLOFF)  
tsIS(ON)  
1.3  
–
1.8  
5
2.3  
40  
V
–
P_9.6.4.5  
P_9.6.4.6  
SENSE Settling Time with  
Nominal Load Current  
Stable  
µs  
IL = IL(NOM)  
DEN from “low” to  
“high”  
1)  
SENSE Disable Time  
tsIS(OFF)  
–
–
5
5
20  
20  
µs  
µs  
P_9.6.4.8  
P_9.6.4.3  
From DEN falling  
edge to IIS = IIS(OFF)  
See Figure 36  
1)  
SENSE Settling Time after  
Load Change  
tsIS(LC)  
from IL = IL19 to  
IL = IL20  
See Figure 36  
1) Not subject to production test - specified by design.  
Data Sheet  
48  
Rev. 1.10  
2020-12-14  
BTS7002-1EPP  
PROFET™ +2 12V  
Diagnosis  
9.6  
Electrical Characteristics Diagnosis - Power Output Stages  
VS = 6 V to 18 V, TJ = -40 °C to +150 °C  
Typical values: VS = 13.5 V, TJ = 25 °C  
Typical resistive load connected to the output for testing (unless otherwise specified):  
RL = 2.1 Ω  
9.6.1  
Diagnosis Power Output Stage - 2 mΩ  
Table 21 Electrical Characteristics: Diagnosis - 2 mΩ  
Parameter  
Symbol  
Values  
Typ.  
91  
Unit Note or  
Test Condition  
Number  
Min.  
Max.  
Open Load Output Current IL(OL)_4u  
at IIS = 4 µA  
32  
150  
mA  
IIS = IIS(OL) = 4 µA  
see Figure 32  
P_9.7.10.1  
P_9.7.10.9  
P_9.7.10.13  
P_9.7.10.15  
P_9.7.10.19  
P_9.7.10.22  
P_9.7.10.23  
P_9.7.10.24  
P_9.7.10.27  
Current Sense Ratio at  
IL = IL05  
kILIS05  
kILIS09  
kILIS11  
kILIS15  
kILIS18  
kILIS19  
kILIS20  
ΔkILIS(OL)  
-65% 22700 +65%  
-65% 22700 +65%  
-55% 22700 +55%  
-40% 22700 +40%  
-24% 22700 +24%  
IL05 = 100 mA  
IL09 = 450 mA  
IL11 = 1 A  
Current Sense Ratio at  
IL = IL09  
Current Sense Ratio at  
IL = IL11  
Current Sense Ratio at  
IL = IL15  
IL15 = 4 A  
Current Sense Ratio at  
IL = IL18  
IL18 = 10 A  
Current Sense Ratio at  
IL = IL19  
-8%  
-8%  
-30  
22700 +8%  
22700 +8%  
IL19 = 15 A  
1)  
Current Sense Ratio at  
IL = IL20  
IL20 = 22 A  
1)  
SENSE Current Derating  
with Low Current  
Calibration  
0
+30  
%
%
IL(CAL) = IL09  
IL(CAL)_H = IL11  
IL(CAL)_L = IL05  
TA(CAL) = 25 °C  
1)  
SENSE Current Derating  
with Nominal Current  
Calibration  
ΔkILIS(NOM) -4  
0
+4  
P_9.7.10.29  
IL(CAL) = IL19  
IL(CAL)_H = IL20  
IL(CAL)_L = IL18  
TA(CAL) = 25 °C  
1) Not subject to production test - specified by design.  
Data Sheet  
49  
Rev. 1.10  
2020-12-14  
BTS7002-1EPP  
PROFET™ +2 12V  
Application Information  
10  
Application Information  
Note:  
10.1  
The following information is given as a hint for the implementation of the device only and shall not  
be regarded as a description or warranty of a certain functionality, condition or quality of the device.  
Application setup  
VBAT  
ZWIRE  
Optional  
Optional  
CVSGND  
CVS  
RGND  
T1  
Logic Supply  
VDD  
GND  
VS  
GPIO  
RIN  
IN  
OUT  
GPIO  
RDEN  
DEN  
COUT0  
PROFET™ +2  
12V  
Microcontroller  
DZ2  
CVS2  
ADC  
VSS  
RADC  
RIS_PROT  
IS  
CSENSE  
DZ1  
Logic GND  
Power GND  
Optional  
Chassis GND  
*See Chapter 1 „Potential Applications“  
App_1CH_INTD IO_CVG.emf  
Figure 37 BTS7002-1EPP Application Diagram  
Note:  
This is a very simplified example of an application circuit. The function must be verified in the real  
application.  
Data Sheet  
50  
Rev. 1.10  
2020-12-14  
BTS7002-1EPP  
PROFET™ +2 12V  
Application Information  
10.2  
External Components  
Table 22 Suggested Component values  
Reference  
Value  
Purpose  
RIN  
4.7 kΩ  
Protection of the microcontroller during Overvoltage and Reverse Polarity  
Necessary to switch OFF BTS7002-1EPP output during Loss of Ground  
RDEN  
RPD  
4.7 kΩ  
47 kΩ  
Protection of the microcontroller during Overvoltage and Reverse Polarity  
Necessary to switch OFF BTS7002-1EPP output during Loss of Ground  
Output polarization (pull-down)  
Ensures polarization of BTS7002-1EPP outputs to distinguish between  
Open Load and Short to VS in OFF Diagnosis  
ROL  
1.5 kΩ  
Output polarization (pull-up)  
Ensures polarization of BTS7002-1EPP output during Open Load in OFF  
diagnosis  
COUT  
T1  
10 nF  
Protection of BTS7002-1EPP output during ESD events and BCI  
Switch the battery voltage for Open Load in OFF diagnosis  
Filtering of voltage spikes on the battery line  
BC 807  
100 nF  
47 nF  
CVS  
CVSGND  
Buffer capacitor for fast transient  
See Table 5 (P_4.3.0.7) for the boundary conditions  
A placeholder on PCB layout is recommended  
DZ2  
33 V TVS Diode Transient Voltage Suppressor diode  
Protection during Overvoltage and in case of Loss of Battery while driving  
an inductive load  
CVS2  
–
Filtering / buffer capacitor located at VBAT connector  
SENSE resistor  
RSENSE  
RIS_PROT  
1.2 kΩ  
4.7 kΩ  
Protection during Overvoltage, Reverse Polarity, Loss of Ground  
Value to be tuned according to microcontroller specifications  
DZ1  
7 V Z-Diode  
Protection of microcontroller during Overvoltage  
RADC  
4.7 kΩ  
Protection of microcontroller ADC input during Overvoltage, Reverse  
Polarity, Loss of Ground  
Value to be tuned according to microcontroller specifications  
CSENSE  
RGND  
220 pF  
Sense signal filtering  
A time constant (RADC + RIS_PROT) * CSENSE longer than 1 µs is recommended  
47 Ω  
Protection in case of Overvoltage and Loss of Battery while driving  
inductive loads  
10.3  
Further Application Information  
•
•
Please contact us for information regarding the Pin FMEA  
For further information you may contact http://www.infineon.com/  
Data Sheet  
51  
Rev. 1.10  
2020-12-14  
BTS7002-1EPP  
PROFET™ +2 12V  
Package Outlines  
11  
Package Outlines  
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ꢀꢁ  
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Figure 38 PG-TSDSO-14 (Thin (Slim) Dual Small Outline 14 pins) Package Outline  
ꢂꢃꢉꢄ  
ꢂꢃꢆꢄ  
ꢂꢃꢉꢄ  
ꢂꢃꢆꢄ  
ꢀꢃꢂꢇꢄ  
ꢆ
ꢀꢃꢈꢄ  
FRSSHU  
VROGHU PDVN  
VWHQFLO DSHUWXUHV  
$// ',0(16,216 $5( ,1 81,76 00  
Figure 39 PG-TSDSO-14 (Thin (Slim) Dual Small Outline 14 pins) Package pads and stencil  
Data Sheet  
52  
Rev. 1.10  
2020-12-14  
BTS7002-1EPP  
PROFET™ +2 12V  
Package Outlines  
Green product (RoHS compliant)  
To meet the world-wide customer requirements for environmentally friendly products and to be compliant  
with government regulations the device is available as a green product. Green products are RoHS-Compliant  
(i.e Pb-free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020).  
Further information on packages  
https://www.infineon.com/packages  
Data Sheet  
53  
Rev. 1.10  
2020-12-14  
BTS7002-1EPP  
PROFET™ +2 12V  
Revision History  
12  
Revision History  
Table 23 BTS7002-1EPP - List of changes  
Revision  
1.10, 2020-12-14 Typo fixed (PROFET™+2 → PROFET™ +2)  
Figure 1, Figure 16, Figure 17, Figure 18, Figure 20, Figure 21, Figure 22, Figure 25,  
Changes  
Figure 29, Figure 30, Figure 34, Figure 37 updated  
Chapter 1, Chapter 6.1, Chapter 6.1.3, Chapter 6.1.4, Chapter 8.2, Chapter 9.2.2  
updated  
Chapter 8.4.1 updated (typo fixed)  
P_7.4.5.1, P_7.4.5.2, P_7.4.5.3, P_7.4.5.4, P_7.4.5.6, P_7.4.5.7 updated (added in Note or  
Test Condition: See Figure 15)  
P_8.6.4.1 updated (added in Note or Test Condition: See Figure 26)  
P_8.6.4.2 updated (added in Note or Test Condition: See Figure 27)  
P_9.6.0.6 updated (Parameter: SENSE Operative Range for kILIS Operation (VS - VIS) →  
Saturation Voltage in kILIS Operation (VS - VIS))  
P_9.6.0.7 updated (Parameter: SENSE Operative Range for Open Load at OFF Diagnosis (VS  
- VIS) → Saturation Voltage in Open Load at OFF Diagnosis (VS - VIS))  
P_9.6.0.8 updated (Parameter: SENSE Operative Range for Fault Diagnosis (VS - VIS) →  
Saturation Voltage in Fault Diagnosis (VS - VIS))  
1.04, 2019-10-15 P_6.5.20.1 updated (Typ.: 0.01 µA → 0.1 µA)  
P_8.7.10.1, P_8.7.10.7, P_8.7.10.8 updated (added in Note or Test Condition: link to  
Figure 24)  
P_7.5.10.5 updated (added in Note or Test Condition: see Figure 18)  
P_7.5.10.12 updated (added in Note or Test Condition: see Figure 20; deleted unnecessary  
space in Symbol: |dVOUT / dt | → |dVOUT / dt|)  
P_8.7.10.6 updated (added in Note or Test Condition: see Figure 25)  
P_9.7.10.1 updated (added in Note or Test Condition: see Figure 32)  
Figure 1, Figure 37 updated  
P_4.3.0.7 added  
Table 22 updated  
Chapter 5.1 updated (added: see Chapter 10 for the complete application setup  
overview)  
Chapter 9.2 updated (2 V → VDS(OLOFF)  
)
General: updated (ReverSave™ → ReverseON)  
1.03, 2019-04-29 Chapter 1 updated ((inserted headline "Product Validation"), (Qualified in accordance  
with AEC Q100 grade 1 → Qualified for automotive applications. Product validation  
according to AEC-Q100 Grade 1.))  
General: updated Product Name (High Current PROFET™ 12V → PROFET™+2 12V)  
P_9.7.10.1 updated (Min./Typ./Max.: 62/-/138 mA → 32/91/150 mA)  
Data Sheet  
54  
Rev. 1.10  
2020-12-14  
BTS7002-1EPP  
PROFET™ +2 12V  
Revision History  
Table 23 BTS7002-1EPP - List of changes  
Revision  
Changes  
1.02, 2019-02-05 Figure 9, Figure 10 updated  
Page 1: updated (figure product)  
Table 22 updated (punctuation)  
Chapter 9.3, Chapter 9.3.1 updated (typo)  
Page 1: updated (Package PG-TSDSO-14-22 → Package PG-TSDSO-14)  
Figure 38 updated (PG-TSDSO-14-22 (Thin (Slim) Dual Small Outline 14 pins) Package  
Outline → PG-TSDSO-14 (Thin (Slim) Dual Small Outline 14 pins) Package Outline)  
Figure 39 updated (PG-TSDSO-14-22 (Thin (Slim) Dual Small Outline 14 pins) Package pads  
and stencil → PG-TSDSO-14 (Thin (Slim) Dual Small Outline 14 pins) Package pads and  
stencil)  
Table 1 updated (Parameter: Minimum Overvoltage protection (TJ = 25 °C) → Minimum  
Overvoltage protection (TJ ≥ 25 °C))  
Table 1 updated (corrected typo in table Product Summary: IVS(OFF): 1 → 0.9 µA)  
Table 1 updated (Symbol: IVS(OFF) → IVS(OFF)_85  
P_6.5.20.1 updated (Symbol: IVS(OFF) → IVS(OFF)_85  
P_6.5.20.2 updated (Symbol: IVS(OFF) → IVS(OFF)_150  
)
)
)
P_9.7.10.27, P_9.7.10.29 updated (Note or Test Condition: formatted physical symbols as  
subscript)  
1.01, 2018-06-14 Page numbering corrected  
Figure Application Diagram, Figure 29, Figure 37 updated  
1.00, 2018-05-23 Data Sheet available  
Data Sheet  
55  
Rev. 1.10  
2020-12-14  
BTS7002-1EPP  
PROFET™ +2 12V  
Table of Contents  
Table of Contents  
1
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1  
2
2.1  
2.2  
Block Diagram and Terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3  
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3  
Terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4  
3
3.1  
3.2  
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5  
Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5  
Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6  
4
4.1  
4.2  
4.2.1  
4.3  
4.4  
4.4.1  
4.4.2  
General Product Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7  
Absolute Maximum Ratings - General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7  
Absolute Maximum Ratings - Power Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9  
Power Stage - 2 mΩ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9  
Functional Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9  
Thermal Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10  
PCB Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11  
Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12  
5
Logic Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13  
Input Pin (IN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13  
Diagnosis Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14  
Electrical Characteristics Logic Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14  
5.1  
5.2  
5.3  
6
6.1  
Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15  
Operation Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15  
OFF mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16  
ON mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16  
OFF_Diag mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16  
ON_Diag mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16  
Fault mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16  
Undervoltage on VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17  
Electrical Characteristics Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18  
Electrical Characteristics Power Supply - Product Specific . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19  
BTS7002-1EPP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19  
6.1.1  
6.1.2  
6.1.3  
6.1.4  
6.1.5  
6.2  
6.3  
6.4  
6.4.1  
7
7.1  
7.2  
Power Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20  
Output ON-State Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20  
Switching loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21  
Switching Resistive Loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21  
Switching Inductive Loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22  
Output Voltage Limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23  
Advanced Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23  
Inverse Current behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23  
Cross Current robustness with H-Bridge configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25  
Electrical Characteristics Power Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26  
Electrical Characteristics Power Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26  
Electrical Characteristics - Power Output Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27  
Power Output Stage - 2 mΩ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27  
7.2.1  
7.2.2  
7.2.3  
7.3  
7.3.1  
7.3.2  
7.4  
7.4.1  
7.5  
7.5.1  
Data Sheet  
56  
Rev. 1.10  
2020-12-14  
BTS7002-1EPP  
PROFET™ +2 12V  
Table of Contents  
8
Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30  
8.1  
8.2  
8.3  
8.3.1  
8.4  
8.4.1  
8.4.2  
8.5  
8.5.1  
8.5.2  
8.6  
8.6.1  
8.7  
8.7.1  
Overtemperature Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30  
Overload Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32  
Protection and Diagnosis in case of Fault . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34  
Intelligent Latch Strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34  
Additional protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37  
Reverse Polarity Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37  
Overvoltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37  
Protection against loss of connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38  
Loss of Battery and Loss of Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38  
Loss of Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38  
Electrical Characteristics Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39  
Electrical Characteristics Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39  
Electrical Characteristics Protection - Power Output Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40  
Protection Power Output Stage - 2 mΩ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40  
9
9.1  
9.2  
Diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41  
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42  
Diagnosis in ON state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42  
Current Sense (kILIS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43  
Fault Current (IIS(FAULT)) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44  
Diagnosis in OFF state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44  
Open Load current (IIS(OLOFF)) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44  
SENSE Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46  
Electrical Characteristics Diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47  
Electrical Characteristics Diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48  
Electrical Characteristics Diagnosis - Power Output Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49  
Diagnosis Power Output Stage - 2 mΩ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49  
9.2.1  
9.2.2  
9.3  
9.3.1  
9.4  
9.5  
9.5.1  
9.6  
9.6.1  
10  
Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50  
Application setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50  
External Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51  
Further Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51  
10.1  
10.2  
10.3  
11  
12  
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52  
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54  
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56  
Data Sheet  
57  
Rev. 1.10  
2020-12-14  
Please read the Important Notice and Warnings at the end of this document  
Trademarks  
All referenced product or service names and trademarks are the property of their respective owners.  
IMPORTANT NOTICE  
The information given in this document shall in no For further information on technology, delivery terms  
Edition 2020-12-14  
Published by  
Infineon Technologies AG  
81726 Munich, Germany  
event be regarded as a guarantee of conditions or and conditions and prices, please contact the nearest  
characteristics ("Beschaffenheitsgarantie").  
Infineon Technologies Office (www.infineon.com).  
With respect to any examples, hints or any typical  
values stated herein and/or any information regarding  
the application of the product, Infineon Technologies  
hereby disclaims any and all warranties and liabilities  
of any kind, including without limitation warranties of  
non-infringement of intellectual property rights of any  
third party.  
In addition, any information given in this document is  
subject to customer's compliance with its obligations  
stated in this document and any applicable legal  
requirements, norms and standards concerning  
customer's products and any use of the product of  
Infineon Technologies in customer's applications.  
The data contained in this document is exclusively  
intended for technically trained staff. It is the  
responsibility of customer's technical departments to  
evaluate the suitability of the product for the intended  
application and the completeness of the product  
information given in this document with respect to  
such application.  
WARNINGS  
© 2020 Infineon Technologies AG.  
All Rights Reserved.  
Due to technical requirements products may contain  
dangerous substances. For information on the types  
in question please contact your nearest Infineon  
Technologies office.  
Do you have a question about any  
aspect of this document?  
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Except as otherwise explicitly approved by Infineon  
Technologies in  
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a written document signed by  
Document reference  
Z8F65709154  

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