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BTS7080-2EPA [INFINEON]

BTS7080-2EPA-2EPA 是一款 80mΩ 智能双通道高端电源开关，提供保护功能和诊断。该设备被集成到 SMART7 技术中。;
BTS7080-2EPA
型号： BTS7080-2EPA
厂家： Infineon    Infineon
描述：

BTS7080-2EPA-2EPA 是一款 80mΩ 智能双通道高端电源开关，提供保护功能和诊断。该设备被集成到 SMART7 技术中。

开关 电源开关
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BTS7080-2EPA  
PROFET™ +2 12V  
2x 80 mΩ  
Smart High-Side Power Switch  
Package  
Marking  
PG-TSDSO-14  
7080-2A  
1
Overview  
Potential Applications  
•
•
•
Suitable for resistive, inductive and capacitive loads  
Replaces electromechanical relays, fuses and discrete circuits  
Driving capability suitable for 3 A loads and high inrush current loads  
such as P21W lamps or equivalent electronic loads (e.g. LED modules)  
VBAT  
ZWIRE  
Optional  
Optional  
CVS  
RGND  
CVSGND  
T1  
Logic Supply  
VDD  
GND  
VS  
GPIO  
RIN  
RIN  
IN0  
IN1  
GPIO  
GPIO  
GPIO  
OUT0  
RDEN  
RDSEL  
DEN  
DSEL  
COUT0  
PROFET™ +2  
12V  
Microcontroller  
DZ2  
CVS2  
OUT1  
ADC  
VSS  
RADC  
RIS_PROT  
IS  
COUT1  
CSENSE  
DZ1  
Logic GND  
Power GND  
Optional  
Chassis GND  
*See Chapter 1 „Potential Applications“  
App_2CH_INTD IO_CVG_LO.emf  
Figure 1  
BTS7080-2EPA Application Diagram. Further information in Chapter 10  
Data Sheet  
www.infineon.com  
Rev. 1.10  
2020-12-14  
1
BTS7080-2EPA  
PROFET™ +2 12V  
Overview  
Basic Features  
•
•
•
•
•
High-Side Switch with Diagnosis and Embedded Protection  
Part of PROFET™ +2 12V Family  
ReverseON for low power dissipation in Reverse Polarity  
Switch ON capability while Inverse Current condition (InverseON)  
Green Product (RoHS compliant)  
Protection Features  
•
•
•
•
Absolute and dynamic temperature limitation with controlled restart  
Overcurrent protection (tripping) with Intelligent Restart Control  
Undervoltage shutdown  
Overvoltage protection with external components  
Diagnostic Features  
•
•
•
Proportional load current sense  
Open Load in ON and OFF state  
Short circuit to ground and battery  
Product Validation  
Qualified for automotive applications. Product validation according to AEC-Q100 Grade 1.  
Description  
The BTS7080-2EPA is a Smart High-Side Power Switch, providing protection functions and diagnosis. The  
device is integrated in SMART7 technology.  
Table 1  
Product Summary  
Parameter  
Symbol  
VS(OP)  
Values  
4.1 V  
3.1 V  
28 V  
Minimum Operating voltage (at switch ON)  
Minimum Operating voltage (cranking)  
Maximum Operating voltage  
VS(UV)  
VS  
Minimum Overvoltage protection (TJ ≥ 25 °C)  
Maximum current in Sleep mode (TJ ≤ 85 °C)  
Maximum operative current  
VDS(CLAMP)_25  
IVS(SLEEP)_85  
IGND(ACTIVE)  
RDS(ON)_150  
IL(NOM)  
35 V  
0.5 µA  
4 mA  
39.6 mΩ  
3 A  
Maximum ON-state resistance (TJ = 150 °C)  
Nominal load current (TA = 85 °C)  
Typical current sense ratio at IL = IL(NOM)  
kILIS  
1800  
Data Sheet  
2
Rev.1.10  
2020-12-14  
BTS7080-2EPA  
PROFET™ +2 12V  
Block Diagram and Terms  
2
Block Diagram and Terms  
2.1  
Block Diagram  
VS  
SupplyVoltage  
Monitoring  
Overvoltage  
Protection  
Internal Power Supply  
Channel 1  
Channel 0  
Intelligent Restart  
Control  
IS  
SENSE Output  
Voltage Sensor  
T
Overtemperature  
Overvoltage  
IN0  
IN1  
Clamping  
ESD  
Protection  
+
Gate Control  
Overcurrent  
Protection  
Driver  
Logic  
+
Chargepump  
DEN  
DSEL  
OUT1  
OUT0  
Input Logic  
ReverseON  
InverseON  
Internal Reverse  
PolarityProtection  
Load Current Sense  
GND Circuitry  
Output Voltage Limitation  
GND  
Block_PROFET2ch_REVON.emf  
Figure 2  
Block Diagram of BTS7080-2EPA  
Data Sheet  
3
Rev. 1.10  
2020-12-14  
BTS7080-2EPA  
PROFET™ +2 12V  
Block Diagram and Terms  
2.2  
Terms  
Figure 3 shows all terms used in this data sheet, with associated convention for positive values.  
IVS  
VSIS  
VS  
IINn  
VDSn  
INn  
DEN  
DSEL  
IS  
IDEN  
ILn  
VS  
OUTn  
IDSEL  
VINn  
IIS  
VDEN  
VOUTn  
VDSEL  
GND  
VIS  
IGND  
Terms_PROFET.emf  
Figure 3  
Voltage and Current Convention  
Data Sheet  
4
Rev. 1.10  
2020-12-14  
BTS7080-2EPA  
PROFET™ +2 12V  
Pin Configuration  
3
Pin Configuration  
3.1  
Pin Assignment  
GND  
IN0  
DEN  
IS  
DSEL  
IN1  
n.c.  
1
2
3
4
5
6
7
14  
13  
12  
11  
10  
9
OUT0  
OUT0  
OUT0  
n.c.  
OUT1  
OUT1  
OUT1  
VS  
expos ed pad (bo tto m)  
8
PinOut_PROFET2ch.emf  
Figure 4  
Pin Configuration  
Data Sheet  
5
Rev. 1.10  
2020-12-14  
BTS7080-2EPA  
PROFET™ +2 12V  
Pin Configuration  
3.2  
Pin Definitions and Functions  
Table 2  
Pin  
Pin Definition  
Symbol  
Function  
EP  
VS  
Supply Voltage  
(exposed pad)  
Battery voltage  
1
GND  
Ground  
Signal ground  
2, 6  
INn  
Input Channel n  
Digital signal to switch ON channel n (“high” active)  
If not used: connect with a 10 kΩ resistor either to GND pin or to module  
ground  
3
DEN  
Diagnostic Enable  
Digital signal to enable device diagnosis (“high” active) and to clear the  
protection counter of channel selected with DSEL pin  
If not used: connect with a 10 kΩ resistor either to GND pin or to module  
ground  
4
5
IS  
SENSE current output  
Analog/digital signal for diagnosis  
If not used: left open  
DSEL  
Diagnosis Selection  
Digital signal to select one channel to perform ON and OFF state diagnosis  
(“high” active)  
If not used: connect with a 10 kΩ resistor either to GND pin or to module  
ground  
7, 11  
n.c.  
Not connected, internally not bonded  
8-10, 12- OUTn  
14  
Output n  
Protected high-side power output channel n1)  
1) All output pins of the channel must be connected together on the PCB. All pins of the output are internally connected  
together. PCB traces have to be designed to withstand the maximum current which can flow.  
Data Sheet  
6
Rev. 1.10  
2020-12-14  
BTS7080-2EPA  
PROFET™ +2 12V  
General Product Characteristics  
4
General Product Characteristics  
4.1  
Absolute Maximum Ratings - General  
Table 3  
Absolute Maximum Ratings1)  
TJ = -40 °C to +150 °C; all voltages with respect to ground, positive current flowing into pin  
(unless otherwise specified)  
Parameter  
Symbol  
Values  
Typ.  
Unit Note or  
Test Condition  
Number  
Min.  
Max.  
Supply pins  
Power Supply Voltage  
Load Dump Voltage  
VS  
-0.3  
–
–
–
28  
35  
V
V
–
P_4.1.0.1  
P_4.1.0.3  
VBAT(LD)  
suppressed  
Load Dump  
acc. to  
ISO16750-2  
(2010).  
Ri = 2 Ω  
Supply Voltage for Short Circuit VBAT(SC)  
Protection  
0
–
–
–
24  
16  
V
V
Setup acc. to  
AEC-Q100-012  
P_4.1.0.25  
P_4.1.0.5  
Reverse Polarity Voltage  
-VBAT(REV)  
t ≤ 2 min  
TA = +25 °C  
Setup as  
described in  
Chapter 10  
Current through GND Pin  
IGND  
-50  
–
50  
mA  
RGND according P_4.1.0.9  
to Chapter 10  
Logic & control pins (Digital Input = DI)  
DI = INn, DEN, DSEL  
2)  
Current through DI Pin  
IDI  
-1  
-1  
–
–
2
mA  
mA  
P_4.1.0.14  
2)  
Current through DI Pin  
IDI(REV)  
10  
P_4.1.0.36  
Reverse Battery Condition  
t ≤ 2 min  
IS pin  
Voltage at IS Pin  
Current through IS Pin  
VIS  
IIS  
-1.5  
-25  
–
–
VS  
V
IIS = 10 μA  
P_4.1.0.16  
P_4.1.0.18  
IIS(SAT),M mA  
–
AX  
Temperatures  
Junction Temperature  
Storage Temperature  
TJ  
-40  
-55  
–
–
150  
150  
°C  
°C  
–
–
P_4.1.0.19  
P_4.1.0.20  
TSTG  
Data Sheet  
7
Rev. 1.10  
2020-12-14  
BTS7080-2EPA  
PROFET™ +2 12V  
General Product Characteristics  
Table 3  
Absolute Maximum Ratings1) (continued)  
TJ = -40 °C to +150 °C; all voltages with respect to ground, positive current flowing into pin  
(unless otherwise specified)  
Parameter  
Symbol  
Values  
Typ.  
Unit Note or  
Test Condition  
Number  
Min.  
Max.  
ESD Susceptibility  
ESD Susceptibility all Pins  
(HBM)  
VESD(HBM)  
-2  
–
–
–
–
2
kV  
kV  
V
HBM3)  
P_4.1.0.21  
P_4.1.0.22  
P_4.1.0.23  
P_4.1.0.24  
ESD Susceptibility OUTn vs GND VESD(HBM)_OU -4  
and VS connected (HBM)  
4
HBM3)  
CDM4)  
CDM4)  
T
ESD Susceptibility all Pins  
(CDM)  
VESD(CDM)  
-500  
500  
750  
ESD Susceptibility Corner Pins VESD(CDM)_CR -750  
V
(CDM)  
N
(pins 1, 7, 8, 14)  
1) Not subject to production test - specified by design.  
2) Maximum VDI to be considered for Latch-Up tests: 5.5 V.  
3) ESD susceptibility, Human Body Model “HBM”, according to AEC Q100-002.  
4) ESD susceptibility, Charged Device Model “CDM”, according to AEC Q100-011.  
Notes  
1. Stresses above the ones listed here may cause permanent damage to the device. Exposure to absolute  
maximum rating conditions for extended periods may affect device reliability.  
2. Integrated protection functions are designed to prevent IC destruction under fault conditions described in the  
data sheet. Fault conditions are considered as “outside” normal operating range. Protection functions are  
not designed for continuous repetitive operation.  
Data Sheet  
8
Rev. 1.10  
2020-12-14  
BTS7080-2EPA  
PROFET™ +2 12V  
General Product Characteristics  
4.2  
Absolute Maximum Ratings - Power Stages  
4.2.1  
Power Stage - 80 mΩ  
Table 4  
Absolute Maximum Ratings1)  
TJ = -40 °C to +150 °C; all voltages with respect to ground, positive current flowing into pin  
(unless otherwise specified)  
Parameter  
Symbol  
Values  
Typ.  
–
Unit Note or  
Test Condition  
Number  
Min.  
Max.  
Maximum Energy Dissipation  
Single Pulse  
EAS  
–
36  
mJ  
IL = 2*IL(NOM)  
TJ(0) = 150 °C  
VS = 28 V  
P_4.2.7.1  
Maximum Energy Dissipation  
Repetitive Pulse  
EAR  
–
–
–
13  
mJ  
IL = IL(NOM)  
TJ(0) = 85 °C  
VS = 13.5 V  
1M cycles  
P_4.2.7.2  
P_4.2.7.3  
Load Current  
|IL|  
–
IL(OVL),M  
A
–
AX  
1) Not subject to production test - specified by design.  
4.3  
Functional Range  
Table 5  
Functional Range - Supply Voltage and Temperature1)  
Parameter  
Symbol  
Values  
Unit Note or  
Test Condition  
Number  
Min. Typ. Max.  
Supply Voltage Range for  
Normal Operation  
VS(NOR)  
6
13.5  
18  
V
–
P_4.3.0.1  
P_4.3.0.2  
2)3)  
Lower Extended Supply  
VS(EXT,LOW)  
3.1  
–
6
V
Voltage Range for Operation  
(parameter  
deviations possible)  
Supply Voltage Range  
reached after Overload  
Protection activation  
leading to“Undervoltage on  
VS” condition  
VS(EXT,CVG)  
–
–
3.1  
V
CVSGND is required  
when the Overload  
Protection is  
triggered (see  
Chapter 8.2) and  
the observed  
P_4.3.0.7  
number of retries is  
different from what  
specified in  
Chapter 8.3.1  
Data Sheet  
9
Rev. 1.10  
2020-12-14  
BTS7080-2EPA  
PROFET™ +2 12V  
General Product Characteristics  
Table 5  
Functional Range - Supply Voltage and Temperature1) (continued)  
Parameter  
Symbol  
Values  
Unit Note or  
Test Condition  
Number  
Min. Typ. Max.  
3)  
Upper Extended Supply  
VS(EXT,UP)  
18  
–
28  
V
P_4.3.0.3  
Voltage Range for Operation  
(parameter  
deviations possible)  
Junction Temperature  
TJ  
-40  
–
150 °C  
–
P_4.3.0.5  
1) Not subject to production test - specified by design.  
2) In case of VS voltage decreasing: VS(EXT,LOW),MIN = 3.1 V. In case of VS voltage increasing: VS(EXT,LOW),MIN = 4.1 V.  
3) Protection functions still operative.  
Note:  
Within the functional or operating range, the IC operates as described in the circuit description. The  
electrical characteristics are specified within the conditions given in the Electrical Characteristics  
tables.  
4.4  
Thermal Resistance  
Note:  
This thermal data was generated in accordance with JEDEC JESD51 standards. For more  
information, go to www.jedec.org.  
Table 6  
Thermal Resistance1)  
Parameter  
Symbol  
Values  
Typ.  
2.4  
Unit Note or  
Test Condition  
Number  
Min.  
Max.  
2)  
Thermal Characterization  
Parameter Junction-Top  
ΨJTOP  
–
4.1  
K/W  
P_4.4.0.1  
P_4.4.0.2  
2)  
Thermal Resistance  
Junction-to-Case  
RthJC  
–
–
1.6  
2.7  
–
K/W  
simulated at  
exposed pad  
2)  
Thermal Resistance  
Junction-to-Ambient  
RthJA  
31.8  
K/W  
P_4.4.0.3  
1) Not subject to production test - specified by design.  
2) According to Jedec JESD51-2,-5,-7 at natural convection on FR4 2s2p board; the Product (Chip + Package) was  
simulated on a 76.2 × 114.3 × 1.5 mm board with 2 inner copper layers (2 × 70 µm Cu, 2 × 35 µm Cu). Where applicable  
a thermal via array under the exposed pad contacted the first inner copper layer. Simulation done at TA = 105°C,  
P
DISSIPATION = 1 W.  
Data Sheet  
10  
Rev. 1.10  
2020-12-14  
BTS7080-2EPA  
PROFET™ +2 12V  
General Product Characteristics  
4.4.1  
PCB Setup  
70 µm modeled (traces, cooling area)  
70 µm, 5% metalization*  
*: means percentual Cu metalization on each layer  
PCB_Zth_1s0p.emf  
Figure 5  
1s0p PCB Cross Section  
70 µm modeled (traces)  
35 µm, 90% metalization*  
35 µm, 90% metalization*  
70 µm, 5% metalization*  
*: means percentual Cu metalization on each layer  
PCB_Zth_2s2p.emf  
Figure 6  
2s2p PCB Cross Section  
PCB 1s0p + 600 mm2 cooling  
PCB 2s2p / 1s0p footprint  
PCB_sim _setup_TSDSO14.emf  
Figure 7  
PCB setup for thermal simulations  
PCB_ 2s2p_vias_TSDSO14.emf  
Figure 8  
Thermal vias on PCB for 2s2p PCB setup  
Data Sheet  
11  
Rev. 1.10  
2020-12-14  
BTS7080-2EPA  
PROFET™ +2 12V  
General Product Characteristics  
4.4.2  
Thermal Impedance  
Figure 9  
Typical Thermal Impedance. PCB setup according Chapter 4.4.1  
Figure 10 Thermal Resistance on 1s0p PCB with various cooling surfaces  
Data Sheet  
12  
Rev. 1.10  
2020-12-14  
BTS7080-2EPA  
PROFET™ +2 12V  
Logic Pins  
5
Logic Pins  
The device has 4 digital pins for direct control.  
5.1  
Input Pins (INn)  
The input pins IN0, IN1 activate the corresponding output channel. The input circuitry is compatible with 3.3V  
and 5V microcontroller (see Chapter 10 for the complete application setup overview). The electrical  
equivalent of the input circuitry is shown in Figure 11. In case the pin is not used, it must be connected with a  
10 kΩ resistor either to GND pin or to module ground.  
VS  
IN  
VS(CLAMP)  
IDI  
IDI  
ESD  
VDI(CLAMP)  
VDI  
GND  
IGND  
Input_IN_INTDIO.emf  
Figure 11 Input circuitry  
The logic thresholds for “low” and “high” states are defined by parameters VDI(TH) and VDI(HYS). The relationship  
between these two values is shown in Figure 12. The voltage VIN needed to ensure a “high” state is always  
higher than the voltage needed to ensure a “low” state.  
VDI  
VDI(TH ),MAX  
VDI(TH)  
VDI(HYS)  
VDI(TH ),MIN  
t
Internal channel  
activation signal  
0
x
1
x
0
t
Input_VDITH_2.emf  
Figure 12 Input Threshold voltages and hysteresis  
Data Sheet  
13  
Rev. 1.10  
2020-12-14  
BTS7080-2EPA  
PROFET™ +2 12V  
Logic Pins  
5.2  
Diagnosis Pin  
The Diagnosis Enable (DEN) pin controls the diagnosis circuitry and the protection circuitry. When DEN pin is  
set to “high”, the diagnosis is enabled (see Chapter 9.2 for more details). When it is set to “low”, the diagnosis  
is disabled (IS pin is set to high impedance).  
The Diagnosis Selection (DSEL) pin selects the channel where diagnosis is performed (see Chapter 9.1.1).  
The transition from “high” to “low” of DEN pin clears the protection latch of the channel selected with DSEL  
pin depending on the logic state of IN pin and DEN pulse length (see Chapter 8.3 for more details). The internal  
structure of diagnosis pins is the same as the one of input pins. See Figure 11 for more details.  
5.3  
Electrical Characteristics Logic Pins  
VS = 6 V to 18 V, TJ = -40 °C to +150 °C  
Typical values: VS = 13.5 V, TJ = 25 °C  
Digital Input (DI) pins = IN, DEN, DSEL  
Table 7  
Electrical Characteristics: Logic Pins - General  
Parameter  
Symbol  
Values  
Typ.  
1.3  
Unit Note or  
Test Condition  
Number  
Min.  
Max.  
Digital Input Voltage  
Threshold  
VDI(TH)  
0.8  
2
V
See Figure 11 and P_5.4.0.1  
Figure 12  
1)  
Digital Input Clamping  
Voltage  
VDI(CLAMP1)  
–
7
–
V
P_5.4.0.2  
IDI = 1 mA  
See Figure 11 and  
Figure 12  
Digital Input Clamping  
Voltage  
VDI(CLAMP2)  
VDI(HYS)  
IDI(H)  
6.5  
–
7.5  
0.25  
10  
8.5  
–
V
IDI = 2 mA  
See Figure 11 and  
Figure 12  
1)  
P_5.4.0.3  
P_5.4.0.4  
P_5.4.0.5  
P_5.4.0.6  
Digital Input Hysteresis  
V
See Figure 11 and  
Figure 12  
Digital Input Current  
(“high”)  
2
25  
25  
µA  
µA  
VDI = 2 V  
See Figure 11 and  
Figure 12  
Digital Input Current (“low”) IDI(L)  
2
10  
VDI = 0.8 V  
See Figure 11 and  
Figure 12  
1) Not subject to production test - specified by design.  
Data Sheet  
14  
Rev. 1.10  
2020-12-14  
BTS7080-2EPA  
PROFET™ +2 12V  
Power Supply  
6
Power Supply  
The BTS7080-2EPA is supplied by VS, which is used for the internal logic as well as supply for the power output  
stages. VS has an undervoltage detection circuit, which prevents the activation of the power output stages and  
diagnosis in case the applied voltage is below the undervoltage threshold.  
6.1  
Operation Modes  
BTS7080-2EPA has the following operation modes:  
•
•
•
Sleep mode  
Active mode  
Stand-by mode  
The transition between operation modes is determined according to these variables:  
•
•
Logic level at INn pins  
Logic level at DEN pin  
The state diagram including the possible transitions is shown in Figure 13. The behavior of BTS7080-2EPA as  
well as some parameters may change in dependence from the operation mode of the device. Furthermore,  
due to the undervoltage detection circuitry which monitors VS supply voltage, some changes within the same  
operation mode can be seen accordingly.  
There are three parameters describing each operation mode of BTS7080-2EPA:  
•
•
•
Status of the output channels  
Status of the diagnosis  
Current consumption at VS pin (measured by IVS in Sleep mode, IGND in all other operative modes)  
Table 8 shows the correlation between operation modes, VS supply voltage, and the state of the most  
important functions (channel status, diagnosis).  
Power-up  
Unsupplied  
V
S > VS(OP)  
IN = „low“  
& DEN = „low“  
IN = „high“  
Sleep  
IN = „low“ &  
DEN = „high“  
IN = „low“  
& DEN = „low“  
IN = „high“  
Active  
DEN = „high“  
Stand-by  
IN = „low“  
& DEN = „high“  
DEN = „low“  
PowerSupply_OpMode_PROFET.emf  
Figure 13 Operation Mode State Diagram  
Data Sheet  
15  
Rev. 1.10  
2020-12-14  
BTS7080-2EPA  
PROFET™ +2 12V  
Power Supply  
Table 8  
Device function in relation to operation modes and VS voltage  
Operative Mode Function  
VS in undervoltage  
VS not in undervoltage  
Sleep  
Channels  
Diagnosis  
Channels  
Diagnosis  
Channels  
Diagnosis  
OFF  
OFF  
OFF  
OFF  
OFF  
OFF  
OFF  
OFF  
Active  
available  
available in OFF and ON states  
OFF  
Stand-by  
available in OFF state  
6.1.1  
Unsupplied  
In this state, the device is either unsupplied (no voltage applied to VS pin) or the supply voltage is below the  
undervoltage threshold.  
6.1.2  
Power-up  
The Power-up condition is entered when the supply voltage (VS) is applied to the device. The supply is rising  
until it is above the undervoltage threshold VS(OP) therefore the internal Power-On signals are set.  
6.1.3  
Sleep mode  
The device is in Sleep mode when all Digital Input pins (INn, DEN, DSEL) are set to “low”. When BTS7080-2EPA  
is in Sleep mode, all outputs are OFF. The current consumption is minimum (see parameter IVS(SLEEP)). No  
Overtemperature or Overload protection mechanism is active when the device is in Sleep mode. The device  
can go in Sleep mode only if the protection is not active (counter = 0, see Chapter 8.3.1 for further details).  
6.1.4  
Stand-by mode  
The device is in Stand-by mode as long as DEN pin is set to “high” while input pins are set to “low”. All channels  
are OFF therefore only Open Load in OFF diagnosis is possible. Depending on the load condition, either a fault  
current IIS(FAULT) or an Open Load in OFF current IIS(OLOFF) may be present at IS pin. In such situation, the current  
consumption of the device is increased.  
6.1.5  
Active mode  
Active mode is the normal operation mode of BTS7080-2EPA. The device enters Active mode as soon as one IN  
pin is set to “high”. Device current consumption is specified with IGND(ACTIVE) (measured at GND pin because the  
current at VS pin includes the load current). Overload, Overtemperature and Overvoltage protections are  
active. Diagnosis is available.  
Data Sheet  
16  
Rev. 1.10  
2020-12-14  
BTS7080-2EPA  
PROFET™ +2 12V  
Power Supply  
6.2  
Undervoltage on VS  
Between VS(OP) and VS(UV) the undervoltage mechanism is triggered. If the device is operative (in Active mode)  
and the supply voltage drops below the undervoltage threshold VS(UV), the internal logic switches OFF the  
output channels.  
As soon as the supply voltage VS is above the operative threshold VS(OP), the channels having the corresponding  
input pin set to “high” are switched ON again. The restart is delayed with a time tDELAY(UV) which protects the  
device in case the undervoltage condition is caused by a short circuit event (according to AEC-Q100-012), as  
shown in Figure 14.  
If the device is in Sleep mode and one input is set to “high”, the corresponding channel is switched ON if  
VS > VS(OP) without waiting for tDELAY(UV)  
.
VS  
VS(OP)  
VS(HYS)  
VS(UV)  
t
t
Channel  
activation signal  
VOUT  
tDELAY(UV)  
t
PowerSupply_UVRVS.emf  
Figure 14 VS undervoltage behavior  
Data Sheet  
17  
Rev. 1.10  
2020-12-14  
BTS7080-2EPA  
PROFET™ +2 12V  
Power Supply  
6.3  
Electrical Characteristics Power Supply  
VS = 6 V to 18 V, TJ = -40 °C to +150 °C  
Typical values: VS = 13.5 V, TJ = 25 °C  
Typical resistive loads connected to the outputs for testing (unless otherwise specified):  
RL = 3.8 Ω  
Table 9  
Electrical Characteristics: Power Supply - General  
Parameter  
Symbol  
Values  
Typ.  
Unit Note or  
Test Condition  
Number  
Min.  
Max.  
VS pin  
Power Supply Undervoltage VS(UV)  
Shutdown  
1.8  
2.3  
3.0  
3.1  
V
VS decreasing  
IN = “high”  
From VDS ≤ 0.5 V to  
P_6.4.0.1  
V
DS = VS  
See Figure 14  
Power Supply Minimum  
Operating Voltage  
VS(OP)  
2.0  
4.1  
V
VS increasing  
IN = “high”  
P_6.4.0.3  
From VDS = VS to  
V
DS ≤ 0.5 V  
See Figure 14  
1)  
Power Supply Undervoltage VS(HYS)  
Shutdown Hysteresis  
–
0.7  
5
–
V
P_6.4.0.6  
P_6.4.0.7  
P_6.4.0.9  
VS(OP) - VS(UV)  
See Figure 14  
Power Supply Undervoltage tDELAY(UV)  
Recovery Time  
2.5  
16  
7.5  
30  
ms  
V
dVS/dt ≤ 0.5 V/µs  
VS ≥ -1 V  
See Figure 14  
1)  
Breakdown Voltage  
between GND and VS Pins in  
Reverse Battery  
-VS(REV)  
–
IGND(REV) = 7 mA  
TJ = 150 °C  
1) Not subject to production test - specified by design.  
Data Sheet  
18  
Rev. 1.10  
2020-12-14  
BTS7080-2EPA  
PROFET™ +2 12V  
Power Supply  
6.4  
Electrical Characteristics Power Supply - Product Specific  
VS = 6 V to 18 V, TJ = -40 °C to +150 °C  
Typical values: VS = 13.5 V, TJ = 25 °C  
Typical resistive loads connected to the outputs for testing (unless otherwise specified):  
RL = 3.8 Ω  
6.4.1  
BTS7080-2EPA  
Table 10 Electrical Characteristics: Power Supply BTS7080-2EPA  
Parameter  
Symbol  
Values  
Typ.  
Unit Note or  
Test Condition  
Number  
Min.  
Max.  
1)  
Power Supply Current  
IVS(SLEEP)_85  
–
0.03  
0.5  
µA  
P_6.5.7.1  
Consumption in Sleep Mode  
with Loads at TJ ≤ 85 °C  
VS = 18 V  
VOUT = 0 V  
IN = DEN = “low”  
TJ ≤ 85 °C  
Power Supply Current  
IVS(SLEEP)_150  
–
3
10  
µA  
VS = 18 V  
P_6.5.7.2  
Consumption in Sleep Mode  
with Loads at TJ = 150 °C  
VOUT = 0 V  
IN = DEN = “low”  
TJ = 150 °C  
Operating Current in Active IGND(ACTIVE)  
Mode (all Channels ON)  
–
–
3
4
mA  
mA  
VS = 18 V  
IN = DEN = “high”  
P_6.5.7.3  
P_6.5.7.5  
Operating Current in Stand- IGND(STBY)  
1.2  
1.8  
VS = 18 V  
by Mode  
IN = “low”  
DEN = “high”  
1) Not subject to production test - specified by design.  
Data Sheet  
19  
Rev. 1.10  
2020-12-14  
BTS7080-2EPA  
PROFET™ +2 12V  
Power Stages  
7
Power Stages  
The high-side power stages are built using a N-channel vertical Power MOSFET with charge pump.  
7.1  
Output ON-State Resistance  
The ON-state resistance RDS(ON) depends mainly on junction temperature TJ. Figure 15 shows the variation of  
RDS(ON) across the whole TJ range. The value “2” on the y-axis corresponds to the maximum RDS(ON) measured  
at TJ = 150 °C.  
RDS(ON) variation over TJ  
2.20  
Reference value:  
"2" = RDS(ON),MAX @ 150 °C  
2.00  
1.80  
1.60  
1.40  
1.20  
1.00  
0.80  
0.60  
0.40  
Typical  
0.20  
0.00  
-40  
-30  
-20  
-10  
0
10  
20  
30  
40  
50  
60  
70  
80  
90  
100  
110  
120  
130  
140  
150  
160  
Junction Temperature (°C)  
Figure 15  
RDS(ON) variation factor  
The behavior in Reverse Polarity is described in Chapter 8.4.1.  
Data Sheet  
20  
Rev. 1.10  
2020-12-14  
BTS7080-2EPA  
PROFET™ +2 12V  
Power Stages  
7.2  
Switching loads  
7.2.1  
Switching Resistive Loads  
When switching resistive loads, the switching times and slew rates shown in Figure 16 can be considered. The  
switch energy values EON and EOFF are proportional to load resistance and times tON and tOFF  
.
IN  
VIN(TH)  
VIN(HYS)  
t
VOUT  
tON  
90% of VS  
tOFF(DELAY)  
70% of VS  
70% of VS  
30% of VS  
-(dV/dt)OFF  
(dV/dt)ON  
30% of VS  
10% of VS  
tON(DELAY)  
tOFF  
t
PDMOS  
EON  
EOFF  
t
Power St age_SwitchRes.emf  
Figure 16 Switching a Resistive Load  
Data Sheet  
21  
Rev. 1.10  
2020-12-14  
BTS7080-2EPA  
PROFET™ +2 12V  
Power Stages  
7.2.2  
Switching Inductive Loads  
When switching OFF inductive loads with high-side switches, the voltage VOUT drops below ground potential,  
because the inductance intends to continue driving the current. To prevent the destruction of the device due  
to overvoltage, a voltage clamp mechanism is implemented. The clamping structure limits the negative  
output voltage so that VDS = VDS(CLAMP). Figure 17 shows a concept drawing of the implementation. The  
clamping structure protects the device in all operation modes listed in Chapter 6.1.  
VS  
High-side  
Channel  
VS  
VDS  
VSIS(CLAMP)  
VDS(CLAMP)  
IS  
IL  
VOU Tn  
VS(CLAMP)  
OUTn  
GND  
L,  
RL  
IL  
PowerStage_Clamp_INTDIO.emf  
Figure 17 Output Clamp concept  
During demagnetization of inductive loads, energy has to be dissipated in BTS7080-2EPA. The energy can be  
calculated with Equation (7.1):  
RL IL  
ln 1 – ------------------------------------------- + IL  
VS – VDS(CLAMP)  
-------------------------------------------  
RL  
L
RL  
æ
ö
------  
E = VDS(CLAMP)  
(7.1)  
è
ø
VS – VDS(CLAMP)  
The maximum energy, therefore the maximum inductance for a given current, is limited by the thermal design  
of the component.  
Data Sheet  
22  
Rev. 1.10  
2020-12-14  
BTS7080-2EPA  
PROFET™ +2 12V  
Power Stages  
7.2.3  
Output Voltage Limitation  
To increase the current sense accuracy, VDS voltage is monitored. When the output current IL decreases while  
the channel is diagnosed (DEN pin set to “high”, channel selected with DSEL pins - see Figure 18) bringing VDS  
equal or lower than VDS(SLC), the output DMOS gate is partially discharged. This increases the output resistance  
so that VDS = VDS(SLC) even for very small output currents. The VDS increase allows the current sensing circuitry  
to work more efficiently, providing better kILIS accuracy for output current in the low range.  
IN  
t
DEN  
tsIS(ON)  
tsIS(OFF)  
t
IL  
t
VDS  
VS  
VDS(SLC)  
t
PowerStage_GBR_diag.emf  
Figure 18 Output Voltage Limitation activation during diagnosis  
7.3  
Advanced Switching Characteristics  
7.3.1  
Inverse Current behavior  
When VOUT > VS, a current IINV flows into the power output transistor (see Figure 19). This condition is known  
as “Inverse Current”.  
If the channel is in OFF state, the current flows through the intrinsic body diode generating high power losses  
therefore an increase of overall device temperature. This may lead to a switch OFF of unaffected channels due  
to Overtemperature. If the channel is in ON state, RDS(INV) can be expected and power dissipation in the output  
stage is comparable to normal operation in RDS(ON)  
.
During Inverse Current condition, the channel remains in ON or OFF state as long as IINV < IL(INV). If one channel  
has inverse current applied, the neighbor channel is not influenced, meaning that switching ON and OFF  
timings, protection (Overcurrent, Overtemperature) and current sensing (kILIS) are still within specified limits.  
With InverseON, it is possible to switch ON the channel during Inverse Current condition as long as IINV < IL(INV)  
(see Figure 20).  
Data Sheet  
23  
Rev. 1.10  
2020-12-14  
BTS7080-2EPA  
PROFET™ +2 12V  
Power Stages  
VBAT  
VS  
Gate  
Driver  
VINV = VOU T > VS  
IINV  
Device  
Logic  
INV  
Comp.  
OUT  
GND  
PowerStage_InvCurr_INTDIO.emf  
Figure 19 Inverse Current Circuitry  
IN  
IN  
CASE 1 : Switch is ON  
CASE 2 : Switch is OFF  
OFF  
ON  
t
t
t
IL  
IL  
NORMAL  
NORMAL  
NORMAL  
NORMAL  
t
INVERSE  
OFF  
INVERSE  
ON  
DMOS state  
DMOS state  
t
t
CASE 3 : Switch ON into Inverse Current  
CASE 4 : Switch OFF into Inverse Current  
IN  
IN  
OFF  
ON  
OFF  
ON  
t
t
IL  
IL  
NORMAL  
NORMAL  
NORMAL  
NORMAL  
t
t
t
t
INVERSE  
INVERSE  
DMOS state  
DMOS state  
ON  
OFF  
OFF  
ON  
PowerStage_InvCurr_INVON.emf  
Figure 20 InverseON - Channel behavior in case of applied Inverse Current  
Note:  
No protection mechanism like Overtemperature or Overload protection is active during applied  
Inverse Currents.  
Data Sheet  
24  
Rev. 1.10  
2020-12-14  
BTS7080-2EPA  
PROFET™ +2 12V  
Power Stages  
7.3.2  
Switching Channels in Parallel  
In case of appearance of a short circuit with connected in parallel to drive a single load, it may happen that the  
two channels switch OFF asynchronously, therefore bringing an additional thermal stress to the channel that  
switches OFF last. For this reason it is not recommended to use the device with channels in parallel.  
7.3.3  
Cross Current robustness with H-Bridge configuration  
When BTS7080-2EPA is used as high-side switch e.g. in a bridge configuration (therefore paired with a low-side  
switch as shown in Figure 21), the maximum slew rate applied to the output by the low-side switch must be  
lower than | dVOUT / dt |.  
VBAT  
R/L cable  
VS  
T
T
IN1 OFF  
ON (DC)  
IN0  
OUT1  
OUT0  
| dVOUT / dt |  
Cross  
Current  
Current through Motor  
M
ON (PWM)  
OFF  
PowerStage_PassiveSl ew_PROFET.emf  
Figure 21 High-Side switch used in Bridge configuration  
Data Sheet  
25  
Rev. 1.10  
2020-12-14  
BTS7080-2EPA  
PROFET™ +2 12V  
Power Stages  
7.4  
Electrical Characteristics Power Stages  
VS = 6 V to 18 V, TJ = -40 °C to +150 °C  
Typical values: VS = 13.5 V, TJ = 25 °C  
Typical resistive loads connected to the outputs for testing (unless otherwise specified):  
RL = 3.8 Ω  
Table 11 Electrical Characteristics: Power Stages - General  
Parameter  
Symbol  
Values  
Typ.  
Unit Note or  
Test Condition  
Number  
Min.  
Max.  
Voltages  
Drain to Source Clamping VDS(CLAMP)_-40 33  
Voltage at TJ = -40 °C  
36.5  
38  
42  
V
V
IL = 5 mA  
P_7.4.0.1  
P_7.4.0.2  
TJ = -40°C  
See Figure 17  
1)  
Drain to Source Clamping VDS(CLAMP)_25 35  
Voltage at TJ ≥ 25 °C  
44  
IL = 5 mA  
TJ ≥ 25°C  
See Figure 17  
1) Tested at TJ = 150°C.  
7.4.1  
Electrical Characteristics Power Stages - PROFET™  
Table 12 Electrical Characteristics: Power Stages - PROFET™  
Parameter  
Symbol  
Values  
Typ.  
Unit Note or  
Number  
Test Condition  
Min.  
Max.  
Timings  
Switch-ON Delay  
tON(DELAY)  
tOFF(DELAY)  
tON  
10  
35  
25  
60  
50  
20  
60  
μs  
μs  
μs  
μs  
μs  
VS = 13.5 V  
P_7.4.1.1  
P_7.4.1.2  
P_7.4.1.3  
P_7.4.1.4  
P_7.4.1.5  
VOUT = 10% VS  
See Figure 16  
Switch-OFF Delay  
Switch-ON Time  
Switch-OFF Time  
10  
30  
15  
-20  
50  
VS = 13.5 V  
VOUT = 90% VS  
See Figure 16  
110  
100  
60  
VS = 13.5 V  
VOUT = 90% VS  
See Figure 16  
tOFF  
VS = 13.5 V  
VOUT = 10% VS  
See Figure 16  
Switch-ON/OFF Matching  
ΔtSW  
VS = 13.5 V  
tON - tOFF  
Data Sheet  
26  
Rev. 1.10  
2020-12-14  
BTS7080-2EPA  
PROFET™ +2 12V  
Power Stages  
Table 12 Electrical Characteristics: Power Stages - PROFET™ (continued)  
Parameter  
Symbol  
Values  
Typ.  
Unit Note or  
Test Condition  
Number  
Min.  
Max.  
Voltage Slope  
Switch-ON Slew Rate  
(dV/dt)ON  
0.3  
0.6  
0.9  
V/μs VS = 13.5 V  
P_7.4.1.6  
VOUT = 30% to 70%  
of VS  
See Figure 16  
Switch-OFF Slew Rate  
-(dV/dt)OFF 0.3  
0.6  
0.9  
V/μs VS = 13.5 V  
P_7.4.1.7  
VOUT = 70% to 30%  
of VS  
See Figure 16  
Slew Rate Matching  
(dV/dt)ON - (dV/dt)OFF  
Δ(dV/dt)SW -0.15  
0
7
0.15  
18  
V/μs VS = 13.5 V  
P_7.4.1.8  
P_7.4.1.9  
Voltages  
1)  
Output Voltage Drop  
Limitation at Small Load  
Currents  
VDS(SLC)  
2
mV  
DEN = “high”  
channel selected  
with DSEL pin  
IL = IL(OL) = 20 mA  
See Figure 18  
1) Not subject to production test - specified by design.  
7.5  
Electrical Characteristics - Power Output Stages  
VS = 6 V to 18 V, TJ = -40 °C to +150 °C  
Typical values: VS = 13.5 V, TJ = 25 °C  
Typical resistive loads connected to the outputs for testing (unless otherwise specified):  
RL = 3.8 Ω  
7.5.1  
Power Output Stage - 80 mΩ  
Table 13 Electrical Characteristics: Power Stages - 80 mΩ  
Parameter  
Symbol  
Values  
Typ.  
Unit Note or  
Test Condition  
Number  
Min.  
Max.  
Output characteristics  
1)  
ON-State Resistance at  
TJ = 25 °C  
RDS(ON)_25  
RDS(ON)_150  
–
–
–
20.9  
–
mΩ  
mΩ  
mΩ  
P_7.5.7.1  
P_7.5.7.2  
P_7.5.7.3  
TJ = 25 °C  
ON-State Resistance at  
TJ = 150 °C  
–
–
39.6  
49.5  
TJ = 150 °C  
IL = 2 A  
ON-State Resistance in  
Cranking  
RDS(ON)_CRAN  
TJ = 150 °C  
VS = 3.1 V  
IL = 0.75 A  
K
Data Sheet  
27  
Rev. 1.10  
2020-12-14  
BTS7080-2EPA  
PROFET™ +2 12V  
Power Stages  
Table 13 Electrical Characteristics: Power Stages - 80 mΩ (continued)  
Parameter  
Symbol  
Values  
Typ.  
Unit Note or  
Test Condition  
Number  
Min.  
Max.  
1)  
ON-State Resistance in  
RDS(INV)_25  
–
23.1  
–
mΩ  
P_7.5.7.4  
Inverse Current at TJ = 25 °C  
TJ = 25 °C  
VS = 13.5 V  
IL = -2 A  
DEN = “low”  
see Figure 19  
ON-State Resistance in  
Inverse Current at TJ = 150 °C  
RDS(INV)_150  
–
–
–
–
49.5  
–
mΩ  
mΩ  
mΩ  
TJ = 150 °C  
VS = 13.5 V  
IL = -2 A  
DEN = “low”  
see Figure 19  
1)  
P_7.5.7.5  
P_7.5.7.6  
P_7.5.7.7  
ON-State Resistance in  
Reverse Polarity at TJ = 25 °C  
RDS(REV)_25  
23.1  
–
TJ = 25 °C  
VS = -13.5 V  
IL = -2 A  
RSENSE = 1.2 kΩ  
ON-State Resistance in  
Reverse Polarity at  
TJ = 150 °C  
RDS(REV)_150  
80  
TJ = 150 °C  
VS = -13.5 V  
IL = -2 A  
R
SENSE = 1.2 kΩ  
1)  
Nominal Load Current per  
Channel (all Channels  
Active)  
IL(NOM)  
–
–
3
–
A
P_7.5.7.8  
P_7.5.7.9  
TA = 85 °C  
TJ ≤ 150 °C  
1)  
Output Leakage Current at IL(OFF)_85  
TJ ≤ 85 °C  
0.01  
0.5  
μA  
VOUT = 0 V  
VIN = “low”  
TA ≤ 85 °C  
Output Leakage Current at IL(OFF)_150  
TJ = 150 °C  
–
–
1.2  
3
4
–
μA  
VOUT = 0 V  
P_7.5.7.10  
P_7.5.7.11  
VIN = “low”  
TA = 150 °C  
1)  
Inverse Current Capability  
IL(INV)  
A
VS < VOUT  
IN = “high”  
see Figure 19  
Voltage Slope  
1)  
Passive Slew Rate (e.g. for  
Half Bridge Configuration)  
|dVOUT / dt|  
–
–
–
10  
V/μs  
P_7.5.7.12  
P_7.5.7.13  
VS = 13.5 V  
see Figure 21  
Voltages  
Drain Source Diode Voltage |VDS(DIODE)  
|
650  
700  
mV  
IL = -190 mA  
TJ = 150 °C  
Data Sheet  
28  
Rev. 1.10  
2020-12-14  
BTS7080-2EPA  
PROFET™ +2 12V  
Power Stages  
Table 13 Electrical Characteristics: Power Stages - 80 mΩ (continued)  
Parameter  
Symbol  
Values  
Typ.  
Unit Note or  
Test Condition  
Number  
Min.  
Max.  
Switching Energy  
1)  
Switch-ON Energy  
EON  
–
0.32  
0.35  
–
mJ  
mJ  
P_7.5.7.14  
P_7.5.7.15  
VS = 18 V  
see Figure 16  
1)  
Switch-OFF Energy  
EOFF  
–
–
VS = 18 V  
see Figure 16  
1) Not subject to production test - specified by design.  
Data Sheet  
29  
Rev. 1.10  
2020-12-14  
BTS7080-2EPA  
PROFET™ +2 12V  
Protection  
8
Protection  
The BTS7080-2EPA is protected against Overtemperature, Overload, Reverse Battery (with ReverseON) and  
Overvoltage. Overtemperature and Overload protections are working when the device is not in Sleep mode.  
Overvoltage protection works in all operation modes. Reverse Battery protection works when the GND and VS  
pins are reverse supplied.  
8.1  
Overtemperature Protection  
The device incorporates both an absolute (TJ(ABS)) and a dynamic (TJ(DYN)) temperature protection circuitry for  
each channel. An increase of junction temperature TJ above either one of the two thresholds (TJ(ABS) or TJ(DYN)  
)
switches OFF the overheated channel to prevent destruction. The channel remains switched OFF until  
junction temperature has reached the “Restart” condition described in Table 14. The behavior is shown in  
Figure 22 (absolute Overtemperature Protection) and Figure 23 (dynamic Overtemperature Protection).  
TJ(REF) is the reference temperature used for dynamic temperature protection.  
IN  
t
t
DEN  
IL  
IL(OVL)  
t
TJ  
TJ(ABS)  
t
tIS(FAUL T)_D  
IIS  
IIS(SA T)  
IIS(FAUL T)  
IL / kILIS  
t
t
In ter nal  
count er  
0
1
Protection_PROFET_OT_IRC.emf  
Figure 22 Overtemperature Protection (Absolute)  
Data Sheet  
30  
Rev. 1.10  
2020-12-14  
BTS7080-2EPA  
PROFET™ +2 12V  
Protection  
IN  
t
t
DEN  
IL  
IL(OVL)  
t
TJ  
TJ(ABS)  
TJ(REF)  
t
tIS(FAUL T)_D  
IIS  
IIS(FAUL T)  
IL / kILIS  
t
t
In ter nal  
counter  
0
1
2
Protection_PROFET_dT_IRC.emf  
Figure 23 Overtemperature Protection (Dynamic)  
When the Overtemperature protection circuitry allows the channel to be switched ON again, the retry strategy  
described in Chapter 8.3 is followed.  
Data Sheet  
31  
Rev. 1.10  
2020-12-14  
BTS7080-2EPA  
PROFET™ +2 12V  
Protection  
8.2  
Overload Protection  
The BTS7080-2EPA is protected in case of Overload or short circuit to ground. Two Overload thresholds are  
defined (see Figure 24) and selected automatically depending on the voltage VDS across the power DMOS:  
•
•
IL(OVL0) when VDS < 13 V  
IL(OVL1) when VDS > 22 V  
IL(OVL0)  
IL(OVL1)  
Figure 24 Overload Current Thresholds variation with VDS  
In order to allow a higher load inrush at low ambient temperature, Overload threshold is maximum at low  
temperature and decreases when TJ increases (see Figure 25). IL(OVL0) typical value remains approximately  
constant up to a junction temperature of +75 °C.  
Data Sheet  
32  
Rev. 1.10  
2020-12-14  
BTS7080-2EPA  
PROFET™ +2 12V  
Protection  
reference value  
"1" = IL(OVL0) typ @ -40 °C  
Figure 25 Overload Current Thresholds variation with TJ  
Power supply voltage VS can increase above 18 V for short time, for instance in Load Dump or in Jump Start  
condition. Whenever VS ≥ VS(JS), the overload detection current is set to IL(OVL_JS) as shown in Figure 26.  
IL(OVL)  
IL(OVL0)  
IL(OVL_JS)  
VS  
VS(JS),min VS(JS),max  
Protection_JS.emf  
Figure 26 Overload Detection Current variation with VS voltage  
When IL ≥ IL(OVL) (either IL(OVL0), IL(OVL1) or IL(OVL_JS)), the channel is switched OFF. The channel is allowed to restart  
according to the retry strategy described in Chapter 8.3.  
Data Sheet  
33  
Rev. 1.10  
2020-12-14  
BTS7080-2EPA  
PROFET™ +2 12V  
Protection  
8.3  
Protection and Diagnosis in case of Fault  
Any event that triggers a protection mechanism (either Overtemperature or Overload) has 2 consequences:  
•
•
The affected channel switches OFF and the internal counter is incremented  
If the diagnosis is active for the affected channel, a current IIS(FAULT) is provided by IS pin (see Chapter 9.2.2  
for further details)  
The channel can be switched ON again if all the protection mechanisms fulfill the “restart” conditions  
described in Table 14. Furthermore, the device has an internal retry counter (one for each channel) to  
maximize the robustness in case of fault.  
Table 14 Protection “Restart” Condition  
Fault condition  
Switch OFF event  
“Restart” Condition  
Overtemperature  
TJ ≥ TJ(ABS) or (TJ - TJ(REF)) ≥ TJ(DYN)  
TJ < TJ(ABS) and (TJ - TJ(REF)) < TJ(DYN)  
(including hysteresis)  
Overload  
IL ≥ IL(OVL)  
IL < 50 mA  
TJ within TJ(ABS) and TJ(DYN) ranges  
(including hysteresis)  
8.3.1  
Retry Strategy  
When IN is set to “high”, the channel is switched ON. In case of fault condition the output stage is switched  
OFF. The channel can be allowed to restart only if the “restart” conditions for the protection mechanisms are  
fulfilled (see Table 14).  
The channel is allowed to switch ON for nRETRY(CR) times before switching OFF. After a time tRETRY, if the input pin  
is set to “high”, the channel switches ON again for nRETRY(NT) times before switching OFF again (“retry” cycle).  
After nRETRY(CYC) consecutive “retry” cycles, the channel latches OFF. It is necessary to set the input pin to “low”  
for a time longer than tDELAY(CR) to de-latch the channel (“counter reset delay” time) and to reset the internal  
counter to the default value.  
During the “counter reset delay” time, if the input is set to “high” the channel remains switched OFF and the  
timer counting tDELAY(CR) is reset, starting to count again as soon as the input pin is set to “low” again. If the  
input pin remains “low” for a time longer than tDELAY(CR) the internal retry counter is reset to the default value,  
allowing nRETRY(CR) retries at the next channel activation.  
The retry strategy is shown in Figure 29 (flowchart), Figure 27 (timing diagram - input pin always “high”) and  
Figure 28 (timing diagram - channel controlled in PWM).  
Data Sheet  
34  
Rev. 1.10  
2020-12-14  
BTS7080-2EPA  
PROFET™ +2 12V  
Protection  
IN  
t
t
Short circu it  
to ground  
nRETRY(CYC)  
"retry" cycle  
nRETRY(CR)  
nRETRY(NT)  
nRETRY(NT)  
IL  
t
tRETRY  
tRETRY  
tDELA Y(CR)  
In ter nal  
0
1
nRETRY(CR)  
nRETRY(CR) + nRETRY(NT)  
nRETRY(CR) + (nRETRY(CYC) * nRETRY(NT)  
)
0
counter  
t
DEN  
IIS(FAUL T)  
t
IL / kILIS  
IL / kILIS  
IIS  
t
Protection_PROFET_time_noPWM.emf  
Figure 27 Retry Strategy Timing Diagram  
IN  
t
t
Short circu it  
to ground  
nRETRY(CYC)  
"retry" cycle  
nRETRY(CR)  
nRETRY(NT)  
nRETRY(NT)  
IL  
t
tRETRY  
tRETRY  
tDELA Y(CR)  
In ter nal  
counter  
0
1
nRETRY(CR)  
nRETRY(CR) + nRETRY(NT)  
nRETRY(CR) + (nRETRY(CYC) * nRETRY(NT)  
)
0
t
Protection_PROFET_Timings.emf  
Figure 28 Retry Strategy Timing Diagram - Channel operated in PWM  
Data Sheet  
35  
Rev. 1.10  
2020-12-14  
BTS7080-2EPA  
PROFET™ +2 12V  
Protection  
START  
Channel remains OFF  
no  
IN is "high"  
yes  
yes  
"Retry" cycles =  
nRETRY(CYC)  
no  
no  
ALL "Restart"  
conditions fulfilled  
Switch channel OFF  
no  
yes  
Switch channel ON  
IN is "high"  
yes  
Channel remains ON  
no  
Fault  
(Overtemperature or  
Overload)  
yes  
Switch channel OFF  
Counter++  
"Retry" cycles++  
Wait for tRETRY  
Counter < nRETRY(CR)  
yes  
no  
"Retry" cycles =  
nRETRY(CYC)  
no  
yes  
Wait until IN is "low" then  
start counting for tDELAY(CR)  
no  
IN is "low"  
yes  
Continue counting for  
tDELAY(CR)  
tDELAY(CR) elapsed  
no  
yes  
Counter = 0  
"Retry" cycles = 0  
Protection_PRO FET _Flow.emf  
Figure 29 Retry Strategy Flowchart  
Data Sheet  
36  
Rev. 1.10  
2020-12-14  
BTS7080-2EPA  
PROFET™ +2 12V  
Protection  
It is possible to “force” a reset of the internal counter without waiting for tDELAY(CR) by applying a pulse (rising  
edge followed by a falling edge) to the DEN pin while IN pin is “low”. The pulse applied to DEN pin must have  
a duration longer than tDEN(CR) to ensure a reset of the internal counter. The DSEL pin must select the channel  
that has to be de-latched and keep the same logic value while DEN pin toggles twice (rising edge followed by  
a falling edge).  
The timings are shown in Figure 30.  
IN  
t
Short circu it  
to ground  
t
nRETRY(CR)  
nRETRY(CR)  
IL  
t
In ter nal  
counter  
0
1
nRETRY(CR)  
0
1
nRETRY(CR)  
0
t
t
DEN  
tDEN(CR)  
tDEN(CR)  
tDEN(CR)  
Protection_PROFET_DENforce_time2.emf  
Figure 30 Retry Strategy Timing Diagram with Forced Reset  
8.4  
Additional protections  
8.4.1  
Reverse Polarity Protection  
In Reverse Polarity condition (also known as Reverse Battery), the output stages are switched ON (see  
parameter RDS(REV)) because of ReverseON feature which limits the power dissipation in the output stages.  
Each ESD diode of the logic contributes to total power dissipation. The reverse current through the output  
stages must be limited by the connected loads. The current through Digital Input pins has to be limited as well  
by an external resistor (please refer to the Absolute Maximum Ratings listed in Chapter 4.1 and to Application  
Information in Chapter 10).  
Figure 31 shows a typical application including a device with ReverseON. A current flowing into GND pin (-IGND  
)
during Reverse Polarity condition is necessary to activate ReverseON, therefore a resistive path between  
module ground and device GND pin must be present.  
Data Sheet  
37  
Rev. 1.10  
2020-12-14  
BTS7080-2EPA  
PROFET™ +2 12V  
Protection  
-VBAT(REV)  
High-side  
Channel  
VS  
IDI  
Microcontroller  
DO  
DI  
RDI  
ReverseON  
OUTn  
-IL  
GND  
IS  
GND  
L, C, R  
-IIS  
-IGND  
Protection_RevBatt.emf  
Figure 31 Reverse Battery Protection (application example)  
8.4.2  
Overvoltage Protection  
In the case of supply voltages between VS(EXT,UP) and VBAT(LD), the output transistors are still operational and  
follow the input pin. In addition to the output clamp for inductive loads as described in Chapter 7.2.2, there  
is a clamp mechanism available for Overvoltage protection for the logic and the output channels, monitoring  
the voltage between VS and GND pins (VS(CLAMP)).  
8.5  
Protection against loss of connection  
8.5.1  
Loss of Battery and Loss of Load  
The loss of connection to battery or to the load has no influence on device robustness when load and wire  
harness are purely resistive. In case of driving an inductive load, the energy stored in the inductance must be  
handled. PROFET™ +2 12V devices can handle the inductivity of the wire harness up to 10 µH with IL(NOM). In  
case of applications where currents and/or the aforementioned inductivity are exceeded, an external  
suppressor diode (like diode DZ2 shown in Chapter 10) is recommended to handle the energy and to provide  
a well-defined path to the load current.  
8.5.2  
Loss of Ground  
In case of loss of device ground, it is recommended to have a resistor connected between any Digital Input pin  
and the microcontroller to ensure a channel switch OFF (as described in Chapter 10).  
Note:  
In case any Digital Input pin is pulled to ground (either by a resistor or active) a parasitic ground  
path is available, which could keep the device operational during loss of device ground.  
Data Sheet  
38  
Rev. 1.10  
2020-12-14  
BTS7080-2EPA  
PROFET™ +2 12V  
Protection  
8.6  
Electrical Characteristics Protection  
VS = 6 V to 18 V, TJ = -40 °C to +150 °C  
Typical values: VS = 13.5 V, TJ = 25 °C  
Typical resistive loads connected to the outputs for testing (unless otherwise specified):  
RL = 3.8 Ω  
Table 15 Electrical Characteristics: Protection - General  
Parameter  
Symbol  
Values  
Typ.  
175  
Unit Note or  
Test Condition  
Number  
Min.  
Max.  
1)2)  
Thermal Shutdown  
Temperature (Absolute)  
TJ(ABS)  
150  
200  
°C  
P_8.6.0.1  
P_8.6.0.2  
P_8.6.0.3  
P_8.6.0.6  
See Figure 22  
3)  
Thermal Shutdown  
Hysteresis (Absolute)  
THYS(ABS)  
TJ(DYN)  
–
–
30  
–
K
See Figure 22  
3)  
Thermal Shutdown  
Temperature (Dynamic)  
80  
–
K
See Figure 23  
Power Supply Clamping  
Voltage at TJ = -40 °C  
VS(CLAMP)_-40 33  
36.5  
42  
V
IVS = 5 mA  
TJ = -40 °C  
See Figure 17  
2)  
Power Supply Clamping  
Voltage at TJ ≥ 25 °C  
VS(CLAMP)_25 35  
38  
44  
V
V
P_8.6.0.7  
P_8.6.0.8  
IVS = 5 mA  
TJ ≥ 25 °C  
See Figure 17  
3)  
Power Supply Voltage  
Threshold for Overcurrent  
Threshold Reduction in case  
of Short Circuit  
VS(JS)  
20.5  
22.5  
24.5  
Setup acc. to AEC-  
Q100-012  
1) Functional test only.  
2) Tested at TJ = 150°C only.  
3) Not subject to production test - specified by design.  
8.6.1  
Electrical Characteristics Protection - PROFET™  
Table 16 Electrical Characteristics: Protection - PROFET™  
Parameter  
Symbol  
Values  
Typ.  
5
Unit Note or  
Number  
Test Condition  
Min.  
Max.  
1)  
Automatic Retries in Case of nRETRY(CR)  
–
–
P_8.6.1.1  
Fault after a Counter Reset  
See Figure 27 and  
Figure 28  
1)  
Automatic Retries in Case of nRETRY(NT)  
Fault after the First tRETRY  
Activation  
–
–
1
2
–
–
P_8.6.1.3  
P_8.6.1.4  
See Figure 27 and  
Figure 28  
1)  
Maximum “Retry” Cycles  
allowed before Channel  
Latch OFF  
nRETRY(CYC)  
See Figure 27 and  
Figure 28  
Data Sheet  
39  
Rev. 1.10  
2020-12-14  
BTS7080-2EPA  
PROFET™ +2 12V  
Protection  
Table 16 Electrical Characteristics: Protection - PROFET™ (continued)  
Parameter  
Symbol  
Values  
Typ.  
70  
Unit Note or  
Test Condition  
Number  
Min.  
Max.  
1)  
Auto Retry Time after Fault tRETRY  
Condition  
40  
100  
ms  
ms  
µs  
P_8.6.1.5  
See Figure 27 and  
Figure 28  
1)  
Counter Reset Delay Time  
after Fault Condition  
tDELAY(CR)  
40  
50  
70  
100  
150  
P_8.6.1.6  
P_8.6.1.7  
See Figure 27 and  
Figure 28  
2)  
Minimum DEN Pulse  
tDEN(CR)  
100  
Duration for Counter Reset  
See Figure 30  
1) Functional test only.  
2) Not subject to production test - specified by design.  
8.7  
Electrical Characteristics Protection - Power Output Stages  
VS = 6 V to 18 V, TJ = -40 °C to +150 °C  
Typical values: VS = 13.5 V, TJ = 25 °C  
Typical resistive loads connected to the outputs for testing (unless otherwise specified):  
RL = 3.8 Ω  
8.7.1  
Protection Power Output Stage - 80 mΩ  
Table 17 Electrical Characteristics: Protection - 80 mΩ  
Parameter  
Symbol  
Values  
Typ.  
36  
Unit Note or  
Test Condition  
Number  
Min.  
Max.  
1)  
Overload Detection Current IL(OVL0)_-40  
at TJ = -40 °C  
32  
40  
A
A
A
P_8.7.7.1  
TJ = -40 °C  
dI/dt = 0.2 A/µs  
see Figure 24 and  
Figure 25  
2)  
Overload Detection Current IL(OVL0)_25  
at TJ = 25 °C  
30  
26  
36  
30  
40  
34  
P_8.7.7.7  
P_8.7.7.8  
TJ = 25 °C  
dI/dt = 0.2 A/µs  
see Figure 24 and  
Figure 25  
2)  
Overload Detection Current IL(OVL0)_150  
at TJ = 150 °C  
TJ = 150 °C  
dI/dt = 0.2 A/µs  
see Figure 24 and  
Figure 25  
Data Sheet  
40  
Rev. 1.10  
2020-12-14  
BTS7080-2EPA  
PROFET™ +2 12V  
Protection  
Table 17 Electrical Characteristics: Protection - 80 mΩ (continued)  
Parameter  
Symbol  
Values  
Typ.  
Unit Note or  
Test Condition  
Number  
Min.  
Max.  
2)  
Overload Detection Current IL(OVL1)  
at High VDS  
–
21.5  
–
A
P_8.7.7.5  
dI/dt = 0.2 A/µs  
see Figure 24  
2)  
Overload Detection Current IL(OVL_JS)  
–
21.5  
–
A
P_8.7.7.6  
Jump Start Condition  
VS > VS(JS)  
dI/dt = 0.2 A/µs  
see Figure 26  
1) Functional test only.  
2) Not subject to production test - specified by design.  
Data Sheet  
41  
Rev. 1.10  
2020-12-14  
BTS7080-2EPA  
PROFET™ +2 12V  
Diagnosis  
9
Diagnosis  
For diagnosis purpose, the BTS7080-2EPA provides a combination of digital and analog signals at pin IS. These  
signals are generically named SENSE and written IIS. In case of disabled diagnostic (DEN pin set to “low”), IS  
pin becomes high impedance.  
A sense resistor RSENSE must be connected between IS pin and module ground if the current sense diagnosis is  
used. RSENSE value has to be higher than 820 Ω (or 400 Ω when a central Reverse Battery protection is present  
on the battery feed) to limit the power losses in the sense circuitry. A typical value is RSENSE = 1.2 kΩ.  
Due to the internal connection between IS pin and VS supply voltage, it is not recommended to connect the IS  
pin to the sense current output of other devices, if they are supplied by a different battery feed.  
See Figure 32 for details as an overview.  
VS  
Channel 1  
Channel 0  
T
Overtemperature  
OUT1  
Internal Counters  
IS Pin Control  
OUT0  
Logic  
INn  
DEN  
DSEL  
IL / kILIS  
MUX  
+
IIS(FAULT)  
VDS(OLOFF)  
MUX  
IIS(OLOFF)  
MUX  
IS  
RSENSE  
Diagnosis_PROFET_2CH.emf  
Figure 32 Diagnosis Block Diagram  
Data Sheet  
42  
Rev. 1.10  
2020-12-14  
BTS7080-2EPA  
PROFET™ +2 12V  
Diagnosis  
9.1  
Overview  
Table 18 gives a quick reference to the state of the IS pin during BTS7080-2EPA operation.  
Table 18 SENSE Signal, Function of Application Condition  
Application Condition  
Input level DEN level VOUT  
Diagnostic Output  
Normal operation  
“low”  
“high”  
~ GND  
Z
IIS(FAULT) if counter > 0  
Short circuit to GND  
~ GND  
Z
IIS(FAULT) if counter > 0  
Overtemperature  
Z
IIS(FAULT)  
Short circuit to VS  
VS  
IIS(OLOFF)  
(IIS(FAULT) if counter > 0)  
Open Load  
< VS - VDS(OLOFF)  
> VS - VDS(OLOFF)  
Z
1)  
IIS(OLOFF)  
(in both cases IIS(FAULT) if  
counter > 0)  
Inverse current  
~ VINV = VOUT > VS IIS(OLOFF)  
(IIS(FAULT) if counter > 0)  
Normal operation  
Overcurrent  
“high”  
~ VS  
< VS  
~ GND  
Z
IIS = IL / kILIS  
IIS(FAULT)  
Short circuit to GND  
Overtemperature  
Short circuit to VS  
Open Load  
IIS(FAULT)  
IIS(FAULT)  
VS  
IIS < IL / kILIS  
IIS = IIS(EN)  
2)  
~ VS  
3)  
Under load (e.g. Output Voltage  
Limitation condition)  
~ VS  
IIS(EN) < IIS < IL(NOM) / kILIS  
Inverse current  
~ VINV = VOUT > VS IIS = IIS(EN)  
n.a.  
All conditions  
n.a.  
“low”  
Z
1) With additional pull-up resistor.  
2) The output current has to be smaller than IL(OL)  
3) The output current has to be higher than IL(OL)  
.
.
9.1.1  
SENSE signal truth table  
In case DEN is set to “high”, the SENSE for the selected channel is enabled or disabled using DSEL pin. Table 19  
gives the truth table.  
Table 19 Diagnostic Truth Table  
DEN  
DSEL  
IS  
“low”  
“high”  
“high”  
not relevant  
“low”  
Z
SENSE output 0  
SENSE output 1  
“high”  
Data Sheet  
43  
Rev. 1.10  
2020-12-14  
BTS7080-2EPA  
PROFET™ +2 12V  
Diagnosis  
9.2  
Diagnosis in ON state  
A current proportional to the load current (ratio kILIS = IL / IIS) is provided at pin IS when the following conditions  
are fulfilled:  
•
•
•
The power output stage is switched ON with VDS < VDS(OLOFF)  
The diagnosis is enabled for that channel  
No fault (as described in Chapter 8.3) is present or was present and not cleared yet (see Chapter 9.2.2 for  
further details)  
If a “hard” failure mode is present or was present and not cleared yet a current IIS(FAULT) is provided at IS pin.  
9.2.1  
Current Sense (kILIS)  
The accuracy of the sense current depends on temperature and load current. IIS increases linearly with IL  
output current until it reaches the saturation current IIS(SAT). In case of Open Load at the output stage (IL close  
to 0 A), the maximum sense current IIS(EN) (no load, diagnosis enabled) is specified. This condition is shown in  
Figure 34. The blue line represents the ideal kILIS line, while the red lines show the behavior of a typical  
product.  
An external RC filter between IS pin and microcontroller ADC input pin is recommended to reduce signal ripple  
and oscillations (a minimum time constant of 1 µs for the RC filter is recommended).  
The kILIS factor is specified with limits that take into account effects due to temperature, supply voltage and  
manufacturing process. Tighter limits are possible (within a defined current window) with calibration:  
•
•
•
A well-defined and precise current (IL(CAL)) is applied at the output during End of Line test at customer side  
The corresponding current at IS pin is measured and the kILIS is calculated (kILIS @ IL(CAL)  
)
Within the current range going from IL(CAL)_L to IL(CAL)_H the kILIS is equal to kILIS @ IL(CAL) with limits defined by  
ΔkILIS  
The derating of kILIS after calibration is calculated using the formulas in Figure 33 and it is specified by ΔkILIS  
Diagnosis_dKILIS.emf  
Figure 33 ΔkILIS calculation formulas  
The calibration is intended to be performed at TA(CAL) = 25°C. The parameter ΔkILIS includes the drift  
overtemperature as well as the drift over the current range from IL(CAL)_L to IL(CAL)_H  
.
Data Sheet  
44  
Rev. 1.10  
2020-12-14  
BTS7080-2EPA  
PROFET™ +2 12V  
Diagnosis  
IIS  
IIS(OL)  
IIS(EN)  
IL  
IL(OL)  
Diagnosis_ OLON _adv .emf  
Figure 34 Current Sense Ratio in Open Load at ON condition  
9.2.2  
Fault Current (IIS(FAULT))  
As soon a protection event occurs, changing the value of the internal retry counter (see Chapter 8.3 for more  
details) from its reset state, a current IIS(FAULT) is provided by pin IS when DEN is set to “high” and the affected  
channel is selected. The following 3 situations may occur:  
•
If the channel is ON and the number of retries is lower than “nRETRY(CR) + nRETRY(CYC) * nRETRY(NT)”, the current  
IS(FAULT) is provided for a time tIS(FAULT)_D after the channel is allowed to restart, after which IIS = IL / kILIS (as  
I
shown in Figure 35). During a retry cycle (while timer tRETRY is running) the current IIS(FAULT) is provided each  
time the channel diagnosis is checked  
•
•
If the channel is ON and the number of retries is equal than “nRETRY(CR) + nRETRY(CYC) * nRETRY(NT)”, the current  
IIS(FAULT) is provided until the internal counter is reset (either by expiring of tDELAY(CR) time or by DEN pin  
pulse, as described in Chapter 8.3.1)  
If the channel is OFF and the internal counter is not in the reset state, the current IIS(FAULT) is provided each  
time the channel diagnosis is checked  
IN  
t
t
IL  
IL(OVL)  
In ter nal  
counter  
0
1
2
0
t
DEN  
tIS(FAUL T)_D  
IIS(FAUL T)  
t
IIS(FAUL T)  
IIS  
IL / kILIS  
t
Diagnosis_PROFET_IISFAULT_load.emf  
Figure 35 IIS(FAULT) at Load Switching  
Data Sheet  
45  
Rev. 1.10  
2020-12-14  
BTS7080-2EPA  
PROFET™ +2 12V  
Diagnosis  
Figure 36 adds the behavior of SENSE signal to the timing diagram seen in Figure 28, while Figure 37 shows  
the relation between IIS = IL / kILIS, IIS(SAT) and IIS(FAULT)  
.
IN  
t
t
Short circu it  
to ground  
nRETRY(CYC)  
"retry" cycle  
nRETRY(CR)  
nRETRY(NT)  
nRETRY(NT)  
IL  
t
tRETRY  
tRETRY  
tDELA Y(CR)  
In ter nal  
counter  
0
1
nRETRY(CR)  
nRETRY(CR) + nRETRY(NT)  
nRETRY(CR) + (nRETRY(CYC) * nRETRY(NT)  
)
0
t
DEN  
t
IIS(FAUL T)  
IIS(FAUL T)  
IIS(FAUL T)  
IL / kILIS  
IIS  
t
Diagnosis_PROFET_IISFAULT.emf  
Figure 36 SENSE behavior in Fault condition  
IIS  
IIS(SA T),max  
IIS(SAT)  
IIS(FAUL T),max  
IIS(FAUL T)  
IIS(SA T),min  
=
IIS(FAUL T),min  
IL / kILIS  
IL(OVL)  
IL  
Diagnosis_PROFET_IISFAULT_IISSAT.emf  
Figure 37 SENSE behavior - overview  
9.3  
Diagnosis in OFF state  
When a power output stage is in OFF state, the BTS7080-2EPA can measure the output voltage and compare  
it with a threshold voltage. In this way, using some additional external components (a pull-down resistor and  
a switchable pull-up current source), it is possible to detect if the load is missing or if there is a short circuit to  
battery. If a Fault condition was detected by the device (the internal counter has a value different from the  
reset value, as described in Chapter 9.2.2) a current IIS(FAULT) is provided by IS pin each time the channel  
diagnosis is checked also in OFF state.  
Data Sheet  
46  
Rev. 1.10  
2020-12-14  
BTS7080-2EPA  
PROFET™ +2 12V  
Diagnosis  
9.3.1  
Open Load current (IIS(OLOFF))  
In OFF state, when DEN pin is set to “high” and a channel is selected using DSEL pin, the VDS voltage is  
compared with a threshold voltage VDS(OLOFF). If the load is properly connected and there is no short circuit to  
battery, VDS ~ VS therefore VDS > VDS(OLOFF). When the diagnosis is active and VDS ≤ VDS(OLOFF), a current IIS(OLOFF) is  
provided by IS pin. Figure 38 shows the relationship between IIS(OLOFF) and IIS(FAULT) as functions of VDS. The two  
currents do not overlap making it always possible to differentiate between Open Load in OFF and Fault  
condition.  
IIS  
IIS(FAULT)  
IIS(OLOFF)  
VDS(OLOFF)  
VDS  
Figure 38  
IIS in OFF State  
It is necessary to wait a time tIS(OLOFF)_D between the falling edge of the input pin and the sensing at pin IS for  
Open Load in OFF diagnosis to allow the internal comparator to settle. In Figure 39 the timings for an Open  
Load detection are shown - the load is always disconnected.  
IN  
t
DEN  
tIS(OLOFF)_D  
t
VOUT  
VDS(OLOFF)  
~ VS  
Load  
conn ect ed  
t
t
IIS  
IIS(OLOFF)  
IIS(OL)  
Diagnosis_PROFET_OLOFF_time.emf  
Figure 39 Open Load in OFF Timings - load disconnected  
Data Sheet  
47  
Rev. 1.10  
2020-12-14  
BTS7080-2EPA  
PROFET™ +2 12V  
Diagnosis  
9.4  
SENSE Timings  
Figure 40 and Figure 42 show the timing during settling tsIS(ON) and disabling tsIS(OFF) of the SENSE (including  
the case of load change). As a proper signal cannot be established before the load current is stable (therefore  
before tON), tsIS(DIAG) = tsIS(ON) + tON  
.
IN  
OFF  
OFF  
ON  
t
t
DEN  
tO FF  
IL  
t
t
tsIS(LC)  
tsIS(O FF)  
tsIS(ON)  
tsIS(O FF)  
tsIS(DI AG)  
IIS  
Diagnose_PROFET_SENSE_timings.emf  
Figure 40 SENSE Settling / Disabling Timing  
IN  
OFF  
OFF  
ON  
t
DEN  
IL  
t
t
tsIS(ON)_SLC  
tsIS(ON)  
tsIS(LC)_SLC  
IIS  
t
Diagnose_PROFET_SENSE_timings_SLC.emf  
Figure 41 SENSE Timing with Small Load Current  
Data Sheet  
48  
Rev. 1.10  
2020-12-14  
BTS7080-2EPA  
PROFET™ +2 12V  
Diagnosis  
DEN  
t
DSEL  
t
t
IL0  
IL1  
IIS  
IL(CAL)  
IL(CAL)_L  
IL(CAL)_O L  
tsI S(CC)_SLC  
t
t
tsI S(CC)  
tsIS(O FF)  
tsIS (ON)  
Diagnose_PROFET_SENSE_timings_CC.emf  
Figure 42 SENSE Settling Timing - Channel Change  
Data Sheet  
49  
Rev. 1.10  
2020-12-14  
BTS7080-2EPA  
PROFET™ +2 12V  
Diagnosis  
9.5  
Electrical Characteristics Diagnosis  
VS = 6 V to 18 V, TJ = -40 °C to +150 °C  
Typical values: VS = 13.5 V, TJ = 25 °C  
Typical resistive loads connected to the outputs for testing (unless otherwise specified):  
RL = 3.8 Ω  
Table 20 Electrical Characteristics: Diagnosis - General  
Parameter  
Symbol  
Values  
Typ.  
–
Unit Note or  
Test Condition  
Number  
Min.  
Max.  
1)  
SENSE Saturation Current  
IIS(SAT)  
4.4  
15  
mA  
P_9.6.0.13  
VS = 8 V to 18 V  
RSENSE = 1.2 kΩ  
See Figure 37  
1)  
SENSE Saturation Current  
IIS(SAT)  
4.1  
–
15  
mA  
P_9.6.0.14  
VS = 6 V to 18 V  
RSENSE = 1.2 kΩ  
See Figure 37  
SENSE Leakage Current  
when Disabled  
IIS(OFF)  
–
–
0.01  
0.2  
0.5  
1
µA  
µA  
DEN = “low”  
IL ≥ IL(NOM)  
VIS = 0 V  
1)  
P_9.6.0.2  
P_9.6.0.3  
SENSE Leakage Current  
IIS(EN)_85  
when Enabled at TJ ≤ 85 °C  
TJ ≤ 85 °C  
DEN = “high”  
IL = 0 A  
See Figure 34  
SENSE Leakage Current  
when Enabled at TJ = 150 °C  
IIS(EN)_150  
–
–
–
–
0.2  
0.5  
0.5  
0.5  
1
1
1
1
µA  
V
TJ = 150 °C  
DEN = “high”  
IL = 0 A  
See Figure 34  
1)  
P_9.6.0.4  
P_9.6.0.6  
P_9.6.0.7  
P_9.6.0.8  
Saturation Voltage in kILIS  
Operation  
(VS - VIS)  
VSIS_k  
VS = 6 V  
IN = DEN = “high”  
IL ≤ 1.2 * IL(NOM)  
1)  
Saturation Voltage in Open VSIS_OL  
Load at OFF Diagnosis  
(VS - VIS)  
V
VS = 6 V  
IN = “low”  
DEN = “high”  
1)  
Saturation Voltage in Fault VSIS_F  
V
Diagnosis  
VS = 6 V  
(VS - VIS)  
IN = “low”  
DEN = “high”  
counter >0  
Data Sheet  
50  
Rev. 1.10  
2020-12-14  
BTS7080-2EPA  
PROFET™ +2 12V  
Diagnosis  
Table 20 Electrical Characteristics: Diagnosis - General (continued)  
Parameter  
Symbol  
Values  
Typ.  
Unit Note or  
Test Condition  
Number  
Min.  
Max.  
Power Supply to IS Pin  
Clamping Voltage at  
TJ = -40 °C  
VSIS(CLAMP)_- 33  
36.5  
42  
V
IIS = 1 mA  
P_9.6.0.9  
TJ = -40 °C  
See Figure 17  
2)  
40  
Power Supply to IS Pin  
Clamping Voltage at  
TJ ≥ 25 °C  
VSIS(CLAMP)_25 35  
38  
44  
V
P_9.6.0.10  
IIS = 1 mA  
TJ ≥ 25 °C  
See Figure 17  
1) Not subject to production test - specified by design.  
2) Tested at TJ = 150°C.  
9.5.1  
Electrical Characteristics Diagnosis - PROFET™  
Table 21 Electrical Characteristics: Diagnosis - PROFET™  
Parameter  
Symbol  
Values  
Typ.  
5.5  
Unit Note or  
Test Condition  
Number  
Min.  
Max.  
SENSE Fault Current  
IIS(FAULT)  
IIS(OLOFF)  
tIS(FAULT)_D  
4.4  
10  
mA  
mA  
µs  
See Figure 37 and P_9.6.1.1  
Figure 38  
SENSE Open Load in OFF  
Current  
1.9  
–
2.5  
3.5  
–
See Figure 37 and P_9.6.1.2  
Figure 38  
1)  
SENSE Delay Time at  
Channel Switch ON after  
Last Fault Condition  
500  
P_9.6.1.3  
See Figure 35  
SENSE Open Load in OFF  
Delay Time  
tIS(OLOFF)_D 30  
70  
120  
µs  
VDS < VOL(OFF)  
from IN falling  
edge to IIS =  
P_9.6.1.4  
IS(OLOFF),MIN * 0.9  
DEN = “high”  
counter = 0  
See Figure 39  
Open Load VDS Detection  
Threshold in OFF State  
VDS(OLOFF)  
tsIS(ON)  
1.3  
–
1.8  
5
2.3  
20  
V
See Figure 38  
P_9.6.1.5  
P_9.6.1.6  
SENSE Settling Time with  
Nominal Load Current  
Stable  
µs  
IL = IL(CAL)  
from DEN rising  
edge to IIS = IL /  
(kILIS,MAX @ IL) * 0.9  
See Figure 40  
1)  
SENSE Settling Time with  
Small Load Current Stable  
tsIS(ON)_SLC  
–
–
60  
µs  
P_9.6.1.13  
IL = IL(CAL)_OL  
from DEN rising  
edge to IIS = IL /  
(kILIS,MAX @ IL) * 0.9  
Data Sheet  
51  
Rev. 1.10  
2020-12-14  
BTS7080-2EPA  
PROFET™ +2 12V  
Diagnosis  
Table 21 Electrical Characteristics: Diagnosis - PROFET™ (continued)  
Parameter  
Symbol  
Values  
Typ.  
5
Unit Note or  
Test Condition  
Number  
Min.  
Max.  
1)  
SENSE Disable Time  
tsIS(OFF)  
–
20  
µs  
µs  
P_9.6.1.8  
From DEN falling  
edge to IIS = IIS(OFF)  
See Figure 40  
1)  
SENSE Settling Time after  
Load Change  
tsIS(LC)  
–
–
5
20  
P_9.6.1.9  
from IL = IL(CAL)_L to  
IL = IL(CAL) (see  
ΔkILIS(NOM)  
)
See Figure 40  
1)  
SENSE Settling Time after  
Load Change with Small  
Load Current  
tsIS(LC)_SLC  
250  
400  
µs  
µs  
P_9.6.1.14  
DEN = “high”  
from Load Change  
toIIS = IL /(kILIS @ IL)  
from IL(CAL) to  
IL(CAL)_OL  
1)  
SENSE Settling Time after  
Channel Change  
tsIS(CC)  
–
–
5
–
20  
60  
P_9.6.1.10  
P_9.6.1.15  
Start channel:  
IL = IL(CAL)  
End channel:  
IL = IL(CAL)_L  
(see ΔkILIS(NOM)  
See Figure 42  
1)  
)
SENSE Settling Time after  
Channel Change with Small  
Load Current  
tsIS(CC)_SLC  
µs  
DEN = “high”  
fromDSELtoggling  
to IIS = IL /  
(kILIS,MIN @ IL) * 1.1  
Start channel:  
IL = IL(CAL)  
End Channel:  
IL = IL(CAL)_OL  
(see ΔkILIS(NOM) and  
ΔkILIS(OL)  
)
1) Not subject to production test - specified by design.  
Data Sheet  
52  
Rev. 1.10  
2020-12-14  
BTS7080-2EPA  
PROFET™ +2 12V  
Diagnosis  
9.6  
Electrical Characteristics Diagnosis - Power Output Stages  
VS = 6 V to 18 V, TJ = -40 °C to +150 °C  
Typical values: VS = 13.5 V, TJ = 25 °C  
Typical resistive loads connected to the outputs for testing (unless otherwise specified):  
RL = 3.8 Ω  
9.6.1  
Diagnosis Power Output Stage - 80 mΩ  
Table 22 Electrical Characteristics: Diagnosis - 80 mΩ  
Parameter  
Symbol  
Values  
Typ.  
6
Unit Note or  
Test Condition  
Number  
Min.  
Max.  
Open Load Output Current IL(OL)_4u  
at IIS = 4 µA  
1
11  
mA  
IIS = IIS(OL) = 4 µA  
See Figure 34  
P_9.7.7.1  
P_9.7.7.5  
P_9.7.7.6  
P_9.7.7.8  
P_9.7.7.12  
P_9.7.7.15  
P_9.7.7.17  
P_9.7.7.19  
P_9.7.7.27  
Current Sense Ratio at  
IL = IL01  
kILIS01  
kILIS02  
kILIS04  
kILIS08  
kILIS11  
kILIS13  
kILIS15  
ΔkILIS(OL)  
-28.0% 1750  
-25.5% 1750  
-23.5% 1750  
-19.0% 1750  
-9.5% 1800  
-6.0% 1800  
-4.5% 1800  
+28.0%  
+25.5%  
+23.5%  
+19.0%  
+9.5%  
+6.0%  
+4.5%  
+30  
IL01 = 10 mA  
IL02 = 20 mA  
IL04 = 50 mA  
IL08 = 250 mA  
IL11 = 1 A  
Current Sense Ratio at  
IL = IL02  
Current Sense Ratio at  
IL = IL04  
Current Sense Ratio at  
IL = IL08  
Current Sense Ratio at  
IL = IL11  
Current Sense Ratio at  
IL = IL13  
IL13 = 2 A  
Current Sense Ratio at  
IL = IL15  
IL15 = 4 A  
1)  
SENSE Current Derating  
with Low Current  
Calibration  
-30  
0
%
%
IL(CAL)_OL = IL02  
IL(CAL)_OL_H = IL04  
IL(CAL)_OL_L = IL01  
TA(CAL) = 25 °C  
See Figure 33  
1)  
SENSE Current Derating  
with Nominal Current  
Calibration  
ΔkILIS(NOM) -4  
0
+4  
P_9.7.7.29  
IL(CAL) = IL13  
IL(CAL)_H = IL15  
IL(CAL)_L = IL11  
TA(CAL) = 25 °C  
See Figure 33  
1) Not subject to production test - specified by design.  
Data Sheet  
53  
Rev. 1.10  
2020-12-14  
BTS7080-2EPA  
PROFET™ +2 12V  
Application Information  
10  
Application Information  
Note:  
10.1  
The following information is given as a hint for the implementation of the device only and shall not  
be regarded as a description or warranty of a certain functionality, condition or quality of the device.  
Application Setup  
VBAT  
ZWIRE  
Optional  
Optional  
CVSGND  
CVS  
RGND  
T1  
Logic Supply  
VDD  
GND  
VS  
GPIO  
RIN  
RIN  
IN0  
IN1  
GPIO  
GPIO  
GPIO  
OUT0  
RDEN  
RDSEL  
DEN  
DSEL  
COUT0  
PROFET™ +2  
12V  
Microcontroller  
DZ2  
CVS2  
OUT1  
ADC  
VSS  
RADC  
RIS_PROT  
IS  
COUT1  
CSENSE  
DZ1  
Logic GND  
Power GND  
Optional  
Chassis GND  
*See Chapter 1 „Potential Applications“  
App_2CH_INTD IO_CVG_LO.emf  
Figure 43 BTS7080-2EPA Application Diagram  
Note:  
This is a very simplified example of an application circuit. The function must be verified in the real  
application.  
Table 23 Loads considered for Reverse Polarity setup (see P_4.1.0.5)  
Output  
RDS(ON),max @ TJ = 150 °C  
Load connected  
80 mΩ  
39.6 mΩ  
P21W  
Data Sheet  
54  
Rev. 1.10  
2020-12-14  
BTS7080-2EPA  
PROFET™ +2 12V  
Application Information  
10.2  
External Components  
Table 24 Suggested Component values  
Reference  
Value  
Purpose  
RIN  
4.7 kΩ  
Protection of the microcontroller during Overvoltage and Reverse Polarity  
Necessary to switch OFF BTS7080-2EPA output during Loss of Ground  
RDEN  
RDSEL  
RPD  
4.7 kΩ  
4.7 kΩ  
47 kΩ  
Protection of the microcontroller during Overvoltage and Reverse Polarity  
Necessary to switch OFF BTS7080-2EPA output during Loss of Ground  
Protection of the microcontroller during Overvoltage and Reverse Polarity  
Necessary to switch OFF BTS7080-2EPA output during Loss of Ground  
Output polarization (pull-down)  
Ensures polarization of BTS7080-2EPA outputs to distinguish between  
Open Load and Short to VS in OFF Diagnosis  
ROL  
1.5 kΩ  
Output polarization (pull-up)  
Ensures polarization of BTS7080-2EPA output during Open Load in OFF  
diagnosis  
COUT  
T1  
10 nF  
Protection of BTS7080-2EPA output during ESD events and BCI  
Switch the battery voltage for Open Load in OFF diagnosis  
Filtering of voltage spikes on the battery line  
BC 807  
100 nF  
47 nF  
CVS  
CVSGND  
Buffer capacitor for fast transient  
See Table 5 (P_4.3.0.7) for the boundary conditions  
A placeholder on PCB layout is recommended  
DZ2  
33 V TVS Diode Transient Voltage Suppressor diode  
Protection during Overvoltage and in case of Loss of Battery while driving  
an inductive load  
CVS2  
–
Filtering / buffer capacitor located at VBAT connector  
SENSE resistor  
RSENSE  
RIS_PROT  
1.2 kΩ  
4.7 kΩ  
Protection during Overvoltage, Reverse Polarity, Loss of Ground  
Value to be tuned according to microcontroller specifications  
DZ1  
7 V Z-Diode  
Protection of microcontroller during Overvoltage  
RADC  
4.7 kΩ  
Protection of microcontroller ADC input during Overvoltage, Reverse  
Polarity, Loss of Ground  
Value to be tuned according to microcontroller specifications  
CSENSE  
RGND  
220 pF  
Sense signal filtering  
A time constant (RADC * CSENSE) longer than 1 µs is recommended  
47 Ω  
Protection in case of Overvoltage and Loss of Battery while driving  
inductive loads  
Data Sheet  
55  
Rev. 1.10  
2020-12-14  
BTS7080-2EPA  
PROFET™ +2 12V  
Application Information  
10.3  
Further Application Information  
•
•
Please contact us for information regarding the Pin FMEA  
For further information you may contact http://www.infineon.com/  
Data Sheet  
56  
Rev. 1.10  
2020-12-14  
BTS7080-2EPA  
PROFET™ +2 12V  
Package Outlines  
11  
Package Outlines  
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Figure 45 PG-TSDSO-14 (Thin (Slim) Dual Small Outline 14 pins) Package pads and stencil  
Data Sheet  
57  
Rev. 1.10  
2020-12-14  
BTS7080-2EPA  
PROFET™ +2 12V  
Package Outlines  
Green product (RoHS compliant)  
To meet the world-wide customer requirements for environmentally friendly products and to be compliant  
with government regulations the device is available as a green product. Green products are RoHS-Compliant  
(i.e Pb-free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020).  
Further information on packages  
https://www.infineon.com/packages  
Data Sheet  
58  
Rev. 1.10  
2020-12-14  
BTS7080-2EPA  
PROFET™ +2 12V  
Revision History  
12  
Revision History  
Table 25 BTS7080-2EPA - List of changes  
Revision  
Changes  
1.10, 2020-12-14 Typo fixed (PROFET™+2 → PROFET™ +2)  
Figure 26, Figure 38 updated  
Chapter 8.2 updated  
Chapter 8.4.1 updated (typo fixed)  
P_9.6.0.6 updated (Parameter: SENSE Operative Range for kILIS Operation (VS - VIS) →  
Saturation Voltage in kILIS Operation (VS - VIS))  
P_9.6.0.7 updated (Parameter: SENSE Operative Range for Open Load at OFF Diagnosis (VS  
- VIS) → Saturation Voltage in Open Load at OFF Diagnosis (VS - VIS))  
P_9.6.0.8 updated (Parameter: SENSE Operative Range for Fault Diagnosis (VS - VIS) →  
Saturation Voltage in Fault Diagnosis (VS - VIS))  
1.06, 2019-10-30 P_9.7.7.15 updated (Min./Typ./Max.: -9.8%/1805/+9.8% → -9.5%/1800/+9.5%)  
P_9.7.7.17, P_9.7.7.19 updated (Typ.: 1805 → 1800)  
1.05, 2019-10-15 P_8.7.7.1, P_8.7.7.7, P_8.7.7.8 updated (added in Note or Test Condition: link to Figure 25)  
P_7.5.7.4, P_7.5.7.5 updated (added in Note or Test Condition: DEN = “low”; link to  
Figure 19)  
P_7.5.7.12 updated (added in Note or Test Condition: see Figure 21; deleted unnecessary  
space in Symbol: |dVOUT / dt | → |dVOUT / dt|)  
P_8.7.7.6 updated (added in Note or Test Condition: see Figure 26)  
P_9.7.7.1 updated (added in Note or Test Condition: see Figure 34)  
P_9.7.7.5 updated (Min./Typ./Max.: -45%/1800/+45% → -28.0%/1750/+28.0%)  
P_9.7.7.6 updated (Min./Typ./Max.: -40%/1800/+40% → -25.5%/1750/+25.5%)  
P_9.7.7.8 updated (Min./Typ./Max.: -35%/1800/+35% → -23.5%/1750/+23.5%)  
P_9.7.7.12 updated (Min./Typ./Max.: -26%/1800/+26% → -19.0%/1750/+19.0%)  
P_9.7.7.15 updated (Min./Typ./Max.: -11%/1800/+11% → -9.8%/1805/+9.8%)  
P_9.7.7.17 updated (Min./Typ./Max.: -6%/1800/+6% → -6.0%/1805/+6.0%)  
P_9.7.7.19 updated (Min./Typ./Max.: -5%/1800/+5% → -4.5%/1805/+4.5%)  
P_7.5.7.11 updated (added in Note or Test Condition: see Figure 19)  
Figure 1, Figure 43 updated  
Chapter 1 updated (or LED equivalent → or equivalent electronic loads (e.g. LED modules))  
P_4.3.0.7 added  
Table 24 updated  
Chapter 5.1 updated (added: see Chapter 10 for the complete application setup  
overview)  
Data Sheet  
59  
Rev. 1.10  
2020-12-14  
BTS7080-2EPA  
PROFET™ +2 12V  
Revision History  
Table 25 BTS7080-2EPA - List of changes  
Revision  
Changes  
1.04, 2019-06-26 Chapter 9.2 updated (2 V → VDS(OLOFF)  
)
General: updated (ReverSave™ → ReverseON)  
Chapter 1 updated ((inserted headline "Product Validation"), (Qualified in accordance  
with AEC Q100 grade 1 → Qualified for automotive applications. Product validation  
according to AEC-Q100 Grade 1.))  
General: updated Product Name (PROFET™+2 → PROFET™+2 12V)  
Page 1: updated figure product  
Table 24 updated punctuation  
Chapter 9.3.1 updated (typo)  
Page 1: updated (Package PG-TSDSO-14-22 → Package PG-TSDSO-14)  
Figure 29 updated  
Figure 44 updated (PG-TSDSO-14-22 (Thin (Slim) Dual Small Outline 14 pins) Package  
Outline → PG-TSDSO-14 (Thin (Slim) Dual Small Outline 14 pins) Package Outline)  
Figure 45 updated (PG-TSDSO-14-22 (Thin (Slim) Dual Small Outline 14 pins) Package pads  
and stencil → PG-TSDSO-14 (Thin (Slim) Dual Small Outline 14 pins) Package pads and  
stencil)  
Table 1 updated ((Symbol: IVS(SLEEP) → IVS(SLEEP)_85), (Parameter: Minimum Overvoltage  
protection (TJ = 25 °C) → Minimum Overvoltage protection (TJ ≥ 25 °C))  
P_9.6.0.6 updated (Note or Test Condition: removed unnecessary line-break)  
1.03, 2018-06-14 Chapter 7.4.1 updated chapter title (PROFET → PROFET™)  
Table 12 updated table title (PROFET → PROFET™)  
Chapter 8.6.1 updated chapter title (PROFET → PROFET™)  
Table 16 updated table title (PROFET → PROFET™)  
Chapter 9.5.1 updated chapter title (PROFET → PROFET™)  
Table 21 updated table title (PROFET → PROFET™)  
P_4.1.0.21, P_4.1.0.22, P_4.1.0.23, P_4.1.0.24 updated (footnote ESD standards)  
Table 1 updated (RDS(ON) → RDS(ON)_150), (VDS(CLAMP) → VDS(CLAMP)_25  
Chapter 8.5.2 updated phrasing  
)
P_7.5.7.14 Table subheading "Switching Energy" added  
P_7.5.7.15 Table subheading "Switching Energy" added  
Chapter 6.4 added conditions  
Chapter 7.5 added conditions  
P_7.5.7.14 updated (Test condition: add "See Figure")  
P_7.5.7.15 updated (Test condition: add "See Figure")  
Chapter 8.7 added conditions  
Chapter 9.6 added conditions  
P_9.7.7.27 updated (Test condition: add "See Figure")  
P_9.7.7.29 updated (Test condition: add "See Figure")  
1.02, 2017-11-17 Table 6 footnote updated ("Specified RthJA value is" removed)  
Figure 17 symbol updated (VIS(CLAMP) → VSIS(CLAMP)  
)
Data Sheet  
60  
Rev. 1.10  
2020-12-14  
BTS7080-2EPA  
PROFET™ +2 12V  
Revision History  
Table 25 BTS7080-2EPA - List of changes  
Revision  
Changes  
1.01, 2017-10-24 Figures updated (straight lines for signals that are crossing, points for connections; typos,  
capitalization/lower case printing)  
Typos and misspelling corrected according to style guidelines, inconsistencies among  
document resolved  
P_4.1.0.36 updated (symbol: IDI → IDI(REV)  
P_5.4.0.5 symbol updated (IDI → IDI(H)  
)
)
P_5.4.0.6 symbol updated (IDI → IDI(L)  
Chapter 7.3.3 updated  
)
Table 24 updated (RDSEL included)  
1.00, 2017-08-24 Data Sheet available  
Data Sheet  
61  
Rev. 1.10  
2020-12-14  
BTS7080-2EPA  
PROFET™ +2 12V  
Table of Contents  
Table of Contents  
1
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1  
2
2.1  
2.2  
Block Diagram and Terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3  
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3  
Terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4  
3
3.1  
3.2  
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5  
Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5  
Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6  
4
4.1  
4.2  
4.2.1  
4.3  
4.4  
4.4.1  
4.4.2  
General Product Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7  
Absolute Maximum Ratings - General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7  
Absolute Maximum Ratings - Power Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9  
Power Stage - 80 mΩ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9  
Functional Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9  
Thermal Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10  
PCB Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11  
Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12  
5
Logic Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13  
Input Pins (INn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13  
Diagnosis Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14  
Electrical Characteristics Logic Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14  
5.1  
5.2  
5.3  
6
6.1  
Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15  
Operation Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15  
Unsupplied . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16  
Power-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16  
Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16  
Stand-by mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16  
Active mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16  
Undervoltage on VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17  
Electrical Characteristics Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18  
Electrical Characteristics Power Supply - Product Specific . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19  
BTS7080-2EPA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19  
6.1.1  
6.1.2  
6.1.3  
6.1.4  
6.1.5  
6.2  
6.3  
6.4  
6.4.1  
7
7.1  
7.2  
Power Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20  
Output ON-State Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20  
Switching loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21  
Switching Resistive Loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21  
Switching Inductive Loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22  
Output Voltage Limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23  
Advanced Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23  
Inverse Current behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23  
Switching Channels in Parallel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25  
Cross Current robustness with H-Bridge configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25  
Electrical Characteristics Power Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26  
Electrical Characteristics Power Stages - PROFET™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26  
Electrical Characteristics - Power Output Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27  
Power Output Stage - 80 mΩ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27  
7.2.1  
7.2.2  
7.2.3  
7.3  
7.3.1  
7.3.2  
7.3.3  
7.4  
7.4.1  
7.5  
7.5.1  
Data Sheet  
62  
Rev. 1.10  
2020-12-14  
BTS7080-2EPA  
PROFET™ +2 12V  
Table of Contents  
8
Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30  
8.1  
8.2  
8.3  
8.3.1  
8.4  
8.4.1  
8.4.2  
8.5  
8.5.1  
8.5.2  
8.6  
8.6.1  
8.7  
8.7.1  
Overtemperature Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30  
Overload Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32  
Protection and Diagnosis in case of Fault . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34  
Retry Strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34  
Additional protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37  
Reverse Polarity Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37  
Overvoltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38  
Protection against loss of connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38  
Loss of Battery and Loss of Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38  
Loss of Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38  
Electrical Characteristics Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39  
Electrical Characteristics Protection - PROFET™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39  
Electrical Characteristics Protection - Power Output Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40  
Protection Power Output Stage - 80 mΩ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40  
9
9.1  
Diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42  
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43  
SENSE signal truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43  
Diagnosis in ON state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44  
Current Sense (kILIS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44  
Fault Current (IIS(FAULT)) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45  
Diagnosis in OFF state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46  
Open Load current (IIS(OLOFF)) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47  
SENSE Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48  
Electrical Characteristics Diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50  
Electrical Characteristics Diagnosis - PROFET™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51  
Electrical Characteristics Diagnosis - Power Output Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53  
Diagnosis Power Output Stage - 80 mΩ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53  
9.1.1  
9.2  
9.2.1  
9.2.2  
9.3  
9.3.1  
9.4  
9.5  
9.5.1  
9.6  
9.6.1  
10  
Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54  
Application Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54  
External Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55  
Further Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56  
10.1  
10.2  
10.3  
11  
12  
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57  
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59  
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62  
Data Sheet  
63  
Rev. 1.10  
2020-12-14  
Please read the Important Notice and Warnings at the end of this document  
Trademarks  
All referenced product or service names and trademarks are the property of their respective owners.  
IMPORTANT NOTICE  
The information given in this document shall in no For further information on technology, delivery terms  
Edition 2020-12-14  
Published by  
Infineon Technologies AG  
81726 Munich, Germany  
event be regarded as a guarantee of conditions or and conditions and prices, please contact the nearest  
characteristics ("Beschaffenheitsgarantie").  
Infineon Technologies Office (www.infineon.com).  
With respect to any examples, hints or any typical  
values stated herein and/or any information regarding  
the application of the product, Infineon Technologies  
hereby disclaims any and all warranties and liabilities  
of any kind, including without limitation warranties of  
non-infringement of intellectual property rights of any  
third party.  
In addition, any information given in this document is  
subject to customer's compliance with its obligations  
stated in this document and any applicable legal  
requirements, norms and standards concerning  
customer's products and any use of the product of  
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The data contained in this document is exclusively  
intended for technically trained staff. It is the  
responsibility of customer's technical departments to  
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information given in this document with respect to  
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Document reference  
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SI9130DB

 5- and 3.3-V Step-Down Synchronous Converters

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VISHAY

SI9135LG-T1

 SMBus Multi-Output Power-Supply Controller

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VISHAY

SI9135LG-T1-E3

 SMBus Multi-Output Power-Supply Controller

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SI9135_11

 SMBus Multi-Output Power-Supply Controller

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SI9136_11

 Multi-Output Power-Supply Controller

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SI9130CG-T1-E3

 Pin-Programmable Dual Controller - Portable PCs

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SI9130LG-T1-E3

 Pin-Programmable Dual Controller - Portable PCs

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SI9130_11

 Pin-Programmable Dual Controller - Portable PCs

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SI9137

 Multi-Output, Sequence Selectable Power-Supply Controller for Mobile Applications

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SI9137DB

 Multi-Output, Sequence Selectable Power-Supply Controller for Mobile Applications

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VISHAY

SI9137LG

 Multi-Output, Sequence Selectable Power-Supply Controller for Mobile Applications

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VISHAY

SI9122E

 500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification Drivers

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VISHAY
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