C161KLMHABXUMA1_技术文档

Data Sheet, V2.0, Jan. 2001

C161K

C161O

16-Bit Single-Chip Microcontroller

Microcontrollers

N e v e r s t o p t h i n k i n g .

Edition 2001-01

Published by Infineon Technologies AG,

St.-Martin-Strasse 53,

D-81541 München, Germany

Attention please!

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characteristics.

Terms of delivery and rights to technical change reserved.

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circuits, descriptions and charts stated herein.

Infineon Technologies is an approved CECC manufacturer.

Information

For further information on technology, delivery terms and conditions and prices please contact your nearest

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Due to technical requirements components may contain dangerous substances. For information on the types in

question please contact your nearest Infineon Technologies Office.

Infineon Technologies Components may only be used in life-support devices or systems with the express written

approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure

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Data Sheet, V2.0, Jan. 2001

C161K

C161O

16-Bit Single-Chip Microcontroller

Microcontrollers

N e v e r s t o p t h i n k i n g .

C161K/O

Revision History:

2001-01

V2.0

Previous Version:

03.97

09.96

(Preliminary)

(Advance Information)

Page

All

Subjects (major changes since last revision)

Converted to Infineon layout

C161V removed

All

2

Ordering Codes and Cross-Reference replaced with Derivative Synopsis

Open drain functionality described for P2, P3, P6

Bidirectional reset introduced

5 - 8

8

19

Figure updated

28, 29

32 - 56

35

Revised description of Absolute Max. Ratings and Operating Conditions

Specifications for reduced supply voltage introduced

Reduced power consumption

36, 37

38, 39

41 - 56

Clock Generation Modes added

Description of External Clock Drive improved

Standard 25-MHz timing introduced (timing granularity 2 ns)

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16-Bit Single-Chip Microcontroller

C166 Family

C161K/O

• High Performance 16-bit CPU with 4-Stage Pipeline

– 80 ns Instruction Cycle Time at 25 MHz CPU Clock

– 400 ns Multiplication (16 × 16 bit), 800 ns Division (32 / 16 bit)

– Enhanced Boolean Bit Manipulation Facilities

– Additional Instructions to Support HLL and Operating Systems

– Register-Based Design with Multiple Variable Register Banks

– Single-Cycle Context Switching Support

– 16 MBytes Total Linear Address Space for Code and Data

– 1024 Bytes On-Chip Special Function Register Area

• 16-Priority-Level Interrupt System with 20 Sources, Sample-Rate down to 40 ns

• 8-Channel Interrupt-Driven Single-Cycle Data Transfer Facilities via

Peripheral Event Controller (PEC)

• Clock Generation via prescaler or via direct clock input

• On-Chip Memory Modules

– 2 KBytes On-Chip Internal RAM (IRAM) on C161O,

1 KByte IRAM on C161K

• On-Chip Peripheral Modules

– Two Multi-Functional General Purpose Timer Units with 5 Timers on C161O,

one Timer Unit with 3 Timers on C161K

– Two Serial Channels (Synchronous/Asynchronous and High-Speed-Synchronous)

• Up to 4 MBytes External Address Space for Code and Data

– Programmable External Bus Characteristics for Different Address Ranges

– Multiplexed or Demultiplexed External Address/Data Buses with 8-Bit or 16-Bit

Data Bus Width

– Four Programmable Chip-Select Signals on C161O,

two Chip-Select Signals on C161K

• Idle and Power Down Modes

• Programmable Watchdog Timer

• Up to 63 General Purpose I/O Lines

• Power Supply: the C161K/O can operate from a 5 V or a 3 V power supply

• Supported by a Large Range of Development Tools like C-Compilers,

Macro-Assembler Packages, Emulators, Evaluation Boards, HLL-Debuggers,

Simulators, Logic Analyzer Disassemblers, Programming Boards

• On-Chip Bootstrap Loader

• 80-Pin MQFP Package (0.65 mm pitch)

Data Sheet

1

V2.0, 2001-01

C161K

C161O

This document describes several derivatives of the C161 group. Table 1 enumerates

these derivatives and summarizes the differences. As this document refers to all of these

derivatives, some descriptions may not apply to a specific product.

Table 1

Derivative¹⁾

C161K/O Derivative Synopsis

Max. Oper. Operating

Frequency Voltage

IRAM Nr of Ext. CAP

[KB] CSs Intr. IN

SAF-C161K-LM

20 MHz

25 MHz

20 MHz

25 MHz

20 MHz

4.5 to 5.5 V

1

2

4

7

---

SAB-C161K-LM

4.5 to 5.5 V

3.0 to 3.6 V

4.5 to 5.5 V

3.0 to 3.6 V

---

SAF-C161K-L25M

SAB-C161K-L25M

SAF-C161K-LM3V

SAB-C161K-LM3V

SAF-C161O-LM

SAB-C161O-LM

SAF-C161O-L25M

SAB-C161O-L25M

SAF-C161O-LM3V

---

Yes

SAB-C161O-LM3V

1)

This Data Sheet is valid for devices starting with and including design step HA.

For simplicity all versions are referred to by the term C161K/O throughout this document.

Ordering Information

The ordering code for Infineon microcontrollers provides an exact reference to the

required product. This ordering code identifies:

• the derivative itself, i.e. its function set, the temperature range, and the supply voltage

• the package and the type of delivery.

For the available ordering codes for the C161K/O please refer to the “Product Catalog

Microcontrollers”, which summarizes all available microcontroller variants.

Note: The ordering codes for Mask-ROM versions are defined for each product after

verification of the respective ROM code.

Data Sheet

2

V2.0, 2001-01

C161K

C161O

Introduction

The C161K/O is a derivative of the Infineon C166 Family of full featured single-chip

CMOS microcontrollers. It combines high CPU performance (up to 12.5 million

instructions per second) with peripheral functionality and enhanced IO-capabilities. The

C161K/O is especially suited for cost sensitive applications.

V_DD

V_SS

Port 0

16 Bit

XTAL1

XTAL2

RSTIN

Port 1

16 Bit

RSTOUT

Port 2

7 Bit

NMI

EA

C161

Port 3

12 Bit

ALE

Port 4

6 Bit

RD

WR/WRL

Port 5

2 Bit

Port 6

4 Bit

MCL02949

Figure 1

Logic Symbol

Data Sheet

3

V2.0, 2001-01

C161K

C161O

Pin Configuration MQFP Package

(top view)

V_SS

1

60

59

58

57

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

P1H.5/A13

P1H.4/A12

P1H.3/A11

P1H.2/A10

P1H.1/A9

XTAL1

XTAL2

V_DD

2

3

4

P3.2/CAPIN

P3.3/T3OUT

P3.4/T3EUD

P3.5/T4IN

5

6

P1H.0/A8

7

P1L.7/A7

8

P1L.6/A6

P3.6/T3IN

9

P1L.5/A5

P3.7/T2IN

10

11

12

13

14

15

16

17

18

19

20

P1L.4/A4

C161K/O

P3.8/MRST

P3.9/MTSR

P3.10/TxD0

P3.11/RxD0

P3.12/BHE/WRH

P3.13/SCLK

P4.0/A16

P1L.3/A3

P1L.2/A2

P1L.1/A1

P1L.0/A0

P0H.7/AD15

P0H.6/AD14

P0H.5/AD13

P0H.4/AD12

P0H.3/AD11

P0H.2/AD10

P4.1/A17

P4.2/A18

P4.3/A19

MCP04858

Figure 2

Note: The marked signals are only available in the C161O.

Please also refer to the detailed description below (shaded lines).

Data Sheet

4

V2.0, 2001-01

C161K

C161O

Table 2

Pin Definitions and Functions

Symbol Pin

Input Function

Outp.

Num

XTAL1 2

I

XTAL1:

Input to the oscillator amplifier and input

to the internal clock generator

XTAL2 3

O

XTAL2:

Output of the oscillator amplifier circuit.

To clock the device from an external source, drive XTAL1,

while leaving XTAL2 unconnected. Minimum and maximum

high/low and rise/fall times specified in the AC

Characteristics must be observed.

P3

IO

Port 3 is a 12-bit bidirectional I/O port. It is bit-wise

programmable for input or output via direction bits. For a pin

configured as input, the output driver is put into high-

impedance state. Port 3 outputs can be configured as push/

pull or open drain drivers. The Port 3 pins serve for following

alternate functions:

P3.2

5

I

CAPIN

GPT2 Register CAPREL Capture Input

This alternate input is only available in the C161O.

P3.3

P3.4

P3.5

P3.6

P3.7

P3.8

P3.9

P3.10

P3.11

P3.12

6

7

8

9

10

11

12

13

14

15

O

I

I/O

O

I/O

O

I/O

T3OUT

T3EUD

T4IN

T3IN

T2IN

MRST

MTSR

TxD0

RxD0

BHE

GPT1 Timer T3 Toggle Latch Output

GPT1 Timer T3 External Up/Down Control Input

GPT1 Timer T4 Count/Gate/Reload/Capture Inp

GPT1 Timer T3 Count/Gate Input

GPT1 Timer T2 Count/Gate/Reload/Capture Inp

SSC Master-Receive/Slave-Transmit Inp./Outp.

SSC Master-Transmit/Slave-Receive Outp./Inp.

ASC0 Clock/Data Output (Async./Sync.)

ASC0 Data Input (Async.) or Inp./Outp. (Sync.)

External Memory High Byte Enable Signal,

External Memory High Byte Write Strobe

SSC Master Clock Output / Slave Clock Input

WRH

SCLK

P3.13

16

P4

IO

Port 4 is a 6-bit bidirectional I/O port. It is bit-wise

programmable for input or output via direction bits. For a pin

configured as input, the output driver is put into high-

impedance state. Port 4 can be used to output the segment

address lines:

P4.0

P4.1

P4.2

P4.3

P4.4

P4.5

17

18

19

20

23

24

O

A16 Least Significant Segment Address Line

A17 Segment Address Line

A18 Segment Address Line

A19 Segment Address Line

A20 Segment Address Line

A21 Most Significant Segment Address Line

Data Sheet

5

V2.0, 2001-01

C161K

C161O

Table 2

Pin Definitions and Functions (cont’d)

Symbol Pin

Input Function

Outp.

Num

RD

25

O

External Memory Read Strobe. RD is activated for every

external instruction or data read access.

WR/

WRL

26

O

External Memory Write Strobe. In WR-mode this pin is

activated for every external data write access. In WRL-mode

this pin is activated for low byte data write accesses on a 16-

bit bus, and for every data write access on an 8-bit bus. See

WRCFG in register SYSCON for mode selection.

ALE

EA

27

28

O

I

Address Latch Enable Output. Can be used for latching the

address into external memory or an address latch in the

multiplexed bus modes.

External Access Enable pin. A low level at this pin during and

after Reset forces the C161K/O to begin instruction

execution out of external memory. A high level forces

execution out of the internal program memory.

“ROMless” versions must have this pin tied to ‘0’.

PORT0

P0L.0-7 29-36

IO

PORT0 consists of the two 8-bit bidirectional I/O ports P0L

and P0H. It is bit-wise programmable for input or output via

direction bits. For a pin configured as input, the output driver

is put into high-impedance state. In case of an external bus

configuration, PORT0 serves as the address (A) and

address/data (AD) bus in multiplexed bus modes and as the

data (D) bus in demultiplexed bus modes.

P0H.0-7 39-46

Demultiplexed bus modes:

Data Path Width:

P0L.0 – P0L.7:

P0H.0 – P0H.7:

8-bit

D0 – D7

I/O

16-bit

D0 – D7

D8 – D15

Multiplexed bus modes:

Data Path Width:

P0L.0 – P0L.7:

P0H.0 – P0H.7:

8-bit

16-bit

AD0 – AD7 AD0 – AD7

A8 – A15 AD8 – AD15

PORT1

P1L.0-7 47-54

IO

PORT1 consists of the two 8-bit bidirectional I/O ports P1L

and P1H. It is bit-wise programmable for input or output via

direction bits. For a pin configured as input, the output driver

is put into high-impedance state. PORT1 is used as the 16-

bit address bus (A) in demultiplexed bus modes and also

after switching from a demultiplexed bus mode to a

multiplexed bus mode.

P1H.0-7 55-62

Data Sheet

6

V2.0, 2001-01

C161K

C161O

Table 2

Pin Definitions and Functions (cont’d)

Symbol Pin

Input Function

Outp.

Num

RSTIN 65

I/O

Reset Input with Schmitt-Trigger characteristics. A low level

at this pin while the oscillator is running resets the C161K/O.

An internal pullup resistor permits power-on reset using only

a capacitor connected to V_SS. A spike filter suppresses input

pulses < 10 ns. Input pulses >100 ns safely pass the filter.

The minimum duration for a safe recognition should be

100 ns + 2 CPU clock cycles.

In bidirectional reset mode (enabled by setting bit BDRSTEN

in register SYSCON) the RSTIN line is internally pulled low

for the duration of the internal reset sequence upon any reset

(HW, SW, WDT). See note below this table.

Note: To let the reset configuration of PORT0 settle a reset

duration of ca. 1 ms is recommended.

RST

OUT

66

67

O

I

Internal Reset Indication Output. This pin is set to a low level

when the part is executing either a hardware-, a software- or

a watchdog timer reset. RSTOUT remains low until the EINIT

(end of initialization) instruction is executed.

NMI

Non-Maskable Interrupt Input. A high to low transition at this

pin causes the CPU to vector to the NMI trap routine. When

the PWRDN (power down) instruction is executed, the NMI

pin must be low in order to force the C161K/O to go into

power down mode. If NMI is high, when PWRDN is

executed, the part will continue to run in normal mode.

If not used, pin NMI should be pulled high externally.

P6

IO

Port 6 is a 4-bit bidirectional I/O port. It is bit-wise

programmable for input or output via direction bits. For a pin

configured as input, the output driver is put into high-

impedance state. Port 6 outputs can be configured as push/

pull or open drain drivers.

The Port 6 pins also serve for alternate functions:

P6.0

P6.1

P6.2

P6.3

68

69

O

CS0

CS1

Chip Select 0 Output

Chip Select 1 Output

70

71

O

CS2

CS3

Chip Select 2 Output

Chip Select 3 Output

These chip select outputs are only available in the C161O.

Data Sheet

7

V2.0, 2001-01

C161K

C161O

Table 2

Pin Definitions and Functions (cont’d)

Symbol Pin

Input Function

Outp.

Num

P2

IO

Port 2 is a 7-bit bidirectional I/O port. It is bit-wise

programmable for input or output via direction bits. For a pin

configured as input, the output driver is put into high-

impedance state. Port 2 outputs can be configured as push/

pull or open drain drivers. The following Port 2 pins serve for

alternate functions:

P2.9

72

73

74

75

I

EX1IN

EX2IN

EX3IN

EX4IN

Fast External Interrupt 1 Input

Fast External Interrupt 2 Input

Fast External Interrupt 3 Input

Fast External Interrupt 4 Input

P2.10

P2.11

P2.12

76

77

78

I

EX5IN

EX6IN

EX7IN

Fast External Interrupt 5 Input

Fast External Interrupt 6 Input

Fast External Interrupt 7 Input

These external interrupts are only available in the C161O.

P5

I

Port 5 is a 2-bit input-only port with Schmitt-Trigger char. The

pins of Port 5 also serve as timer inputs:

P5.14

P5.15

79

80

I

T4EUD

T2EUD

GPT1 Timer T4 External Up/Down Control Input

GPT1 Timer T2 External Up/Down Control Input

V_DD

4, 22,

–

Digital Supply Voltage:

37, 64

+ 5 V or + 3 V during normal operation and idle mode.

≥ 2.5 V during power down mode.

V_SS

1, 21,

–

Digital Ground.

38, 63

Note: The following behavioral differences must be observed when the bidirectional

reset is active:

• Bit BDRSTEN in register SYSCON cannot be changed after EINIT and is cleared

automatically after a reset.

• The reset indication flags always indicate a long hardware reset.

• The PORT0 configuration is treated like on a hardware reset. Especially the bootstrap

loader may be activated when P0L.4 is low.

• Pin RSTIN may only be connected to external reset devices with an open drain output

driver.

• A short hardware reset is extended to the duration of the internal reset sequence.

Data Sheet

8

V2.0, 2001-01

C161K

C161O

Functional Description

The architecture of the C161K/O combines advantages of both RISC and CISC

processors and of advanced peripheral subsystems in a very well-balanced way. In

addition the on-chip memory blocks allow the design of compact systems with maximum

performance.

The following block diagram gives an overview of the different on-chip components and

of the advanced, high bandwidth internal bus structure of the C161K/O.

Note: All time specifications refer to a CPU clock of 25 MHz

(see definition in the AC Characteristics section).

C166-Core

ProgMem

IRAM

Internal

RAM

16

Data

32

16

Internal

ROM

Area

Instr. / Data

CPU

1/2 Kbyte

XTAL

Osc

PEC

External Instr. / Data

16-Level

Priority

Interrupt Controller

WDT

16

Interrupt Bus

Peripheral Data Bus

16

ASC0 SSC GPT1 GPT2

(USART)

(SPI)

T2

T3

T4

EBC

8

XBUS Control

External Bus

Control

8

T5

T6

BRGen

Port 0

16

Port 1

Port 3

Port 5

6

16

15

MCB04323_1ko

Figure 3

Block Diagram

The program memory, the internal RAM (IRAM) and the set of generic peripherals are

connected to the CPU via separate buses. A fourth bus, the XBUS, connects external

resources as well as additional on-chip resources, the X-Peripherals (see Figure 3).

Data Sheet

9

V2.0, 2001-01

C161K

C161O

Memory Organization

The memory space of the C161K/O is configured in a Von Neumann architecture which

means that code memory, data memory, registers and I/O ports are organized within the

same linear address space which includes 16 MBytes. The entire memory space can be

accessed bytewise or wordwise. Particular portions of the on-chip memory have

additionally been made directly bitaddressable.

The C161K/O is prepared to incorporate on-chip program memory (not in the ROM-less

derivatives, of course) for code or constant data. The internal ROM area can be mapped

either to segment 0 or segment 1.

On-chip Internal RAM (IRAM) is provided (1 KByte in the C161K, 2 KBytes in the

C161O) as a storage for user defined variables, for the system stack, general purpose

register banks and even for code. A register bank can consist of up to 16 wordwide (R0

to R15) and/or bytewide (RL0, RH0, …, RL7, RH7) so-called General Purpose Registers

(GPRs).

1024 bytes (2 × 512 bytes) of the address space are reserved for the Special Function

Register areas (SFR space and ESFR space). SFRs are wordwide registers which are

used for controlling and monitoring functions of the different on-chip units. Unused SFR

addresses are reserved for future members of the C166 Family.

In order to meet the needs of designs where more memory is required than is provided

on chip, up to 4 MBytes of external RAM and/or ROM can be connected to the

microcontroller.

Data Sheet

10

V2.0, 2001-01

C161K

C161O

External Bus Controller

All of the external memory accesses are performed by a particular on-chip External Bus

Controller (EBC). It can be programmed either to Single Chip Mode when no external

memory is required, or to one of four different external memory access modes, which are

as follows:

– 16-/18-/20-/22-bit Addresses, 16-bit Data, Demultiplexed

– 16-/18-/20-/22-bit Addresses, 16-bit Data, Multiplexed

– 16-/18-/20-/22-bit Addresses, 8-bit Data, Multiplexed

– 16-/18-/20-/22-bit Addresses, 8-bit Data, Demultiplexed

In the demultiplexed bus modes, addresses are output on PORT1 and data is input/

output on PORT0 or P0L, respectively. In the multiplexed bus modes both addresses

and data use PORT0 for input/output.

Important timing characteristics of the external bus interface (Memory Cycle Time,

Memory Tri-State Time, Length of ALE and Read Write Delay) have been made

programmable to allow the user the adaption of a wide range of different types of

memories and external peripherals.

In addition, up to 4 independent address windows may be defined (via register pairs

ADDRSELx / BUSCONx) which control the access to different resources with different

bus characteristics. These address windows are arranged hierarchically where

BUSCON4 overrides BUSCON3 and BUSCON2 overrides BUSCON1. All accesses to

locations not covered by these 4 address windows are controlled by BUSCON0.

Up to 2 or 4 external CS signals (1 or 3 windows plus default, depending on the device)

can be generated in order to save external glue logic. The C161K/O offers the possibility

to switch the CS outputs to an unlatched mode. In this mode the internal filter logic is

switched off and the CS signals are directly generated from the address. The unlatched

CS mode is enabled by setting CSCFG (SYSCON.6).

For applications which require less than 4 MBytes of external memory space, this

address space can be restricted to 1 MByte, 256 KByte, or to 64 KByte. In this case

Port 4 outputs four, two, or no address lines at all. It outputs all 6 address lines, if an

address space of 4 MBytes is used.

Data Sheet

11

V2.0, 2001-01

C161K

C161O

Central Processing Unit (CPU)

The main core of the CPU consists of a 4-stage instruction pipeline, a 16-bit arithmetic

and logic unit (ALU) and dedicated SFRs. Additional hardware has been spent for a

separate multiply and divide unit, a bit-mask generator and a barrel shifter.

Based on these hardware provisions, most of the C161K/O’s instructions can be

executed in just one machine cycle which requires 80 ns at 25 MHz CPU clock. For

example, shift and rotate instructions are always processed during one machine cycle

independent of the number of bits to be shifted. All multiple-cycle instructions have been

optimized so that they can be executed very fast as well: branches in 2 cycles, a 16 × 16

bit multiplication in 5 cycles and a 32-/16 bit division in 10 cycles. Another pipeline

optimization, the so-called ‘Jump Cache’, allows reducing the execution time of

repeatedly performed jumps in a loop from 2 cycles to 1 cycle.

CPU

16

Internal

RAM

SP

STKOV

STKUN

MDH

MDL

R15

Exec. Unit

Instr. Ptr.

Instr. Reg.

Mul/Div-HW

Bit-Mask Gen

General

Purpose

Registers

R15

ALU

32

4-Stage

Pipeline

(16-bit)

ROM

Barrel - Shifter

Context Ptr.

R0

PSW

SYSCON

BUSCON 0

BUSCON 1

BUSCON 2

BUSCON 3

BUSCON 4

16

R0

ADDRSEL 1

ADDRSEL 2

ADDRSEL 3

ADDRSEL 4

Data Page Ptr.

Code Seg. Ptr.

MCB02147

Figure 4

CPU Block Diagram

Data Sheet

12

V2.0, 2001-01

C161K

C161O

The CPU has a register context consisting of up to 16 wordwide GPRs at its disposal.

These 16 GPRs are physically allocated within the on-chip RAM area. A Context Pointer

(CP) register determines the base address of the active register bank to be accessed by

the CPU at any time. The number of register banks is only restricted by the available

internal RAM space. For easy parameter passing, a register bank may overlap others.

A system stack of up to 1024 words is provided as a storage for temporary data. The

system stack is allocated in the on-chip RAM area, and it is accessed by the CPU via the

stack pointer (SP) register. Two separate SFRs, STKOV and STKUN, are implicitly

compared against the stack pointer value upon each stack access for the detection of a

stack overflow or underflow.

The high performance offered by the hardware implementation of the CPU can efficiently

be utilized by a programmer via the highly efficient C161K/O instruction set which

includes the following instruction classes:

– Arithmetic Instructions

– Logical Instructions

– Boolean Bit Manipulation Instructions

– Compare and Loop Control Instructions

– Shift and Rotate Instructions

– Prioritize Instruction

– Data Movement Instructions

– System Stack Instructions

– Jump and Call Instructions

– Return Instructions

– System Control Instructions

– Miscellaneous Instructions

The basic instruction length is either 2 or 4 bytes. Possible operand types are bits, bytes

and words. A variety of direct, indirect or immediate addressing modes are provided to

specify the required operands.

Data Sheet

13

V2.0, 2001-01

C161K

C161O

Interrupt System

With an interrupt response time within a range from just 5 to 12 CPU clocks (in case of

internal program execution), the C161K/O is capable of reacting very fast to the

occurrence of non-deterministic events.

The architecture of the C161K/O supports several mechanisms for fast and flexible

response to service requests that can be generated from various sources internal or

external to the microcontroller. Any of these interrupt requests can be programmed to

being serviced by the Interrupt Controller or by the Peripheral Event Controller (PEC).

In contrast to a standard interrupt service where the current program execution is

suspended and a branch to the interrupt vector table is performed, just one cycle is

‘stolen’ from the current CPU activity to perform a PEC service. A PEC service implies a

single byte or word data transfer between any two memory locations with an additional

increment of either the PEC source or the destination pointer. An individual PEC transfer

counter is implicity decremented for each PEC service except when performing in the

continuous transfer mode. When this counter reaches zero, a standard interrupt is

performed to the corresponding source related vector location. PEC services are very

well suited, for example, for supporting the transmission or reception of blocks of data.

The C161K/O has 8 PEC channels each of which offers such fast interrupt-driven data

transfer capabilities.

A separate control register which contains an interrupt request flag, an interrupt enable

flag and an interrupt priority bitfield exists for each of the possible interrupt sources. Via

its related register, each source can be programmed to one of sixteen interrupt priority

levels. Once having been accepted by the CPU, an interrupt service can only be

interrupted by a higher prioritized service request. For the standard interrupt processing,

each of the possible interrupt sources has a dedicated vector location.

Fast external interrupt inputs are provided to service external interrupts with high

precision requirements. These fast interrupt inputs feature programmable edge

detection (rising edge, falling edge or both edges).

Software interrupts are supported by means of the ‘TRAP’ instruction in combination with

an individual trap (interrupt) number.

Table 3 shows all of the possible C161K/O interrupt sources and the corresponding

hardware-related interrupt flags, vectors, vector locations and trap (interrupt) numbers.

Note: Interrupt nodes which are not used by associated peripherals, may be used to

generate software controlled interrupt requests by setting the respective interrupt

request bit (xIR).

Data Sheet

14

V2.0, 2001-01

C161K

C161O

Table 3

C161K/O Interrupt Nodes

Source of Interrupt or Request

PEC Service Request Flag

Enable

Flag

Interrupt Vector

Trap

Vector

Location Number

External Interrupt 1

External Interrupt 2

External Interrupt 3

External Interrupt 4

External Interrupt 5

External Interrupt 6

External Interrupt 7

GPT1 Timer 2

CC9IR

CC10IR

CC11IR

CC12IR

CC13IR

CC14IR

CC15IR

T2IR

CC9IE

CC10IE

CC11IE

CC12IE

CC13IE

CC14IE

CC15IE

T2IE

CC9INT

00’0064_H19_H

CC10INT 00’0068_H1A_H

CC11INT 00’006C_H1B_H

CC12INT 00’0070_H1C_H

CC13INT 00’0074_H1D_H

CC14INT 00’0078_H1E_H

CC15INT 00’007C_H1F_H

T2INT

T3INT

T4INT

T5INT

T6INT

CRINT

S0TINT

00’0088_H22_H

00’008C_H23_H

00’0090_H24_H

00’0094_H25_H

00’0098_H26_H

00’009C_H27_H

00’00A8_H2A_H

GPT1 Timer 3

T3IR

T3IE

GPT1 Timer 4

T4IR

T4IE

GPT2 Timer 5

T5IR

T5IE

GPT2 Timer 6

T6IR

T6IE

GPT2 CAPREL Reg.

ASC0 Transmit

CRIR

CRIE

S0TIR

S0TIE

S0TBIE

S0RIE

S0EIE

SCTIE

SCRIE

SCEIE

ASC0 Transmit Buffer S0TBIR

S0TBINT 00’011C_H47_H

ASC0 Receive

ASC0 Error

S0RIR

S0EIR

SCTIR

SCRIR

SCEIR

S0RINT

S0EINT

SCTINT

SCRINT

SCEINT

00’00AC_H2B_H

00’00B0_H2C_H

00’00B4_H2D_H

00’00B8_H2E_H

00’00BC_H2F_H

SSC Transmit

SSC Receive

SSC Error

Note: The shaded interrupt nodes are only available in the C161O, not in the C161K.

Data Sheet

15

V2.0, 2001-01

C161K

C161O

The C161K/O also provides an excellent mechanism to identify and to process

exceptions or error conditions that arise during run-time, so-called ‘Hardware Traps’.

Hardware traps cause immediate non-maskable system reaction which is similar to a

standard interrupt service (branching to a dedicated vector table location). The

occurrence of a hardware trap is additionally signified by an individual bit in the trap flag

register (TFR). Except when another higher prioritized trap service is in progress, a

hardware trap will interrupt any actual program execution. In turn, hardware trap services

can normally not be interrupted by standard or PEC interrupts.

Table 4 shows all of the possible exceptions or error conditions that can arise during run-

time:

Table 4

Hardware Trap Summary

Exception Condition

Trap

Flag

Trap

Vector

Location

Trap

Number

Trap

Priority

Reset Functions:

–

– Hardware Reset

– Software Reset

– W-dog Timer Overflow

RESET

00’0000_H

00_H

III

Class A Hardware Traps:

– Non-Maskable Interrupt NMI

NMITRAP 00’0008_H

STOTRAP 00’0010_H

STUTRAP 00’0018_H

02_H

04_H

06_H

II

– Stack Overflow

– Stack Underflow

STKOF

STKUF

Class B Hardware Traps:

– Undefined Opcode

– Protected Instruction

Fault

UNDOPC BTRAP

PRTFLT BTRAP

00’0028_H

0A_H

I

– Illegal Word Operand

Access

– Illegal Instruction

Access

– Illegal External Bus

Access

ILLOPA

ILLINA

ILLBUS

BTRAP

00’0028_H

0A_H

I

Reserved

–

[2C_H–

3C_H]

[0B_H–

0F_H]

–

Software Traps

– TRAP Instruction

Any

Current

CPU

Priority

[00’0000_H– [00_H–

00’01FC_H] 7F_H]

in steps

of 4_H

Data Sheet

16

V2.0, 2001-01

C161K

C161O

General Purpose Timer (GPT) Unit

The GPT unit represents a very flexible multifunctional timer/counter structure which

may be used for many different time related tasks such as event timing and counting,

pulse width and duty cycle measurements, pulse generation, or pulse multiplication.

The GPT unit incorporates five 16-bit timers which are organized in two separate

modules, GPT1 and GPT2. Each timer in each module may operate independently in a

number of different modes, or may be concatenated with another timer of the same

module.

Each of the three timers T2, T3, T4 of module GPT1 can be configured individually for

one of four basic modes of operation, which are Timer, Gated Timer, Counter, and

Incremental Interface Mode. In Timer Mode, the input clock for a timer is derived from

the CPU clock, divided by a programmable prescaler, while Counter Mode allows a timer

to be clocked in reference to external events.

Pulse width or duty cycle measurement is supported in Gated Timer Mode, where the

operation of a timer is controlled by the ‘gate’ level on an external input pin. For these

purposes, each timer has one associated port pin (TxIN) which serves as gate or clock

input. The maximum resolution of the timers in module GPT1 is 16 TCL.

The count direction (up/down) for each timer is programmable by software or may

additionally be altered dynamically by an external signal on a port pin (TxEUD) to

facilitate e.g. position tracking.

In Incremental Interface Mode the GPT1 timers (T2, T3, T4) can be directly connected

to the incremental position sensor signals A and B via their respective inputs TxIN and

TxEUD. Direction and count signals are internally derived from these two input signals,

so the contents of the respective timer Tx corresponds to the sensor position. The third

position sensor signal TOP0 can be connected to an interrupt input.

Timer T3 has an output toggle latch (T3OTL) which changes its state on each timer over-

flow/underflow. The state of this latch may be output on pin T3OUT e.g. for time out

monitoring of external hardware components, or may be used internally to clock timers

T2 and T4 for measuring long time periods with high resolution.

In addition to their basic operating modes, timers T2 and T4 may be configured as reload

or capture registers for timer T3. When used as capture or reload registers, timers T2

and T4 are stopped. The contents of timer T3 is captured into T2 or T4 in response to a

signal at their associated input pins (TxIN). Timer T3 is reloaded with the contents of T2

or T4 triggered either by an external signal or by a selectable state transition of its toggle

latch T3OTL. When both T2 and T4 are configured to alternately reload T3 on opposite

state transitions of T3OTL with the low and high times of a PWM signal, this signal can

be constantly generated without software intervention.

Data Sheet

17

V2.0, 2001-01

C161K

C161O

T2EUD

f_CPU

T2IN

U/D

Interrupt

Request

2ⁿ: 1

GPT1 Timer T2

T2

Mode

Control

Reload

Capture

Interrupt

Request

f_CPU

2ⁿ: 1

Toggle FF

T3OTL

T3

Mode

Control

T3IN

GPT1 Timer T3

T3OUT

U/D

T3EUD

Other

Timers

Capture

Reload

T4IN

T4

Mode

Control

Interrupt

Request

2ⁿ: 1

GPT1 Timer T4

U/D

f_CPU

T4EUD

MCT02141

n = 3 … 10

Figure 5

Block Diagram of GPT1

With its maximum resolution of 8 TCL, the GPT2 module provides precise event control

and time measurement. It includes two timers (T5, T6) and a capture/reload register

(CAPREL). Both timers can be clocked with an input clock which is derived from the CPU

clock. The count direction (up/down) for each timer is programmable by software.

Concatenation of the timers is supported via the output toggle latch (T6OTL) of timer T6,

which changes its state on each timer overflow/underflow.

The state of this latch may be used to clock timer T5. The overflows/underflows of timer

T6 can cause a reload from the CAPREL register. The CAPREL register may capture

the contents of timer T5 based on an external signal transition on the corresponding port

pin (CAPIN), and timer T5 may optionally be cleared after the capture procedure. This

allows the C161K/O to measure absolute time differences or to perform pulse

multiplication without software overhead.

Data Sheet

18

V2.0, 2001-01

C161K

C161O

The capture trigger (timer T5 to CAPREL) may also be generated upon transitions of

GPT1 timer T3’s inputs T3IN and/or T3EUD. This is especially advantageous when T3

operates in Incremental Interface Mode.

Note: Block GPT2 is only available in the C161O, not in the C161K.

f_CPU

2ⁿ: 1

T5

Mode

Control

U/D

Interrupt

Request

GPT2 Timer T5

Clear

Capture

T3

Interrupt

Request

MUX

CT3

CAPIN

GPT2 CAPREL

Interrupt

Request

T6OTL

GPT2 Timer T6

U/D

T6OUT

T6

Mode

Control

f_CPU

2ⁿ: 1

Other

Timers

MCB02938

n = 2 … 9

Figure 6

Block Diagram of GPT2

Data Sheet

19

V2.0, 2001-01

C161K

C161O

Serial Channels

Serial communication with other microcontrollers, processors, terminals or external

peripheral components is provided by two serial interfaces with different functionality, an

Asynchronous/Synchronous Serial Channel (ASC0) and a High-Speed Synchronous

Serial Channel (SSC).

The ASC0 is upward compatible with the serial ports of the Infineon 8-bit microcontroller

families and supports full-duplex asynchronous communication at up to 781 kBaud and

half-duplex synchronous communication at up to 3.1 MBaud (@ 25 MHz CPU clock).

A dedicated baud rate generator allows to set up all standard baud rates without

oscillator tuning. For transmission, reception and error handling 4 separate interrupt

vectors are provided. In asynchronous mode, 8- or 9-bit data frames are transmitted or

received, preceded by a start bit and terminated by one or two stop bits. For

multiprocessor communication, a mechanism to distinguish address from data bytes has

been included (8-bit data plus wake up bit mode).

In synchronous mode, the ASC0 transmits or receives bytes (8 bits) synchronously to a

shift clock which is generated by the ASC0. The ASC0 always shifts the LSB first. A loop

back option is available for testing purposes.

A number of optional hardware error detection capabilities has been included to increase

the reliability of data transfers. A parity bit can automatically be generated on

transmission or be checked on reception. Framing error detection allows to recognize

data frames with missing stop bits. An overrun error will be generated, if the last

character received has not been read out of the receive buffer register at the time the

reception of a new character is complete.

The SSC supports full-duplex synchronous communication at up to 6.25 MBaud

(@ 25 MHz CPU clock). It may be configured so it interfaces with serially linked

peripheral components. A dedicated baud rate generator allows to set up all standard

baud rates without oscillator tuning. For transmission, reception, and error handling three

separate interrupt vectors are provided.

The SSC transmits or receives characters of 2 … 16 bits length synchronously to a shift

clock which can be generated by the SSC (master mode) or by an external master (slave

mode). The SSC can start shifting with the LSB or with the MSB and allows the selection

of shifting and latching clock edges as well as the clock polarity.

A number of optional hardware error detection capabilities has been included to increase

the reliability of data transfers. Transmit and receive error supervise the correct handling

of the data buffer. Phase and baudrate error detect incorrect serial data.

Data Sheet

20

V2.0, 2001-01

C161K

C161O

Watchdog Timer

The Watchdog Timer represents one of the fail-safe mechanisms which have been

implemented to prevent the controller from malfunctioning for longer periods of time.

The Watchdog Timer is always enabled after a reset of the chip, and can only be

disabled in the time interval until the EINIT (end of initialization) instruction has been

executed. Thus, the chip’s start-up procedure is always monitored. The software has to

be designed to service the Watchdog Timer before it overflows. If, due to hardware or

software related failures, the software fails to do so, the Watchdog Timer overflows and

generates an internal hardware reset and pulls the RSTOUT pin low in order to allow

external hardware components to be reset.

The Watchdog Timer is a 16-bit timer, clocked with the system clock divided by 2/128.

The high byte of the Watchdog Timer register can be set to a prespecified reload value

(stored in WDTREL) in order to allow further variation of the monitored time interval.

Each time it is serviced by the application software, the high byte of the Watchdog Timer

is reloaded. Thus, time intervals between 20 µs and 336 ms can be monitored

(@ 25 MHz).

The default Watchdog Timer interval after reset is 5.24 ms (@ 25 MHz).

Parallel Ports

The C161K/O provides up to 63 I/O lines which are organized into six input/output ports

and one input port. All port lines are bit-addressable, and all input/output lines are

individually (bit-wise) programmable as inputs or outputs via direction registers. The I/O

ports are true bidirectional ports which are switched to high impedance state when

configured as inputs. The output drivers of three I/O ports can be configured (pin by pin)

for push/pull operation or open-drain operation via control registers. During the internal

reset, all port pins are configured as inputs.

All port lines have programmable alternate input or output functions associated with

them. All port lines that are not used for these alternate functions may be used as general

purpose IO lines.

PORT0 and PORT1 may be used as address and data lines when accessing external

memory, while Port 4 outputs the additional segment address bits A21/19/17 … A16 in

systems where segmentation is enabled to access more than 64 KBytes of memory.

Port 6 provides optional chip select signals.

Port 3 includes alternate functions of timers, serial interfaces, and the optional bus

control signal BHE/WRH.

Port 5 is used for timer control signals.

Data Sheet

21

V2.0, 2001-01

C161K

C161O

Instruction Set Summary

Table 5 lists the instructions of the C161K/O in a condensed way.

The various addressing modes that can be used with a specific instruction, the operation

of the instructions, parameters for conditional execution of instructions, and the opcodes

for each instruction can be found in the “C166 Family Instruction Set Manual”.

This document also provides a detailed description of each instruction.

Table 5

Mnemonic

ADD(B)

ADDC(B)

SUB(B)

SUBC(B)

MUL(U)

DIV(U)

Instruction Set Summary

Description

Bytes

2 / 4

Add word (byte) operands

Add word (byte) operands with Carry

Subtract word (byte) operands

Subtract word (byte) operands with Carry

(Un)Signed multiply direct GPR by direct GPR (16-16-bit) 2

(Un)Signed divide register MDL by direct GPR (16-/16-bit) 2

(Un)Signed long divide reg. MD by direct GPR (32-/16-bit) 2

DIVL(U)

CPL(B)

NEG(B)

AND(B)

OR(B)

Complement direct word (byte) GPR

Negate direct word (byte) GPR

Bitwise AND, (word/byte operands)

Bitwise OR, (word/byte operands)

Bitwise XOR, (word/byte operands)

Clear direct bit

2

2 / 4

2

XOR(B)

BCLR

BSET

Set direct bit

2

BMOV(N)

Move (negated) direct bit to direct bit

AND/OR/XOR direct bit with direct bit

4

BAND, BOR,

BXOR

4

BCMP

Compare direct bit to direct bit

4

BFLDH/L

Bitwise modify masked high/low byte of bit-addressable

direct word memory with immediate data

CMP(B)

CMPD1/2

CMPI1/2

PRIOR

Compare word (byte) operands

2 / 4

Compare word data to GPR and decrement GPR by 1/2 2 / 4

Compare word data to GPR and increment GPR by 1/2

2 / 4

2

Determine number of shift cycles to normalize direct

word GPR and store result in direct word GPR

SHL / SHR

ROL / ROR

ASHR

Shift left/right direct word GPR

2

Rotate left/right direct word GPR

Arithmetic (sign bit) shift right direct word GPR

Data Sheet

22

V2.0, 2001-01

C161K

C161O

Table 5

Instruction Set Summary (cont’d)

Description

Mnemonic

MOV(B)

MOVBS

MOVBZ

Bytes

Move word (byte) data

2 / 4

Move byte operand to word operand with sign extension 2 / 4

Move byte operand to word operand. with zero extension 2 / 4

JMPA, JMPI,

JMPR

Jump absolute/indirect/relative if condition is met

4

JMPS

J(N)B

JBC

Jump absolute to a code segment

4

Jump relative if direct bit is (not) set

Jump relative and clear bit if direct bit is set

Jump relative and set bit if direct bit is not set

JNBS

CALLA, CALLI,

CALLR

Call absolute/indirect/relative subroutine if condition is met 4

CALLS

PCALL

Call absolute subroutine in any code segment

4

Push direct word register onto system stack and call

absolute subroutine

TRAP

Call interrupt service routine via immediate trap number

Push/pop direct word register onto/from system stack

2

4

PUSH, POP

SCXT

Push direct word register onto system stack and update

register with word operand

RET

Return from intra-segment subroutine

Return from inter-segment subroutine

2

RETS

RETP

Return from intra-segment subroutine and pop direct

word register from system stack

RETI

Return from interrupt service subroutine

Software Reset

2

SRST

4

IDLE

Enter Idle Mode

4

PWRDN

SRVWDT

DISWDT

EINIT

Enter Power Down Mode (supposes NMI-pin being low)

Service Watchdog Timer

4

Disable Watchdog Timer

4

Signify End-of-Initialization on RSTOUT-pin

Begin ATOMIC sequence

4

ATOMIC

EXTR

2

Begin EXTended Register sequence

Begin EXTended Page (and Register) sequence

Begin EXTended Segment (and Register) sequence

Null operation

2

EXTP(R)

EXTS(R)

NOP

2 / 4

2

Data Sheet

23

V2.0, 2001-01

C161K

C161O

Special Function Registers Overview

The following table lists all SFRs which are implemented in the C161K/O in alphabetical

order.

Bit-addressable SFRs are marked with the letter “b” in column “Name”. SFRs within the

Extended SFR-Space (ESFRs) are marked with the letter “E” in column “Physical

Address”. Registers within on-chip X-peripherals are marked with the letter “X” in column

“Physical Address”.

An SFR can be specified via its individual mnemonic name. Depending on the selected

addressing mode, an SFR can be accessed via its physical address (using the Data

Page Pointers), or via its short 8-bit address (without using the Data Page Pointers).

Note: The shaded registers are only available in the C161O, not in the C161K.

Table 6

Name

C161K/O Registers, Ordered by Name

Physical 8-Bit Description

Reset

Value

Address

FE18_H

FE1A_H

FE1C_H

FE1E_H

Addr.

0C_H

0D_H

0E_H

0F_H

86_H

ADDRSEL1

ADDRSEL2

ADDRSEL3

ADDRSEL4

Address Select Register 1

0000_H

0XX0_H

0000_H

FC00_H

0000_H

Address Select Register 2

Address Select Register 3

Address Select Register 4

BUSCON0 b FF0C_H

BUSCON1 b FF14_H

BUSCON2 b FF16_H

BUSCON3 b FF18_H

BUSCON4 b FF1A_H

Bus Configuration Register 0

Bus Configuration Register 1

Bus Configuration Register 2

Bus Configuration Register 3

Bus Configuration Register 4

GPT2 Capture/Reload Register

EX2IN Interrupt Control Register

EX3IN Interrupt Control Register

EX4IN Interrupt Control Register

EX5IN Interrupt Control Register

8A_H

8B_H

8C_H

8D_H

25_H

CAPREL

CC10IC

CC11IC

CC12IC

CC13IC

CC14IC

CC15IC

CC9IC

CP

FE4A_H

b FF8C_H

b FF8E_H

b FF90_H

b FF92_H

b FF94_H

b FF96_H

b FF8A_H

FE10_H

C6_H

C7_H

C8_H

C9_H

CA_HEX6IN Interrupt Control Register

CB_HEX7IN Interrupt Control Register

C5_H

08_H

B5_H

04_H

EX1IN Interrupt Control Register

CPU Context Pointer Register

CRIC

b FF6A_H

FE08_H

GPT2 CAPREL Interrupt Ctrl. Reg.

CPU Code Seg. Pointer Reg. (read only)

CSP

Data Sheet

24

V2.0, 2001-01

C161K

C161O

Table 6

Name

C161K/O Registers, Ordered by Name (cont’d)

Physical 8-Bit Description

Reset

Value

Address

Addr.

DP0H

DP0L

DP1H

DP1L

DP2

b F102_HE 81_H

b F100_HE 80_H

b F106_HE 83_H

b F104_HE 82_H

P0H Direction Control Register

P0L Direction Control Register

P1H Direction Control Register

P1L Direction Control Register

Port 2 Direction Control Register

Port 3 Direction Control Register

Port 4 Direction Control Register

Port 6 Direction Control Register

CPU Data Page Pointer 0 Reg. (10 bits)

CPU Data Page Pointer 1 Reg. (10 bits)

CPU Data Page Pointer 2 Reg. (10 bits)

CPU Data Page Pointer 3 Reg. (10 bits)

External Interrupt Control Register

Identifier

00_H

b FFC2_H

b FFC6_H

b FFCA_H

b FFCE_H

FE00_H

E1_H

E3_H

E5_H

E7_H

00_H

01_H

02_H

03_H

0000_H

00_H

DP3

DP4

DP6

00_H

DPP0

DPP1

DPP2

DPP3

EXICON

IDCHIP

IDMANUF

IDMEM

IDMEM2

IDPROG

MDC

0000_H

0001_H

0002_H

0003_H

0000_H

05XX_H

1820_H

0000_H

00_H

FE02_H

FE04_H

FE06_H

b F1C0_HE E0_H

F07C_HE 3E_H

F07E_HE 3F_H

F07A_HE 3D_H

F076_HE 3B_H

F078_HE 3C_H

Identifier

b FF0E_H

FE0C_H

87_H

06_H

07_H

CPU Multiply Divide Control Register

CPU Multiply Divide Reg. – High Word

CPU Multiply Divide Reg. – Low Word

Port 2 Open Drain Control Register

Port 3 Open Drain Control Register

Port 6 Open Drain Control Register

Constant Value 1’s Register (read only)

Port 0 High Reg. (Upper half of PORT0)

Port 0 Low Reg. (Lower half of PORT0)

Port 1 High Reg. (Upper half of PORT1)

Port 1 Low Reg.(Lower half of PORT1)

Port 2 Register

MDH

MDL

FE0E_H

ODP2

ODP3

ODP6

ONES

P0H

b F1C2_HE E1_H

b F1C6_HE E3_H

b F1CE_HE E7_H

b FF1E_H

b FF02_H

b FF00_H

b FF06_H

b FF04_H

b FFC0_H

8F_H

81_H

80_H

83_H

82_H

E0_H

FFFF_H

00_H

P0L

00_H

P1H

00_H

P1L

00_H

P2

0000_H

Data Sheet

25

V2.0, 2001-01

C161K

C161O

Table 6

Name

C161K/O Registers, Ordered by Name (cont’d)

Physical 8-Bit Description

Reset

Value

Address

b FFC4_H

b FFC8_H

b FFA2_H

b FFCC_H

FEC0_H

Addr.

E2_H

E4_H

D1_H

E6_H

60_H

61_H

62_H

63_H

64_H

65_H

66_H

67_H

88_H

P3

Port 3 Register

0000_H

00_H

P4

Port 4 Register (8 bits)

P5

Port 5 Register (read only)

XXXX_H

00_H

P6

Port 6 Register (8 bits)

PECC0

PECC1

PECC2

PECC3

PECC4

PECC5

PECC6

PECC7

PSW

PEC Channel 0 Control Register

PEC Channel 1 Control Register

PEC Channel 2 Control Register

PEC Channel 3 Control Register

PEC Channel 4 Control Register

PEC Channel 5 Control Register

PEC Channel 6 Control Register

PEC Channel 7 Control Register

CPU Program Status Word

System Startup Config. Reg. (Rd. only)

0000_H

XX_H

FEC2_H

FEC4_H

FEC6_H

FEC8_H

FECA_H

FECC_H

FECE_H

b FF10_H

RP0H

S0BG

b F108_HE 84_H

FEB4_H

5A_H

Serial Channel 0 Baud Rate Generator

Reload Register

0000_H

S0CON

S0EIC

b FFB0_H

b FF70_H

FEB2_H

D8_H

B8_H

59_H

Serial Channel 0 Control Register

0000_H

XX_H

Serial Channel 0 Error Interrupt Ctrl. Reg

S0RBUF

Serial Channel 0 Receive Buffer Reg.

(read only)

S0RIC

b FF6E_H

B7_H

Serial Channel 0 Receive Interrupt

Control Register

0000_H

00_H

S0TBIC

S0TBUF

S0TIC

b F19C_HE CE_HSerial Channel 0 Transmit Buffer

Interrupt Control Register

FEB0_H

b FF6C_H

FE12_H

58_H

B6_H

09_H

Serial Channel 0 Transmit Buffer

Register (write only)

Serial Channel 0 Transmit Interrupt

Control Register

0000_H

SP

CPU System Stack Pointer Register

SSC Baudrate Register

FC00_H

0000_H

SSCBR

F0B4_HE 5A_H

SSCCON b FFB2_H

D9_H

SSC Control Register

Data Sheet

26

V2.0, 2001-01

C161K

C161O

Table 6

Name

C161K/O Registers, Ordered by Name (cont’d)

Physical 8-Bit Description

Reset

Value

Address

Addr.

SSCEIC

SSCRB

SSCRIC

SSCTB

SSCTIC

STKOV

STKUN

b FF76_H

BB_H

SSC Error Interrupt Control Register

SSC Receive Buffer

0000_H

XXXX_H

0000_H

FA00_H

FC00_H

¹⁾0XX0_H

0000_H

²⁾00XX_H

0000_H

F0B2_HE 59_H

b FF74_H

BA_H

SSC Receive Interrupt Control Register

SSC Transmit Buffer

F0B0_HE 58_H

b FF72_H

B9_H

0A_H

0B_H

89_H

20_H

A0_H

B0_H

21_H

A1_H

B1_H

22_H

A2_H

B2_H

23_H

A3_H

B3_H

24_H

A4_H

B4_H

D6_H

57_H

D7_H

8E_H

SSC Transmit Interrupt Control Register

CPU Stack Overflow Pointer Register

CPU Stack Underflow Pointer Register

CPU System Configuration Register

GPT1 Timer 2 Register

FE14_H

FE16_H

SYSCON b FF12_H

T2

FE40_H

b FF40_H

b FF60_H

FE42_H

T2CON

T2IC

T3

GPT1 Timer 2 Control Register

GPT1 Timer 2 Interrupt Control Register

GPT1 Timer 3 Register

T3CON

T3IC

T4

b FF42_H

b FF62_H

FE44_H

GPT1 Timer 3 Control Register

GPT1 Timer 3 Interrupt Control Register

GPT1 Timer 4 Register

T4CON

T4IC

T5

b FF44_H

b FF64_H

FE46_H

GPT1 Timer 4 Control Register

GPT1 Timer 4 Interrupt Control Register

GPT2 Timer 5 Register

T5CON

T5IC

T6

b FF46_H

b FF66_H

FE48_H

GPT2 Timer 5 Control Register

GPT2 Timer 5 Interrupt Control Register

GPT2 Timer 6 Register

T6CON

T6IC

TFR

b FF48_H

b FF68_H

b FFAC_H

FEAE_H

GPT2 Timer 6 Control Register

GPT2 Timer 6 Interrupt Control Register

Trap Flag Register

WDT

Watchdog Timer Register (read only)

Watchdog Timer Control Register

Constant Value 0’s Register (read only)

WDTCON b FFAE_H

ZEROS

b FF1C_H

1)

The system configuration is selected during reset.

2)

The reset value depends on the indicated reset source.

Data Sheet

27

V2.0, 2001-01

C161K

C161O

Absolute Maximum Ratings

Table 7

Absolute Maximum Rating Parameters

Parameter

Symbol

Limit Values

Unit Notes

min.

max.

150

6.5

Storage temperature

Junction temperature

T_ST

T_J

-65

-40

-0.5

°C

V

–

under bias

Voltage on V_DDpins with V_DD

respect to ground (V_SS)

–

Voltage on any pin with

respect to ground (V_SS)

V_IN

-0.5

-10

–

V

_DD+ 0.5 V

–

Input current on any pin

during overload condition

–

10

mA

Absolute sum of all input

currents during overload

condition

–

|100|

Power dissipation

P_DISS

–

1.5

W

–

Note: Stresses above those listed under “Absolute Maximum Ratings” may cause

permanent damage to the device. This is a stress rating only and functional

operation of the device at these or any other conditions above those indicated in

the operational sections of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect device reliability.

During absolute maximum rating overload conditions (V_IN> V_DDor V_IN< V_SS) the

voltage on V_DDpins with respect to ground (V_SS) must not exceed the values

defined by the absolute maximum ratings.

Data Sheet

28

V2.0, 2001-01

C161K

C161O

Operating Conditions

The following operating conditions must not be exceeded in order to ensure correct

operation of the C161K/O. All parameters specified in the following sections refer to

these operating conditions, unless otherwise noticed.

Table 8

Operating Condition Parameters

Parameter

Symbol

Limit Values

Unit Notes

min.

max.

Standard

digital supply voltage

(5 V versions)

V_DD

4.5

5.5

V

Active mode,

_CPUmax= 25 MHz

f

2.5¹⁾

3.0

5.5

3.6

V

Power Down mode

Reduced

V_DD

Active mode,

digital supply voltage

(3 V versions)

f_CPUmax= 20 MHz

2.5¹⁾

3.6

V

Power Down mode

Digital ground voltage

Overload current

V_SS

I_OV

0

Reference voltage

mA Per pin²⁾³⁾

–

±5

3)

Absolute sum of overload Σ|I_OV|

50

mA

currents

External Load

Capacitance

C_L

T_A

–

100

pF

–

Ambient temperature

0

70

°C

SAB-C161K/O …

SAF-C161K/O …

SAK-C161K/O …

-40

85

125

1)

Output voltages and output currents will be reduced when V_DDleaves the range defined for active mode.

2)

Overload conditions occur if the standard operatings conditions are exceeded, i.e. the voltage on any pin

exceeds the specified range (i.e. V_OV> V_DD+ 0.5 V or V_OV< V_SS- 0.5 V). The absolute sum of input overload

currents on all pins may not exceed 50 mA. The supply voltage must remain within the specified limits.

Proper operation is not guaranteed if overload conditions occur on functional pins such as XTAL1, RD, WR,

etc.

3)

Not 100% tested, guaranteed by design and characterization.

Data Sheet

29

V2.0, 2001-01

C161K

C161O

Parameter Interpretation

The parameters listed in the following partly represent the characteristics of the C161K/

O and partly its demands on the system. To aid in interpreting the parameters right, when

evaluating them for a design, they are marked in column “Symbol”:

CC (Controller Characteristics):

The logic of the C161K/O will provide signals with the respective timing characteristics.

SR (System Requirement):

The external system must provide signals with the respective timing characteristics to

the C161K/O.

DC Characteristics (Standard Supply Voltage Range)

(Operating Conditions apply)¹⁾

Parameter

Symbol

Limit Values Unit Test Condition

min.

max.

Input low voltage (TTL,

all except XTAL1)

V_ILSR -0.5

0.2 V_DD

- 0.1

V

–

Input low voltage XTAL1

V_IL2SR -0.5

0.3 V_DD

V

–

Input high voltage (TTL,

all except RSTIN and XTAL1)

V_IHSR 0.2 V_DDV_DD

+ 0.9 0.5

+

Input high voltage RSTIN

(when operated as input)

V_IH1SR 0.6 V_DDV_DD

V

–

0.5

Input high voltage XTAL1

V_IH2SR 0.7 V_DDV_DD

0.5

Output low voltage

V_OLCC –

0.45

I

_OL= 2.4 mA

(PORT0, PORT1, Port 4, ALE,

RD, WR, BHE, RSTOUT,

RSTIN²⁾)

Output low voltage

(all other outputs)

V

_OL1CC –

0.45

V

I_OL= 1.6 mA

Output high voltage³⁾

(PORT0, PORT1, Port 4, ALE,

RD, WR, BHE, RSTOUT)

V_OHCC 2.4

0.9V_DD

–

V

I

_OH= -2.4 mA

_OH= -0.5 mA

I

Output high voltage³⁾

(all other outputs)

V

_OH1CC 2.4

0.9V_DD

I_OZ1CC –

–

V

I

_OH= -1.6 mA

_OH= -0.5 mA

I

Input leakage current (Port 5)

±200

±500

-10

nA 0 V < V_IN< V_DD

nA 0.45 V < V_IN< V_DD

µA V_IN= V_IH1

Input leakage current (all other) I_OZ2CC –

RSTIN inactive current⁴⁾

5)

I_RSTH

–

Data Sheet

30

V2.0, 2001-01

C161K

C161O

DC Characteristics (Standard Supply Voltage Range) (cont’d)

(Operating Conditions apply)¹⁾

Parameter

Symbol

Limit Values Unit Test Condition

min.

-100

–

max.

–

6)

RSTIN active current⁴⁾

RD/WR inact. current⁷⁾

RD/WR active current⁷⁾

ALE inactive current⁷⁾

ALE active current⁷⁾

Port 6 inactive current⁷⁾

Port 6 active current⁷⁾

PORT0 configuration current⁷⁾I_P0H

I_RSTL

µA V_IN= V_IL

5)

I_RWH

-40

–

µA

V

_OUT= 2.4 V

6)

I_RWL

-500

–

_OUT= V_OLmax

_OUT= 2.4 V

5)

I_ALEL

40

–

6)

I_ALEH

500

–

5)

I_P6H

-40

–

_OUT= 2.4 V

6)

I_P6L

-500

–

_OUT= V_OL1max

5)

-10

–

µA V_IN= V_IHmin

µA V_IN= V_ILmax

µA 0 V < V_IN< V_DD

6)

I_P0L

-100

XTAL1 input current

Pin capacitance⁸⁾

(digital inputs/outputs)

I_ILCC –

C_IOCC –

±20

10

pF f = 1 MHz

T_A= 25 °C

1)

Keeping signal levels within the levels specified in this table, ensures operation without overload conditions.

For signal levels outside these specifications also refer to the specification of the overload current I_OV

.

2)

3)

Valid in bidirectional reset mode only.

This specification is not valid for outputs which are switched to open drain mode. In this case the respective

output will float and the voltage results from the external circuitry.

4)

5)

6)

7)

8)

These parameters describe the RSTIN pullup, which equals a resistance of ca. 50 to 250 kΩ.

The maximum current may be drawn while the respective signal line remains inactive.

The minimum current must be drawn in order to drive the respective signal line active.

This specification is valid during Reset and during Adapt-mode.

Not 100% tested, guaranteed by design and characterization.

Data Sheet

31

V2.0, 2001-01

C161K

C161O

DC Characteristics (Reduced Supply Voltage Range)

(Operating Conditions apply)¹⁾

Parameter

Symbol

Limit Values Unit Test Condition

min.

max.

Input low voltage (TTL,

all except XTAL1)

V_ILSR -0.5

0.8

V

–

Input low voltage XTAL1

V_IL2SR -0.5

V_IHSR 1.8

0.3 V_DD

V

–

Input high voltage (TTL,

all except RSTIN and XTAL1)

V_DD

0.5

+

Input high voltage RSTIN

(when operated as input)

V_IH1SR 0.6 V_DDV_DD

V

–

0.5

Input high voltage XTAL1

V_IH2SR 0.7 V_DDV_DD

0.5

Output low voltage

V_OLCC –

0.45

I

_OL= 1.6 mA

(PORT0, PORT1, Port 4, ALE,

RD, WR, BHE, RSTOUT,

RSTIN²⁾)

Output low voltage

(all other outputs)

Output high voltage³⁾

V

_OL1CC –

0.45

V

I

_OL= 1.0 mA

_OH= -0.5 mA

V_OHCC 0.9 V_DD

–

I

(PORT0, PORT1, Port 4, ALE,

RD, WR, BHE, RSTOUT)

Output high voltage³⁾

(all other outputs)

V

_OH1CC 0.9 V_DD

–

V

I_OH= -0.25 mA

Input leakage current (Port 5) I_OZ1CC –

±200

±500

-10

–

nA 0 V < V_IN< V_DD

nA 0.45 V < V_IN< V_DD

µA V_IN= V_IH1

Input leakage current (all other) I_OZ2CC –

5)

RSTIN inactive current⁴⁾

RSTIN active current⁴⁾

RD/WR inact. current⁷⁾

RD/WR active current⁷⁾

ALE inactive current⁷⁾

ALE active current⁷⁾

I_RSTH

–

6)

I_RSTL

-100

–

µA V_IN= V_IL

5)

I_RWH

-10

–

µA

V

_OUT= 2.4 V

6)

I_RWL

-500

–

_OUT= V_OLmax

_OUT= 2.4 V

5)

6)

I_ALEL

20

–

I_ALEH

500

–

5)

Port 6 inactive current⁷⁾

Port 6 active current⁷⁾

I_P6H

-10

–

_OUT= 2.4 V

6)

I_P6L

-500

_OUT= V_OL1max

Data Sheet

32

V2.0, 2001-01

C161K

C161O

DC Characteristics (Reduced Supply Voltage Range) (cont’d)

(Operating Conditions apply)¹⁾

Parameter

Symbol

Limit Values Unit Test Condition

min.

–

max.

-5

5)

PORT0 configuration current⁷⁾I_P0H

µA V_IN= V_IHmin

µA V_IN= V_ILmax

µA 0 V < V_IN< V_DD

6)

I_P0L

-100

–

XTAL1 input current

Pin capacitance⁸⁾

(digital inputs/outputs)

I_ILCC –

C_IOCC –

±20

10

pF f = 1 MHz

T_A= 25 °C

1)

Keeping signal levels within the levels specified in this table, ensures operation without overload conditions.

For signal levels outside these specifications also refer to the specification of the overload current I_OV

.

2)

3)

Valid in bidirectional reset mode only.

This specification is not valid for outputs which are switched to open drain mode. In this case the respective

output will float and the voltage results from the external circuitry.

4)

5)

6)

7)

8)

These parameters describe the RSTIN pullup, which equals a resistance of ca. 50 to 250 kΩ.

The maximum current may be drawn while the respective signal line remains inactive.

The minimum current must be drawn in order to drive the respective signal line active.

This specification is valid during Reset and during Adapt-mode.

Not 100% tested, guaranteed by design and characterization.

Data Sheet

33

V2.0, 2001-01

C161K

C161O

Power Consumption C161K/O (Standard Supply Voltage Range)

(Operating Conditions apply)

Parameter

Symbol

Limit Values

min. max.

Unit Test Condition

Power supply current (active) I_DD5

with all peripherals active

–

15 +

1.8 × f_CPU

mA RSTIN = V_IL

_CPUin [MHz]¹⁾

mA RSTIN = V_IH1

_CPUin [MHz]¹⁾

f

Idle mode supply current

with all peripherals active

I_IDX5

2 +

0.4 × f_CPU

f

2)

Power-down mode supply

current

I_PDO5

50

µA

V_DD= V_DDmax

1)

The supply current is a function of the operating frequency. This dependency is illustrated in Figure 7.

These parameters are tested at V_DDmaxand maximum CPU clock with all outputs disconnected and all inputs

at V_ILor V_IH.

2)

This parameter is tested including leakage currents. All inputs (including pins configured as inputs) at 0 V to

0.1 V or at V_DD- 0.1 V to V_DD, all outputs (including pins configured as outputs) disconnected.

Power Consumption C161K/O (Reduced Supply Voltage Range)

(Operating Conditions apply)

Parameter

Symbol

Limit Values

min. max.

Unit Test Condition

Power supply current (active)

with all peripherals active

I_DD3

–

3 +

1.3 × f_CPU

mA RSTIN = V_IL

f

_CPUin [MHz]¹⁾

Idle mode supply current

with all peripherals active

I_IDX3

I_PDO3

1 +

0.4 × f_CPU

mA RSTIN = V_IH1

_CPUin [MHz]¹⁾

f

2)

Power-down mode supply

current

30

µA

V_DD= V_DDmax

1)

The supply current is a function of the operating frequency. This dependency is illustrated in Figure 7.

These parameters are tested at V_DDmaxand maximum CPU clock with all outputs disconnected and all inputs

at V_ILor V_IH.

2)

This parameter is tested including leakage currents. All inputs (including pins configured as inputs) at 0 V to

0.1 V or at V_DD- 0.1 V to V_DD, all outputs (including pins configured as outputs) disconnected.

Data Sheet

34

V2.0, 2001-01

C161K

C161O

I

mA

I_DD5max

100

80

60

40

20

0

I_DD5typ

I_DD3max

I_DD3typ

I_IDX5max

I_IDX3max

I_IDX5typ

I_IDX3typ

f_CPU

0

10

20

30

40 MHz

MCD04860

Figure 7

Supply/Idle Current as a Function of Operating Frequency

Data Sheet

35

V2.0, 2001-01

C161K

C161O

AC Characteristics

Definition of Internal Timing

The internal operation of the C161K/O is controlled by the internal CPU clock f_CPU. Both

edges of the CPU clock can trigger internal (e.g. pipeline) or external (e.g. bus cycles)

operations.

The specification of the external timing (AC Characteristics) therefore depends on the

time between two consecutive edges of the CPU clock, called “TCL” (see Figure 8).

Direct Clock Drive

f_OSC

TCL

f_CPU

TCL

Prescaler Operation

f_OSC

TCL

f_CPU

MCT04826

TCL

Figure 8

Generation Mechanisms for the CPU Clock

The CPU clock signal f_CPUcan be generated from the oscillator clock signal f_OSCvia

different mechanisms. The duration of TCLs and their variation (and also the derived

external timing) depends on the used mechanism to generate f_CPU. This influence must

be regarded when calculating the timings for the C161K/O.

The used mechanism to generate the basic CPU clock is selected by bitfield CLKCFG

in register RP0H.7-5. Upon a long hardware reset register RP0H is loaded with the logic

levels present on the upper half of PORT0 (P0H), i.e. bitfield CLKCFG represents the

logic levels on pins P0.15-13 (P0H.7-5).

Table 9 associates the combinations of these three bits with the respective clock

generation mode.

Data Sheet

36

V2.0, 2001-01

C161K

C161O

Table 9

C161K/O Clock Generation Modes

CPU Frequency External Clock

CLKCFG

(P0H.7-5)

Notes

f

_CPU= f_OSC× F Input Range

0 X X

f

_OSC× 1

1 to 25 MHz

2 to 50 MHz

Direct drive¹⁾

1 X X

_OSC/ 2

CPU clock via prescaler

1)

The maximum frequency depends on the duty cycle of the external clock signal.

Prescaler Operation

When prescaler operation is configured (CLKCFG = 1XX_B) the CPU clock is derived

from the internal oscillator (input clock signal) by a 2:1 prescaler.

The frequency of f_CPUis half the frequency of f_OSCand the high and low time of f_CPU(i.e.

the duration of an individual TCL) is defined by the period of the input clock f_OSC

.

The timings listed in the AC Characteristics that refer to TCLs therefore can be

calculated using the period of f_OSCfor any TCL.

Direct Drive

When direct drive is configured (CLKCFG = 0XX_B) the CPU clock is directly driven from

the internal oscillator with the input clock signal.

The frequency of f_CPUdirectly follows the frequency of f_OSCso the high and low time of

f

_CPU(i.e. the duration of an individual TCL) is defined by the duty cycle of the input clock

f_OSC

.

The timings listed below that refer to TCLs therefore must be calculated using the

minimum TCL that is possible under the respective circumstances. This minimum value

can be calculated via the following formula:

TCL_min= 1/f_OSC× DC_min

(DC = duty cycle)

For two consecutive TCLs the deviation caused by the duty cycle of f_OSCis compensated

so the duration of 2TCL is always 1/f_OSC. The minimum value TCL_mintherefore has to

be used only once for timings that require an odd number of TCLs (1, 3, …). Timings that

require an even number of TCLs (2, 4, …) may use the formula 2TCL = 1/f_OSC

.

Data Sheet

37

V2.0, 2001-01

C161K

C161O

AC Characteristics

Table 10

External Clock Drive XTAL1 (Standard Supply Voltage Range)

(Operating Conditions apply)

Parameter

Symbol Direct Drive

1:1

max.

Prescaler

2:1

Unit

min.

Oscillator period t_OSCSR 40

High time¹⁾

Low time¹⁾

Rise time¹⁾

min.

20

6

max.

–

6

ns

t₁

t₂

t₃

t₄

SR 20²⁾

SR –

–

6

10

–

Fall time¹⁾

SR –

–

1)

The clock input signal must reach the defined levels V_IL2and V_IH2

.

2)

The minimum high and low time refers to a duty cycle of 50%. The maximum operating frequency (f_CPU) in

direct drive mode depends on the duty cycle of the clock input signal.

Table 11

External Clock Drive XTAL1 (Reduced Supply Voltage Range)

(Operating Conditions apply)

Parameter

Symbol

Direct Drive

1:1

Prescaler

2:1

Unit

min.

Oscillator period t_OSCSR 50

max.

–

min.

25

8

max.

–

6

ns

High time¹⁾

Low time¹⁾

Rise time¹⁾

t₁

t₂

t₃

t₄

SR 25²⁾

SR –

–

8

10

–

Fall time¹⁾

SR –

–

1)

The clock input signal must reach the defined levels V_IL2and V_IH2

.

2)

The minimum high and low time refers to a duty cycle of 50%. The maximum operating frequency (f_CPU) in

direct drive mode depends on the duty cycle of the clock input signal.

Data Sheet

38

V2.0, 2001-01

C161K

C161O

t₁

t₃

t₄

V_IH2

V_IL

0.5 V_DD

t₂

t_OSC

MCT02534

Figure 9

External Clock Drive XTAL1

Note: If the on-chip oscillator is used together with a crystal, the oscillator frequency is

limited to a range of 4 MHz to 40 MHz.

It is strongly recommended to measure the oscillation allowance (or margin) in the

final target system (layout) to determine the optimum parameters for the oscillator

operation. Please refer to the limits specified by the crystal supplier.

When driven by an external clock signal it will accept the specified frequency

range. Operation at lower input frequencies is possible but is guaranteed by

design only (not 100% tested).

Data Sheet

39

V2.0, 2001-01

C161K

C161O

Testing Waveforms

2.4 V

1.8 V

0.8 V

1.8 V

0.8 V

Test Points

0.45 V

’

AC inputs during testing are driven at 2.4 V for a logic 1’ and 0.45 V for a logic 0’.

Timing measurements are made at _IHmin for a logic 1’ and _ILmax for a logic 0’.

V

MCA04414

Figure 10

Input Output Waveforms

V_Load+ 0.1 V

V_OH- 0.1 V

Timing

Reference

Points

V_Load- 0.1 V

V_OL+ 0.1 V

For timing purposes a port pin is no longer floating when a 100 mV change from load voltage occurs,

but begins to float when a 100 mV change from the loaded V_OH

/

V_OLlevel occurs (I_OH

/

I

_OL= 20 mA).

MCA00763

Figure 11

Float Waveforms

Data Sheet

40

V2.0, 2001-01

C161K

C161O

Memory Cycle Variables

The timing tables below use three variables which are derived from the BUSCONx

registers and represent the special characteristics of the programmed memory cycle.

The following table describes, how these variables are to be computed.

Table 12

Memory Cycle Variables

Symbol Values

Description

ALE Extension

t_A

TCL × <ALECTL>

Memory Cycle Time Waitstates t_C

Memory Tristate Time

2TCL × (15 - <MCTC>)

2TCL × (1 - <MTTC>)

t_F

Note: Please respect the maximum operating frequency of the respective derivative.

AC Characteristics

Multiplexed Bus (Standard Supply Voltage Range)

(Operating Conditions apply)

ALE cycle time = 6 TCL + 2t_A+ t_C+ t_F(120 ns at 25 MHz CPU clock without waitstates)

Parameter

Symbol Max. CPU Clock Variable CPU Clock Unit

= 25 MHz 1 / 2TCL = 1 to 25 MHz

min.

max.

min.

max.

ALE high time

t₅CC 10 + t_A

t₆CC 4 + t_A

t₇CC 10 + t_A

t₈CC 10 + t_A

t₉CC -10 + t_A

t₁₀CC –

–

TCL - 10

+ t_A

–

ns

Address setup to ALE

Address hold after ALE

–

TCL - 16

+ t_A

–

TCL - 10

+ t_A

–

ALE falling edge to RD,

WR (with RW-delay)

–

TCL - 10

+ t_A

–

ALE falling edge to RD,

WR (no RW-delay)

–

-10 + t_A

–

Address float after RD,

WR (with RW-delay)

6

–

6

Address float after RD,

WR (no RW-delay)

t₁₁CC –

26

–

TCL + 6

RD, WR low time

(with RW-delay)

t₁₂CC 30 + t_C

2TCL - 10 –

+ t_C

Data Sheet

41

V2.0, 2001-01

C161K

C161O

Multiplexed Bus (Standard Supply Voltage Range) (cont’d)

(Operating Conditions apply)

ALE cycle time = 6 TCL + 2t_A+ t_C+ t_F(120 ns at 25 MHz CPU clock without waitstates)

Parameter

Symbol Max. CPU Clock Variable CPU Clock Unit

= 25 MHz 1 / 2TCL = 1 to 25 MHz

min. max.

min.

max.

RD, WR low time

(no RW-delay)

t₁₃CC 50 + t_C

–

3TCL - 10 –

+ t_C

ns

RD to valid data in

(with RW-delay)

t₁₄SR –

20 + t_C

40 + t_C

–

0

–

2TCL - 20 ns

+ t_C

RD to valid data in

(no RW-delay)

t₁₅SR –

3TCL - 20 ns

+ t_C

ALE low to valid data in

t₁₆SR –

40 + t_A

+ t_C

3TCL - 20 ns

+ t_A+ t_C

Address to valid data in

t₁₇SR –

50 + 2t_A

+ t_C

4TCL - 30 ns

+ 2t_A+ t_C

Data hold after RD

rising edge

t₁₈SR 0

–

ns

Data float after RD

Data valid to WR

Data hold after WR

t₁₉SR –

26 + t_F

2TCL - 14 ns

+ t_F

t₂₂CC 20 + t_C

t₂₃CC 26 + t_F

–

2TCL - 20 –

+ t_C

ns

–

2TCL - 14 –

+ t_F

ALE rising edge after RD, t₂₅CC 26 + t_F

WR

–

2TCL - 14 –

+ t_F

Address hold after RD,

WR

ALE falling edge to CS¹⁾t₃₈CC -4 - t_A

CS low to Valid Data In¹⁾t₃₉SR –

t₂₇CC 26 + t_F

–

2TCL - 14 –

+ t_F

10 - t_A

- 4 - t_A

10 - t_A

40 + t_C

+ 2t_A

–

3TCL - 20 ns

+ t_C+ 2t_A

CS hold after RD, WR¹⁾t₄₀CC 46 + t_F

–

3TCL - 14 –

+ t_F

ns

ALE fall. edge to RdCS, t₄₂CC 16 + t_A

WrCS (with RW delay)

TCL - 4

–

+ t_A

ALE fall. edge to RdCS, t₄₃CC -4 + t_A

-4

–

WrCS (no RW delay)

+ t_A

Data Sheet

42

V2.0, 2001-01

C161K

C161O

Multiplexed Bus (Standard Supply Voltage Range) (cont’d)

(Operating Conditions apply)

ALE cycle time = 6 TCL + 2t_A+ t_C+ t_F(120 ns at 25 MHz CPU clock without waitstates)

Parameter

Symbol Max. CPU Clock Variable CPU Clock Unit

= 25 MHz 1 / 2TCL = 1 to 25 MHz

min.

max.

min.

max.

Address float after RdCS, t₄₄CC –

WrCS (with RW delay)

0

–

0

ns

Address float after RdCS, t₄₅CC –

WrCS (no RW delay)

20

–

TCL

RdCS to Valid Data In

(with RW delay)

t₄₆SR –

t₄₇SR –

16 + t_C

2TCL - 24 ns

+ t_C

RdCS to Valid Data In

(no RW delay)

36 + t_C

3TCL - 24 ns

+ t_C

RdCS, WrCS Low Time t₄₈CC 30 + t_C

(with RW delay)

–

2TCL - 10 –

+ t_C

ns

RdCS, WrCS Low Time t₄₉CC 50 + t_C

(no RW delay)

3TCL - 10 –

+ t_C

Data valid to WrCS

t₅₀CC 26 + t_C

2TCL - 14 –

+ t_C

Data hold after RdCS

Data float after RdCS

t₅₁SR 0

t₅₂SR –

–

0

–

20 + t_F

–

2TCL - 20 ns

+ t_F

Address hold after

RdCS, WrCS

t₅₄CC 20 + t_F

t₅₆CC 20 + t_F

–

2TCL - 20 –

+ t_F

ns

Data hold after WrCS

2TCL - 20 –

+ t_F

1)

These parameters refer to the latched chip select signals (CSxL). The early chip select signals (CSxE) are

specified together with the address and signal BHE (see figures below).

Data Sheet

43

V2.0, 2001-01

C161K

C161O

AC Characteristics

Multiplexed Bus (Reduced Supply Voltage Range)

(Operating Conditions apply)

ALE cycle time = 6 TCL + 2t_A+ t_C+ t_F(150 ns at 20 MHz CPU clock without waitstates)

Parameter

Symbol Max. CPU Clock Variable CPU Clock Unit

= 20 MHz 1 / 2TCL = 1 to 20 MHz

min.

max.

min.

max.

ALE high time

t₅CC 11 + t_A

t₆CC 5 + t_A

t₇CC 15 + t_A

t₈CC 15 + t_A

t₉CC -10 + t_A

t₁₀CC –

–

TCL - 14

+ t_A

–

ns

Address setup to ALE

Address hold after ALE

–

TCL - 20

+ t_A

–

TCL - 10

+ t_A

–

ALE falling edge to RD,

WR (with RW-delay)

–

TCL - 10

+ t_A

–

ALE falling edge to RD,

WR (no RW-delay)

–

-10 + t_A

–

Address float after RD,

WR (with RW-delay)

6

–

6

Address float after RD,

WR (no RW-delay)

t₁₁CC –

31

TCL + 6

RD, WR low time

(with RW-delay)

t₁₂CC 34 + t_C

t₁₃CC 59 + t_C

t₁₄SR –

–

2TCL - 16 –

+ t_C

RD, WR low time

(no RW-delay)

–

3TCL - 16 –

+t_C

RD to valid data in

(with RW-delay)

22 + t_C

47 + t_C

–

0

2TCL - 28 ns

+ t_C

RD to valid data in

(no RW-delay)

t₁₅SR –

3TCL - 28 ns

+ t_C

ALE low to valid data in

t₁₆SR –

45 + t_A

+ t_C

3TCL - 30 ns

+ t_A+ t_C

Address to valid data in

t₁₇SR –

57 + 2t_A

+ t_C

4TCL - 43 ns

+ 2t_A+ t_C

Data hold after RD

rising edge

t₁₈SR 0

–

ns

Data Sheet

44

V2.0, 2001-01

C161K

C161O

Multiplexed Bus (Reduced Supply Voltage Range) (cont’d)

(Operating Conditions apply)

ALE cycle time = 6 TCL + 2t_A+ t_C+ t_F(150 ns at 20 MHz CPU clock without waitstates)

Parameter

Symbol Max. CPU Clock Variable CPU Clock Unit

= 20 MHz 1 / 2TCL = 1 to 20 MHz

min.

max.

min.

max.

Data float after RD

Data valid to WR

Data hold after WR

t₁₉SR –

36 + t_F

–

2TCL - 14 ns

+ t_F

t₂₂CC 24 + t_C

t₂₃CC 36 + t_F

–

2TCL - 26 –

+ t_C

ns

–

2TCL - 14 –

+ t_F

ALE rising edge after RD, t₂₅CC 36 + t_F

WR

–

2TCL - 14 –

+ t_F

Address hold after RD,

WR

ALE falling edge to CS¹⁾t₃₈CC -8 - t_A

CS low to Valid Data In¹⁾t₃₉SR –

t₂₇CC 36 + t_F

–

2TCL - 14 –

+ t_F

10 - t_A

-8 - t_A

10 - t_A

47+ t_C

+ 2t_A

–

3TCL - 28 ns

+ t_C+ 2t_A

CS hold after RD, WR¹⁾t₄₀CC 57 + t_F

–

3TCL - 18 –

+ t_F

ns

ALE fall. edge to RdCS, t₄₂CC 19 + t_A

WrCS (with RW delay)

–

TCL - 6

–

+ t_A

ALE fall. edge to RdCS, t₄₃CC -6 + t_A

WrCS (no RW delay)

–

-6

–

+ t_A

Address float after RdCS, t₄₄CC –

WrCS (with RW delay)

0

–

0

Address float after RdCS, t₄₅CC –

WrCS (no RW delay)

25

TCL

RdCS to Valid Data In

(with RW delay)

t₄₆SR –

t₄₇SR –

20 + t_C

2TCL - 30 ns

+ t_C

RdCS to Valid Data In

(no RW delay)

45 + t_C

3TCL - 30 ns

+ t_C

RdCS, WrCS Low Time t₄₈CC 38 + t_C

(with RW delay)

–

2TCL - 12 –

+ t_C

ns

RdCS, WrCS Low Time t₄₉CC 63 + t_C

(no RW delay)

3TCL - 12 –

+ t_C

Data Sheet

45

V2.0, 2001-01

C161K

C161O

Multiplexed Bus (Reduced Supply Voltage Range) (cont’d)

(Operating Conditions apply)

ALE cycle time = 6 TCL + 2t_A+ t_C+ t_F(150 ns at 20 MHz CPU clock without waitstates)

Parameter

Symbol Max. CPU Clock Variable CPU Clock Unit

= 20 MHz 1 / 2TCL = 1 to 20 MHz

min. max.

min.

max.

Data valid to WrCS

t₅₀CC 28 + t_C

–

2TCL - 22 –

+ t_C

ns

Data hold after RdCS

Data float after RdCS

t₅₁SR 0

t₅₂SR –

–

0

–

ns

30 + t_F

–

2TCL - 20 ns

+ t_F

Address hold after

RdCS, WrCS

t₅₄CC 30 + t_F

t₅₆CC 30 + t_F

–

2TCL - 20 –

+ t_F

ns

Data hold after WrCS

2TCL - 20 –

+ t_F

1)

These parameters refer to the latched chip select signals (CSxL). The early chip select signals (CSxE) are

specified together with the address and signal BHE (see figures below).

Data Sheet

46

V2.0, 2001-01

C161K

C161O

t₅

t₁₆

t₂₅

ALE

t₃₈

t₃₉

t₄₀

CSxL

t₁₇

t₂₇

A21-A16

Address

(A15-A8)

BHE, CSxE

t₅₄

t₁₉

t₆

t₇

t₁₈

Read Cycle

Address

Data IN

BUS

t₈

t₁₀

t₁₄

t₁₂

`

RD

t₄₂

t₄₄

t₅₁

t₅₂

t₄₆

t₄₈

RdCSx

t₂₃

Write Cycle

Address

Data OUT

BUS

t₈

t₁₀

t₂₂

t₅₆

t₁₂

WR, WRL,

WRH

t₄₂

t₄₄

t₅₀

t₄₈

WrCSx

MCT04861

Figure 12

External Memory Cycle:

Multiplexed Bus, With Read/Write Delay, Normal ALE

Data Sheet

47

V2.0, 2001-01

C161K

C161O

t₅

t₁₆

t₂₅

ALE

t₃₈

t₃₉

t₄₀

CSxL

t₁₇

t₂₇

A21-A16

Address

(A15-A8)

BHE, CSxE

t₆

t₅₄

t₁₉

t₇

t₁₈

Read Cycle

Address

Data IN

BUS

t₈

t₁₀

t₁₄

t₁₂

RD

t₄₂

t₄

t₅₁

t₅₂

t₄₆

t₄₈

RdCSx

t₂₃

Write Cycle

Address

Data OUT

BUS

t₈

t₁₀

t₂₂

t₅₆

t₁₂

WR, WRL,

WRH

t₄₂

t₄₄

t₅₀

t₄₈

WrCSx

MCT04862

Figure 13

External Memory Cycle:

Multiplexed Bus, With Read/Write Delay, Extended ALE

Data Sheet

48

V2.0, 2001-01

C161K

C161O

t₅

t₁₆

t₂₅

ALE

t₃₈

t₃₉

t₄₀

CSxL

t₁₇

t₂₇

A21-A16

Address

(A15-A8)

BHE, CSxE

t₅₄

t₁₉

t₆

t₇

t₁₈

Read Cycle

Address

Data IN

BUS

t₉

t₁₁

t₁₅

t₁₃

RD

t₄₃

t₄₅

t₅₁

t₅₂

t₄₇

t₄₉

RdCSx

t₂₃

Write Cycle

Address

Data OUT

BUS

t₉

t₁₁

t₂₂

t₅₆

t₁₃

WR, WRL,

WRH

t₄₃

t₄₅

t₅₀

t₄₉

WrCSx

MCT04863

Figure 14

External Memory Cycle:

Multiplexed Bus, No Read/Write Delay, Normal ALE

Data Sheet

49

V2.0, 2001-01

C161K

C161O

t₅

t₁₆

t₂₅

ALE

t₃₈

t₃₉

t₄₀

CSxL

t₁₇

t₂₇

A21-A16

Address

(A15-A8)

BHE, CSxE

t₆

t₅₄

t₁₉

t₇

t₁₈

Read Cycle

Address

Data IN

BUS

t₉

t₁₁

t₁₅

t₁₃

RD

t₄₃

t₄₅

t₅₁

t₄₇

t₄₉

t₅₂

RdCSx

t₂₃

Write Cycle

Address

Data OUT

BUS

t₉

t₁₁

t₂₂

t₅₆

t₁₃

WR, WRL,

WRH

t₄₃

t₄₅

t₅₀

t₄₉

WrCSx

MCT04864

Figure 15

External Memory Cycle:

Multiplexed Bus, No Read/Write Delay, Extended ALE

Data Sheet

50

V2.0, 2001-01

C161K

C161O

AC Characteristics

Demultiplexed Bus (Standard Supply Voltage Range)

(Operating Conditions apply)

ALE cycle time = 4 TCL + 2t_A+ t_C+ t_F(80 ns at 25 MHz CPU clock without waitstates)

Parameter

Symbol Max. CPU Clock

= 25 MHz

Variable CPU Clock Unit

1 / 2TCL = 1 to 25 MHz

min.

max.

min.

max.

ALE high time

t₅CC 10 + t_A

–

TCL - 10

+ t_A

–

ns

Address setup to ALE

t₆CC 4 + t_A

–

TCL - 16

+ t_A

–

ALE falling edge to RD, t₈CC 10 + t_A

WR (with RW-delay)

–

TCL - 10

+ t_A

ALE falling edge to RD, t₉CC -10 + t_A

WR (no RW-delay)

–

-10

+ t_A

RD, WR low time

(with RW-delay)

t₁₂CC 30 + t_C

t₁₃CC 50 + t_C

t₁₄SR –

–

2TCL - 10 –

+ t_C

RD, WR low time

(no RW-delay)

–

3TCL - 10 –

+ t_C

RD to valid data in

(with RW-delay)

20 + t_C

40 + t_C

–

0

–

2TCL - 20 ns

+ t_C

RD to valid data in

(no RW-delay)

t₁₅SR –

3TCL - 20 ns

+ t_C

ALE low to valid data in t₁₆SR –

Address to valid data in t₁₇SR –

40 +

t_A+ t_C

3TCL - 20 ns

+ t_A+ t_C

50 +

2t_A+ t_C

4TCL - 30 ns

+ 2t_A+ t_C

Data hold after RD

rising edge

t₁₈SR 0

–

ns

Data float after RD rising t₂₀SR –

26 +

2t_A+ t_F

2TCL - 14 ns

+ 22t_A

+ t_F

1)

edge (with RW-delay¹⁾)

1)

Data float after RD rising t₂₁SR –

10 +

2t_A+ t_F

–

TCL - 10

ns

1)

edge (no RW-delay¹⁾)

+ 22t_A

1)

+ t_F

Data Sheet

51

V2.0, 2001-01

C161K

C161O

Demultiplexed Bus (Standard Supply Voltage Range) (cont’d)

(Operating Conditions apply)

ALE cycle time = 4 TCL + 2t_A+ t_C+ t_F(80 ns at 25 MHz CPU clock without waitstates)

Parameter

Symbol Max. CPU Clock

= 25 MHz

Variable CPU Clock Unit

1 / 2TCL = 1 to 25 MHz

min.

max.

min.

max.

Data valid to WR

t₂₂CC 20 + t_C

–

2TCL - 20 –

+ t_C

ns

Data hold after WR

t₂₄CC 10 + t_F

t₂₆CC -10 + t_F

–

TCL - 10

–

+ t_F

ALE rising edge after

RD, WR

-10 + t_F

–

Address hold after WR²⁾t₂₈CC 0 + t_F

ALE falling edge to CS³⁾t₃₈CC -4 - t_A

CS low to Valid Data In³⁾t₃₉SR –

–

0 + t_F

-4 - t_A

–

ns

10 - t_A

40 +

3TCL - 20 ns

t_C+ 2t_A

+ t_C+ 2t_A

CS hold after RD, WR³⁾t₄₁CC 6 + t_F

–

TCL - 14

–

ns

+ t_F

ALE falling edge to

RdCS, WrCS (with RW-

delay)

t₄₂CC 16 + t_A

t₄₃CC -4 + t_A

–

TCL - 4

+ t_A

–

ALE falling edge to

RdCS, WrCS (no RW-

delay)

–

-4

+ t_A

–

ns

RdCS to Valid Data In

(with RW-delay)

t₄₆SR –

t₄₇SR –

16 + t_C

–

2TCL - 24 ns

+ t_C

RdCS to Valid Data In

(no RW-delay)

36 + t_C

3TCL - 24 ns

+ t_C

RdCS, WrCS Low Time t₄₈CC 30 + t_C

(with RW-delay)

–

2TCL - 10 –

+ t_C

ns

RdCS, WrCS Low Time t₄₉CC 50 + t_C

(no RW-delay)

3TCL - 10 –

+ t_C

Data valid to WrCS

t₅₀CC 26 + t_C

t₅₁SR 0

2TCL - 14 –

+ t_C

Data hold after RdCS

0

–

Data Sheet

52

V2.0, 2001-01

C161K

C161O

Demultiplexed Bus (Standard Supply Voltage Range) (cont’d)

(Operating Conditions apply)

ALE cycle time = 4 TCL + 2t_A+ t_C+ t_F(80 ns at 25 MHz CPU clock without waitstates)

Parameter

Symbol Max. CPU Clock

= 25 MHz

Variable CPU Clock Unit

1 / 2TCL = 1 to 25 MHz

min.

t₅₃SR –

max.

min.

max.

Data float after RdCS

(with RW-delay)¹⁾

20 + t_F

–

2TCL - 20 ns

+ 2t_A+ t_F

1)

Data float after RdCS

(no RW-delay)¹⁾

t₆₈SR –

0 + t_F

–

TCL - 20

ns

+ 2t_A+ t_F

1)

Address hold after

RdCS, WrCS

t₅₅CC -6 + t_F

t₅₇CC 6 + t_F

–

-6 + t_F

–

ns

Data hold after WrCS

TCL - 14

+ t_F

1)

RW-delay and t_Arefer to the next following bus cycle (including an access to an on-chip X-Peripheral).

2)

Read data are latched with the same clock edge that triggers the address change and the rising RD edge.

Therefore address changes before the end of RD have no impact on read cycles.

3)

These parameters refer to the latched chip select signals (CSxL). The early chip select signals (CSxE) are

specified together with the address and signal BHE (see figures below).

Data Sheet

53

V2.0, 2001-01

C161K

C161O

AC Characteristics

Demultiplexed Bus (Reduced Supply Voltage Range)

(Operating Conditions apply)

ALE cycle time = 4 TCL + 2t_A+ t_C+ t_F(100 ns at 20 MHz CPU clock without waitstates)

Parameter

Symbol Max. CPU Clock

= 20 MHz

Variable CPU Clock Unit

1 / 2TCL = 1 to 20 MHz

min.

max.

min.

max.

ALE high time

t₅CC 11 + t_A

–

TCL - 14

+ t_A

–

ns

Address setup to ALE

t₆CC 5 + t_A

–

TCL - 20

+ t_A

–

ALE falling edge to RD, t₈CC 15 + t_A

WR (with RW-delay)

–

TCL - 10

+ t_A

ALE falling edge to RD, t₉CC -10 + t_A

WR (no RW-delay)

–

-10

+ t_A

RD, WR low time

(with RW-delay)

t₁₂CC 34 + t_C

t₁₃CC 59 + t_C

t₁₄SR –

–

2TCL - 16 –

+ t_C

RD, WR low time

(no RW-delay)

–

3TCL - 16 –

+ t_C

RD to valid data in

(with RW-delay)

22 + t_C

47 + t_C

–

0

–

2TCL - 28 ns

+ t_C

RD to valid data in

(no RW-delay)

t₁₅SR –

3TCL - 28 ns

+ t_C

ALE low to valid data in t₁₆SR –

Address to valid data in t₁₇SR –

45 +

t_A+ t_C

3TCL - 30 ns

+ t_A+ t_C

57 +

2t_A+ t_C

4TCL - 43 ns

+ 2t_A+ t_C

Data hold after RD

rising edge

t₁₈SR 0

–

ns

Data float after RD rising t₂₀SR –

36 +

2t_A+ t_F

2TCL - 14 ns

+ 22t_A

+ t_F

1)

edge (with RW-delay¹⁾)

1)

Data float after RD rising t₂₁SR –

15 +

2t_A+ t_F

–

TCL - 10

ns

1)

edge (no RW-delay¹⁾)

+ 22t_A

1)

+ t_F

Data Sheet

54

V2.0, 2001-01

C161K

C161O

Demultiplexed Bus (Reduced Supply Voltage Range) (cont’d)

(Operating Conditions apply)

ALE cycle time = 4 TCL + 2t_A+ t_C+ t_F(100 ns at 20 MHz CPU clock without waitstates)

Parameter

Symbol Max. CPU Clock

= 20 MHz

Variable CPU Clock Unit

1 / 2TCL = 1 to 20 MHz

min.

max.

min.

max.

Data valid to WR

t₂₂CC 24 + t_C

–

2TCL - 26 –

+ t_C

ns

Data hold after WR

t₂₄CC 15 + t_F

t₂₆CC -12 + t_F

–

TCL - 10

–

+ t_F

ALE rising edge after

RD, WR

-12 + t_F

–

Address hold after WR²⁾t₂₈CC 0 + t_F

ALE falling edge to CS³⁾t₃₈CC -8 - t_A

CS low to Valid Data In³⁾t₃₉SR –

–

0 + t_F

-8 - t_A

–

ns

10 - t_A

47 +

3TCL - 28 ns

t_C+ 2t_A

+ t_C+ 2t_A

CS hold after RD, WR³⁾t₄₁CC 9 + t_F

–

TCL - 16

–

ns

+ t_F

ALE falling edge to

RdCS, WrCS (with RW-

delay)

t₄₂CC 19 + t_A

t₄₃CC -6 + t_A

–

TCL - 6

+ t_A

–

ALE falling edge to

RdCS, WrCS (no RW-

delay)

–

-6

+ t_A

–

ns

RdCS to Valid Data In

(with RW-delay)

t₄₆SR –

t₄₇SR –

20 + t_C

–

2TCL - 30 ns

+ t_C

RdCS to Valid Data In

(no RW-delay)

45 + t_C

3TCL - 30 ns

+ t_C

RdCS, WrCS Low Time t₄₈CC 38 + t_C

(with RW-delay)

–

2TCL - 12 –

+ t_C

ns

RdCS, WrCS Low Time t₄₉CC 63 + t_C

(no RW-delay)

3TCL - 12 –

+ t_C

Data valid to WrCS

t₅₀CC 28 + t_C

t₅₁SR 0

2TCL - 22 –

+ t_C

Data hold after RdCS

0

–

Data Sheet

55

V2.0, 2001-01

C161K

C161O

Demultiplexed Bus (Reduced Supply Voltage Range) (cont’d)

(Operating Conditions apply)

ALE cycle time = 4 TCL + 2t_A+ t_C+ t_F(100 ns at 20 MHz CPU clock without waitstates)

Parameter

Symbol Max. CPU Clock

= 20 MHz

Variable CPU Clock Unit

1 / 2TCL = 1 to 20 MHz

min.

t₅₃SR –

max.

min.

max.

Data float after RdCS

(with RW-delay)¹⁾

30 + t_F

–

2TCL - 20 ns

+ 2t_A+ t_F

1)

Data float after RdCS

(no RW-delay)¹⁾

t₆₈SR –

5 + t_F

–

TCL - 20

ns

+ 2t_A+ t_F

1)

Address hold after

RdCS, WrCS

t₅₅CC -16 + t_F

t₅₇CC 9 + t_F

–

-16 + t_F

–

ns

Data hold after WrCS

TCL - 16

+ t_F

1)

RW-delay and t refer to the next following bus cycle (including an access to an on-chip X-Peripheral).

A

2)

Read data are latched with the same clock edge that triggers the address change and the rising RD edge.

Therefore address changes before the end of RD have no impact on read cycles.

3)

These parameters refer to the latched chip select signals (CSxL). The early chip select signals (CSxE) are

specified together with the address and signal BHE (see figures below).

Data Sheet

56

V2.0, 2001-01

C161K

C161O

t₅

t₁₆

t₂₆

ALE

t₃₈

t₃₉

t₄₁

CSxL

t₂₈

t₁₇

A21-A16

A15-A0

Address

BHE, CSxE

t₅₅

t₆

t₂₀

Read Cycle

t₁₈

BUS

Data IN

(D15-D8)

D7-D0

t₈

t₁₄

t₁₂

RD

t₄₂

t₅₁

t₄₆

t₄₈

t₅₃

RdCSx

Write Cycle

t₂₄

BUS

(D15-D8)

D7-D0

Data OUT

t₈

t₂₂

t₅₇

t₁₂

WR, WRL,

WRH

t₄₂

t₅₀

t₄₈

WrCSx

MCT04865

Figure 16

External Memory Cycle:

Demultiplexed Bus, With Read/Write Delay, Normal ALE

Data Sheet

57

V2.0, 2001-01

C161K

C161O

t₅

t₁₆

t₂₆

ALE

t₃₈

t₃₉

t₄₁

CSxL

t₁₇

t₂₈

A21-A16

A15-A0

Address

BHE, CSxE

t₆

t₅₅

t₂₀

Read Cycle

t₁₈

BUS

Data IN

(D15-D8)

D7-D0

t₈

t₁₄

t₁₂

RD

t₄₂

t₅₁

t₄₆

t₄₈

t₅₃

RdCSx

Write Cycle

t₂₄

BUS

Data OUT

(D15-D8)

D7-D0

t₈

t₂₂

t₅₇

t₁₂

WR, WRL,

WRH

t₄₂

t₅₀

t₄₈

WrCSx

MCT04866

Figure 17

External Memory Cycle:

Demultiplexed Bus, With Read/Write Delay, Extended ALE

Data Sheet

58

V2.0, 2001-01

C161K

C161O

t₅

t₁₆

t₂₆

ALE

t₃₈

t₃₉

t₄₁

CSxL

t₂₈

t₁₇

A21-A16

A15-A0

Address

BHE, CSxE

t₅₅

t₆

t₂₁

Read Cycle

t₁₈

BUS

Data IN

(D15-D8)

D7-D0

t₉

t₁₅

t₁₃

RD

t₄₃

t₅₁

t₄₇

t₄₉

t₆₈

RdCSx

Write Cycle

t₂₄

BUS

(D15-D8)

D7-D0

Data OUT

t₂₂

t₅₇

t₉

t₁₃

WR, WRL,

WRH

t₄₃

t₅₀

t₄₉

WrCSx

MCT04867

Figure 18

External Memory Cycle:

Demultiplexed Bus, No Read/Write Delay, Normal ALE

Data Sheet

59

V2.0, 2001-01

C161K

C161O

t₅

t₁₆

t₂₆

ALE

t₃₈

t₃₉

t₄₁

CSxL

t₁₇

t₂₈

A21-A16

A15-A0

Address

BHE, CSxE

t₆

t₅₅

t₂₁

Read Cycle

t₁₈

BUS

Data IN

(D15-D8)

D7-D0

t₉

t₁₅

t₁₃

RD

t₄₃

t₅₁

t₄₇

t₄₉

t₆₈

RdCSx

Write Cycle

t₂₄

BUS

Data OUT

(D15-D8)

D7-D0

t₉

t₂₂

t₅₇

t₁₃

WR, WRL,

WRH

t₄₃

t₅₀

t₄₉

WrCSx

MCT04868

Figure 19

External Memory Cycle:

Demultiplexed Bus, No Read/Write Delay, Extended ALE

Data Sheet

60

V2.0, 2001-01

C161K

C161O

Package Outlines

P-MQFP-80-1 (SMD)

(Plastic Metric Quad Flat Package)

H

0.65

±0.08

0.88

80x

0.3

C

0.1

12.35

17.2

14 ¹⁾

M

0.12

A-B D C

0.2 A-B D 80x

0.2 A-B D 4x

H

D

B

A

80

1

Index Marking

0.6x45˚

1) Does not include plastic or metal protrusions of 0.25 max per side

Sorts of Packing

Package outlines for tubes, trays etc. are contained in our

Data Book “Package Information”.

Dimensions in mm

SMD = Surface Mounted Device

Data Sheet

61

V2.0, 2001-01

Infineon goes for Business Excellence

“Business excellence means intelligent approaches and clearly

defined processes, which are both constantly under review and

ultimately lead to good operating results.

Better operating results and business excellence mean less

idleness and wastefulness for all of us, more professional

success, more accurate information, a better overview and,

thereby, less frustration and more satisfaction.”

Dr. Ulrich Schumacher

h t t p : / / w w w . i n f i n e o n . c o m

Published by Infineon Technologies AG


型号：	C161KLMHABXUMA1
厂家：	Infineon
描述：	Microcontroller, 16-Bit, 20MHz, CMOS, PQFP80, 0.65 MM PITCH, PLASTIC, MQFP-80 微控制器
文件：	总68页 (文件大小：1080K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

C161KLMHABXUMA1 [INFINEON]

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