CHL8325A-00CRT [INFINEON]
Digital Multi-Phase Buck Controller Dual OCP support for I-spike enhanced AMD CPUs; 因为我秒杀的数字多相降压控制器双OCP支持增强的AMD处理器
| 型号： | CHL8325A-00CRT |
| 厂家： | 
Infineon |
| 描述： | Digital Multi-Phase Buck Controller Dual OCP support for I-spike enhanced AMD CPUs |
| 文件： | 总3页 (文件大小：390K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IR3541
Digital Multi-Phase Buck Controller
FEATURES
DESCRIPTION
5-phase dual output PWM Controller
The IR3541 and CHL8325A/B are dual-loop digital
multi-phase buck controllers that drive up to 5 phases.
The IR3541 and CHL8325A/B are fully Intel® VR12 and AMD®
SVI compliant on both loops and provides a Vtt tracking
function for DDR memory.
Phases are flexibly assigned between Loops 1 & 2
Intel® VR12, AMD® 400kHz & 3.4MHz SVI and
Memory modes
Dual OCP support for I-spike enhanced AMD CPUs
SMB_Alert Pin for Servers
NVM storage saves pins and enables a small package size.
PMBus Address pin or Variable Gate Drive
(IR3541/CHL8325A)
2nd Temperature Sense for VR12 Desktop
(CHL8325B)
The IR3541 and CHL8325A/B include the IR Efficiency
Shaping Technology to deliver exceptional efficiency at
minimum cost across the entire load range. IR Variable Gate
Drive optimizes the MOSFET gate drive voltage as a function
of real-time load current. IR Dynamic Phase Control
adds/drops active phases based upon load current.
The IR3541 and CHL8325A/B can be configured to enter
1-phase operation and active diode emulation mode
automatically or by command.
Overclocking & Gaming Mode with Vmax setting
Switching frequency from 200kHz to 1.2MHz per
phase
IR Efficiency Shaping Features including Variable
Gate Drive (IR3541/CHL8325A only) and Dynamic
Phase Control
IR’s unique Adaptive Transient Algorithm (ATA), based on
proprietary non-linear digital PWM algorithms, minimizes
output bulk capacitors.
Programmable 1-phase or 2-phase for Light Loads
and Active Diode Emulation for Very Light Loads
IR Adaptive Transient Algorithm (ATA) on both
loops minimizes output bulk capacitors and
system cost
The I2C/PMBus interface can communicate with up to 16
IR3541 and CHL8325A/B based VR loops. Device
configuration and fault parameters are easily defined using
the IR Intuitive Power Designer (DPDC) GUI and stored in
on-chip NVM.
Auto-Phase Detection with auto-compensation
Per-Loop Fault Protection: OVP, UVP, OCP,
OTP, CFP
The IR3541 and CHL8325A/B also include numerous
features like register diagnostics for fast design cycles and
platform differentiation, truly simplifying VRD design and
enabling fastest time-to-market with its “set-and-forget”
methodology.
I2C/SMBus/PMBus system interface for telemetry
of Temperature, Voltage, Current & Power for
both loops
Non-Volatile Memory (NVM) for custom
configuration
Compatible with IR ATL and 3.3V Tri-state Drivers
PIN DIAGRAM
+3.3V supply voltage; -20ºC to 85ºC ambient
operation
Pb-Free, RoHS, 6x6 40-pin QFN, MSL2 package
APPLICATIONS
Intel ® VR12 & AMD® SVI based systems
DDR Memory with Vtt tracking
Overclocked & Gaming platforms
Figure 1: IR3541 Package Top View
1
June 21, 2013 | FINAL | V1.09
IR3541
Digital Multi-Phase Buck Controller
ORDERING INFORMATION
Packing
Package
Part Number
IR3541MTRPBF
Programming
Qty
IR3541M
TR=3000
TY=4900
QFN
Default
IR3541MTYPBF
P/PBF – Lead Free
Customer
Configuration
QFN
TR=3000
IR3541MxxyyTRP1
TR – Tape & Reel / TY - Tray
yy – Configuration File ID
xx – Customer ID
Notes:
1. Customer Specific Configuration File, where
xx = Customer ID and yy = Configuration File
(Codes assigned by IR Marketing).
Package Type (QFN)
Package
QFN
Packing Qty
T=3000
TY=4900
Part Number
CHL8325A-00CRT
CHL8325A-00CRTY
CHL8325A-xxCRT1
CHL8325 ―
QFN
T=3000
T=3000
TY=4900
T=3000
CHL8325B-00CRT
CHL8325B-00CRTY
QFN
T – Tape & Reel / TY - Tray
R – Package Type (QFN)
QFN
CHL8325B-xxCRT1
Notes:
C – Operating Temperature,
1. “xx” indicates a customer specific configuration
Commercial
file.
xx – Configuration File
Part –
A: CHL8325A
B: CHL8328B
40
39
38
37
36
35
34
33
32
31
1
2
30
29
28
27
26
25
24
23
22
21
RCSP_L2
RCSM_L2
VCC
RCSP
RCSM
VCC
3
4
VSEN_L2
VRTN_L2
PWM5
VSEN
VRTN
RRES
TSEN
V18A
CHL8325A/B
40 Pin 6x6 QFN
Top View
5
6
7
PWM4
8
PWM3
VR_READY_L11
/
PWM2
9
PWRGD2
Notes
1 Pin definition in Intel & MPoL modes
2 Pin definition in AMD mode
41 GND
VR_READY_L21
PWM1
10
/ PWROK2
11
12
13
14
15
16
17
18
19
20
Figure 2: IR3541 Package Top View, Enlarged
Figure 3: CHL8325A/B Package Top View, Enlarged
2
June 21, 2013 | FINAL | V1.09
IR3541
Digital Multi-Phase Buck Controller
FUNCTIONAL BLOCK DIAGRAM
V18A
VCC
LDO
RCSP_L2
VID_2
RSCM_L2
AFE_2
1.8V
VSEN_L2
VRTN_L2
ITOT_2
Vout1_Error
Voltage
PWM1
PWM2
PWM3
PWM4
ADC
RCSP
RSCM
Vout2_Error
AFE_1
VSEN
VRTN
VID_1
PWM Generator
ISEN1
IRTN1
ISEN2
IRTN2
ISEN3
IRTN3
ISEN4
IRTN4
ISEN5
IRTN5
IP1
Mode Control
PWM5
Phase_
Period_1
Control
and
Monitoring
IP2
VAR_GATE_PM_ADDR
(IR3541 & CHL8325A)
Phase_
Period_2
ITOT_1
Σ
IP3
IP4
Iout
Vin
ITOT_2
Vout
Temp
IP5
Current ADC
Σ
Fault Bus
System Clock
IP1
IP2
IP3
IP4
System Clock
ADC Clocks
MUX Clocks
IP5
Phase_Period_1
TSEN2
(CHL8325B)
Phase_Period_2
VID_1
Reference,
VID_2
Oscillator,
State Control,
Interfaces,
Registers and
NVM
TSEN
Iout
Vin
Monitor ADC
VINSEN
V3_3
Temp
SMB_DIO
SMB_CLK
SV_CLK1/SVC2
SV_DIO1/SVD2
EN
Fault Bus
SMB_ALERT#
SV_ALERT#1/VFIXEN2
VR_HOT#1/VRHOT_ICRIT#2
VR_READY_L11/PWRGD2
VR_READY_L21/PWROK2
Notes
1 Pin definition in Intel & MPoL modes
2 Pin definition in AMD mode
RRES
Figure 4: IR3541 and CHL8325A/B Functional Block Diagram
3
June 21, 2013 | FINAL | V1.09
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