CY14B101LA-SP45XI [INFINEON]
nvSRAM (non-volatile SRAM);
| 型号： | CY14B101LA-SP45XI |
| 厂家： | 
Infineon |
| 描述： | nvSRAM (non-volatile SRAM) 静态存储器 |
| 文件： | 总31页 (文件大小：1079K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Please note that Cypress is an Infineon Technologies Company.
The document following this cover page is marked as “Cypress” document as this is the
company that originally developed the product. Please note that Infineon will continue
to offer the product to new and existing customers as part of the Infineon product
portfolio.
Continuity of document content
The fact that Infineon offers the following product as part of the Infineon product
portfolio does not lead to any changes to this document. Future revisions will occur
when appropriate, and any changes will be set out on the document history page.
Continuity of ordering part numbers
Infineon continues to support existing part numbers. Please continue to use the
ordering part numbers listed in the datasheet for ordering.
www.infineon.com
CY14B101LA
CY14B101NA
1-Mbit (128 K × 8/64 K × 16) nvSRAM
CY14B101LA/CY14B101NA, 1-Mbit (128
K × 8/64 K × 16) nvSRAM
■ Packages
Features
❐ 32-pin small-outline integrated circuit (SOIC)
❐ 44-/54-pin thin small outline package (TSOP) Type II
■ 20 ns, 25 ns, and 45 ns access times
❐ 48-pin shrink small-outline package (SSOP)
❐ 48-ball fine-pitch ball grid array (FBGA)
■ Internally organized as 128 K × 8 (CY14B101LA) or 64 K × 16
(CY14B101NA)
■ Pb-free and restriction of hazardous substances (RoHS)
compliant
■ Hands off automatic STORE on power-down with only a small
capacitor
■ STORE to QuantumTrap nonvolatile elements initiated by
software, device pin, or AutoStore on power-down
Functional Description
The Cypress CY14B101LA/CY14B101NA is a fast static RAM
(SRAM), with a nonvolatile element in each memory cell. The
memory is organized as 128 K bytes of 8 bits each or 64 K words
of 16 bits each. The embedded nonvolatile elements incorporate
QuantumTrap technology, producing the world’s most reliable
nonvolatile memory. The SRAM provides infinite read and write
cycles, while independent nonvolatile data resides in the highly
reliable QuantumTrap cell. Data transfers from the SRAM to the
nonvolatile elements (the STORE operation) takes place
automatically at power-down. On power-up, data is restored to
the SRAM (the RECALL operation) from the nonvolatile memory.
Both the STORE and RECALL operations are also available
under software control.
■ RECALL to SRAM initiated by software or power-up
■ Infinite read, write, and RECALL cycles
■ 1 million STORE cycles to QuantumTrap
■ 20 year data retention
■ Single 3 V +20% to –10% operation
■ Industrial temperature
For a complete list of related resources, click here.
Logic Block Diagram [1, 2, 3]
VCAP
VCC
Quatrum Trap
1024 X 1024
R
O
W
A5
A6
A7
A8
A9
POWER
CONTROL
STORE
RECALL
D
E
C
O
D
E
R
STORE/RECALL
CONTROL
HSB
STATIC RAM
ARRAY
1024 X 1024
A12
A13
A14
SOFTWARE
DETECT
A15
A14 - A2
A16
DQ0
DQ1
DQ2
DQ3
DQ4
I
N
P
U
T
B
U
F
F
E
R
S
DQ5
DQ6
DQ7
COLUMN I/O
DQ8
DQ9
DQ10
OE
COLUMN DEC
WE
DQ11
DQ12
DQ13
DQ14
CE
BLE
A0 A1 A2 A3 A4 A10 A11
DQ15
BHE
Notes
1. Address A –A for × 8 configuration and Address A –A for × 16 configuration.
0
16
0
15
2. Data DQ –DQ for × 8 configuration and Data DQ –DQ for × 16 configuration.
0
7
0
15
3. BHE and BLE are applicable for × 16 configuration only.
Cypress Semiconductor Corporation
Document Number: 001-42879 Rev. *S
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised April 24, 2020
CY14B101LA
CY14B101NA
Contents
Pinouts ..............................................................................3
Pin Definitions ..................................................................5
Device Operation ..............................................................6
SRAM Read ................................................................6
SRAM Write .................................................................6
AutoStore Operation ....................................................6
Hardware STORE Operation .......................................6
Hardware RECALL (Power-up) ...................................7
Software STORE .........................................................7
Software RECALL .......................................................7
Preventing AutoStore ..................................................8
Data Protection ............................................................8
Maximum Ratings .............................................................9
Operating Range ...............................................................9
DC Electrical Characteristics ..........................................9
Data Retention and Endurance .....................................10
Capacitance ....................................................................10
Thermal Resistance ........................................................10
AC Test Loads ................................................................11
AC Test Conditions ........................................................11
AC Switching Characteristics .......................................12
SRAM Read Cycle ....................................................12
SRAM Write Cycle .....................................................12
Switching Waveforms ....................................................12
AutoStore/Power-Up RECALL .......................................15
Switching Waveforms ....................................................15
Software Controlled STORE/RECALL Cycle ................16
Switching Waveforms ....................................................16
Hardware STORE Cycle .................................................17
Switching Waveforms ....................................................17
Truth Table For SRAM Operations ................................18
Ordering Information ......................................................19
Ordering Code Definitions .........................................20
Package Diagrams ..........................................................21
Acronyms ........................................................................26
Document Conventions .................................................26
Units of Measure .......................................................26
Document History Page .................................................27
Sales, Solutions, and Legal Information ......................30
Worldwide Sales and Design Support .......................30
Products ....................................................................30
PSoC® Solutions .......................................................30
Cypress Developer Community .................................30
Technical Support .....................................................30
Document Number: 001-42879 Rev. *S
Page 2 of 30
CY14B101LA
CY14B101NA
Pinouts
Figure 1. Pin Diagram – 44-pin TSOP II
[5]
A
NC
NC
1
2
0
NC
NC
44
43
42
41
1
2
44
43
42
41
HSB
NC
[7]
[4]
A
1
[6]
A
3
4
5
6
7
8
A
3
4
5
6
2
NC
NC
NC
A
A
0
15
[5]
[4]
A
3
A
1
OE
A
4
A
2
BHE
40
39
40
39
CE
A
3
BLE
DQ
16
DQ
38
37
36
35
34
A
4
7
8
38
37
36
35
34
0
1
2
3
A
15
15
DQ
CE
DQ
DQ
DQ
OE
14
13
DQ
44-pin TSOP II
DQ
DQ
V
9
10
44-pin TSOP II
9
10
DQ
DQ
V
0
1
7
[8]
(× 8)
DQ
V
(× 16)
12
6
11
12
13
14
11
12
13
14
CC
V
SS
CC
SS
Top View
(not to scale)
V
Top View
(not to scale)
SS
V
DQ
V
V
33
32
31
33
32
31
CC
SS
CC
DQ
DQ
DQ
DQ
4
5
11
2
3
5
DQ
DQ
DQ
DQ
DQ
V
10
4
15
16
17
18
WE
A
5
15
16
17
18
6
7
30
29
28
27
26
25
24
23
DQ
DQ
30
29
28
27
26
25
24
23
9
8
CAP
A
14
A
6
WE
A
V
A
13
12
CAP
A
A
7
5
A
14
A
6
A
19
20
21
22
19
20
21
22
A
A
8
A
13
11
A
9
A
7
A
12
10
A
8
NC
NC
A
A
NC
NC
11
A
9
10
Figure 2. Pin Diagram – 48-pin SSOP and 32-pin SOIC
V
CAP
48
47
V
CC
1
2
3
A
16
A
15
A
14
46
45
44
43
42
HSB
WE
A
12
4
A
7
5
A
A
13
A
6
6
8
A
5
A
9
7
NC
A
4
8
41
40
NC
A
11
9
48-pin SSOP
32-pin SOIC
NC
NC
NC
10
11
12
13
14
39
NC
NC
NC
(×8)
(×8)
38
37
36
Top View
(not to scale)
Top View
(not to scale)
V
SS
V
SS
NC
NC
NC
35
NC
DQ0
15
16
17
18
19
20
21
34
33
32
31
DQ6
OE
A
3
A
2
A
10
A
1
30
29
28
CE
DQ7
A
0
DQ1
DQ2
NC
DQ5
DQ4
DQ3
22
23
24
27
26
25
NC
V
CC
Notes
4. Address expansion for 2-Mbit. NC pin not connected to die.
5. Address expansion for 4-Mbit. NC pin not connected to die.
6. Address expansion for 8-Mbit. NC pin not connected to die.
7. Address expansion for 16-Mbit. NC pin not connected to die.
8. HSB pin is not available in 44-pin TSOP II (× 16) package.
Document Number: 001-42879 Rev. *S
Page 3 of 30
CY14B101LA
CY14B101NA
Pinouts (continued)
Figure 3. 48-ball FBGA and 54-pin TSOP II pinout
NC
1
54
53
52
51
50
49
HSB
48-FBGA
[12]
[11]
NC
(x8)
NC
A
0
2
3
[10]
NC
Top View
(not to scale)
[9]
A
1
NC
4
A
2
A
15
5
A
3
OE
BHE
BLE
DQ
15
DQ
14
6
1
2
4
3
5
6
48
47
46
45
A
4
7
CE
8
A
A
A
2
NC
OE
NC
NC
NC
NC
0
1
A
B
C
DQ
DQ
0
1
9
10
11
12
13
14
54 - TSOP II
(x16)
A
A
4
CE NC
NC DQ4
V
3
DQ
DQ
V
44
43
42
41
40
39
DQ
2
3
13
DQ
12
A
A
6
DQ0
V
CC
V
5
SS
Top View
V
SS
V
CC
(not to scale)
[9]
NC
DQ
A
DQ
11
DQ
10
DQ5
DQ6
NC
4
15
16
17
18
19
20
21
22
23
24
CC
D
E
F
SS DQ1
7
DQ
5
38
37
36
35
DQ
DQ
DQ
9
DQ
8
A
V
V
SS
VCAP
6
7
CC
DQ2
NC
16
WE
A
5
V
CAP
A
A
15
DQ3
NC
DQ7
14
A
14
34
33
32
31
30
29
28
A
6
A
13
A
A
G
H
HSB
WE NC
[11]
13
12
A
A
7
A
8
12
A
11
[10]
NC
A
A
9
A
11
A
8
10
NC
A
10
A
9
NC
NC
NC
25
26
27
NC
NC
NC
Notes
9. Address expansion for 2-Mbit. NC pin not connected to die.
10. Address expansion for 4-Mbit. NC pin not connected to die.
11. Address expansion for 8-Mbit. NC pin not connected to die.
12. Address expansion for 16-Mbit. NC pin not connected to die.
Document Number: 001-42879 Rev. *S
Page 4 of 30
CY14B101LA
CY14B101NA
Pin Definitions
Pin Name
A0–A16
I/O Type
Description
Address inputs. Used to select one of the 131,072 bytes of the nvSRAM for × 8 configuration.
Address inputs. Used to select one of the 65,536 words of the nvSRAM for × 16 configuration.
Bidirectional data I/O lines for × 8 configuration. Used as input or output lines depending on operation.
Bidirectional Data I/O Lines for × 16 configuration. Used as input or output lines depending on operation.
Input
A0–A15
DQ0–DQ7
DQ0–DQ15
WE
Input/Output
Input
Write Enable input, Active LOW. When the chip is enabled and WE is LOW, data on the I/O pins is written
to the specific address location.
Input
Input
Chip Enable input, Active LOW. When LOW, selects the chip. When HIGH, deselects the chip.
CE
OE
Output Enable, Active LOW. The active LOW OE input enables the data output buffers during read
cycles. I/O pins are tristated on deasserting OE HIGH.
Input
Input
Byte High Enable, Active LOW. Controls DQ15–DQ8.
BHE
Byte Low Enable, Active LOW. Controls DQ7–DQ0.
BLE
VSS
Ground
Ground for the device. Must be connected to the ground of the system.
VCC
Power supply Power supply inputs to the device. 3.0 V +20%, –10%
HSB[13]
Input/Output Hardware STORE Busy (HSB). When LOW, this output indicates that a Hardware STORE is in progress.
When pulled LOW, external to the chip, it initiates a nonvolatile STORE operation. After each Hardware
and Software STORE operation HSB is driven HIGH for a short time (tHHHD) with standard output high
current and then a weak internal pull-up resistor keeps this pin HIGH (external pull-up resistor connection
optional).
VCAP
NC
Power supply AutoStore capacitor. Supplies power to the nvSRAM during power loss to store data from SRAM to
nonvolatile elements.
No connect No connect. This pin is not connected to the die.
Note
13. HSB pin is not available in 44-pin TSOP II (× 16) package.
Document Number: 001-42879 Rev. *S
Page 5 of 30
CY14B101LA
CY14B101NA
Note If the capacitor is not connected to VCAP pin, AutoStore
must be disabled using the soft sequence specified in Preventing
AutoStore on page 8. In case AutoStore is enabled without a
capacitor on VCAP pin, the device attempts an AutoStore
operation without sufficient charge to complete the store. This
corrupts the data stored in nvSRAM.
Device Operation
The CY14B101LA/CY14B101NA nvSRAM is made up of two
functional components paired in the same physical cell. They are
an SRAM memory cell and a nonvolatile QuantumTrap cell. The
SRAM memory cell operates as a standard fast static RAM. Data
in the SRAM is transferred to the nonvolatile cell (the STORE
operation), or from the nonvolatile cell to the SRAM (the RECALL
operation). Using this unique architecture, all cells are stored and
recalled in parallel. During the STORE and RECALL operations,
SRAM read and write operations are inhibited. The
CY14B101LA/CY14B101NA supports infinite reads and writes
similar to a typical SRAM. In addition, it provides infinite RECALL
operations from the nonvolatile cells and up to 1 million STORE
operations. See the Truth Table For SRAM Operations on page
18 for a complete description of read and write modes.
Figure 4 shows the proper connection of the storage capacitor
(VCAP) for automatic STORE operation. See the DC Electrical
Characteristics on page 9 for the size of VCAP. The voltage on
the VCAP pin is driven to VCC by a regulator on the chip. A pull-up
should be placed on WE to hold it inactive during power-up. This
pull-up is effective only if the WE signal is tristate during
power-up. Many MPUs tristate their controls on power-up. This
should be verified when using the pull-up. When the nvSRAM
comes out of power-on-RECALL, the MPU must be active or the
WE held inactive until the MPU comes out of reset.
SRAM Read
To reduce unnecessary nonvolatile stores, AutoStore and
Hardware STORE operations are ignored unless at least one
write operation has taken place since the most recent STORE or
RECALL cycle. Software initiated STORE cycles are performed
regardless of whether a write operation has taken place. The
HSB signal is monitored by the system to detect if an AutoStore
cycle is in progress.
The CY14B101LA/CY14B101NA performs a read cycle when
CE and OE are LOW and WE and HSB are HIGH. The address
specified on pins A0–16 or A0–15 determines which of the 131,072
data bytes or 65,536 words of 16 bits each are accessed. Byte
enables (BHE, BLE) determine which bytes are enabled to the
output, in the case of 16-bit words. When the read is initiated by
an address transition, the outputs are valid after a delay of tAA
(read cycle 1). If the read is initiated by CE or OE, the outputs
are valid at tACE or at tDOE, whichever is later (read cycle 2). The
data output repeatedly responds to address changes within the
tAA access time without the need for transitions on any control
input pins. This remains valid until another address change or
until CE or OE is brought HIGH, or WE or HSB is brought LOW.
Figure 4. AutoStore Mode
VCC
0.1 uF
VCC
SRAM Write
A write cycle is performed when CE and WE are LOW and HSB
is HIGH. The address inputs must be stable before entering the
write cycle and must remain stable until CE or WE goes HIGH at
the end of the cycle. The data on the common I/O pins DQ0–15
are written into the memory if the data is valid tSD before the end
of a WE-controlled write or before the end of a CE-controlled
write. The Byte Enable inputs (BHE, BLE) determine which bytes
are written, in the case of 16-bit words. Keep OE HIGH during
the entire write cycle to avoid data bus contention on common
I/O lines. If OE is left LOW, internal circuitry turns off the output
buffers tHZWE after WE goes LOW.
WE
VCAP
VCAP
VSS
Hardware STORE Operation
AutoStore Operation
The CY14B101LA/CY14B101NA provides the HSB[14] pin to
control and acknowledge the STORE operations. Use the HSB
pin to request a Hardware STORE cycle. When the HSB pin is
driven LOW, the CY14B101LA/CY14B101NA conditionally
initiates a STORE operation after tDELAY. An actual STORE cycle
only begins if a write to the SRAM has taken place since the last
STORE or RECALL cycle. The HSB pin also acts as an open
drain driver (internal 100 kΩ weak pull-up resistor) that is
internally driven LOW to indicate a busy condition when the
STORE (initiated by any means) is in progress.
The CY14B101LA/CY14B101NA stores data to the nvSRAM
using one of the following three storage operations: Hardware
STORE activated by HSB; Software STORE activated by an
address sequence; AutoStore on device power-down. The
AutoStore operation is a unique feature of QuantumTrap
technology
and
is
enabled
by
default
on
the
CY14B101LA/CY14B101NA.
During a normal operation, the device draws current from VCC to
charge a capacitor connected to the VCAP pin. This stored
charge is used by the chip to perform a single STORE operation.
If the voltage on the VCC pin drops below VSWITCH, the part
automatically disconnects the VCAP pin from VCC. A STORE
operation is initiated with power provided by the VCAP capacitor.
Note After each Hardware and Software STORE operation HSB
is driven HIGH for a short time (tHHHD) with standard output high
current and then remains HIGH by internal 100 kΩ pull-up
resistor.
Note
14. HSB pin is not available in 44-pin TSOP II (× 16) package.
Document Number: 001-42879 Rev. *S
Page 6 of 30
CY14B101LA
CY14B101NA
SRAM write operations that are in progress when HSB is driven
LOW by any means are given time (tDELAY) to complete before
the STORE operation is initiated. However, any SRAM write
cycles requested after HSB goes LOW are inhibited until HSB
returns HIGH. In case the write latch is not set, HSB is not driven
LOW by the CY14B101LA/CY14B101NA. But any SRAM read
and write cycles are inhibited until HSB is returned HIGH by MPU
or other external source.
To initiate the Software STORE cycle, the following read
sequence must be performed:
1. Read address 0x4E38 Valid READ
2. Read address 0xB1C7 Valid READ
3. Read address 0x83E0 Valid READ
4. Read address 0x7C1F Valid READ
5. Read address 0x703F Valid READ
6. Read address 0x8FC0 Initiate STORE cycle
During any STORE operation, regardless of how it is initiated,
the CY14B101LA/CY14B101NA continues to drive the HSB pin
LOW, releasing it only when the STORE is complete. Upon
completion of the STORE operation, the nvSRAM memory
access is inhibited for tLZHSB time after HSB pin returns HIGH.
Leave the HSB unconnected if it is not used.
The software sequence may be clocked with CE controlled reads
or OE controlled reads, with WE kept HIGH for all the six READ
sequences. After the sixth address in the sequence is entered,
the STORE cycle commences and the chip is disabled. HSB is
driven LOW. After the tSTORE cycle time is fulfilled, the SRAM is
activated again for the read and write operation.
Hardware RECALL (Power-up)
During power-up or after any low power condition
(VCC< VSWITCH), an internal RECALL request is latched. When
VCC again exceeds the VSWITCH on power up, a RECALL cycle
is automatically initiated and takes tHRECALL to complete. During
this time, the HSB pin is driven LOW by the HSB driver and all
reads and writes to nvSRAM are inhibited.
Software RECALL
Data is transferred from the nonvolatile memory to the SRAM by
a software address sequence. A Software RECALL cycle is
initiated with a sequence of read operations in a manner similar
to the Software STORE initiation. To initiate the RECALL cycle,
the following sequence of CE or OE controlled read operations
must be performed:
Software STORE
Data is transferred from the SRAM to the nonvolatile memory by
a software address sequence. The CY14B101LA/CY14B101NA
Software STORE cycle is initiated by executing sequential CE or
OE controlled read cycles from six specific address locations in
exact order. During the STORE cycle an erase of the previous
nonvolatile data is first performed, followed by a program of the
nonvolatile elements. After a STORE cycle is initiated, further
input and output are disabled until the cycle is completed.
1. Read address 0x4E38 Valid READ
2. Read address 0xB1C7 Valid READ
3. Read address 0x83E0 Valid READ
4. Read address 0x7C1F Valid READ
5. Read address 0x703F Valid READ
6. Read address 0x4C63 Initiate RECALL cycle
Internally, RECALLis a two step procedure. First, the SRAM data
is cleared. Next, the nonvolatile information is transferred into the
SRAM cells. After the tRECALL cycle time, the SRAM is again
ready for read and write operations. The RECALL operation
does not alter the data in the nonvolatile elements.
Because a sequence of READs from specific addresses is used
for STORE initiation, it is important that no other read or write
accesses intervene in the sequence, or the sequence is aborted
and no STORE or RECALL takes place.
Table 1. Mode Selection
[16]
A15–A0
Mode
I/O
Power
Standby
Active
CE
WE
OE
BHE, BLE[15]
H
X
X
X
X
X
X
Not selected
Read SRAM
Write SRAM
Output high Z
Output data
Input data
L
L
L
H
L
L
X
L
L
L
X
Active
Active[17]
H
0x4E38
0xB1C7
0x83E0
0x7C1F
0x703F
0x8B45
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
AutoStore
Output data
Output data
Output data
Output data
Output data
Output data
Disable
Notes
15. BHE and BLE are applicable for x16 configuration only.
16. While there are 17 address lines on the CY14B101LA (16 address lines on the CY14B101NA), only the 13 address lines (A - A ) are used to control software modes.
14
2
Rest of the address lines are do not care.
17. The six consecutive address locations must be in the order listed. WE must be HIGH during all six cycles to enable a nonvolatile cycle.
Document Number: 001-42879 Rev. *S
Page 7 of 30
CY14B101LA
CY14B101NA
Table 1. Mode Selection (continued)
[16]
BHE, BLE[15]
A15–A0
Mode
I/O
Power
CE
WE
OE
L
H
L
X
0x4E38
0xB1C7
0x83E0
0x7C1F
0x703F
0x4B46
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
AutoStore
Output data
Output data
Output data
Output data
Output data
Output data
Active[18]
Enable
[18]
L
L
H
H
L
L
X
X
0x4E38
0xB1C7
0x83E0
0x7C1F
0x703F
0x8FC0
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Nonvolatile
STORE
Output data
Output data
Output data
Output data
Output data
Output high Z
Active ICC2
0x4E38
0xB1C7
0x83E0
0x7C1F
0x703F
0x4C63
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Nonvolatile
RECALL
Output data
Output data
Output data
Output data
Output data
Output high Z
Active[18]
If the AutoStore function is disabled or reenabled, a manual
STORE operation (Hardware or Software) must be issued to
save the AutoStore state through subsequent power-down
cycles. The part comes from the factory with AutoStore enabled
and 0x00 written in all cells.
Preventing AutoStore
The AutoStore function is disabled by initiating an AutoStore
disable sequence. A sequence of read operations is performed
in a manner similar to the Software STORE initiation. To initiate
the AutoStore disable sequence, the following sequence of CE
or OE controlled read operations must be performed:
Data Protection
1. Read address 0x4E38 Valid READ
2. Read address 0xB1C7 Valid READ
3. Read address 0x83E0 Valid READ
4. Read address 0x7C1F Valid READ
5. Read address 0x703F Valid READ
6. Read address 0x8B45 AutoStore Disable
The CY14B101LA/CY14B101NA protects data from corruption
during low voltage conditions by inhibiting all externally initiated
STORE and write operations. The low voltage condition is
detected when VCC is less than VSWITCH
.
If the
CY14B101LA/CY14B101NA is in a write mode (both CE and WE
are LOW) at power-up, after a RECALL or STORE, the write is
inhibited until the SRAM is enabled after tLZHSB (HSB to output
active). This protects against inadvertent writes during power-up
or brown out conditions.
The AutoStore is reenabled by initiating an AutoStore enable
sequence. A sequence of read operations is performed in a
manner similar to the Software RECALL initiation. To initiate the
AutoStore enable sequence, the following sequence of CE or OE
controlled read operations must be performed:
1. Read address 0x4E38 Valid READ
2. Read address 0xB1C7 Valid READ
3. Read address 0x83E0 Valid READ
4. Read address 0x7C1F Valid READ
5. Read address 0x703F Valid READ
6. Read address 0x4B46 AutoStore Enable
Note
18. The six consecutive address locations must be in the order listed. WE must be HIGH during all six cycles to enable a nonvolatile cycle.
Document Number: 001-42879 Rev. *S
Page 8 of 30
CY14B101LA
CY14B101NA
Package power dissipation
capability (TA = 25 °C) ................................................. 1.0 W
Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the
device. These user guidelines are not tested.
Surface mount Pb soldering
temperature (3 Seconds) ......................................... +260 °C
Storage temperature ................................ –65 °C to +150 °C
DC output current (1 output at a time, 1s duration) .... 15 mA
Maximum accumulated storage time:
Static discharge voltage
(per MIL-STD-883, Method 3015) ......................... > 2001 V
At 150 °C ambient temperature ...................... 1000 h
At 85 °C ambient temperature .................... 20 Years
Latch up current .................................................... > 200 mA
Maximum junction temperature ................................. 150 °C
Supply voltage on VCC relative to VSS ...........–0.5 V to 4.1 V
Operating Range
Voltage applied to outputs
in High Z state .................................... –0.5 V to VCC + 0.5 V
Range
Industrial
Ambient Temperature
VCC
Input voltage .......................................–0.5 V to VCC + 0.5 V
–40 °C to +85 °C
2.7 V to 3.6 V
Transient voltage (< 20 ns) on
any pin to ground potential .................–2.0 V to VCC + 2.0 V
DC Electrical Characteristics
Over the Operating Range
Parameter
VCC
Description
Power supply voltage
Average VCC current
Test Conditions
Min
2.7
–
Typ [19]
Max
Unit
3.0
–
3.6
V
ICC1
tRC = 20 ns
RC = 25 ns
tRC = 45 ns
70
70
52
mA
mA
mA
t
Values obtained without output loads
(IOUT = 0 mA)
ICC2
ICC3
Average VCC current during
STORE
All inputs don’t care, VCC = Max
Average current for duration tSTORE
–
–
–
10
–
mA
mA
Average VCC current at
tRC = 200 ns, VCC(Typ), 25 °C
All inputs cycling at CMOS levels.
Values obtained without output loads
(IOUT = 0 mA)
35
ICC4
ISB
Average VCAP current during
AutoStore cycle
All inputs don’t care. Average current for
duration tSTORE
–
–
–
–
5
5
mA
mA
VCC standby current
CE > (VCC – 0.2 V).
VIN < 0.2 V or > (VCC – 0.2 V).
Standby current level after nonvolatile cycle
is complete.
Inputs are static. f = 0 MHz
[20]
IIX
Input leakage current (except
HSB)
VCC = Max, VSS < VIN < VCC
–1
–
+1
µA
Input leakage current (for HSB) VCC = Max, VSS < VIN < VCC
Off-state output leakage current VCC = Max, VSS < VOUT < VCC
–100
–1
–
–
+1
+1
µA
µA
IOZ
,
CE or OE > VIH or BHE/BLE > VIH or WE < VIL
VIH
VIL
Input HIGH voltage
Input LOW voltage
Output HIGH voltage
Output LOW voltage
2.0
VSS – 0.5
2.4
–
–
–
–
VCC + 0.5
V
V
V
V
0.8
–
VOH
VOL
IOUT = –2 mA
IOUT = 4 mA
–
0.4
Notes
19. Typical values are at 25 °C, V = V
. Not 100% tested.
CC(Typ)
CC
20. The HSB pin has I
= -2 µA for V of 2.4 V when both active high and low drivers are disabled. When they are enabled standard V and V are valid. This
OUT
O
H
O
H
O
L
parameter is characterized but not tested.
Document Number: 001-42879 Rev. *S
Page 9 of 30
CY14B101LA
CY14B101NA
DC Electrical Characteristics (continued)
Over the Operating Range
Parameter
Description
Storage capacitor
Test Conditions
Min
61
–
Typ [19]
Max
180
VCC
Unit
µF
V
[21]
VCAP
Between VCAP pin and VSS
68
–
[22, 23]
VVCAP
Maximum voltage driven on VCAP VCC = Max
pin by the device
Data Retention and Endurance
Over the Operating Range
Parameter
Description
Min
20
Unit
Years
K
DATAR
NVC
Data retention
Nonvolatile STORE operations
1,000
Capacitance
Parameter[23]
Description
Test Conditions
Max
Unit
pF
CIN
Input capacitance (except BHE, BLE and HSB)
Input capacitance (for BHE, BLE and HSB)
Output capacitance (except HSB)
TA = 25 °C, f = 1 MHz, VCC = VCC(Typ)
7
8
7
8
pF
COUT
pF
Output capacitance (for HSB)
pF
Thermal Resistance
54-pin
48-pin 48-ball 44-pin
32-pin
Parameter[23]
Description
Test Conditions
Unit
TSOP II SSOP
FBGA TSOP II SOIC
ΘJA
Thermal resistance
(junction to ambient)
Test
conditions
follow 36.4
37.47
24.71
48.19
6.5
41.74
11.90
41.55 °C/W
24.43 °C/W
standard test methods and
procedures for measuring
thermal
ΘJC
Thermal resistance
(junction to case)
10.13
impedance,
in
accordance
with
EIA/JESD51.
Notes
21. Min V
value guarantees that there is a sufficient charge available to complete a successful AutoStore operation. Max V
value guarantees that the capacitor
CAP
CAP
on V
is charged to a minimum voltage during a Power-Up RECALL cycle so that an immediate power-down cycle can complete a successful AutoStore. Therefore
CAP
it is always recommended to use a capacitor within the specified min and max limits. See application note AN43593 for more details on V
options.
CAP
22. Maximum voltage on V
pin (V
) is provided for guidance when choosing the V
capacitor. The voltage rating of the V capacitor across the operating
CAP
VCAP
CAP
CAP
temperature range should be higher than the V
voltage.
VCAP
23. These parameters are guaranteed by design and are not tested.
Document Number: 001-42879 Rev. *S
Page 10 of 30
CY14B101LA
CY14B101NA
AC Test Loads
Figure 5. AC Test Loads
577 Ω
for tristate specs
577 Ω
3.0 V
3.0 V
R1
R1
OUTPUT
OUTPUT
R2
789 Ω
R2
789 Ω
5 pF
30 pF
AC Test Conditions
Input pulse levels ...................................................0 V to 3 V
Input rise and fall times (10%–90%) ........................... < 3 ns
Input and output timing reference levels ....................... 1.5 V
Document Number: 001-42879 Rev. *S
Page 11 of 30
CY14B101LA
CY14B101NA
AC Switching Characteristics
Over the Operating Range
Parameters [24]
20 ns
25 ns
45 ns
Unit
Description
Cypress
Alt Parameter
Parameter
Min
Max
Min
Max
Min
Max
SRAM Read Cycle
tACE
tACS
tRC
Chip enable access time
Read cycle time
–
20
20
–
–
25
25
–
–
45
45
ns
ns
[25]
tRC
[26]
tAA
tOE
tOH
tLZ
Address access time
–
–
3
3
–
0
–
0
–
20
10
–
–
–
3
3
–
0
–
0
–
25
12
–
–
–
3
3
–
0
–
0
–
45
20
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAA
Output enable to data valid
Output hold after address change
Chip enable to output active
Chip disable to output inactive
Output enable to output active
Output disable to output inactive
Chip enable to power active
Chip disable to power standby
tDOE
[26]
tOHA
[27, 28]
–
–
–
tLZCE
tHZCE
tLZOE
[27, 28]
[27, 28]
[27, 28]
tHZ
tOLZ
tOHZ
tPA
8
10
–
15
–
–
8
10
–
15
–
tHZOE
[27]
–
tPU
[27]
tPS
20
25
45
20
tPD
[27]
tDBE[
–
–
–
Byte enable to data valid
Byte enable to output active
Byte disable to output inactive
–
0
–
10
–
8
–
0
–
12
–
10
–
0
–
ns
ns
ns
[27]
[27]
tLZBE
tHZBE
15
SRAM Write Cycle
tWC
tPWE
tSCE
tSD
tHD
tAW
tSA
tWC
tWP
tCW
tDW
tDH
tAW
tAS
Write cycle time
Write pulse width
20
15
15
8
0
15
0
–
–
–
–
–
–
–
–
8
25
20
20
10
0
20
0
0
–
–
–
–
–
–
–
–
10
45
30
30
15
0
30
0
0
–
–
–
–
–
–
–
–
15
ns
ns
ns
ns
ns
ns
ns
ns
ns
Chip enable to end of write
Data setup to end of write
Data hold after end of write
Address setup to end of write
Address setup to start of write
Address hold after end of write
Write enable to output disable
tHA
tWR
tWZ
0
–
[27, 28, 29]
–
–
tHZWE
[27, 28]
tOW
–
Output active after end of write
Byte enable to end of write
3
–
–
3
–
–
3
–
–
ns
ns
tLZWE
tBW
15
20
30
Switching Waveforms
Figure 6. SRAM Read Cycle #1 (Address Controlled) [25, 26, 30]
tRC
Address
Address Valid
tAA
Output Data Valid
Previous Data Valid
tOHA
Data Output
Notes
24. Test conditions assume signal transition time of 3 ns or less, timing reference levels of V /2, input pulse levels of 0 to V
, and output loading of the specified
CC(typ)
CC
I
/I and load capacitance shown in Figure 5 on page 11.
OL OH
25. WE must be HIGH during SRAM read cycles.
26. Device is continuously selected with CE, OE, and BHE/BLE LOW.
27. These parameters are guaranteed by design and are not tested.
28. Measured ±200 mV from steady state output voltage.
29. If WE is low when CE goes low, the outputs remain in the high impedance state.
30. HSB must remain HIGH during Read and Write cycles.
Document Number: 001-42879 Rev. *S
Page 12 of 30
CY14B101LA
CY14B101NA
Switching Waveforms (continued)
Figure 7. SRAM Read Cycle #2 (CE and OE Controlled) [31, 32, 33]
Address
CE
Address Valid
tRC
tHZCE
tACE
tAA
tLZCE
tHZOE
tDOE
OE
tHZBE
tLZOE
tDBE
BHE, BLE
tLZBE
High Impedance
Standby
Data Output
Output Data Valid
tPU
tPD
Active
ICC
Figure 8. SRAM Write Cycle #1 (WE Controlled) [31, 33, 34, 35]
tWC
Address
Address Valid
tSCE
tHA
CE
tBW
BHE, BLE
tAW
tPWE
WE
Data Input
Data Output
tSA
tHD
tSD
Input Data Valid
tLZWE
tHZWE
High Impedance
Previous Data
Notes
31. BHE and BLE are applicable for × 16 configuration only.
32. WE must be HIGH during SRAM read cycles.
33. HSB must remain HIGH during Read and Write cycles.
34. CE or WE must be > V during address transitions.
IH
35. If WE is low when CE goes low, the outputs remain in the high impedance state.
Document Number: 001-42879 Rev. *S
Page 13 of 30
CY14B101LA
CY14B101NA
Switching Waveforms (continued)
Figure 9. SRAM Write Cycle #2 (CE Controlled) [36, 37, 38, 39]
tWC
Address Valid
tSCE
Address
tSA
tHA
CE
tBW
tPWE
tSD
BHE, BLE
WE
tHD
Input Data Valid
High Impedance
Data Input
Data Output
Figure 10. SRAM Write Cycle #3 (BHE and BLE Controlled) [36, 37, 38, 39]
tWC
Address
CE
Address Valid
tSCE
tSA
tHA
tBW
BHE, BLE
WE
tAW
tPWE
tSD
tHD
Data Input
Input Data Valid
High Impedance
Data Output
Notes
36. BHE and BLE are applicable for × 16 configuration only.
37. If WE is low when CE goes low, the outputs remain in the high-impedance state.
38. HSB must remain HIGH during Read and Write cycles.
39. CE or WE must be > V during address transitions.
IH
Document Number: 001-42879 Rev. *S
Page 14 of 30
CY14B101LA
CY14B101NA
AutoStore/Power-Up RECALL
Over the Operating Range
20 ns
25 ns
45 ns
Unit
Parameter
Description
Min
Max
Min
Max
Min
Max
[40]
Power-Up RECALL duration
STORE cycle duration
–
20
–
20
–
20
8
ms
ms
ns
tHRECALL
[41]
–
–
8
–
–
8
–
–
tSTORE
[42]
Time allowed to complete SRAM
write cycle
20
25
25
tDELAY
Low voltage trigger level
VCC rise time
–
150
–
2.65
–
–
150
–
2.65
–
–
150
–
2.65
–
V
µs
V
VSWITCH
[43]
tVCCRISE
[43]
HSB output disable voltage
1.9
1.9
1.9
VHDIS
[43]
tLZHSB
HSB to output active time
HSB High active time
–
–
5
–
–
5
–
–
5
µs
ns
[43]
tHHHD
500
500
500
Switching Waveforms
Figure 11. AutoStore or Power-Up RECALL [44]
VCC
VSWITCH
VHDIS
41
41
tVCCRISE
tSTORE
tSTORE
Note
Note
tHHHD
tHHHD
45
45
Note
Note
HSB OUT
AutoStore
tDELAY
tLZHSB
tLZHSB
tDELAY
POWER-
UP
RECALL
tHRECALL
tHRECALL
Read & Write
Inhibited
(RWI)
Read & Write
Read & Write
POWER-UP
RECALL
BROWN
OUT
AutoStore
POWER
DOWN
AutoStore
POWER-UP
RECALL
Notes
40. t
starts from the time V rises higher than V .
SWITCH
HRECALL
CC
41. If an SRAM write has not taken place since the last nonvolatile cycle, no AutoStore or Hardware STORE takes place.
42. On a Hardware STORE and AutoStore initiation, SRAM write operation continues to be enabled for time t
43. These parameters are guaranteed by design and are not tested.
.
DELAY
44. Read and Write cycles are ignored during STORE, RECALL, and while V is lower than V
.
CC
SWITCH
45. During power-up and power-down, HSB glitches when HSB pin is pulled up through an external resistor.
Document Number: 001-42879 Rev. *S
Page 15 of 30
CY14B101LA
CY14B101NA
Software Controlled STORE/RECALL Cycle
Over the Operating Range
20 ns
25 ns
45 ns
Unit
Parameter[46, 47]
Description
Min
Max
Min
Max
Min
Max
tRC
STORE/RECALL initiation cycle time
Address setup time
20
–
25
–
45
0
–
ns
ns
ns
ns
µs
tSA
0
15
0
–
–
0
20
0
–
–
–
–
tCW
Clock pulse width
30
0
tHA
Address hold time
–
–
–
tRECALL
RECALL duration
–
200
–
200
–
200
Switching Waveforms
Figure 12. CE and OE Controlled Software STORE/RECALL Cycle [47]
tRC
tRC
Address
CE
Address #1
tCW
Address #6
tCW
tSA
tHA
tHA
tHA
tSA
tHA
OE
tHHHD
tHZCE
HSB (STORE only)
DQ (DATA)
48
Note
tDELAY
tLZCE
tLZHSB
High Impedance
tSTORE/tRECALL
RWI
Figure 13. AutoStore Enable/Disable Cycle [47]
tRC
tRC
Address
Address #1
tCW
Address #6
tCW
tSA
CE
tSA
tHA
tHA
tHA
tHA
OE
tSS
tHZCE
48
Note
tLZCE
tDELAY
DQ (DATA)
RWI
Notes
46. The software sequence is clocked with CE controlled or OE controlled reads.
47. The six consecutive addresses must be read in the order listed in Table 1 on page 7. WE must be HIGH during all six consecutive cycles.
48. DQ output data at the sixth read may be invalid because the output is disabled at t
time.
DELAY
Document Number: 001-42879 Rev. *S
Page 16 of 30
CY14B101LA
CY14B101NA
Hardware STORE Cycle
Over the Operating Range
20 ns
25 ns
45 ns
Unit
Parameter
Description
Min
–
Max
20
Min
–
Max
25
Min
Max
25
tDHSB
tPHSB
HSB to output active time when write latch not set
Hardware STORE pulse width
–
15
–
ns
ns
μs
15
–
–
15
–
–
–
[49, 50]
tSS
Soft sequence processing time
100
100
100
Switching Waveforms
Figure 14. Hardware STORE Cycle [51]
Write latch set
tPHSB
HSB (IN)
tSTORE
tHHHD
tDELAY
HSB (OUT)
DQ (Data Out)
RWI
tLZHSB
Write latch not set
tPHSB
HSB pin is driven high to VCC only by Internal
100 kOhm resistor,
HSB (IN)
HSB driver is disabled
SRAM is disabled as long as HSB (IN) is driven low.
tDELAY
tDHSB
tDHSB
HSB (OUT)
RWI
Figure 15. Soft Sequence Processing [49, 50]
tSS
tSS
Soft Sequence
Command
Soft Sequence
Command
Address
Address #1
tSA
Address #6
tCW
Address #1
Address #6
tCW
CE
VCC
Notes
49. This is the amount of time it takes to take action on a soft sequence command. V power must remain HIGH to effectively register command.
CC
50. Commands such as STORE and RECALL lock out I/O until operation is complete which further increases this time. See the specific command.
51. If an SRAM write has not taken place since the last nonvolatile cycle, no AutoStore or Hardware STORE takes place.
Document Number: 001-42879 Rev. *S
Page 17 of 30
CY14B101LA
CY14B101NA
Truth Table For SRAM Operations
HSB must remain HIGH for SRAM operations
Table 2. Truth Table for × 8 Configuration
CE
H
L
WE
X
OE
X
Inputs/Outputs[52]
Mode
Deselect/Power-down
Read
Power
High Z
Standby
H
L
Data Out (DQ0–DQ7);
High Z
Active
Active
Active
L
H
H
Output disabled
Write
L
L
X
Data in (DQ0–DQ7);
Table 3. Truth Table for × 16 Configuration
CE
H
L
WE
X
OE
X
BHE[53] BLE[53]
Inputs/Outputs[52]
High Z
Mode
Power
X
H
L
X
H
L
Deselect/Power-down
Output disabled
Read
Standby
Active
Active
Active
X
X
High Z
L
H
L
Data Out (DQ0–DQ15)
L
H
L
H
L
Data Out (DQ0–DQ7);
DQ8–DQ15 in High Z
Read
L
H
L
L
H
Data Out (DQ8–DQ15);
DQ0–DQ7 in High Z
Read
Active
L
L
L
L
L
H
H
H
L
H
H
H
X
X
L
H
L
L
L
H
L
L
High Z
High Z
High Z
Output disabled
Output disabled
Output disabled
Write
Active
Active
Active
Active
Active
L
Data In (DQ0–DQ15)
L
H
Data In (DQ0–DQ7);
DQ8–DQ15 in High Z
Write
L
L
X
L
H
Data In (DQ8–DQ15);
DQ0–DQ7 in High Z
Write
Active
Notes
52. Data DQ –DQ for × 8 configuration and Data DQ –DQ for × 16 configuration.
0
7
0
15
53. BHE and BLE are applicable for × 16 configuration only.
Document Number: 001-42879 Rev. *S
Page 18 of 30
CY14B101LA
CY14B101NA
Ordering Information
Speed
Ordering Code
Package Diagram
Package Type
44-pin TSOP II
Operating Range
(ns)
20
CY14B101LA-ZS20XIT
CY14B101LA-ZS20XI
CY14B101LA-SZ25XIT
CY14B101LA-SZ25XI
CY14B101LA-ZS25XIT
CY14B101LA-ZS25XI
CY14B101LA-SP25XIT
CY14B101LA-SP25XI
CY14B101LA-BA25XIT
CY14B101LA-BA25XI
CY14B101NA-ZS25XIT
CY14B101NA-ZS25XI
CY14B101LA-SZ45XIT
CY14B101LA-SZ45XI
CY14B101LA-ZS45XIT
CY14B101LA-ZS45XI
CY14B101LA-SP45XIT
CY14B101LA-SP45XI
CY14B101LA-BA45XIT
CY14B101LA-BA45XI
CY14B101NA-ZS45XIT
CY14B101NA-ZS45XI
51-85087
51-85087
51-85127
51-85127
51-85087
51-85087
51-85061
51-85061
51-85128
51-85128
51-85087
51-85087
51-85127
51-85127
51-85087
51-85087
51-85061
51-85061
51-85128
51-85128
51-85087
51-85087
Industrial
44-pin TSOP II
32-pin SOIC
25
Industrial
32-pin SOIC
44-pin TSOP II
44-pin TSOP II
48-pin SSOP
48-pin SSOP
48-ball FBGA
48-ball FBGA
44-pin TSOP II
44-pin TSOP II
32-pin SOIC
45
Industrial
32-pin SOIC
44-pin TSOP II
44-pin TSOP II
48-pin SSOP
48-pin SSOP
48-ball FBGA
48-ball FBGA
44-pin TSOP II
44-pin TSOP II
All the above parts are Pb-free.
Document Number: 001-42879 Rev. *S
Page 19 of 30
CY14B101LA
CY14B101NA
Ordering Code Definitions
CY 14 B 101 L A - ZS 20 X I T
Option:
T - Tape and Reel
Blank - Std.
Temperature:
I - Industrial (–40 to 85 °C)
Speed:
20 - 20 ns
Pb-free
Package:
25 - 25 ns
45 - 45 ns
SZ- 32 SOIC
ZS- 44 TSOP II
SP- 48 SSOP
BA- 48 FBGA
ZSP - 54 TSOP II
Die revision:
Blank - No Rev
A - First Rev
Data Bus:
L - × 8
N - × 16
Density:
101 - 1 Mb
Voltage:
B - 3.0 V
14 - nvSRAM
Cypress
Document Number: 001-42879 Rev. *S
Page 20 of 30
CY14B101LA
CY14B101NA
Package Diagrams
Figure 16. 32-pin SOIC (300 Mil) Package Outline, 51-85127
51-85127 *D
Document Number: 001-42879 Rev. *S
Page 21 of 30
CY14B101LA
CY14B101NA
Package Diagrams (continued)
Figure 17. 44-pin TSOP II Package Outline, 51-85087
51-85087 *E
Document Number: 001-42879 Rev. *S
Page 22 of 30
CY14B101LA
CY14B101NA
Package Diagrams (continued)
Figure 18. 48-pin SSOP (300 Mils) Package Outline, 51-85061
51-85061 *F
Document Number: 001-42879 Rev. *S
Page 23 of 30
CY14B101LA
CY14B101NA
Package Diagrams (continued)
Figure 19. 48-ball FBGA (6 × 10 × 1.2 mm) Package Outline, 51-85128
51-85128 *I
Document Number: 001-42879 Rev. *S
Page 24 of 30
CY14B101LA
CY14B101NA
Package Diagrams (continued)
Figure 20. 54-pin TSOP II (22.4 × 11.84 × 1.0 mm) Package Outline, 51-85160
51-85160 *E
Document Number: 001-42879 Rev. *S
Page 25 of 30
CY14B101LA
CY14B101NA
Acronyms
Document Conventions
Units of Measure
Acronym
Description
byte high enable
BHE
BLE
Symbol
°C
Unit of Measure
byte low enable
chip enable
degree Celsius
hertz
CE
Hz
kHz
kΩ
MHz
μA
μF
μs
CMOS
complementary metal oxide semiconductor
electronic industries alliance
fine-pitch ball grid array
kilohertz
kilohm
EIA
FBGA
megahertz
microampere
microfarad
microsecond
milliampere
millisecond
nanosecond
ohm
hardware store busy
HSB
I/O
input/output
nvSRAM
non-volatile static random access memory
output enable
OE
mA
ms
ns
RoHS
restriction of hazardous substances
read and write inhibited
RWI
SOIC
SRAM
SSOP
TSOP
WE
small outline integrated circuit
static random access memory
shrink small outline package
thin small outline package
write enable
Ω
%
percent
pF
V
picofarad
volt
W
watt
Document Number: 001-42879 Rev. *S
Page 26 of 30
CY14B101LA
CY14B101NA
Document History Page
Document Title: CY14B101LA/CY14B101NA, 1-Mbit (128 K × 8/64 K × 16) nvSRAM
Document Number: 001-42879
Submission
Rev.
ECN No.
Description of Change
Date
**
2050747
2607447
01/31/08
11/14/08
New data sheet.
*A
Removed 15 ns access speed
Updated “Features”
Updated Logic block diagram
Added footnote 1 2, 3 and 7
Pin definition: Updated WE, HSB and NC pin description
Page 4: Updated SRAM READ, SRAM WRITE, AutoStore operation description
Updated Figure 4
Page 4: Updated Hardware store operation and Hardware RECALL (Powerup) description
Page 4: Updated Software store and software recall description
Footnote 1 and 11 referenced for Mode selection Table
Added footnote 11
Updated footnote 9 and 10
Page 6: updated Data protection description
Maximum Ratings:Added Max. Accumulated storage time
Changed Output short circuit current parameter name to DC output current
Changed ICC2 from 6 mA to 10 mA
Changed ICC3 from 15 mA to 35 mA
Changed ICC4 from 6 mA to 5 mA
Changed ISB from 3 mA to 5 mA
Added IIX for HSB
Updated ICC1, CC3, SB and IOZ Test conditions
I
I
Changed VCAP voltage min value from 68 µF to 61 µF
Added VCAP voltage max value to 180 µF
Updated footnote 12 and 13
Added footnote 14
Added Data retention and Endurance Table
Added thermal resistance value to 48-pin FBGA and 44-pin TSOP II packages
Updated Input Rise and Fall time in AC test Conditions
Referenced footnote 17 to tOHA parameter
Updated All switching waveforms
Updated footnote 17
Added footnote 20
Added Figure 10 (SRAM WRITE CYCLE:BHE and BLE controlled)
Changed tSTORE max value from 12.5 ms to 8 ms
Updated tDELAY value
Added VHDIS, tHHHD and tLZHSB parameters
Updated footnote 24
Added footnote 26 and 27
Software controlled STORE/RECALL Table: Changed tAS to tSA
Changed tGHAX to tHA
Changed tHA value from 1 ns to 0 ns
Added Figure 13
Added tDHSB parameter
Changed tHLHX to tPHSB
Updated tSS from 70 µs to 100 µs
Added truth table for SRAM operations
Updated ordering information and part numbering nomenclature
*B
2654484
02/05/09
Changed status from Advance information to Preliminary.
Referenced Note 15 to parameters tLZCE, tHZCE, tLZOE, HZOE, LZWE
t
t
and tHZWE
Updated Figure 12
Document Number: 001-42879 Rev. *S
Page 27 of 30
CY14B101LA
CY14B101NA
Document History Page (continued)
Document Title: CY14B101LA/CY14B101NA, 1-Mbit (128 K × 8/64 K × 16) nvSRAM
Document Number: 001-42879
Submission
Rev.
ECN No.
Description of Change
Date
*C
2733909
07/09/09
Removed 48-ball FBGA package and added 54-pin TSOP II Package
Corrected typo error in pin diagram of 48-pin SSOP
Page 4; Added note to AutoStore Operation description
Page 4; Updated Hardware STORE (HSB) Operation description
Page 5; Updated Software STORE Operation description
Added best practices
Updated VHDIS parameter description
Updated tDELAY parameter description
Updated footnote 24 and added footnote 29
*D
2757348
08/28/09
Changed status from Preliminary to Final.
Removed commercial temperature related specs
Updated thermal resistance values for all the packages
*E
*F
2793420
2839453
10/27/09
01/06/10
Updated 48-pin SSOP package diagram
Changed STORE cycles to QuantumTrap from 200 K to 1 Million
Added Contents
*G
*H
2894534
2922854
03/17/10
04/26/10
Removed inactive parts from Ordering Information table.
Updated links in Sales, Solutions, and Legal Information.
Updated Package Diagrams.
Pin Definitions: Added more clarity on HSB pin operation
Hardware STORE Operation: Added more clarity on HSB pin operation
Table 1: Added more clarity on BHE/BLE pin operation
Updated HSB pin operation in Figure 11
Updated footnote 45
Updated package diagram 51-85087
*I
2958648
3074645
06/22/10
10/29/10
Added 48-Ball FBGA package related information
Updated package diagram 51-85128
Updated template and added Acronym table
*J
48 FBGA package: 16 Mb address expansion is not supported
Removed inactive parts from Ordering Information table.
CY14B101NA-ZS20XIT, CY14B101NA-ZS20XI
Added Document Conventions table
*K
*L
3134300
3313245
01/11/2011 Updated style format
Updated input capacitance for BHE and BLE pin
Updated input and output capacitance for HSB pin
Fixed typo in Figure 11
07/14/2011 Updated DC Electrical Characteristics (Added Note 21 and referred the same note in VCAP
parameter).
Updated Thermal Resistance (ΘJA and ΘJC values for 48-ball FBGA package).
Updated AC Switching Characteristics (Added Note 24 and referred the same note in
Parameters).
Updated Package Diagrams.
*M
*N
*O
3457594
3542240
3659138
12/07/2011 Updated Package Diagrams.
03/06/2012 Footnote 48 made visible. Modified Figure 13.
08/14/2012 Updated Maximum Ratings (Changed “Ambient temperature with power applied” to
“Maximum junction temperature”).
Updated DC Electrical Characteristics (Added VVCAP parameter and its details, added Note
22 and referred the same note in VVCAP parameter, also referred Note 23 in VVCAP param-
eter).
Updated Package Diagrams (spec 51-85160 (Changed revision from *C to *D)).
*P
3769328
10/08/2012 Updated Ordering Information (Added CY14B101LA-BA25XI and CY14B101LA-BA25XIT).
Updated Package Diagrams (spec 51-85087 (Changed revision from *D to *E), spec
51-85061 (Changed revision from *E to *F)).
Document Number: 001-42879 Rev. *S
Page 28 of 30
CY14B101LA
CY14B101NA
Document History Page (continued)
Document Title: CY14B101LA/CY14B101NA, 1-Mbit (128 K × 8/64 K × 16) nvSRAM
Document Number: 001-42879
Submission
Rev.
ECN No.
Description of Change
Date
*Q
4567905
11/12/2014 Added related documentation hyperlink in page 1.
Updated Package Diagrams spec 51-85160 (Changed revision from *D to *E),
05/09/2015 Updated Package Diagrams.
*R
*S
5716066
6867685
Updated Cypress Logo and Copyright.
04/24/2020 Updated spec 51-85128 *G to *I in Package Diagrams.
Document Number: 001-42879 Rev. *S
Page 29 of 30
CY14B101LA
CY14B101NA
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
®
Products
PSoC Solutions
Arm® Cortex® Microcontrollers
cypress.com/arm
cypress.com/automotive
cypress.com/clocks
cypress.com/interface
cypress.com/iot
PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP | PSoC 6 MCU
Automotive
Cypress Developer Community
Clocks & Buffers
Interface
Community | Code Examples | Projects | Video | Blogs |
Training | Components
Internet of Things
Memory
Technical Support
cypress.com/memory
cypress.com/mcu
cypress.com/support
Microcontrollers
PSoC
cypress.com/psoc
cypress.com/pmic
cypress.com/touch
cypress.com/usb
Power Management ICs
Touch Sensing
USB Controllers
Wireless Connectivity
cypress.com/wireless
© Cypress Semiconductor Corporation, 2008-2020. This document is the property of Cypress Semiconductor Corporation and its subsidiaries (“Cypress”). This document, including any software or
firmware included or referenced in this document (“Software”), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries worldwide. Cypress reserves
all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other intellectual property rights. If
the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress hereby grants you a personal,
non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to modify and reproduce the Software
solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users (either directly or indirectly through
resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as provided by Cypress, unmodified)
to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation of the Software is prohibited.
TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE
OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. No computing
device can be absolutely secure. Therefore, despite security measures implemented in Cypress hardware or software products, Cypress shall have no liability arising out of any security breach, such
as unauthorized access to or use of a Cypress product. CYPRESS DOES NOT REPRESENT, WARRANT, OR GUARANTEE THAT CYPRESS PRODUCTS, OR SYSTEMS CREATED USING
CYPRESS PRODUCTS, WILLBE FREE FROM CORRUPTION,ATTACK, VIRUSES, INTERFERENCE, HACKING, DATALOSS OR THEFT, OR OTHER SECURITY INTRUSION (collectively, “Security
Breach”). Cypress disclaims any liability relating to any Security Breach, and you shall and hereby do release Cypress from any claim, damage, or other liability arising from any Security Breach. In
addition, the products described in these materials may contain design defects or errors known as errata which may cause the product to deviate from published specifications. To the extent permitted
by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any product or
circuit described in this document.Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is the responsibility
of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. “High-Risk Device” means any
device or system whose failure could cause personal injury, death, or property damage. Examples of High-Risk Devices are weapons, nuclear installations, surgical implants, and other medical devices.
“Critical Component” means any component of a High-Risk Device whose failure to perform can be reasonably expected to cause, directly or indirectly, the failure of the High-Risk Device, or to affect
its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim, damage, or other liability arising from any use of a Cypress product
as a Critical Component in a High-Risk Device. You shall indemnify and hold Cypress, its directors, officers, employees, agents, affiliates, distributors, and assigns harmless from and against all claims,
costs, damages, and expenses, arising out of any claim, including claims for product liability, personal injury or death, or property damage arising from any use of a Cypress product as a Critical
Component in a High-Risk Device. Cypress products are not intended or authorized for use as a Critical Component in any High-Risk Device except to the limited extent that (i) Cypress's published
data sheet for the product explicitly states Cypress has qualified the product for use in a specific High-Risk Device, or (ii) Cypress has given you advance written authorization to use the product as a
Critical Component in the specific High-Risk Device and you have signed a separate indemnification agreement.
Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in
the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
Document Number: 001-42879 Rev. *S
Revised April 24, 2020
Page 30 of 30
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