CY14B104NA-ZSP25XI [INFINEON]
nvSRAM (non-volatile SRAM);
| 型号： | CY14B104NA-ZSP25XI |
| 厂家： | 
Infineon |
| 描述： | nvSRAM (non-volatile SRAM) 静态存储器 光电二极管 内存集成电路 |
| 文件： | 总28页 (文件大小：910K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY14B104LA
CY14B104NA
4-Mbit (512K × 8/256K × 16) nvSRAM
4-Mbit (512K
× 8/256K × 16) nvSRAM
■ Packages
Features
❐ 44-/54-pin thin small outline package (TSOP) Type II
❐ 48-ball fine-pitch ball grid array (FBGA)
■ 20 ns, 25 ns, and 45 ns access times
■ Internally organized as 512K × 8 (CY14B104LA) or 256K × 16
(CY14B104NA)
■ Pb-free and restriction of hazardous substances (RoHS)
compliant
■ Hands off automatic STORE on power-down with only a small
capacitor
Functional Description
The Cypress CY14B104LA/CY14B104NA is a fast static RAM
(SRAM), with a non-volatile element in each memory cell. The
memory is organized as 512K bytes of 8 bits each or 256K words
of 16-bits each. The embedded non-volatile elements incor-
porate QuantumTrap technology, producing the world’s most
reliable non-volatile memory. The SRAM provides infinite read
and write cycles, while independent non-volatile data resides in
the highly reliable QuantumTrap cell. Data transfers from the
SRAM to the non-volatile elements (the STORE operation) takes
place automatically at power-down. On power-up, data is
restored to the SRAM (the RECALL operation) from the
non-volatile memory. Both the STORE and RECALL operations
are also available under software control.
■ STORE to QuantumTrap non-volatile elements initiated by
software, device pin, or AutoStore on power-down
■ RECALL to SRAM initiated by software or power-up
■ Infinite read, write, and recall cycles
■ 1 million STORE cycles to QuantumTrap
■ 20 year data retention
■ Single 3 V +20, –10 operation
■ Industrial temperature
For a complete list of related documentation, click here.
Logic Block Diagram [1, 2, 3]
VCC
VCAP
Quatrum Trap
2048 X 2048
A0
A1
A2
A3
A4
A5
A6
POWER
R
O
W
CONTROL
STORE
RECALL
STORE/RECALL
CONTROL
D
E
C
O
D
E
R
HSB
STATIC RAM
ARRAY
2048 X 2048
A7
A8
A17
SOFTWARE
DETECT
A14 - A2
A18
DQ0
DQ1
DQ2
DQ3
I
DQ4
DQ5
DQ6
N
P
U
T
B
U
F
F
E
R
S
DQ7
COLUMN I/O
DQ8
DQ9
DQ10
OE
COLUMN DEC
WE
DQ11
DQ12
DQ13
DQ14
CE
BLE
A11
A9 A10
A12 A13 A14 A15 A16
DQ15
BHE
Notes
1. Address A –A for × 8 configuration and Address A –A for × 16 configuration.
0
18
0
17
2. Data DQ –DQ for × 8 configuration and Data DQ –DQ for × 16 configuration.
0
7
0
15
3. BHE and BLE are applicable for × 16 configuration only.
Cypress Semiconductor Corporation
Document Number: 001-49918 Rev. *O
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised May 12, 2017
CY14B104LA
CY14B104NA
Contents
Pinouts ..............................................................................3
Pin Definitions ..................................................................5
Device Operation ..............................................................6
SRAM Read ................................................................6
SRAM Write .................................................................6
AutoStore Operation ....................................................6
Hardware STORE Operation .......................................6
Hardware RECALL (Power-Up) ..................................7
Software STORE .........................................................7
Software RECALL .......................................................7
Preventing AutoStore ..................................................8
Data Protection ............................................................8
Maximum Ratings .............................................................9
Operating Range ...............................................................9
DC Electrical Characteristics ..........................................9
Data Retention and Endurance .....................................10
Capacitance ....................................................................10
Thermal Resistance ........................................................10
AC Test Loads ................................................................11
AC Test Conditions ........................................................11
AC Switching Characteristics .......................................12
Switching Waveforms ....................................................13
AutoStore/Power-Up RECALL .......................................16
Switching Waveforms
– AutoStore/Power-up RECALL ....................................16
Software Controlled STORE/RECALL Cycle ................17
Switching Waveforms
– Software Controlled STORE/RECALL Cycle .............17
Hardware STORE Cycle .................................................18
Switching Waveforms – Hardware STORE Cycle ........18
Truth Table For SRAM Operations ................................19
Ordering Information ......................................................20
Ordering Code Definitions .........................................21
Package Diagrams ..........................................................22
Acronyms ........................................................................25
Document Conventions .................................................25
Units of Measure .......................................................25
Document History Page .................................................26
Sales, Solutions, and Legal Information ......................28
Worldwide Sales and Design Support .......................28
Products ....................................................................28
PSoC® Solutions ......................................................28
Cypress Developer Community .................................28
Technical Support .....................................................28
Document Number: 001-49918 Rev. *O
Page 2 of 28
CY14B104LA
CY14B104NA
Pinouts
Figure 1. 48-ball FBGA pinouts
48-ball FBGA
(× 8)
Top View
(not to scale)
48-ball FBGA
(× 16)
Top View
(not to scale)
1
2
4
3
5
6
1
2
OE
NC
NC
4
3
5
6
A
A
A
2
NC
OE
BLE
DQ8
A
A
A
0
1
A
NC
NC
NC
0
1
2
A
B
A
A
4
BHE
DQ10
CE DQ0
DQ1 DQ2
V
B
C
A
A
3
CE NC
NC DQ4
V
3
4
A
A
6
DQ9
C
A
A
6
DQ0
V
5
5
A
V
A17
A
DQ3
DQ4
DQ5
D
E
F
DQ11
DQ12
DQ13
CC
SS
7
A17
DQ5
DQ6
NC
CC
D
E
F
SS DQ1
7
A
V
V
SS
A
VCAP
V
V
SS
CC
16
VCAP
CC DQ2
16
A
A
15
DQ14
DQ15
DQ6
A
A
15
NC
DQ3
NC
DQ7
14
14
A
A
13
G
H
A
A
HSB
WE DQ7
G
H
HSB
WE NC
[4]
12
13
12
[4]
A
A
9
A
A
A
8
A
9
A
NC
A18
A
8
NC
11
10
10
11
NC
Figure 2. 44-pin TSOP II pinouts
[6]
(× 8)
(× 16)
A
A
1
NC
NC
1
2
1
2
HSB
0
A
17
44
44
43
42
41
[5]
NC
NC
43
42
41
A
16
[4]
A
A
3
4
5
6
7
8
3
4
5
6
7
8
0
2
A
15
A
1
A
3
A
18
OE
A
2
A
4
A
17
BHE
40
39
40
39
A
3
CE
A
16
BLE
DQ
DQ
A
4
38
37
36
35
34
38
37
36
35
34
A
15
0
1
2
3
15
CE
DQ
OE
DQ
DQ
DQ
DQ
14
13
DQ
44-pin TSOP II
9
10
44-pin TSOP II
DQ
DQ
V
9
10
0
1
7
(× 16)
(× 8)
DQ
V
DQ
6
12
11
12
13
14
11
12
13
14
CC
V
CC
V
SS
SS
Top View
(not to scale)
Top View
(not to scale)
V
V
V
SS
33
32
31
V
SS
CC
33
32
31
CC
DQ
DQ
DQ
DQ
DQ
2
3
5
4
5
11
DQ
DQ
DQ
DQ
V
DQ
4
10
WE
A
5
15
16
17
18
15
16
17
18
30
29
28
27
26
25
24
23
6
7
30
29
28
27
26
25
24
23
DQ
DQ
CAP
9
8
A
14
A
6
A
WE
13
12
V
CAP
A
7
A
A
5
A
14
A
A
6
19
20
21
22
8
A
19
20
21
22
A
11
13
A
9
A
A
7
10
A
12
NC
NC
A
NC
NC
8
A
11
A
9
A
10
Notes
4. Address expansion for 8-Mbit. NC pin not connected to die.
5. Address expansion for 16-Mbit. NC pin not connected to die.
6. HSB pin is not available in 44-pin TSOP II (× 16) package.
Document Number: 001-49918 Rev. *O
Page 3 of 28
CY14B104LA
CY14B104NA
Pinouts (continued)
Figure 3. Pin Diagram – 54-pin TSOP II pinout
NC
54
53
52
51
50
49
HSB
NC
1
2
3
[7]
[8]
NC
A
0
A
17
A
1
A
16
4
5
A
2
A
15
A
3
OE
6
48
47
46
45
A
4
BHE
BLE
DQ
7
8
9
10
11
12
13
14
CE
DQ
DQ
0
1
15
DQ
DQ
DQ
V
14
13
12
54-pin TSOP II
DQ
DQ
44
43
42
41
40
39
2
3
(× 16)
V
CC
SS
Top View
V
SS
V
CC
(not to scale)
DQ
DQ
4
15
16
17
18
19
20
21
22
23
24
11
DQ
DQ
DQ
5
10
38
37
36
35
DQ
DQ
6
7
9
8
DQ
V
WE
A
5
CAP
A
14
34
33
32
31
30
29
28
A
6
A
13
A
A
7
A
8
12
A
11
A
A
9
10
NC
NC
NC
NC
NC
NC
25
26
27
Notes
7. Address expansion for 16-Mbit. NC pin not connected to die.
8. Address expansion for 8-Mbit. NC pin not connected to die.
Document Number: 001-49918 Rev. *O
Page 4 of 28
CY14B104LA
CY14B104NA
Pin Definitions
Pin Name
A0–A18
I/O Type
Input
Description
Address inputs. Used to select one of the 524,288 bytes of the nvSRAM for × 8 Configuration.
Address inputs. Used to Select one of the 262,144 words of the nvSRAM for × 16 Configuration.
A0–A17
DQ0–DQ7 Input/Output Bidirectional data I/O lines for × 8 configuration. Used as input or output lines depending on operation.
DQ0–DQ15
Bidirectional data I/O lines for × 16 configuration. Used as input or output lines depending on
operation.
WE
Input
Write Enable input, Active LOW. When selected LOW, data on the I/O pins is written to the specific
address location.
Input
Input
Chip Enable input, Active LOW. When LOW, selects the chip. When HIGH, deselects the chip.
CE
OE
Output Enable, Active LOW. The active LOW OE input enables the data output buffers during read
cycles. I/O pins are tristated on deasserting OE HIGH.
Input
Input
Byte High Enable, Active LOW. Controls DQ15–DQ8.
BHE
Byte Low Enable, Active LOW. Controls DQ7–DQ0.
BLE
VSS
Ground
Ground for the device. Must be connected to the ground of the system.
VCC
Power supply Power supply inputs to the device.
HSB[9]
Input/Output Hardware STORE Busy (HSB). When LOW this output indicates that a Hardware STORE is in progress.
When pulled LOW external to the chip it initiates a non-volatile STORE operation. After each Hardware
and Software STORE operation, HSB is driven HIGH for a short time (tHHHD) with standard output high
current, and then a weak internal pull-up resistor keeps this pin HIGH (external pull-up resistor connection
optional).
VCAP
NC
Power supply AutoStore Capacitor. Supplies power to the nvSRAM during power loss to store data from SRAM to
non-volatile elements.
No connect No Connect. This pin is not connected to the die.
Note
9. HSB pin is not available in 44-pin TSOP II (× 16) package.
Document Number: 001-49918 Rev. *O
Page 5 of 28
CY14B104LA
CY14B104NA
automatically disconnects the VCAP pin from VCC. A STORE
operation is initiated with power provided by the VCAP capacitor.
Device Operation
The CY14B104LA/CY14B104NA nvSRAM is made up of two
functional components paired in the same physical cell. They are
a SRAM memory cell and a non-volatile QuantumTrap cell. The
SRAM memory cell operates as a standard fast static RAM. Data
in the SRAM is transferred to the non-volatile cell (the STORE
operation), or from the non-volatile cell to the SRAM (the
RECALL operation). Using this unique architecture, all cells are
stored and recalled in parallel. During the STORE and RECALL
operations, SRAM read and write operations are inhibited. The
CY14B104LA/CY14B104NA supports infinite reads and writes
similar to a typical SRAM. In addition, it provides infinite RECALL
operations from the non-volatile cells and up to 1 million STORE
operations. Refer to the Truth Table For SRAM Operations on
page 19 for a complete description of read and write modes.
Note If the capacitor is not connected to VCAP pin, AutoStore
must be disabled using the soft sequence specified in Preventing
AutoStore on page 8. In case AutoStore is enabled without a
capacitor on VCAP pin, the device attempts an AutoStore
operation without sufficient charge to complete the Store. This
corrupts the data stored in nvSRAM.
Figure 4 shows the proper connection of the storage capacitor
(VCAP) for automatic store operation. Refer to DC Electrical
Characteristics on page 9 for the size of VCAP. The voltage on
the VCAP pin is driven to VCC by a regulator on the chip. A pull-up
should be placed on WE to hold it inactive during power-up. This
pull-up is effective only if the WE signal is tristate during
power-up. Many MPUs tristate their controls on power-up. This
should be verified when using the pull-up. When the nvSRAM
comes out of power-on-RECALL, the MPU must be active or the
WE held inactive until the MPU comes out of reset.
SRAM Read
The CY14B104LA/CY14B104NA performs a read cycle when
CE and OE are LOW and WE and HSB are HIGH. The address
specified on pins A0–18 or A0–17 determines which of the 524,288
data bytes or 262,144 words of 16 bits each are accessed. Byte
enables (BHE, BLE) determine which bytes are enabled to the
output, in the case of 16-bit words. When the read is initiated by
an address transition, the outputs are valid after a delay of tAA
(read cycle 1). If the read is initiated by CE or OE, the outputs
are valid at tACE or at tDOE, whichever is later (read cycle 2). The
data output repeatedly responds to address changes within the
tAA access time without the need for transitions on any control
input pins. This remains valid until another address change or
until CE or OE is brought HIGH, or WE or HSB is brought LOW.
To reduce unnecessary non-volatile stores, AutoStore and
hardware STORE operations are ignored unless at least one
write operation has taken place since the most recent STORE or
RECALL cycle. Software initiated STORE cycles are performed
regardless of whether a write operation has taken place. The
HSB signal is monitored by the system to detect if an AutoStore
cycle is in progress.
Figure 4. AutoStore Mode
VCC
0.1 uF
SRAM Write
VCC
A write cycle is performed when CE and WE are LOW and HSB
is HIGH. The address inputs must be stable before entering the
write cycle and must remain stable until CE or WE goes HIGH at
the end of the cycle. The data on the common I/O pins DQ0–15
are written into the memory if the data is valid (tSD time) before
the end of a WE controlled write or before the end of an CE
controlled write. The Byte Enable inputs (BHE, BLE) determine
which bytes are written, in the case of 16-bit words. It is recom-
mended that OE be kept HIGH during the entire write cycle to
avoid data bus contention on common I/O lines. If OE is left LOW,
internal circuitry turns off the output buffers tHZWE after WE goes
LOW.
WE
VCAP
VCAP
VSS
Hardware STORE Operation
The CY14B104LA/CY14B104NA provides the HSB[10] pin to
control and acknowledge the STORE operations. The HSB pin
is used to request a hardware STORE cycle. When the HSB pin
is driven LOW, the CY14B104LA/CY14B104NA conditionally
initiates a STORE operation after tDELAY. An actual STORE cycle
only begins if a write to the SRAM has taken place since the last
STORE or RECALL cycle. The HSB pin also acts as an open
drain driver (internal 100 k weak pull-up resistor) that is inter-
nally driven LOW to indicate a busy condition when the STORE
(initiated by any means) is in progress.
AutoStore Operation
The CY14B104LA/CY14B104NA stores data to the nvSRAM
using one of the following three storage operations: Hardware
STORE activated by the HSB; Software STORE activated by an
address sequence; AutoStore on device power-down. The
AutoStore operation is a unique feature of QuantumTrap
technology
and
is
enabled
by
default
on
the
CY14B104LA/CY14B104NA.
During a normal operation, the device draws current from VCC to
charge a capacitor connected to the VCAP pin. This stored
charge is used by the chip to perform a single STORE operation.
If the voltage on the VCC pin drops below VSWITCH, the part
Note After each Hardware and Software STORE operation HSB
is driven HIGH for a short time (tHHHD) with standard output high
current and then remains HIGH by internal 100 k pull-up
resistor.
Note
10. HSB pin is not available in 44-pin TSOP II (× 16) package.
Document Number: 001-49918 Rev. *O
Page 6 of 28
CY14B104LA
CY14B104NA
SRAM write operations that are in progress when HSB is driven
LOW by any means are given time (tDELAY) to complete before
the STORE operation is initiated. However, any SRAM write
cycles requested after HSB goes LOW are inhibited until HSB
returns HIGH. In case the write latch is not set, HSB is not driven
LOW by the CY14B104LA/CY14B104NA. But any SRAM read
and write cycles are inhibited until HSB is returned HIGH by MPU
or other external source.
1. Read address 0x4E38 Valid READ
2. Read address 0xB1C7 Valid READ
3. Read address 0x83E0 Valid READ
4. Read address 0x7C1F Valid READ
5. Read address 0x703F Valid READ
6. Read address 0x8FC0 Initiate STORE cycle
The software sequence may be clocked with CE controlled reads
or OE controlled reads, with WE kept HIGH for all the six READ
sequences. After the sixth address in the sequence is entered,
the STORE cycle commences and the chip is disabled. HSB is
driven LOW. After the tSTORE cycle time is fulfilled, the SRAM is
activated again for the read and write operation.
During any STORE operation, regardless of how it is initiated,
the CY14B104LA/CY14B104NA continues to drive the HSB pin
LOW, releasing it only when the STORE is complete. Upon
completion of the STORE operation, the nvSRAM memory
access is inhibited for tLZHSB time after HSB pin returns HIGH.
Leave the HSB unconnected if it is not used.
Software RECALL
Hardware RECALL (Power-Up)
Data is transferred from the non-volatile memory to the SRAM
by a software address sequence. A software RECALL cycle is
initiated with a sequence of read operations in a manner similar
to the software STORE initiation. To initiate the RECALL cycle,
perform the following sequence of CE or OE controlled read
operations must be performed.
During power-up or after any low power condition
(VCC< VSWITCH), an internal RECALL request is latched. When
VCC again exceeds the VSWITCH on power up, a RECALL cycle
is automatically initiated and takes tHRECALL to complete. During
this time, the HSB pin is driven LOW by the HSB driver and all
reads and writes to nvSRAM are inhibited.
1. Read address 0x4E38 Valid READ
2. Read address 0xB1C7 Valid READ
3. Read address 0x83E0 Valid READ
4. Read address 0x7C1F Valid READ
5. Read address 0x703F Valid READ
6. Read address 0x4C63 Initiate RECALL cycle
Software STORE
Data is transferred from the SRAM to the non-volatile memory
by
a
software
address
sequence.
The
CY14B104LA/CY14B104NA software STORE cycle is initiated
by executing sequential CE or OE controlled read cycles from six
specific address locations in exact order. During the STORE
cycle an erase of the previous non-volatile data is first performed,
followed by a program of the non-volatile elements. After a
STORE cycle is initiated, further input and output are disabled
until the cycle is completed.
Internally, RECALL is a two step procedure. First, the SRAM data
is cleared; then, the non-volatile information is transferred into
the SRAM cells. After the tRECALL cycle time, the SRAM is again
ready for read and write operations. The RECALL operation
does not alter the data in the non-volatile elements.
Because a sequence of reads from specific addresses is used
for STORE initiation, it is important that no other read or write
accesses intervene in the sequence, or the sequence is aborted
and no STORE or RECALL takes place.
To initiate the software STORE cycle, the following read
sequence must be performed.
Table 1. Mode Selection
[12]
A15–A0
Mode
I/O
Power
Standby
Active
CE
WE
OE
BHE, BLE[11]
H
X
X
X
X
X
X
Not selected
Read SRAM
Write SRAM
Output high Z
Output data
Input data
L
L
L
H
L
L
X
L
L
L
X
Active
Active[13]
H
0x4E38
0xB1C7
0x83E0
0x7C1F
0x703F
0x8B45
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
AutoStore
Output data
Output data
Output data
Output data
Output data
Output data
Disable
Notes
11. BHE and BLE are applicable for × 16 configuration only.
12. While there are 19 address lines on the CY14B104LA (18 address lines on the CY14B104NA), only 13 address lines (A –A ) are used to control software modes.
14
2
The remaining address lines are don’t care.
13. The six consecutive address locations must be in the order listed. WE must be HIGH during all six cycles to enable a non-volatile cycle.
Document Number: 001-49918 Rev. *O
Page 7 of 28
CY14B104LA
CY14B104NA
Table 1. Mode Selection (continued)
[12]
BHE, BLE[11]
A15–A0
Mode
I/O
Power
CE
WE
OE
L
H
L
X
0x4E38
0xB1C7
0x83E0
0x7C1F
0x703F
0x4B46
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
AutoStore
Output data
Output data
Output data
Output data
Output data
Output data
Active[14]
Enable
[14]
L
L
H
H
L
L
X
X
0x4E38
0xB1C7
0x83E0
0x7C1F
0x703F
0x8FC0
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Non-volatile
STORE
Output data
Output data
Output data
Output data
Output data
Output high Z
Active ICC2
0x4E38
0xB1C7
0x83E0
0x7C1F
0x703F
0x4C63
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Non-volatile
RECALL
Output data
Output data
Output data
Output data
Output data
Output high Z
Active[14]
AutoStore enable sequence, the following sequence of CE or OE
controlled read operations must be performed:
Preventing AutoStore
The AutoStore function is disabled by initiating an AutoStore
disable sequence. A sequence of read operations is performed
in a manner similar to the software STORE initiation. To initiate
the AutoStore disable sequence, the following sequence of CE
or OE controlled read operations must be performed:
1. Read address 0x4E38 Valid READ
2. Read address 0xB1C7 Valid READ
3. Read address 0x83E0 Valid READ
4. Read address 0x7C1F Valid READ
5. Read address 0x703F Valid READ
6. Read address 0x4B46 AutoStore Enable
1. Read address 0x4E38 Valid READ
2. Read address 0xB1C7 Valid READ
3. Read address 0x83E0 Valid READ
4. Read address 0x7C1F Valid READ
5. Read address 0x703F Valid READ
6. Read address 0x8B45 AutoStore Disable
If the AutoStore function is disabled or re-enabled, a manual
STORE operation (hardware or software) must be issued to save
the AutoStore state through subsequent power-down cycles.
The part comes from the factory with AutoStore enabled and
0x00 written in all cells.
The AutoStore is re-enabled by initiating an AutoStore enable
sequence. A sequence of read operations is performed in a
manner similar to the software RECALL initiation. To initiate the
Data Protection
The CY14B104LA/CY14B104NA protects data from corruption
during low voltage conditions by inhibiting all externally initiated
STORE and write operations. The low voltage condition is
detected
when
VCC
<
VSWITCH
.
If
the
CY14B104LA/CY14B104NA is in a write mode (both CE and WE
are LOW) at power-up, after a RECALL or STORE, the write is
inhibited until the SRAM is enabled after tLZHSB (HSB to output
active). This protects against inadvertent writes during power-up
or brown out conditions.
Note
14. The six consecutive address locations must be in the order listed. WE must be HIGH during all six cycles to enable a non-volatile cycle.
Document Number: 001-49918 Rev. *O
Page 8 of 28
CY14B104LA
CY14B104NA
Transient voltage (< 20 ns)
on any pin to ground potential ............ –2.0 V to VCC + 2.0 V
Maximum Ratings
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Package power
dissipation capability (TA = 25 °C) ............................... 1.0 W
Storage temperature ................................ –65 C to +150 C
Maximum accumulated storage time
Surface mount Pb
soldering temperature (3 Seconds) ......................... +260 C
DC output current (1 output at a time, 1s duration) .... 15 mA
At 150 C ambient temperature ...................... 1000 h
At 85 C ambient temperature ..................... 20 Years
Maximum junction temperature ................................. 150 C
Supply voltage on VCC relative to VSS ...........–0.5 V to 4.1 V
Static discharge voltage
(per MIL-STD-883, Method 3015) ..........................> 2001 V
Latch-up current ....................................................> 200 mA
Voltage applied to outputs
in high Z state .....................................–0.5 V to VCC + 0.5 V
Operating Range
Range
Industrial
Ambient Temperature
VCC
Input voltage ........................................–0.5 V to Vcc + 0.5 V
–40 C to +85 C
2.7 V to 3.6 V
DC Electrical Characteristics
Over the Operating Range
Parameter
VCC
Description
Power supply
Test Conditions
Min
2.7
–
Typ [15]
Max
Unit
3.0
–
3.6
V
ICC1
Average VCC current
tRC = 20 ns
RC = 25 ns
RC = 45 ns
70
70
52
mA
mA
mA
t
t
Values obtained without output loads
(IOUT = 0 mA)
ICC2
ICC3
Average VCC current during
STORE
All inputs don’t care, VCC = Max
Average current for duration tSTORE
–
–
–
10
–
mA
mA
Average VCC current at
tRC= 200 ns, VCC(Typ), 25 °C
All inputs cycling at CMOS levels.
Values obtained without output loads
(IOUT = 0 mA).
35
ICC4
ISB
Average VCAP current during
AutoStore cycle
All inputs don’t care. Average current for
duration tSTORE
–
–
–
–
5
5
mA
mA
VCC standby current
CE > (VCC – 0.2 V).
VIN < 0.2 V or > (VCC – 0.2 V).
Standby current level after non-volatile
cycle is complete.
Inputs are static. f = 0 MHz.
[16]
IIX
Input leakage current (except
HSB)
VCC = Max, VSS < VIN < VCC
–1
–
+1
A
Input leakage current (for HSB) VCC = Max, VSS < VIN < VCC
–100
–1
–
–
+1
+1
A
A
IOZ
Off-state output leakage current VCC = Max, VSS < VOUT < VCC
CE or OE > VIH or
,
BHE/BLE > VIH or WE < VIL
VIH
VIL
Input HIGH voltage
Input LOW voltage
2.0
Vss – 0.5
2.4
–
–
–
–
VCC + 0.5
V
V
V
V
0.8
–
VOH
VOL
Output HIGH voltage
Output LOW voltage
IOUT = –2 mA
IOUT = 4 mA
–
0.4
Notes
15. Typical values are at 25 °C, V = V
. Not 100% tested.
CC
CC(Typ)
16. The HSB pin has I
= –2 µA for V of 2.4 V when both active HIGH and LOW drivers are disabled. When they are enabled standard V and V are valid. This
OUT
O
H
O
H
O
L
parameter is characterized but not tested.
Document Number: 001-49918 Rev. *O
Page 9 of 28
CY14B104LA
CY14B104NA
DC Electrical Characteristics (continued)
Over the Operating Range
Parameter
Description
Storage capacitor
Test Conditions
Min
61
–
Typ [15]
Max
180
VCC
Unit
F
V
[17]
VCAP
Between VCAP pin and VSS
68
–
[18, 19]
VVCAP
Maximum voltage driven on VCAP VCC = Max
pin by the device
Data Retention and Endurance
Over the Operating Range
Parameter
Description
Min
Unit
Years
K
DATAR
NVC
Data retention
20
Non-volatile STORE operations
1,000
Capacitance
Parameter[19]
Description
Test Conditions
Max
Unit
CIN
Input capacitance (except BHE, TA = 25 C, f = 1 MHz, VCC = VCC(Typ)
BLE and HSB)
7
pF
Input capacitance (for BHE, BLE
and HSB)
8
pF
COUT
Output capacitance (except HSB)
Output capacitance (for HSB)
7
8
pF
pF
Thermal Resistance
Parameter[19]
Description
Test Conditions
48-pin FBGA 44-pin TSOP II 54-pin TSOP II Unit
JA
Thermal resistance
(junction to ambient)
Test conditions follow
standard test methods
and procedures for
46.09
43.3
42.03
C/W
JC
Thermal resistance
(junction to case)
7.84
5.56
6.08
C/W
measuring
thermal
in
impedance,
accordance
EIA/JESD51.
with
Notes
17. Min V
value guarantees that there is a sufficient charge available to complete a successful AutoStore operation. Max V
value guarantees that the capacitor on
CAP
CAP
V
is charged to a minimum voltage during a Power-Up RECALL cycle so that an immediate power-down cycle can complete a successful AutoStore. Therefore it
CAP
is always recommended to use a capacitor within the specified min and max limits. Refer application note AN43593 for more details on V
options.
CAP
18. Maximum voltage on V
pin (V
) is provided for guidance when choosing the V
capacitor. The voltage rating of the V capacitor across the operating
CAP
VCAP
CAP
CAP
temperature range should be higher than the V
voltage.
VCAP
19. These parameters are guaranteed by design and are not tested.
Document Number: 001-49918 Rev. *O
Page 10 of 28
CY14B104LA
CY14B104NA
AC Test Loads
Figure 5. AC Test Loads
577
for tristate specs
577
3.0 V
OUTPUT
3.0 V
R1
R1
OUTPUT
R2
789
R2
789
5 pF
30 pF
AC Test Conditions
Input pulse levels ..................................................0 V to 3 V
Input rise and fall times (10%–90%) ........................... < 3 ns
Input and output timing reference levels ...................... 1.5 V
Document Number: 001-49918 Rev. *O
Page 11 of 28
CY14B104LA
CY14B104NA
AC Switching Characteristics
Over the Operating Range
Parameters [20]
20 ns
25 ns
45 ns
Unit
Description
Cypress
Alt Parameter
Parameter
Min
Max
Min
Max
Min
Max
SRAM Read Cycle
tACE
tACS
tRC
tAA
tOE
tOH
tLZ
tHZ
tOLZ
tOHZ
tPA
tPS
–
Chip enable access time
–
20
–
20
–
–
25
–
25
–
–
45
–
45
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
[21]
tRC
Read cycle time
[22]
tAA
Address access time
20
10
–
25
12
–
45
20
–
tDOE
Output enable to data valid
Output hold after address change
Chip enable to output active
Chip disable to output inactive
Output enable to output active
Output disable to output inactive
Chip enable to power active
Chip disable to power standby
Byte enable to data valid
–
–
–
[22]
tOHA
3
3
3
[23, 24]
tLZCE
tHZCE
tLZOE
3
–
3
–
3
–
[23, 24]
[23, 24]
[23, 24]
–
8
–
10
–
–
15
–
0
–
0
0
tHZOE
–
8
–
10
–
–
15
–
[23]
tPU
0
–
0
0
[23]
tPD
–
20
10
–
–
25
12
–
–
45
20
–
tDBE
–
–
–
[23]
tLZBE
–
Byte enable to output active
Byte disable to output inactive
0
0
0
[23]
tHZBE
–
–
8
–
10
–
15
SRAM Write Cycle
tWC
tPWE
tSCE
tSD
tWC
tWP
tCW
tDW
tDH
tAW
tAS
tWR
tWZ
tOW
–
Write cycle time
20
15
15
8
–
–
–
–
–
–
–
–
8
–
–
25
20
20
10
0
–
–
45
30
30
15
0
–
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Write pulse width
Chip enable to end of write
Data setup to end of write
Data hold after end of write
Address setup to end of write
Address setup to start of write
Address hold after end of write
Write enable to output disable
Output active after end of write
Byte enable to end of write
–
–
–
–
tHD
0
–
–
tAW
15
0
20
0
–
30
0
–
tSA
–
–
tHA
0
0
–
0
–
[23, 24, 25]
tHZWE
–
–
10
–
–
15
–
[23, 24]
tLZWE
tBW
3
3
3
15
20
–
30
–
Notes
20. Test conditions assume signal transition time of 3 ns or less, timing reference levels of V /2, input pulse levels of 0 to V
, and output loading of the specified
CC
CC(typ)
I
/I and load capacitance shown in Figure 5 on page 11.
OL OH
21. WE must be HIGH during SRAM read cycles.
22. Device is continuously selected with CE, OE and BHE / BLE LOW.
23. These parameters are guaranteed by design but not tested.
24. Measured ±200 mV from steady state output voltage.
25. If WE is LOW when CE goes LOW, the outputs remain in the high impedance state.
Document Number: 001-49918 Rev. *O
Page 12 of 28
CY14B104LA
CY14B104NA
Switching Waveforms
Figure 6. SRAM Read Cycle No. 1 (Address Controlled) [26, 27, 28]
tRC
Address
Address Valid
tAA
Output Data Valid
Previous Data Valid
tOHA
Data Output
Figure 7. SRAM Read Cycle No. 2 (CE and OE Controlled) [26, 28, 29]
Address
CE
Address Valid
tRC
tHZCE
tACE
tAA
tLZCE
tHZOE
tDOE
OE
tHZBE
tLZOE
tDBE
BHE, BLE
tLZBE
High Impedance
Data Output
Output Data Valid
tPU
tPD
Active
ICC
Standby
Notes
26. WE must be HIGH during SRAM read cycles.
27. Device is continuously selected with CE, OE and BHE/BLE LOW.
28. HSB must remain HIGH during read and write cycles.
29. BHE and BLE are applicable for × 16 configuration only.
Document Number: 001-49918 Rev. *O
Page 13 of 28
CY14B104LA
CY14B104NA
Switching Waveforms (continued)
Figure 8. SRAM Write Cycle No. 1 (WE Controlled) [30, 31, 32, 33]
tWC
Address
Address Valid
tSCE
tHA
CE
tBW
BHE, BLE
tAW
tPWE
WE
Data Input
Data Output
tSA
tHD
tSD
Input Data Valid
tLZWE
tHZWE
High Impedance
Previous Data
Notes
30. BHE and BLE are applicable for × 16 configuration only.
31. HSB must remain HIGH during read and write cycles.
32. If WE is LOW when CE goes LOW, the outputs remain in the high impedance state.
33. CE or WE must be >V during address transitions.
IH
Document Number: 001-49918 Rev. *O
Page 14 of 28
CY14B104LA
CY14B104NA
Switching Waveforms (continued)
Figure 9. SRAM Write Cycle No. 2 (CE Controlled) [34, 35, 36, 37]
tWC
Address Valid
tSCE
Address
tSA
tHA
CE
tBW
tPWE
tSD
BHE, BLE
WE
tHD
Input Data Valid
High Impedance
Data Input
Data Output
Figure 10. SRAM Write Cycle No. 3 (BHE and BLE Controlled) [34, 35, 36, 37]
tWC
Address
CE
Address Valid
tSCE
tSA
tHA
tBW
BHE, BLE
WE
tAW
tPWE
tSD
tHD
Data Input
Input Data Valid
High Impedance
Data Output
Notes
34. BHE and BLE are applicable for × 16 configuration only.
35. If WE is LOW when CE goes LOW, the outputs remain in the high impedance state.
36. HSB must remain HIGH during read and write cycles.
37. CE or WE must be >V during address transitions.
IH
Document Number: 001-49918 Rev. *O
Page 15 of 28
CY14B104LA
CY14B104NA
AutoStore/Power-Up RECALL
Over the Operating Range
20 ns
25 ns
45 ns
Unit
Parameter
Description
Min
–
Max
20
8
Min
–
Max
20
8
Min
–
Max
[38]
tHRECALL
Power-Up RECALL duration
STORE cycle duration
20
8
ms
ms
ns
[39]
tSTORE
–
–
–
[40]
tDELAY
Time allowed to complete SRAM
write cycle
–
20
–
25
–
25
VSWITCH
Low voltage trigger level
VCC rise time
–
150
–
2.65
–
–
150
–
2.65
–
–
150
–
2.65
–
V
s
V
[41]
tVCCRISE
[41]
VHDIS
HSB output disable voltage
HSB to output active time
HSB high active time
1.9
5
1.9
5
1.9
5
[41]
tLZHSB
–
–
–
s
ns
[41]
tHHHD
–
500
–
500
–
500
Switching Waveforms – AutoStore/Power-up RECALL
Figure 11. AutoStore or Power-Up RECALL [42]
VCC
VSWITCH
VHDIS
39
39
tVCCRISE
tSTORE
tSTORE
43
Note
Note
tHHHD
tHHHD
43
Note
Note
HSB OUT
AutoStore
tDELAY
tLZHSB
tLZHSB
tDELAY
POWER-
UP
RECALL
tHRECALL
tHRECALL
Read & Write
Inhibited
(RWI)
Read & Write
Read & Write
POWER-UP
RECALL
BROWN
OUT
AutoStore
POWER
DOWN
AutoStore
POWER-UP
RECALL
Notes
38. t
starts from the time V rises above V .
SWITCH
HRECALL
CC
39. If an SRAM write has not taken place since the last non-volatile cycle, no AutoStore or Hardware STORE takes place.
40. On a Hardware STORE and AutoStore initiation, SRAM write operation continues to be enabled for time t
41. These parameters are guaranteed by design but not tested.
.
DELAY
42. Read and write cycles are ignored during STORE, RECALL, and while V is below V
.
CC
SWITCH
43. During power-up and power-down, HSB glitches when HSB pin is pulled up through an external resistor.
Document Number: 001-49918 Rev. *O
Page 16 of 28
CY14B104LA
CY14B104NA
Software Controlled STORE/RECALL Cycle
Over the Operating Range
20 ns
25 ns
45 ns
Unit
Parameter [44, 45]
Description
Min
20
0
Max
–
Min
25
0
Max
–
Min
Max
–
tRC
STORE/RECALL initiation cycle time
Address setup time
45
0
ns
ns
ns
ns
s
tSA
–
–
–
tCW
Clock pulse width
15
0
–
20
0
–
30
0
–
tHA
Address hold time
–
–
–
tRECALL
RECALL duration
–
200
–
200
–
200
Switching Waveforms – Software Controlled STORE/RECALL Cycle
Figure 12. CE and OE Controlled Software STORE/RECALL Cycle [45]
tRC
tRC
Address
CE
Address #1
tCW
Address #6
tCW
tSA
tHA
tHA
tHA
tSA
tHA
OE
tHHHD
tHZCE
HSB (STORE only)
DQ (DATA)
46
Note
tDELAY
tLZCE
tLZHSB
High Impedance
tSTORE/tRECALL
RWI
Figure 13. AutoStore Enable/Disable Cycle[45]
tRC
Address #1
tCW
tRC
Address
Address #6
tCW
tSA
CE
tSA
tHA
tHA
tHA
tHA
OE
tSS
tHZCE
46
Note
tLZCE
tDELAY
DQ (DATA)
RWI
Notes
44. The software sequence is clocked with CE controlled or OE controlled reads.
45. The six consecutive addresses must be read in the order listed in Table 1 on page 7. WE must be HIGH during all six consecutive cycles.
46. DQ output data at the sixth read may be invalid since the output is disabled at t
time.
DELAY
Document Number: 001-49918 Rev. *O
Page 17 of 28
CY14B104LA
CY14B104NA
Hardware STORE Cycle
Over the Operating Range
20 ns
25 ns
45 ns
Unit
Parameter
Description
Min
–
Max
20
Min
–
Max
25
Min
–
Max
25
tDHSB
tPHSB
HSB to output active time when write latch not set
Hardware STORE pulse width
ns
ns
s
15
–
–
15
–
–
15
–
–
[47, 48]
tSS
Soft sequence processing time
100
100
100
Switching Waveforms – Hardware STORE Cycle
Figure 14. Hardware STORE Cycle [49]
Write latch set
tPHSB
HSB (IN)
tSTORE
tHHHD
tDELAY
HSB (OUT)
DQ (Data Out)
RWI
tLZHSB
Write latch not set
tPHSB
HSB pin is driven high to VCC only by Internal
100 kOhm resistor,
HSB (IN)
HSB driver is disabled
SRAM is disabled as long as HSB (IN) is driven low.
tDELAY
tDHSB
tDHSB
HSB (OUT)
RWI
Figure 15. Soft Sequence Processing [47, 48]
tSS
tSS
Soft Sequence
Command
Soft Sequence
Command
Address
Address #1
tSA
Address #6
tCW
Address #1
Address #6
tCW
CE
VCC
Notes
47. This is the amount of time it takes to take action on a soft sequence command. V power must remain HIGH to effectively register command.
CC
48. Commands such as STORE and RECALL lock out I/O until operation is complete which further increases this time. See the specific command.
49. If an SRAM write has not taken place since the last non-volatile cycle, no AutoStore or Hardware STORE takes place.
Document Number: 001-49918 Rev. *O
Page 18 of 28
CY14B104LA
CY14B104NA
Truth Table For SRAM Operations
HSB should remain HIGH for SRAM Operations.
Table 2. Truth Table for × 8 Configuration
CE
H
L
WE
X
OE
X
Inputs/Outputs[50]
Mode
Deselect/Power-down
Read
Power
High Z
Standby
H
L
Data out (DQ0–DQ7);
High Z
Active
Active
Active
L
H
H
Output disabled
Write
L
L
X
Data in (DQ0–DQ7);
Table 3. Truth Table for × 16 Configuration
CE
H
L
WE
X
OE
X
BHE[51] BLE[51]
Inputs/Outputs[50]
High Z
Mode
Power
X
H
L
X
H
L
Deselect/Power-down
Output disabled
Read
Standby
Active
Active
Active
X
X
High Z
L
H
L
Data out (DQ0–DQ15)
L
H
L
H
L
Data out (DQ0–DQ7);
DQ8–DQ15 in High Z
Read
L
H
L
L
H
Data out (DQ8–DQ15);
DQ0–DQ7 in High Z
Read
Active
L
L
L
L
L
H
H
H
L
H
H
H
X
X
L
H
L
L
L
H
L
L
High Z
High Z
High Z
Output disabled
Output disabled
Output disabled
Write
Active
Active
Active
Active
Active
L
Data in (DQ0–DQ15)
L
H
Data in (DQ0–DQ7);
DQ8–DQ15 in High Z
Write
L
L
X
L
H
Data in (DQ8–DQ15);
DQ0–DQ7 in High Z
Write
Active
Notes
50. Data DQ –DQ for × 8 configuration and Data DQ –DQ for × 16 configuration.
0
7
0
15
51. BHE and BLE are applicable for × 16 configuration only.
Document Number: 001-49918 Rev. *O
Page 19 of 28
CY14B104LA
CY14B104NA
Ordering Information
Speed
Package
Diagram
Operating
Range
Ordering Code
(ns)
Package Type
20
CY14B104LA-ZS20XIT
CY14B104LA-ZS20XI
CY14B104NA-ZS20XIT
CY14B104NA-ZS20XI
CY14B104NA-BA20XIT
CY14B104NA-BA20XI
CY14B104LA-ZS25XIT
CY14B104LA-ZS25XI
CY14B104LA-BA25XIT
CY14B104LA-BA25XI
CY14B104NA-ZS25XIT
CY14B104NA-ZS25XI
CY14B104NA-BA25XIT
CY14B104NA-BA25XI
CY14B104NA-BA25I
51-85087 44-pin TSOP II
51-85087 44-pin TSOP II
51-85087 44-pin TSOP II
51-85087 44-pin TSOP II
51-85128 48-ball FBGA
51-85128 48-ball FBGA
51-85087 44-pin TSOP II
51-85087 44-pin TSOP II
51-85128 48-ball FBGA
51-85128 48-ball FBGA
51-85087 44-pin TSOP II
51-85087 44-pin TSOP II
51-85128 48-ball FBGA
51-85128 48-ball FBGA
51-85128 48-ball FBGA
51-85128 48-ball FBGA
51-85160 54-pin TSOP II
51-85160 54-pin TSOP II
51-85087 44-pin TSOP II
51-85087 44-pin TSOP II
51-85128 48-ball FBGA
51-85128 48-ball FBGA
51-85087 44-pin TSOP II
51-85087 44-pin TSOP II
51-85128 48-ball FBGA
51-85128 48-ball FBGA
51-85160 54-pin TSOP II
51-85160 54-pin TSOP II
Industrial
25
CY14B104NA-BA25IT
CY14B104NA-ZSP25XIT
CY14B104NA-ZSP25XI
CY14B104LA-ZS45XIT
CY14B104LA-ZS45XI
CY14B104LA-BA45XIT
CY14B104LA-BA45XI
CY14B104NA-ZS45XIT
CY14B104NA-ZS45XI
CY14B104NA-BA45XIT
CY14B104NA-BA45XI
CY14B104NA-ZSP45XIT
CY14B104NA-ZSP45XI
45
Document Number: 001-49918 Rev. *O
Page 20 of 28
CY14B104LA
CY14B104NA
Ordering Code Definitions
CY 14 B 104 L A - ZS 20 X I T
Option:
T - Tape & Reel
Blank - Std.
Temperature:
I - Industrial (–40 C to 85 C)
X - Pb-free
Blank - Sn Pb
Speed:
20 - 20 ns
25 - 25 ns
45 - 45 ns
Package:
BA – 48-ball FBGA
ZS – 44-pin TSOP II
ZSP – 54-pin TSOP II
Die Revision:
Blank - No Rev
A - 1st Rev
Data Bus:
L - × 8
N - × 16
Density:
104 - 4 Mb
Voltage:
B - 3.0 V
14 -
nvSRAM
Cypress
Document Number: 001-49918 Rev. *O
Page 21 of 28
CY14B104LA
CY14B104NA
Package Diagrams
Figure 16. 44-pin TSOP II Package Outline, 51-85087
51-85087 *E
Document Number: 001-49918 Rev. *O
Page 22 of 28
CY14B104LA
CY14B104NA
Package Diagrams (continued)
Figure 17. 48-ball FBGA (6 × 10 × 1.2 mm) Package Outline, 51-85128
51-85128 *G
Document Number: 001-49918 Rev. *O
Page 23 of 28
CY14B104LA
CY14B104NA
Package Diagrams (continued)
Figure 18. 54-pin TSOP II (22.4 × 11.84 × 1.0 mm) Package Outline, 51-85160
51-85160 *E
Document Number: 001-49918 Rev. *O
Page 24 of 28
CY14B104LA
CY14B104NA
Acronyms
Document Conventions
Units of Measure
Acronym
Description
byte high enable
Symbol
°C
Unit of Measure
BHE
BLE
byte low enable
chip enable
degree Celsius
hertz
Hz
kHz
k
MHz
A
F
s
CE
kilohertz
kilohm
CMOS
complementary metal oxide semiconductor
Electronic Industries Alliance
fine-pitch ball grid array
EIA
megahertz
microampere
microfarad
microsecond
milliampere
millisecond
nanosecond
ohm
FBGA
hardware store busy
HSB
I/O
input/output
nvSRAM
non-volatile static random access memory
output enable
mA
ms
ns
OE
RoHS
restriction of hazardous substances
read and write inhibited
RWI
SRAM
TSOP
WE
static random access memory
thin small outline package
write enable
%
percent
pF
sec
V
picofarad
second
volt
W
watt
Document Number: 001-49918 Rev. *O
Page 25 of 28
CY14B104LA
CY14B104NA
Document History Page
Document Title: CY14B104LA/CY14B104NA, 4-Mbit (512K × 8/256K × 16) nvSRAM
Document Number: 001-49918
Orig. of
Change
Submission
Date
Rev.
ECN
Description of Change
**
2606696
GVCH /
PYRS
11/13/08
New data sheet.
*A
*B
2672700
2710274
GVCH /
PYRS
03/12/09
Added Best Practices.
Updated AC Switching Characteristics (Added Note 23 and referred the same
note in tLZCE, tHZCE, tLZOE, and tHZOE parameters).
Updated Ordering Information (Updated part numbers).
GVCH /
AESA
05/22/09
Changed status from Preliminary to Final.
Updated Device Operation (Updated AutoStore Operation (Updated
description (Added Note))).
Updated DC Electrical Characteristics (Updated test condition for ISB
parameter, updated Note 15).
Updated AutoStore/Power-Up RECALL (Added Note 41 and referred the same
note in tVCCRISE, tLZHSB and tHHHD parameters, updated description of VHDIS
parameter).
Updated Switching Waveforms – Software Controlled STORE/RECALL Cycle
(Updated Figure 12).
*C
*D
2738586
2758397
GVCH
07/15/09
09/01/09
Updated Device Operation (Updated Hardware STORE Operation (Updated
description), updated Software STORE (Updated description)).
Updated AutoStore/Power-Up RECALL (Updated description of tDELAY
parameter, updated Note 40).
Updated Switching Waveforms – Software Controlled STORE/RECALL Cycle
(Added Note 46 and referred the same note in Figure 12 and Figure 13).
GVCH /
AESA
Updated Features (Removed commercial temperature related information).
Updated Operating Range (Removed commercial temperature related
information).
Updated DC Electrical Characteristics (Removed commercial temperature
related information).
Updated Ordering Information (Updated part numbers).
*E
*F
2773362
2826364
GVCH
10/06/09
12/11/09
Updated Ordering Information (Added 20 ns parts in a 48-ball FBGA package).
GVCH /
PYRS
Updated Features (Changed STORE cycles to QuantumTrap from 200K to
1 Million).
*G
2923475
GVCH /
AESA
04/27/2010 Updated Pin Definitions (Added more clarity on HSB pin operation).
Updated Device Operation (Updated Hardware STORE Operation (added
more clarity on HSB pin operation), updated Table 1 (added more clarity on
BHE/BLE pin operation)).
Updated Switching Waveforms – AutoStore/Power-up RECALL (HSB pin
operation in Figure 11 and updated Note 43).
Updated Package Diagrams
Updated Sales, Solutions, and Legal Information.
*H
3132368
GVCH
01/10/2011 Updated Pinouts (Removed the reference of Note 5 in Figure 1).
Updated Capacitance (Included input capacitance for BHE, BLE and HSB pin,
output capacitance for HSB pin).
Updated Switching Waveforms – AutoStore/Power-up RECALL (Fixed typo
error in Figure 11).
Added Acronyms and Units of Measure.
Document Number: 001-49918 Rev. *O
Page 26 of 28
CY14B104LA
CY14B104NA
Document History Page (continued)
Document Title: CY14B104LA/CY14B104NA, 4-Mbit (512K × 8/256K × 16) nvSRAM
Document Number: 001-49918
Orig. of
Change
Submission
Date
Rev.
ECN
Description of Change
*I
3305495
GVCH
07/07/2011 Updated DC Electrical Characteristics (Added Note 17 and referred the same
note in VCAP parameter).
Updated AC Switching Characteristics (Added Note 20 and referred the same
note in Parameters).
Updated Thermal Resistance (Values of JA for all packages).
Updated Package Diagrams.
*J
*K
*L
3389991
3514367
3643590
3724900
GVCH
GVCH
GVCH
GVCH
09/30/2011 Updated Package Diagrams.
Completing Sunset Review.
02/01/2012 Removed Best Practices.
Updated Ordering Information (Updated part numbers).
06/13/2012 Updated DC Electrical Characteristics (Added VVCAP parameter and its details,
added Note 18 and referred the same note in VVCAP parameter).
*M
09/03/2012 Updated Maximum Ratings (Changed “Ambient temperature with power
applied” to “Maximum junction temperature”).
Updated Package Diagrams (spec 51-85087 (Changed revision from *D to *E),
spec 51-85160 (Changed revision from *C to *D)).
Completing Sunset Review.
*N
*O
4563189
5735377
GVCH
GVCH
11/06/2014 Updated Functional Description:
Added “For a complete list of related documentation, click here.” at the end.
Updated Package Diagrams:
spec 51-85160 – Changed revision from *D to *E.
05/12/2017 Updated Package Diagrams:
spec 51-85128 – Changed revision from *F to *G.
Updated to new template.
Document Number: 001-49918 Rev. *O
Page 27 of 28
CY14B104LA
CY14B104NA
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
®
Products
PSoC Solutions
ARM® Cortex® Microcontrollers
cypress.com/arm
cypress.com/automotive
cypress.com/clocks
cypress.com/interface
cypress.com/iot
PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP
Automotive
Cypress Developer Community
Clocks & Buffers
Interface
Forums | WICED IOT Forums | Projects | Video | Blogs |
Training | Components
Internet of Things
Memory
Technical Support
cypress.com/memory
cypress.com/mcu
cypress.com/support
Microcontrollers
PSoC
cypress.com/psoc
Power Management ICs
Touch Sensing
USB Controllers
Wireless Connectivity
cypress.com/pmic
cypress.com/touch
cypress.com/usb
cypress.com/wireless
© Cypress Semiconductor Corporation, 2008–2017. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document,
including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other
intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress
hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to
modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users
(either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as
provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation
of the Software is prohibited.
TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE
OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. To the extent
permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any
product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is
the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress products
are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or
systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the
device or system could cause personal injury, death, or property damage ("Unintended Uses"). A critical component is any component of a device or system whose failure to perform can be reasonably
expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim,
damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other
liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products.
Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in
the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
Document Number: 001-49918 Rev. *O
Revised May 12, 2017
Page 28 of 28
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