CY14B108N-ZSP25XIT [INFINEON]
nvSRAM (non-volatile SRAM);
| 型号： | CY14B108N-ZSP25XIT |
| 厂家： | 
Infineon |
| 描述： | nvSRAM (non-volatile SRAM) 静态存储器 |
| 文件： | 总27页 (文件大小：883K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY14B108L
CY14B108N
8-Mbit (1024 K × 8/512 K × 16) nvSRAM
8-Mbit (1024
K × 8/512 K × 16) nvSRAM
■ Packages
Features
❐ 44-/54-pin thin small outline package (TSOP) Type II
❐ 48-ball fine-pitch ball grid array (FBGA)
■ 20 ns, 25 ns, and 45 ns access times
■ Internally organized as 1024 K × 8 (CY14B108L) or 512 K ×16
(CY14B108N)
■ Pb-free and restriction of hazardous substances (RoHS)
compliant
■ Hands off automatic STORE on power-down with only a small
capacitor
Functional Description
The Cypress CY14B108L/CY14B108N is a fast static RAM
(SRAM), with a nonvolatile element in each memory cell. The
memory is organized as 1024 Kbytes of 8 bits each or 512 K
words of 16 bits each. The embedded nonvolatile elements
incorporate QuantumTrap technology, producing the world’s
most reliable nonvolatile memory. The SRAM provides infinite
read and write cycles, while independent nonvolatile data
resides in the highly reliable QuantumTrap cell. Data transfers
from the SRAM to the nonvolatile elements (the STORE
operation) takes place automatically at power-down. On
power-up, data is restored to the SRAM (the RECALL operation)
from the nonvolatile memory. Both the STORE and RECALL
operations are also available under software control.
■ STORE to QuantumTrap nonvolatile elements initiated by
software, device pin, or AutoStore on power-down
■ RECALL to SRAM initiated by software or power-up
■ Infinite Read, Write, and RECALL cycles
■ 1 million STORE cycles to QuantumTrap
■ 20 year data retention
■ Single 3 V +20, –10 operation
■ Industrial temperature
For a complete list of related documentation, click here.
Logic Block Diagram [1, 2, 3]
VCAP
VCC
Quatrum Trap
2048 X 2048 X 2
A0
A1
A2
A3
A4
A5
A6
POWER
R
O
W
CONTROL
STORE
RECALL
STORE/RECALL
CONTROL
D
E
C
O
D
E
R
HSB
STATIC RAM
ARRAY
2048 X 2048 X 2
A7
A8
A17
SOFTWARE
DETECT
A14 - A2
A18
A19
DQ0
DQ1
DQ2
DQ3
I
DQ4
DQ5
DQ6
N
P
U
T
B
U
F
F
E
R
S
DQ7
COLUMN I/O
DQ8
DQ9
DQ10
OE
COLUMN DEC
WE
DQ11
DQ12
DQ13
DQ14
CE
BLE
A9 A10 A11 A12 A13 A14 A15 A16
DQ15
BHE
Errata: AutoStore Disable feature does not work in the device. For more information, see Errata on page 24. Details include errata trigger conditions, scope of impact,
available workarounds, and silicon revision applicability.
Notes
1. Address A –A for × 8 configuration and Address A –A for × 16 configuration.
0
19
0
18
2. Data DQ –DQ for × 8 configuration and Data DQ –DQ for × 16 configuration.
0
7
0
15
3. BHE and BLE are applicable for × 16 configuration only.
Cypress Semiconductor Corporation
Document Number: 001-45523 Rev. *P
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised April 21, 2017
CY14B108L
CY14B108N
Contents
Pinouts ..............................................................................3
Pin Definitions ..................................................................4
Device Operation ..............................................................5
SRAM Read ................................................................5
SRAM Write .................................................................5
AutoStore Operation ....................................................5
Hardware STORE Operation .......................................5
Hardware RECALL (Power-Up) ..................................6
Software STORE .........................................................6
Software RECALL .......................................................6
Preventing AutoStore ..................................................8
Data Protection ............................................................8
Maximum Ratings .............................................................9
Operating Range ...............................................................9
DC Electrical Characteristics ..........................................9
Data Retention and Endurance .....................................10
Capacitance ....................................................................10
Thermal Resistance ........................................................10
AC Test Loads ................................................................11
AC Test Conditions ........................................................11
AC Switching Characteristics .......................................12
Switching Waveforms ....................................................12
AutoStore/Power-Up RECALL .......................................15
Switching Waveforms ....................................................15
Software Controlled STORE/RECALL Cycle ................16
Switching Waveforms ....................................................16
Hardware STORE Cycle .................................................17
Switching Waveforms ....................................................17
Truth Table For SRAM Operations ................................18
Ordering Information ......................................................19
Ordering Code Definitions .........................................19
Package Diagrams ..........................................................20
Acronyms ........................................................................23
Document Conventions .................................................23
Units of Measure .......................................................23
Errata ...............................................................................24
Part Numbers Affected ..............................................24
8Mb (1024 K × 8, 512 K × 16) nvSRAM
Qualification Status ...........................................................24
8Mb (1024 K × 8, 512 K × 16) nvSRAM
Errata Summary ...............................................................24
Document History Page .................................................25
Sales, Solutions, and Legal Information ......................27
Worldwide Sales and Design Support .......................27
Products ....................................................................27
PSoC® Solutions ......................................................27
Cypress Developer Community .................................27
Technical Support .....................................................27
Document Number: 001-45523 Rev. *P
Page 2 of 27
CY14B108L
CY14B108N
Pinouts
Figure 1. Pin Diagram – 48-ball FBGA
(×
8)
(× 16)
Top View
Top View
(not to scale)
(not to scale)
1
2
4
3
5
6
1
2
OE
NC
NC
4
3
5
6
A
A
A
2
NC
OE
BLE
DQ8
A
A
A
0
1
A
B
C
NC
NC
NC
0
1
2
A
B
C
A
A
BHE
DQ10
CE DQ0
DQ1 DQ2
V
A
A
4
4
3
CE NC
NC DQ4
V
3
A
A
6
DQ9
A
A
6
DQ0
5
5
A
7
V
A17
A
DQ3
DQ4
DQ5
CC
D
E
F
V
SS
DQ11
DQ12
DQ13
A17
DQ5
DQ6
NC
DQ1
DQ2
NC
CC
D
E
F
SS
7
A
V
V
SS
A
VCAP
V
V
SS
CC
16
VCAP
CC
16
A
A
15
DQ14
DQ15
A18
A
A
DQ6
DQ3
NC
DQ7
14
14
15
A
A
13
G
H
A
A
HSB
WE DQ7
A
G
H
HSB
WE NC
12
13
12
A
A
9
A
A
8
A
9
A
11
A18
A
8
A19
10
NC
11
10
Figure 2. Pin Diagram – 44/54-pin TSOP II
44-pin TSOP II
(× 8)
54-pin TSOP II
(× 16)
NC
1
54
HSB
[4]
NC
NC
1
2
44
HSB
NC
NC
A
0
53
52
51
50
49
A
A
2
3
[4]
18
43
42
41
17
A
A
1
3
4
5
6
7
8
9
10
11
12
13
14
A
16
A
0
4
19
A
2
A
15
OE
BHE
A
1
5
A
18
A
3
6
A
2
A
17
40
39
48
47
46
45
A
4
7
A
3
A
16
CE
BLE
DQ
8
A
4
38
37
36
35
34
A
15
DQ
DQ
0
1
9
15
CE
DQ
DQ
DQ
V
10
11
12
13
14
OE
DQ
14
13
12
DQ
DQ
44
43
42
41
40
39
DQ
2
3
0
1
7
DQ
DQ
6
V
CC
SS
Top View
V
CC
V
V
SS
SS
V
CC
(not to scale)
Top View
(not to scale)
V
V
DQ
33
32
31
SS
CC
DQ
DQ
DQ
4
15
16
17
18
19
20
21
22
23
24
11
10
DQ
DQ
DQ
DQ
2
3
5
5
38
37
36
35
DQ
DQ
DQ
6
9
8
4
DQ
7
WE
A
5
15
16
17
18
30
29
28
27
26
25
24
23
V
A
CAP
WE
A
5
V
CAP
14
A
14
A
6
A
34
33
32
31
30
29
28
13
12
A
6
A
13
A
7
A
A
A
7
A
8
12
A
A
11
19
20
21
22
8
A
11
A
A
9
A
9
10
NC
NC
NC
A
10
NC
NC
NC
25
26
27
NC
NC
NC
NC
Note
4. Address expansion for 16-Mbit. NC pin not connected to die.
Document Number: 001-45523 Rev. *P
Page 3 of 27
CY14B108L
CY14B108N
Pin Definitions
Pin Name
A0–A19
I/O Type
Input
Description
Address inputs. Used to select one of the 1,048,576 bytes of the nvSRAM for × 8 configuration.
Address inputs. Used to select one of the 524,288 words of the nvSRAM for × 16 configuration.
A0–A18
DQ0–DQ7 Input/Output Bidirectional data I/O lines for × 8 configuration. Used as input or output lines depending on operation.
DQ0–DQ15
WE
Bidirectional data I/O lines for × 16 configuration. Used as input or output lines depending on operation.
Input
Write Enable input, Active LOW. When selected LOW, data on the I/O pins is written to the specific
address location.
Input
Input
Chip Enable input, Active LOW. When LOW, selects the chip. When HIGH, deselects the chip.
CE
OE
Output Enable, Active LOW. The active LOW OE input enables the data output buffers during read
cycles. I/O pins are tristated on deasserting OE HIGH.
Input
Input
Byte High Enable, Active LOW. Controls DQ15–DQ8.
BHE
Byte Low Enable, Active LOW. Controls DQ7–DQ0.
BLE
VSS
Ground
Ground for the device. Must be connected to the ground of the system.
VCC
Power supply Power supply inputs to the device.
Input/Output Hardware STORE Busy (HSB). When LOW this output indicates that a Hardware STORE is in progress.
When pulled LOW external to the chip it initiates a nonvolatile STORE operation. After each Hardware
and Software STORE operation, HSB is driven HIGH for a short time (tHHHD) with standard output high
current and then a weak internal pull-up resistor keeps this pin HIGH (external pull-up resistor
connection optional).
HSB
VCAP
NC
Power supply AutoStore capacitor. Supplies power to the nvSRAM during power loss to store data from SRAM to
nonvolatile elements.
No connect No connect. This pin is not connected to the die.
Document Number: 001-45523 Rev. *P
Page 4 of 27
CY14B108L
CY14B108N
AutoStore on page 8. In case AutoStore is enabled without a
capacitor on VCAP pin, the device attempts an AutoStore
operation without sufficient charge to complete the Store. This
corrupts the data stored in nvSRAM.
Device Operation
The CY14B108L/CY14B108N nvSRAM is made up of two
functional components paired in the same physical cell. They are
a SRAM memory cell and a nonvolatile QuantumTrap cell. The
SRAM memory cell operates as a standard fast static RAM. Data
in the SRAM is transferred to the nonvolatile cell (the STORE
operation), or from the nonvolatile cell to the SRAM (the RECALL
operation). Using this unique architecture, all cells are stored and
recalled in parallel. During the STORE and RECALL operations,
SRAM read and write operations are inhibited. The
CY14B108L/CY14B108N supports infinite reads and writes
similar to a typical SRAM. In addition, it provides infinite RECALL
operations from the nonvolatile cells and up to 1 million STORE
operations. See Truth Table For SRAM Operations on page 18
for a complete description of read and write modes.
Figure 3 shows the proper connection of the storage capacitor
(VCAP) for automatic STORE operation. Refer to DC Electrical
Characteristics on page 9 for the size of VCAP. The voltage on
the VCAP pin is driven to VCC by a regulator on the chip. A pull-up
should be placed on WE to hold it inactive during power-up. This
pull-up is effective only if the WE signal is tristate during
power-up. Many MPUs tristate their controls on power-up. This
should be verified when using the pull-up. When the nvSRAM
comes out of power-on-RECALL, the MPU must be active or the
WE held inactive until the MPU comes out of reset.
To reduce unnecessary nonvolatile STOREs, AutoStore and
Hardware STORE operations are ignored unless at least one
write operation has taken place since the most recent STORE or
RECALL cycle. Software initiated STORE cycles are performed
regardless of whether a write operation has taken place. The
HSB signal is monitored by the system to detect if an AutoStore
cycle is in progress.
SRAM Read
The CY14B108L/CY14B108N performs a read cycle when CE
and OE are LOW and WE and HSB are HIGH. The address
specified on pins A0–19 or A0–18 determines which of the
1,048,576 data bytes or 524,288 words of 16 bits each are
accessed. Byte enables (BHE, BLE) determine which bytes are
enabled to the output, in the case of 16-bit words. When the read
is initiated by an address transition, the outputs are valid after a
delay of tAA (read cycle 1). If the read is initiated by CE or OE,
the outputs are valid at tACE or at tDOE, whichever is later (read
cycle 2). The data output repeatedly responds to address
changes within the tAA access time without the need for
transitions on any control input pins. This remains valid until
another address change or until CE or OE is brought HIGH, or
WE or HSB is brought LOW.
Figure 3. AutoStore Mode
VCC
0.1 uF
VCC
SRAM Write
WE
VCAP
A write cycle is performed when CE and WE are LOW and HSB
is HIGH. The address inputs must be stable before entering the
write cycle and must remain stable until CE or WE goes HIGH at
the end of the cycle. The data on the common I/O pins DQ0–15
are written into the memory if the data is valid tSD before the end
of a WE controlled write or before the end of an CE controlled
write. The Byte Enable inputs (BHE, BLE) determine which bytes
are written, in the case of 16-bit words. Keep OE HIGH during
the entire write cycle to avoid data bus contention on common
I/O lines. If OE is left LOW, internal circuitry turns off the output
buffers tHZWE after WE goes LOW.
VCAP
VSS
Hardware STORE Operation
The CY14B108L/CY14B108N provides the HSB pin to control
and acknowledge the STORE operations. Use the HSB pin to
request a Hardware STORE cycle. When the HSB pin is driven
LOW, the CY14B108L/CY14B108N conditionally initiates a
STORE operation after tDELAY. An actual STORE cycle only
begins if a write to the SRAM has taken place since the last
STORE or RECALL cycle. The HSB pin also acts as an open
drain driver (internal 100 k weak pull-up resistor) that is inter-
nally driven LOW to indicate a busy condition when the STORE
(initiated by any means) is in progress.
AutoStore Operation
The CY14B108L/CY14B108N stores data to the nvSRAM using
one of the following three storage operations: Hardware STORE
activated by the HSB; Software STORE activated by an address
sequence; AutoStore on device power-down. The AutoStore
operation is a unique feature of QuantumTrap technology and is
enabled by default on the CY14B108L/CY14B108N.
During a normal operation, the device draws current from VCC to
charge a capacitor connected to the VCAP pin. This stored
charge is used by the chip to perform a single STORE operation.
If the voltage on the VCC pin drops below VSWITCH, the part
automatically disconnects the VCAP pin from VCC. A STORE
operation is initiated with power provided by the VCAP capacitor.
Note After each Hardware and Software STORE operation HSB
is driven HIGH for a short time (tHHHD) with standard output high
current and then remains HIGH by internal 100 k pull-up
resistor.
Note If the capacitor is not connected to VCAP pin, AutoStore
must be disabled using the soft sequence specified in Preventing
Document Number: 001-45523 Rev. *P
Page 5 of 27
CY14B108L
CY14B108N
SRAM write operations that are in progress when HSB is driven
LOW by any means are given time (tDELAY) to complete before
the STORE operation is initiated. However, any SRAM write
cycles requested after HSB goes LOW are inhibited until HSB
returns HIGH. In case the write latch is not set, HSB is not driven
LOW by the CY14B108L/CY14B108N. But any SRAM read and
write cycles are inhibited until HSB is returned HIGH by MPU or
other external source.
To initiate the Software STORE cycle, the following read
sequence must be performed.
1. Read address 0x4E38 Valid READ
2. Read address 0xB1C7 Valid READ
3. Read address 0x83E0 Valid READ
4. Read address 0x7C1F Valid READ
5. Read address 0x703F Valid READ
6. Read address 0x8FC0 Initiate STORE cycle
During any STORE operation, regardless of how it is initiated,
the CY14B108L/CY14B108N continues to drive the HSB pin
LOW, releasing it only when the STORE is complete. Upon
completion of the STORE operation, the nvSRAM memory
access is inhibited for tLZHSB time after HSB pin returns HIGH.
Leave the HSB unconnected if it is not used.
The software sequence may be clocked with CE controlled reads
or OE controlled reads, with WE kept HIGH for all the six READ
sequences. After the sixth address in the sequence is entered,
the STORE cycle commences and the chip is disabled. HSB is
driven LOW. After the tSTORE cycle time is fulfilled, the SRAM is
activated again for the read and write operation.
Hardware RECALL (Power-Up)
During power-up or after any low power condition
(VCC< VSWITCH), an internal RECALL request is latched. When
VCC again exceeds the VSWITCH on power-up, a RECALL cycle
is automatically initiated and takes tHRECALL to complete. During
this time, the HSB pin is driven LOW by the HSB driver and all
reads and writes to nvSRAM are inhibited.
Software RECALL
Data is transferred from the nonvolatile memory to the SRAM by
a software address sequence. A software RECALL cycle is
initiated with a sequence of read operations in a manner similar
to the software STORE initiation. To initiate the RECALL cycle,
the following sequence of CE or OE controlled read operations
must be performed.
Software STORE
Data is transferred from the SRAM to the nonvolatile memory by
a software address sequence. The CY14B108L/CY14B108N
Software STORE cycle is initiated by executing sequential CE or
OE controlled read cycles from six specific address locations in
exact order. During the STORE cycle an erase of the previous
nonvolatile data is first performed, followed by a program of the
nonvolatile elements. After a STORE cycle is initiated, further
input and output are disabled until the cycle is completed.
1. Read address 0x4E38 Valid READ
2. Read address 0xB1C7 Valid READ
3. Read address 0x83E0 Valid READ
4. Read address 0x7C1F Valid READ
5. Read address 0x703F Valid READ
6. Read address 0x4C63 Initiate RECALL cycle
Internally, RECALL is a two-step procedure. First, the SRAM
data is cleared; then, the nonvolatile information is transferred
into the SRAM cells. After the tRECALL cycle time, the SRAM is
again ready for read and write operations. The RECALL
operation does not alter the data in the nonvolatile elements.
Because a sequence of READs from specific addresses is used
for STORE initiation, it is important that no other read or write
accesses intervene in the sequence, or the sequence is aborted
and no STORE or RECALL takes place.
Document Number: 001-45523 Rev. *P
Page 6 of 27
CY14B108L
CY14B108N
Table 1. Mode Selection
[6]
A15–A0
Mode
Not Selected Output High Z
I/O
Power
CE
WE
OE
BHE, BLE[5]
H
X
X
X
X
X
X
Standby
Active
L
L
L
H
L
L
X
L
L
L
Read SRAM
Write SRAM
Output data
Input data
Active
Active[7]
H
X
0x4E38
0xB1C7
0x83E0
0x7C1F
0x703F
0x8B45
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
AutoStore
Output data
Output data
Output data
Output data
Output data
Output data
Disable
L
L
L
H
H
H
L
L
L
X
X
X
0x4E38
0xB1C7
0x83E0
0x7C1F
0x703F
0x4B46
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
AutoStore
Output data
Output data
Output data
Output data
Output data
Output data
Active[7]
Active ICC2
Active[7]
Enable
[7]
0x4E38
0xB1C7
0x83E0
0x7C1F
0x703F
0x8FC0
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Nonvolatile
STORE
Output data
Output data
Output data
Output data
Output data
Output High Z
0x4E38
0xB1C7
0x83E0
0x7C1F
0x703F
0x4C63
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Nonvolatile
RECALL
Output data
Output data
Output data
Output data
Output data
Output High Z
Errata: AutoStore Disable feature does not work in the device. For more information, see Errata on page 24.
Notes
5. BHE and BLE are applicable for × 16 configuration only.
6. While there are 20 address lines on the CY14B108L (19 address lines on the CY14B108N), only the 13 address lines (A –A ) are used to control software modes.
14
2
Rest of the address lines are don’t care.
7. The six consecutive address locations must be in the order listed. WE must be HIGH during all six cycles to enable a nonvolatile cycle.
Document Number: 001-45523 Rev. *P
Page 7 of 27
CY14B108L
CY14B108N
AutoStore enable sequence, the following sequence of CE or OE
controlled read operations must be performed:
Preventing AutoStore
The AutoStore function is disabled by initiating an AutoStore
disable sequence. A sequence of read operations is performed
in a manner similar to the Software STORE initiation. To initiate
the AutoStore disable sequence, the following sequence of CE
or OE controlled read operations must be performed:
1. Read address 0x4E38 Valid READ
2. Read address 0xB1C7 Valid READ
3. Read address 0x83E0 Valid READ
4. Read address 0x7C1F Valid READ
5. Read address 0x703F Valid READ
6. Read address 0x4B46 AutoStore Enable
1. Read address 0x4E38 Valid READ
2. Read address 0xB1C7 Valid READ
3. Read address 0x83E0 Valid READ
4. Read address 0x7C1F Valid READ
5. Read address 0x703F Valid READ
6. Read address 0x8B45 AutoStore Disable
If the AutoStore function is disabled or re-enabled, a manual
STORE operation (Hardware or Software) must be issued to
save the AutoStore state through subsequent power-down
cycles. The part comes from the factory with AutoStore enabled
and 0x00 written in all cells.
Note Errata: AutoStore Disable feature does not work in the
device. For more information, see Errata on page 24.
Data Protection
The AutoStore is re-enabled by initiating an AutoStore enable
sequence. A sequence of read operations is performed in a
manner similar to the Software RECALL initiation. To initiate the
The CY14B108L/CY14B108N protects data from corruption
during low voltage conditions by inhibiting all externally initiated
STORE and write operations. The low voltage condition is
detected when VCC < VSWITCH. If the CY14B108L/CY14B108N
is in a write mode (both CE and WE are LOW) at power-up, after
a RECALL or STORE, the write is inhibited until the SRAM is
enabled after tLZHSB (HSB to output active). This protects against
inadvertent writes during power-up or brown out conditions.
Document Number: 001-45523 Rev. *P
Page 8 of 27
CY14B108L
CY14B108N
Transient voltage (< 20 ns) on
any pin to ground potential ................. –2.0 V to VCC + 2.0 V
Maximum Ratings
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Package power dissipation
capability (TA = 25 °C) ................................................. 1.0 W
Storage temperature ................................ –65 C to +150 C
Maximum accumulated storage time
Surface mount Pb soldering
temperature (3 Seconds) ......................................... +260 C
DC output current (1 output at a time, 1s duration) .... 15 mA
At 150 C ambient temperature ...................... 1000 h
At 85 C ambient temperature ..................... 20 Years
Maximum junction temperature .................................. 150 C
Supply voltage on VCC relative to VSS ...........–0.5 V to 4.1 V
Static discharge voltage
(per MIL-STD-883, Method 3015) ..........................> 2001 V
Latch up current .................................................... > 200 mA
Operating Range
Voltage applied to outputs
in High Z state ....................................–0.5 V to VCC + 0.5 V
Range
Industrial
Ambient Temperature
VCC
Input voltage ........................................–0.5 V to Vcc + 0.5 V
–40 C to +85 C
2.7 V to 3.6 V
DC Electrical Characteristics
Over the Operating Range
Parameter
Description
Test Conditions
tRC = 20 ns
Min
2.7
–
Typ [8]
3.0
Max
Unit
VCC
Power supply
3.6
V
ICC1
Average VCC current
–
75
75
57
mA
mA
mA
t
RC = 25 ns
RC = 45 ns
t
Values obtained without output loads
(IOUT = 0 mA)
ICC2
ICC3
Average VCC current during
STORE
All inputs don’t care, VCC = Max
Average current for duration tSTORE
–
–
–
20
–
mA
mA
Average VCC current at
All inputs cycling at CMOS levels.
Values obtained without output loads
(IOUT = 0 mA).
40
tRC= 200 ns, VCC(Typ), 25 °C
ICC4
ISB
Average VCAP current during
AutoStore cycle
All inputs don’t care. Average current
for duration tSTORE
–
–
–
–
10
10
mA
mA
VCC standby current
CE > (VCC – 0.2 V).
VIN < 0.2 V or > (VCC – 0.2 V).
Standby current level after
nonvolatile cycle is complete.
Inputs are static. f = 0 MHz.
[9]
IIX
Input leakage current (except
HSB)
VCC = Max, VSS < VIN < VCC
–2
–
+2
A
Input leakage current (for HSB) VCC = Max, VSS < VIN < VCC
–200
–2
–
–
+2
+2
A
A
IOZ
Off-state output leakage current VCC = Max, VSS < VOUT < VCC
,
CE or OE > VIH or
BHE/BLE > VIH or WE < VIL
VIH
VIL
Input HIGH voltage
Input LOW voltage
2.0
Vss – 0.5
2.4
–
–
–
–
VCC + 0.5
V
V
V
V
0.8
–
VOH
VOL
Output HIGH voltage
Output LOW voltage
IOUT = –2 mA
IOUT = 4 mA
–
0.4
Notes
8. Typical values are at 25 °C, V = V
. Not 100% tested.
CC
CC(Typ)
9. The HSB pin has I
= –2 µA for V of 2.4 V when both active HIGH and LOW drivers are disabled. When they are enabled standard V and V are valid. This
OUT
O
H
O
H
O
L
parameter is characterized but not tested.
Document Number: 001-45523 Rev. *P
Page 9 of 27
CY14B108L
CY14B108N
DC Electrical Characteristics (continued)
Over the Operating Range
Parameter
Description
Test Conditions
Min
122
–
Typ [8]
150
–
Max
360
VCC
Unit
F
V
[10]
VCAP
Storage capacitor
Between VCAP pin and VSS
[11, 12]
VVCAP
Maximum voltage driven on VCAP VCC = Max
pin by the device
Data Retention and Endurance
Over the Operating Range
Parameter
Description
Min
Unit
Years
K
DATAR
NVC
Data retention
20
Nonvolatile STORE operations
1,000
Capacitance
Parameter [12]
Description
Test Conditions
TA = 25 C, f = 1 MHz, VCC = VCC(Typ)
Max
14
Unit
pF
CIN
Input capacitance
Output capacitance
COUT
14
pF
Thermal Resistance
Parameter [12]
Description
Test Conditions
48-ball FBGA 44-pin TSOP II 54-pin TSOP II Unit
JA
Thermal resistance
(Junction to ambient)
Test
conditions
follow
42.2
45.3
44.22
C/W
standard test methods and
procedures for measuring
JC
Thermal resistance
(Junction to case)
6.3
5.2
8.26
C/W
thermal
impedance,
in
with
accordance
EIA/JESD51.
Notes
10. Min V
value guarantees that there is a sufficient charge available to complete a successful AutoStore operation. Max V
value guarantees that the capacitor on
CAP
CAP
V
is charged to a minimum voltage during a Power-Up RECALL cycle so that an immediate power-down cycle can complete a successful AutoStore. Therefore it
CAP
is always recommended to use a capacitor within the specified min and max limits. Refer application note AN43593 for more details on V
options.
CAP
11. Maximum voltage on V
pin (V
) is provided for guidance when choosing the V
capacitor. The voltage rating of the V
capacitor across the operating
CAP
VCAP
CAP
CAP
temperature range should be higher than the V
voltage.
VCAP
12. These parameters are guaranteed by design and are not tested.
Document Number: 001-45523 Rev. *P
Page 10 of 27
CY14B108L
CY14B108N
AC Test Loads
Figure 4. AC Test Loads
577
for tristate specs
577
3.0 V
3.0 V
R1
R1
OUTPUT
OUTPUT
R2
789
R2
789
5 pF
30 pF
AC Test Conditions
Input pulse levels ..................................................0 V to 3 V
Input rise and fall times (10%–90%) ........................... < 3 ns
Input and output timing reference levels ...................... 1.5 V
Document Number: 001-45523 Rev. *P
Page 11 of 27
CY14B108L
CY14B108N
AC Switching Characteristics
Over the Operating Range
Parameters [13]
20 ns
25 ns
45 ns
Unit
Description
Cypress
Alt Parameter
Parameter
Min
Max
Min
Max
Min
Max
SRAM Read Cycle
tACE
tACS
tRC
tAA
tOE
tOH
tLZ
tHZ
tOLZ
tOHZ
tPA
tPS
–
Chip enable access time
–
20
–
20
–
–
25
–
25
–
–
45
–
45
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
[14]
tRC
Read cycle time
[15]
tAA
Address access time
20
10
–
25
12
–
45
20
–
tDOE
tOHA
tLZCE
tHZCE
tLZOE
Output enable to data valid
Output hold after address change
Chip enable to output active
Chip disable to output inactive
Output enable to output active
Output disable to output inactive
Chip enable to power active
Chip disable to power standby
Byte enable to data valid
–
–
–
[15]
3
3
3
[16, 17]
3
–
3
–
3
–
[16, 17]
[16, 17]
[16, 17]
–
8
–
10
–
–
15
–
0
–
0
0
tHZOE
–
8
–
10
–
–
15
–
[16]
tPU
tPD
0
–
0
0
[16]
–
20
10
–
–
25
12
–
–
45
20
–
tDBE
tLZBE
tHZBE
–
–
–
[16]
–
Byte enable to output active
Byte disable to output inactive
0
0
0
[16]
–
–
8
–
10
–
15
SRAM Write Cycle
tWC
tPWE
tSCE
tSD
tHD
tAW
tSA
tHA
tHZWE
tLZWE
tBW
tWC
tWP
tCW
tDW
tDH
tAW
tAS
tWR
tWZ
tOW
–
Write cycle time
20
15
15
8
–
–
–
–
–
–
–
–
8
–
–
25
20
20
10
0
–
–
45
30
30
15
0
–
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Write pulse width
Chip enable to end of write
Data setup to end of write
Data hold after end of write
Address setup to end of write
Address setup to start of write
Address hold after end of write
Write enable to output disable
Output active after end of write
Byte enable to end of write
–
–
–
–
0
–
–
15
0
20
0
–
30
0
–
–
–
0
0
–
0
–
[16, 17, 18]
–
10
–
–
15
–
[16, 17]
3
3
3
15
20
–
30
–
Switching Waveforms
Figure 5. SRAM Read Cycle #1 (Address Controlled) [14, 15, 19]
tRC
Address
Address Valid
tAA
Output Data Valid
Previous Data Valid
tOHA
Data Output
Notes
13. Test conditions assume signal transition time of 3 ns or less, timing reference levels of V /2, input pulse levels of 0 to V
, and output loading of the specified
CC
CC(typ)
I
/I and load capacitance shown in Figure 4 on page 11.
OL OH
14. WE must be HIGH during SRAM read cycles.
15. Device is continuously selected with CE, OE and BHE / BLE LOW.
16. These parameters are guaranteed by design but not tested.
17. Measured ±200 mV from steady state output voltage.
18. If WE is LOW when CE goes LOW, the outputs remain in the high impedance state.
19. HSB must remain HIGH during READ and WRITE cycles.
Document Number: 001-45523 Rev. *P
Page 12 of 27
CY14B108L
CY14B108N
Switching Waveforms (continued)
Figure 6. SRAM Read Cycle #2 (CE and OE Controlled) [20, 21, 22]
Address
CE
Address Valid
tRC
tHZCE
tACE
tAA
tLZCE
tHZOE
tDOE
OE
tHZBE
tLZOE
tDBE
BHE, BLE
tLZBE
High Impedance
Standby
Data Output
Output Data Valid
tPU
tPD
Active
ICC
Figure 7. SRAM Write Cycle #1 (WE Controlled) [20, 22, 23, 24]
tWC
Address
Address Valid
tSCE
tHA
CE
tBW
BHE, BLE
tAW
tPWE
WE
Data Input
Data Output
tSA
tHD
tSD
Input Data Valid
tLZWE
tHZWE
High Impedance
Previous Data
Notes
20. BHE and BLE are applicable for × 16 configuration only.
21. WE must be HIGH during SRAM read cycles.
22. HSB must remain HIGH during READ and WRITE cycles.
23. If WE is LOW when CE goes LOW, the outputs remain in the high impedance state.
24. CE or WE must be >V during address transitions.
IH
Document Number: 001-45523 Rev. *P
Page 13 of 27
CY14B108L
CY14B108N
Switching Waveforms (continued)
Figure 8. SRAM Write Cycle #2 (CE Controlled) [25, 26, 27, 28]
tWC
Address Valid
tSCE
Address
tSA
tHA
CE
tBW
tPWE
tSD
BHE, BLE
WE
tHD
Input Data Valid
High Impedance
Data Input
Data Output
Figure 9. SRAM Write Cycle #3 (BHE and BLE Controlled) [25, 26, 27, 28]
tWC
Address
CE
Address Valid
tSCE
tSA
tHA
tBW
BHE, BLE
WE
tAW
tPWE
tSD
tHD
Data Input
Input Data Valid
High Impedance
Data Output
Notes
25. BHE and BLE are applicable for × 16 configuration only.
26. If WE is LOW when CE goes LOW, the outputs remain in the high impedance state.
27. HSB must remain HIGH during READ and WRITE cycles.
28. CE or WE must be >V during address transitions.
IH
Document Number: 001-45523 Rev. *P
Page 14 of 27
CY14B108L
CY14B108N
AutoStore/Power-Up RECALL
Over the Operating Range
20 ns
25 ns
45 ns
Parameter
Description
Unit
Min
–
Max
20
8
Min
–
Max
20
8
Min
–
Max
20
8
[29]
tHRECALL
Power-Up RECALL duration
STORE cycle duration
ms
ms
ns
[30]
tSTORE
–
–
–
[31]
tDELAY
Time allowed to complete SRAM
write cycle
–
20
–
25
–
25
VSWITCH
Low voltage trigger level
VCC rise time
–
150
–
2.65
–
–
150
–
2.65
–
–
150
–
2.65
–
V
s
V
[32]
tVCCRISE
[32]
VHDIS
HSB output disable voltage
HSB to output active time
HSB high active time
1.9
5
1.9
5
1.9
5
[32]
tLZHSB
–
–
–
s
ns
[32]
tHHHD
–
500
–
500
–
500
Switching Waveforms
Figure 10. AutoStore or Power-Up RECALL [33]
VCC
VSWITCH
VHDIS
30
30
tVCCRISE
tSTORE
tSTORE
Note
Note
tHHHD
tHHHD
34
Note
34
Note
HSB OUT
AutoStore
tDELAY
tLZHSB
tLZHSB
tDELAY
POWER-
UP
RECALL
tHRECALL
tHRECALL
Read & Write
Inhibited
(RWI)
Read & Write
Read & Write
POWER-UP
RECALL
BROWN
OUT
AutoStore
POWER
DOWN
AutoStore
POWER-UP
RECALL
Notes
29. t
starts from the time V rises above V .
SWITCH
HRECALL
CC
30. If an SRAM write has not taken place since the last nonvolatile cycle, no AutoStore or Hardware STORE takes place.
31. On a Hardware STORE and AutoStore initiation, SRAM write operation continues to be enabled for time t
32. These parameters are guaranteed by design but not tested.
.
DELAY
33. Read and Write cycles are ignored during STORE, RECALL, and while V is below V
.
CC
SWITCH
34. During power-up and power-down, HSB glitches when HSB pin is pulled up through an external resistor.
Document Number: 001-45523 Rev. *P
Page 15 of 27
CY14B108L
CY14B108N
Software Controlled STORE/RECALL Cycle
Over the Operating Range
20 ns
25 ns
45 ns
Unit
Parameter [35, 36]
Description
Min
20
0
Max
–
Min
25
0
Max
–
Min
Max
–
tRC
tSA
tCW
tHA
STORE/RECALL initiation cycle time
Address setup time
45
0
ns
ns
ns
ns
s
–
–
–
Clock pulse width
15
0
–
20
0
–
30
0
–
Address hold time
–
–
–
tRECALL
RECALL duration
–
200
–
200
–
200
Switching Waveforms
Figure 11. CE and OE Controlled Software STORE/RECALL Cycle [36]
tRC
tRC
Address
CE
Address #1
tCW
Address #6
tCW
tSA
tHA
tHA
tHA
tSA
tHA
OE
tHHHD
tHZCE
HSB (STORE only)
DQ (DATA)
37
Note
tDELAY
tLZCE
tLZHSB
High Impedance
tSTORE/tRECALL
RWI
Figure 12. Autostore Enable/Disable Cycle [36]
tRC
tRC
Address
Address #1
tCW
Address #6
tCW
tSA
CE
tSA
tHA
tHA
tHA
tHA
OE
tSS
tHZCE
37
tLZCE
tDELAY
Note
DQ (DATA)
RWI
Notes
35. The software sequence is clocked with CE controlled or OE controlled reads.
36. The six consecutive addresses must be read in the order listed in Table 1 on page 7. WE must be HIGH during all six consecutive cycles.
37. DQ output data at the sixth read may be invalid since the output is disabled at t
time.
DELAY
Document Number: 001-45523 Rev. *P
Page 16 of 27
CY14B108L
CY14B108N
Hardware STORE Cycle
Over the Operating Range
20 ns
25 ns
45 ns
Parameter
tDHSB
tPHSB
Description
Unit
Min
Max
Min
Max
Min
Max
HSB to output active time when
write latch not set
–
20
–
25
–
25
ns
Hardware STORE pulse width
Soft sequence processing time
15
–
–
15
–
–
15
–
–
ns
[38, 39]
tSS
100
100
100
s
Switching Waveforms
Figure 13. Hardware STORE Cycle [40]
Write latch set
tPHSB
HSB (IN)
tSTORE
tHHHD
tDELAY
HSB (OUT)
DQ (Data Out)
RWI
tLZHSB
Write latch not set
tPHSB
HSB pin is driven high to VCC only by Internal
100 kOhm resistor,
HSB (IN)
HSB driver is disabled
SRAM is disabled as long as HSB (IN) is driven low.
tDELAY
tDHSB
tDHSB
HSB (OUT)
RWI
Figure 14. Soft Sequence Processing [38, 39]
tSS
tSS
Soft Sequence
Command
Soft Sequence
Command
Address
Address #1
tSA
Address #6
tCW
Address #1
Address #6
tCW
CE
VCC
Notes
38. This is the amount of time it takes to take action on a soft sequence command. Vcc power must remain HIGH to effectively register command.
39. Commands such as STORE and RECALL lock out I/O until operation is complete which further increases this time. See the specific command.
40. If an SRAM write has not taken place since the last nonvolatile cycle, no AutoStore or Hardware STORE takes place.
Document Number: 001-45523 Rev. *P
Page 17 of 27
CY14B108L
CY14B108N
Truth Table For SRAM Operations
HSB should remain HIGH for SRAM Operations.
Table 2. Truth Table for × 8 Configuration
CE
H
L
WE
X
OE
X
Inputs/Outputs[41]
Mode
Deselect/Power-down
Read
Power
High Z
Standby
H
L
Data out (DQ0–DQ7);
High Z
Active
Active
Active
L
H
H
Output disabled
Write
L
L
X
Data in (DQ0–DQ7);
Table 3. Truth Table for × 16 Configuration
CE
H
L
WE
X
OE
X
BHE[42] BLE[42]
Inputs/Outputs[41]
High Z
Mode
Power
X
H
L
X
H
L
Deselect/Power-down
Output disabled
Read
Standby
Active
Active
Active
X
X
High Z
L
H
L
Data out (DQ0–DQ15)
L
H
L
H
L
Data out (DQ0–DQ7);
DQ8–DQ15 in High Z
Read
L
H
L
L
H
Data out (DQ8–DQ15);
DQ0–DQ7 in High Z
Read
Active
L
L
L
L
L
H
H
H
L
H
H
H
X
X
L
H
L
L
L
H
L
L
High Z
High Z
High Z
Output disabled
Output disabled
Output disabled
Write
Active
Active
Active
Active
Active
L
Data in (DQ0–DQ15)
L
H
Data in (DQ0–DQ7);
DQ8–DQ15 in High Z
Write
L
L
X
L
H
Data in (DQ8–DQ15);
DQ0–DQ7 in High Z
Write
Active
Notes
41. Data DQ –DQ for × 8 configuration and Data DQ –DQ for × 16 configuration.
0
7
0
15
42. BHE and BLE are applicable for × 16 configuration only.
Document Number: 001-45523 Rev. *P
Page 18 of 27
CY14B108L
CY14B108N
Ordering Information
Speed
Ordering Code
Package Diagram
Package Type
44-pin TSOP II
Operating Range
(ns)
20
CY14B108L-ZS20XIT
CY14B108L-ZS20XI
CY14B108L-ZS25XIT
CY14B108L-ZS25XI
CY14B108L-BA25XIT
CY14B108L-BA25XI
CY14B108N-BA25XIT
CY14B108N-BA25XI
CY14B108N-ZSP25XIT
CY14B108N-ZSP25XI
CY14B108L-ZS45XIT
CY14B108L-ZS45XI
CY14B108L-BA45XIT
CY14B108L-BA45XI
CY14B108N-BA45XIT
CY14B108N-BA45XI
CY14B108N-ZSP45XIT
CY14B108N-ZSP45XI
51-85087
51-85087
51-85087
51-85087
51-85128
51-85128
51-85128
51-85128
51-85160
51-85160
51-85087
51-85087
51-85128
51-85128
51-85128
51-85128
51-85160
51-85160
Industrial
44-pin TSOP II
44-pin TSOP II
44-pin TSOP II
48-ball FBGA
48-ball FBGA
48-ball FBGA
48-ball FBGA
54-pin TSOP II
54-pin TSOP II
44-pin TSOP II
44-pin TSOP II
48-ball FBGA
48-ball FBGA
48-ball FBGA
48-ball FBGA
54-pin TSOP II
54-pin TSOP II
25
45
All the above parts are Pb-free.
Ordering Code Definitions
CY 14 B 108 L - ZS 20 X I T
Option:
T - Tape & Reel
Blank - Std.
Temperature:
I - Industrial (–40 to 85 °C)
Speed:
20 - 20 ns
Pb-Free
25 - 25 ns
45 - 45 ns
Package:
ZS - 44-pin TSOP II
BA - 48-ball FBGA
ZSP - 54-pin TSOP II
Data Bus:
L - × 8
N - × 16
Density:
108 - 8 Mb
Voltage:
B - 3.0 V
14 - NVSRAM
Cypress
Document Number: 001-45523 Rev. *P
Page 19 of 27
CY14B108L
CY14B108N
Package Diagrams
Figure 15. 44-pin TSOP II Package Outline, 51-85087
51-85087 *E
Document Number: 001-45523 Rev. *P
Page 20 of 27
CY14B108L
CY14B108N
Package Diagrams (continued)
Figure 16. 48-ball FBGA (6 × 10 × 1.2 mm) Package Outline, 51-85128
51-85128 *G
Document Number: 001-45523 Rev. *P
Page 21 of 27
CY14B108L
CY14B108N
Package Diagrams (continued)
Figure 17. 54-pin TSOP II (22.4 × 11.84 × 1.0 mm) Package Outline, 51-85160
51-85160 *E
Document Number: 001-45523 Rev. *P
Page 22 of 27
CY14B108L
CY14B108N
Acronyms
Document Conventions
Units of Measure
Acronym
Description
CMOS
complementary metal oxide semiconductor
byte high enable
Symbol
°C
Unit of Measure
BHE
BLE
degree Celsius
kilohm
byte low enable
k
kHz
MHz
A
F
s
mA
ms
ns
chip enable
CE
kilohertz
EIA
electronic industries alliance
fine-pitch ball grid array
hardware store busy
megahertz
microampere
microfarad
microsecond
milliampere
millisecond
nanosecond
ohm
FBGA
HSB
I/O
input/output
nvSRAM
non-volatile static random access memory
output enable
OE
RoHS
restriction of hazardous substances
read and write inhibited
static random access memory
thin small outline package
write enable
RWI
SRAM
TSOP
WE
%
percent
pF
s
picofarad
second
V
volt
W
watt
Document Number: 001-45523 Rev. *P
Page 23 of 27
CY14B108L
CY14B108N
Errata
This section describes the errata for the 8 Mb (2048 K × 8 and 1024 K × 16) nvSRAM product families. Details include errata trigger
conditions, scope of impact, available workarounds, and silicon revision applicability.
Contact your local Cypress Sales Representative if you have questions. You can also send your related queries directly to
nvSRAM@cypress.com.
Part Numbers Affected
Part Number
CY14B108L
CY14B108N
Device Characteristics
1024 K × 8, Asynchronous Interface nvSRAM in 44 TSOP-II and 48 FBGA package options
512 K × 16, Asynchronous Interface nvSRAM in 54 TSOP-II and 48 FBGA package options
8Mb (1024 K × 8, 512 K × 16) nvSRAM Qualification Status
Production parts.
8Mb (1024 K × 8, 512 K × 16) nvSRAM Errata Summary
The following table defines the errata applicability to available CY14B108L, CY14B108N devices.
Items
Part Number
Silicon Revision
Fix Status
1. AutoStore Disable feature does not work correctly
CY14B108L
CY14B108N
Rev 0
None.
This issue is applicable
toall8MbnvSRAMparts
in production
1. AutoStore Disable feature does not work correctly
■ Problem Definition
The AutoStore Disable soft sequence disables the AutoStore feature in nvSRAMs. The AutoStore Disable feature is used in
applications where data written in the SRAM is not required to be saved automatically on power loss. The 8Mb nvSRAM executes
the nonvolatile Store automatically in half the memory (4Mb) even after the AutoStore feature is disabled. The reason is as follows:
The 8Mb nvSRAM uses two dice stack of 4Mb with HSB pin of each die are tied together. Each nvSRAM die in the stacked-die
monitors the VCC power independently. When the device VCC fails, the die which detects the VCC dropping below VSWITCH first,
internally triggers the power down interrupt and drives its HSB output low. Since the HSB is a bidirectional pin, the low HSB output
driven by one die is detected as HSB input by the other die. Therefore, low on the HSB input of other die internally triggers hardware
Store and executes unintended nonvolatile Store even though AutoStore was disabled by AutoStore Disable soft sequence.
■ Parameters Affected
None.
■ Trigger Condition(S)
Device VCC power down with nvSRAM AutoStore disable.
■ Scope of Impact
It can corrupt the data in half of the memory by overwriting the existing data in its nonvolatile memory with unintended data.
■ Workaround
None. AutoStore disable feature should not be used in 8Mb nvSRAMs.
■ Fix Status
This issue is applicable to all 8Mb nvSRAM parts in production and will continue serving with errata. There is no plan to fix this
issue in the existing parts in production.
Document Number: 001-45523 Rev. *P
Page 24 of 27
CY14B108L
CY14B108N
Document History Page
Document Title: CY14B108L/CY14B108N, 8-Mbit (1024 K × 8/512 K × 16) nvSRAM
Document Number: 001-45523
Orig. of
Change
Submission
Date
Revision
ECN
Description of Change
**
2428826
GVCH
See ECN
06/23/08
New Data Sheet
*A
2520023 GVCH / PYRS
Updated ICC1 for tRC=20ns, 25ns and 45ns access speed for both industrial
and Commercial temperature Grade
UpdatedThermal resistance values for 48-FBGA,44-TSOP II and 54-TSOP
II packages
Changed tCW value from 16ns to 15ns
*B
2676670 GVCH / PYRS 03/20/2009 Added maximum accumulated storage time for 150C and 85C Tempera-
ture
Added best practices
Changed ICC2 from 12mA to 20mA
Changed ICC3 from 38mA to 40mA
Changed ICC4 from 12mA to 10mA
Changed ISB from 6mA to 10mA
Changed VCAP from 164uF to 360uF
Changed Input Rise and Fall Times from 5ns to 3ns
Updated ICC1, ICC3, ISBand IOZ Test conditions
Changed tDELAY to 20ns, 25ns, 25ns for 15ns, 20ns, 45ns part respectively
Changed tSTORE from 15ms to 8ms
Added VHDIS, tHHHD and tLZHSB parameters
Software controlled STORE/RECALL cycle table: Changed tAS to tSA
Changed tGHAX to tHA
Added tDHSB parameter
Changed tHLHX to tPHSB
Updated tSS from 70us to 100us
Added Truth table for SRAM operations
Updated ordering information
*C
*D
2712462 GVCH / PYRS 05/29/2009 Moved data sheet status from Preliminary to Final
Updated AutoStore operation
Updated ISB test condition
Updated footnote 7
Referenced footnote 9 to VCCRISE, tHHHD and tLZHSB parameters
Updated VHDIS parameter description
2746310
GVCH
07/29/2009 Page 4: Updated Hardware STORE (HSB) operation description
page 5: Updated Software STORE description
Updated tDELAY parameter description
Updated footnote 18 and added footnote 23
Referenced footnote 23 to Figure 11 and Figure 12
*E
*F
2759948
2828257
GVCH
GVCH
09/04/2009 Removed commercial temperature related specs
12/15/2009 Changed STORE cycles to QuantumTrap from 200K to 1 Million
Added Contents on page 2
*G
2894560
GVCH
03/18/2010 Removed part numbers CY14B108N-ZSP20XIT and
CY14B108N-ZSP20XI from ordering information table.
Updated Package diagrams 51-85160 and 51-85087.
Updated Sales, Solution, and Legal Information Section.
Updated copyright section.
Updated table of contents.
*H
2923475 GVCH / AESA 04/27/2010 Table 1: Added more clarity on HSB pin operation
Hardware STORE Operation: Added more clarity on HSB pin operation
Table 1: Added more clarity on BHE/BLE pin operation
Updated HSB pin operation in Figure 10
Updated footnote 34
Document Number: 001-45523 Rev. *P
Page 25 of 27
CY14B108L
CY14B108N
Document History Page (continued)
Document Title: CY14B108L/CY14B108N, 8-Mbit (1024 K × 8/512 K × 16) nvSRAM
Document Number: 001-45523
Orig. of
Change
Submission
Date
Revision
ECN
Description of Change
*I
3143765
GVCH
01/17/2011 48-ball FBGA package: 16 Mb address expansion is not supported
Updated thermal resistance values for all packages
Added Acronyms table and Document Conventions table
*J
3311413
GVCH
07/13/2011 Updated DCElectricalCharacteristics(AddedNote9andreferredthesame
note in VCAP parameter).
Updated AC Switching Characteristics (Added Note 13 and referred the
same note in Parameters).
Updated Package Diagrams.
*K
*L
3580269
3658005
GVCH
GVCH
04/12/2012 Updated Package Diagrams.
08/10/2012 Updated Maximum Ratings (Changed “Ambient temperature with power
applied” to “Maximum junction temperature”).
Updated DC Electrical Characteristics (Added VVCAP parameter and its
details, added Note 11 and referred the same note in VVCAP parameter, also
referred Note 12 in VVCAP parameter).
Updated Package Diagrams (spec 51-85160 (Changed revision from *C to
*D)).
*M
4500772
ZSK
09/12/2014 Updated Package Diagrams:
spec 51-85087 – Changed revision from *D to *E.
spec 51-85160 – Changed revision from *D to *E.
Added Errata.
Updated to new template.
*N
*O
4563189
4714292
ZSK
11/12/2014 Added related documentation hyperlink in page 1
GVCH
04/08/2015 No technical updates.
Completing Sunset Review.
*P
5705809
AESATMP7
04/21/2017 Updated Cypress Logo and Copyright.
Document Number: 001-45523 Rev. *P
Page 26 of 27
CY14B108L
CY14B108N
Sales, Solutions, and Legal Information
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© Cypress Semiconductor Corporation, 2008-2017. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document,
including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
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Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in
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Document Number: 001-45523 Rev. *P
Revised April 21, 2017
Page 27 of 27
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