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CY14B256KA-SP45XI [INFINEON]

nvSRAM (non-volatile SRAM);
CY14B256KA-SP45XI
型号： CY14B256KA-SP45XI
厂家： Infineon    Infineon
描述：

nvSRAM (non-volatile SRAM)

时钟 双倍数据速率 静态存储器 光电二极管 外围集成电路
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Please note that Cypress is an Infineon Technologies Company.  
The document following this cover page is marked as “Cypress” document as this is the  
company that originally developed the product. Please note that Infineon will continue  
to offer the product to new and existing customers as part of the Infineon product  
portfolio.  
Continuity of document content  
The fact that Infineon offers the following product as part of the Infineon product  
portfolio does not lead to any changes to this document. Future revisions will occur  
when appropriate, and any changes will be set out on the document history page.  
Continuity of ordering part numbers  
Infineon continues to support existing part numbers. Please continue to use the  
ordering part numbers listed in the datasheet for ordering.  
www.infineon.com  
CY14B256KA  
256-Kbit (32 K × 8) nvSRAM with  
Real Time Clock  
256-Kbit (32  
K × 8) nvSRAM with Real Time Clock  
■ Industry standard configurations  
❐ Single 3 V +20%, –10% operation  
❐ Industrial temperature  
❐ 48-pin shrink small-outline package (SSOP)  
❐ Pb-free and Restriction of hazardous substances (RoHS)  
compliant  
Features  
■ 256-Kbit nonvolatile static random access memory (nvSRAM)  
❐ 25 ns and 45 ns access times  
❐ Internally organized as 32 K × 8 (CY14B256KA)  
❐ HandsoffautomaticSTOREonpower-downwithonlyasmall  
capacitor  
Functional Description  
❐ STORE to QuantumTrap nonvolatile elements is initiated by  
software, hardware, or AutoStore on power-down  
The Cypress CY14B256KA combines a 256-Kbit nonvolatile  
static RAM with a full featured real time clock in a monolithic  
integrated circuit. The embedded nonvolatile elements  
incorporate QuantumTrap technology producing the world’s  
most reliable nonvolatile memory. The SRAM is read and written  
an infinite number of times, while independent nonvolatile data  
resides in the nonvolatile elements.  
❐ RECALL to SRAM initiated on power-up or by software  
■ High reliability  
❐ Infinite Read, Write, and RECALL cycles  
❐ 1 million STORE cycles to QuantumTrap  
❐ 20 year data retention  
■ Real time clock (RTC)  
The real time clock function provides an accurate clock with leap  
year tracking and a programmable, high accuracy oscillator. The  
alarm function is programmable for periodic minutes, hours,  
days, or months alarms. There is also a programmable watchdog  
timer for process control.  
❐ Full-featured real time clock  
❐ Watchdog timer  
❐ Clock alarm with programmable interrupts  
❐ Capacitor or battery backup for RTC  
❐ Backup current of 0.35 µA (Typ)  
For a complete list of related documentation, click here.  
Logic Block Diagram  
V
CC  
V
CAP  
QuantumTrap  
512 X 512  
V
RTCbat  
POWER  
A5  
STORE  
CONTROL  
V
RTCcap  
A6  
A7  
A8  
RECALL  
STORE/  
RECALL  
CONTROL  
STATIC RAM  
ARRAY  
512 X 512  
HSB  
A9  
A11  
A12  
A13  
A14  
SOFTWARE  
DETECT  
A14  
-
A0  
DQ0  
COLUMN IO  
DQ1  
DQ2  
DQ3  
COLUMN DEC  
xout  
xin  
RTC  
MUX  
INT  
DQ4  
DQ5  
DQ6  
DQ7  
A0  
A4  
A10  
A1  
A3  
A2  
A14  
-
A0  
OE  
CE  
WE  
Cypress Semiconductor Corporation  
Document Number: 001-55720 Rev. *I  
•
198 Champion Court  
•
San Jose, CA 95134-1709  
•
408-943-2600  
Revised November 14, 2014  
CY14B256KA  
Contents  
Pinouts ..............................................................................3  
Pin Definitions ..................................................................3  
Device Operation ..............................................................4  
SRAM Read ................................................................4  
SRAM Write .................................................................4  
AutoStore Operation ....................................................4  
Hardware STORE (HSB) Operation ............................4  
Hardware RECALL (Power-Up) ..................................5  
Software STORE .........................................................5  
Software RECALL .......................................................5  
Preventing AutoStore ..................................................6  
Data Protection ............................................................6  
Real Time Clock Operation ..............................................7  
nvTIME Operation .......................................................7  
Clock Operations .........................................................7  
Reading the Clock .......................................................7  
Setting the Clock .........................................................7  
Backup Power .............................................................7  
Stopping and Starting the Oscillator ............................7  
Calibrating the Clock ...................................................8  
Alarm ...........................................................................8  
Watchdog Timer ..........................................................8  
Power Monitor .............................................................9  
Interrupts .....................................................................9  
Interrupt Register .........................................................9  
Flags Register .............................................................9  
RTC External Components .......................................10  
PCB Design Considerations for RTC ............................11  
Layout requirements ..................................................11  
Maximum Ratings ...........................................................16  
Operating Range .............................................................16  
DC Electrical Characteristics ........................................16  
Data Retention and Endurance .....................................17  
Capacitance ....................................................................17  
Thermal Resistance ........................................................17  
AC Test Loads ................................................................18  
AC Test Conditions ........................................................18  
RTC Characteristics .......................................................18  
AC Switching Characteristics .......................................19  
SRAM Read Cycle ....................................................19  
SRAM Write Cycle .....................................................19  
AutoStore/Power-Up RECALL .......................................21  
Switching Waveforms ....................................................21  
Software Controlled STORE/RECALL Cycle ................22  
Switching Waveforms ....................................................22  
Hardware STORE Cycle .................................................23  
Switching Waveforms ....................................................23  
Truth Table For SRAM Operations ................................24  
Ordering Information ......................................................24  
Ordering Code Definitions .........................................24  
Package Diagram ............................................................25  
Acronyms ........................................................................26  
Document Conventions .................................................26  
Units of Measure .......................................................26  
Document History Page .................................................27  
Sales, Solutions, and Legal Information ......................28  
Worldwide Sales and Design Support .......................28  
Products ....................................................................28  
PSoC® Solutions ......................................................28  
Cypress Developer Community .................................28  
Technical Support .....................................................28  
Document Number: 001-55720 Rev. *I  
Page 2 of 28  
CY14B256KA  
Pinouts  
Figure 1. 48-pin SSOP pinout  
VCAP  
[1]  
48  
47  
V
CC  
1
2
3
[1]  
NC  
NC  
A
14  
A12  
A
7
46  
45  
44  
43  
42  
HSB  
WE  
A13  
A8  
4
5
6
7
8
9
10  
11  
12  
13  
14  
A
6
A
5
INT  
A
4
A
9
41  
40  
NC  
A
48 - SSOP  
(x8)  
11  
NC  
NC  
NC  
VSS  
39  
NC  
NC  
NC  
V
SS  
NC  
38  
37  
36  
Top View  
(not to scale)  
NC  
VRTCbat  
35  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
VRTCcap  
34  
33  
32  
31  
DQ0  
A
DQ6  
OE  
A10  
3
A
2
A
1
30  
29  
28  
27  
26  
25  
CE  
DQ7  
A
0
DQ1  
DQ2  
Xout  
Xin  
DQ5  
DQ4  
DQ3  
V
CC  
Pin Definitions  
Pin Name  
I/O Type  
Input  
Description  
Address inputs. Used to select One of the 32,768 bytes of the nvSRAM.  
A0–A14  
DQ0–DQ7 Input/Output Bidirectional data I/O Lines. Used as input or output lines depending on operation.  
NC  
No connect No connect. This pin is not connected to the die.  
Input  
Write Enable input, Active LOW. When the chip is enabled and WE is LOW, data on the I/O pins is written  
to the specific address location.  
WE  
Input  
Input  
Chip Enable input, Active LOW. When LOW, selects the chip. When HIGH, deselects the chip.  
CE  
OE  
Output Enable, Active LOW. The active LOW OE input enables the data output buffers during read cycles.  
Deasserting OE HIGH causes the I/O pins to tristate.  
[2]  
Xout  
Output  
Input  
Crystal connection. Drives crystal on start up.  
Crystal connection. For 32.768 kHz crystal.  
[2]  
Xin  
[2]  
VRTCcap  
Power supply Capacitor supplied backup RTC supply voltage. Left unconnected if VRTCbat is used.  
Power supply Battery supplied backup RTC supply voltage. Left unconnected if VRTCcap is used.  
[2]  
VRTCbat  
INT[2]  
Output  
Interrupt output. Programmable to respond to the clock alarm, the watchdog timer, and the power  
monitor. Also programmable to either active HIGH (push or pull) or LOW (open drain).  
VSS  
VCC  
Ground  
Ground for the device. Must be connected to the ground of the system.  
Power supply Power supply inputs to the Device. 3.0 V +20%, –10%  
Input/Output Hardware STORE Busy (HSB)  
HSB  
Output: Indicates busy status of nvSRAM when LOW. After each Hardware and Software STORE  
operation, HSB is driven HIGH for a short time (tHHHD) with standard output high current and then a  
weak internal pull-up resistor keeps this pin HIGH (external pull-up resistor connection optional).  
Input: Hardware STORE implemented by pulling this pin LOW externally.  
VCAP  
Power supply AutoStore capacitor. Supplies power to the nvSRAM during power loss to store data from SRAM to  
nonvolatile elements.  
Notes  
1. Address expansion for 1-Mbit. NC pin not connected to die.  
2. Left unconnected if RTC feature is not used.  
Document Number: 001-55720 Rev. *I  
Page 3 of 28  
CY14B256KA  
Figure 2. AutoStore Mode  
Device Operation  
VCC  
The CY14B256KA nvSRAM is made up of two functional  
components paired in the same physical cell. These are a SRAM  
memory cell and a nonvolatile QuantumTrap cell. The SRAM  
memory cell operates as a standard fast static RAM. Data in the  
SRAM is transferred to the nonvolatile cell (the STORE  
operation), or from the nonvolatile cell to the SRAM (the RECALL  
operation). Using this unique architecture, all cells are stored and  
recalled in parallel. During the STORE and RECALL operations  
SRAM read and write operations are inhibited. The  
CY14B256KA supports infinite reads and writes similar to a  
typical SRAM. In addition, it provides infinite RECALL operations  
from the nonvolatile cells and up to 1 million STORE operations.  
Refer the Truth Table For SRAM Operations on page 24 for a  
complete description of read and write modes.  
0.1 uF  
VCC  
WE  
VCAP  
VCAP  
VSS  
SRAM Read  
The CY14B256KA performs a read cycle whenever CE and OE  
are LOW, and WE and HSB are HIGH. The address specified on  
pins A0–14 determines which of the 32,768 data bytes are  
accessed. When the read is initiated by an address transition,  
the outputs are valid after a delay of tAA (read cycle #1). If the  
read is initiated by CE or OE, the outputs are valid at tACE or at  
tDOE, whichever is later (read cycle #2). The data output  
repeatedly responds to address changes within the tAA access  
time without the need for transitions on any control input pins.  
This remains valid until another address change or until CE or  
OE is brought HIGH, or WE or HSB is brought LOW.  
Figure 2 shows the proper connection of the storage capacitor  
(VCAP) for automatic STORE operation. Refer to DC Electrical  
Characteristics on page 16 for the size of the VCAP. The voltage  
on the VCAP pin is driven to VCC by a regulator on the chip. Place  
a pull-up on WE to hold it inactive during power-up. This pull-up  
is only effective if the WE signal is tristate during power-up. Many  
MPUs tristate their controls on power-up. This must be verified  
when using the pull-up. When the nvSRAM comes out of  
power-on-RECALL, the MPU must be active or the WE held  
inactive until the MPU comes out of reset.  
SRAM Write  
To reduce unnecessary nonvolatile stores, AutoStore and  
Hardware STORE operations are ignored unless at least one  
write operation has taken place since the most recent STORE or  
RECALL cycle. Software initiated STORE cycles are performed  
regardless of whether a write operation has taken place.  
A write cycle is performed when CE and WE are LOW and HSB  
is HIGH. The address inputs must be stable before entering the  
write cycle and must remain stable until CE or WE goes HIGH at  
the end of the cycle. The data on the common I/O pins IO0–7 are  
written into the memory if it is valid tSD before the end of a  
WE-controlled write, or before the end of an CE-controlled write.  
It is recommended that OE be kept HIGH during the entire write  
cycle to avoid data bus contention on common I/O lines. If OE is  
left LOW, internal circuitry turns off the output buffers tHZWE after  
WE goes LOW.  
Hardware STORE (HSB) Operation  
The CY14B256KA provides the HSB pin to control and  
acknowledge the STORE operations. The HSB pin is used to  
request a Hardware STORE cycle. When the HSB pin is driven  
LOW, the CY14B256KA conditionally initiates a STORE  
operation after tDELAY. An actual STORE cycle begins only if a  
write to the SRAM has taken place since the last STORE or  
RECALL cycle. The HSB pin also acts as an open drain driver  
(internal 100 kweak pull-up resistor) that is internally driven  
LOW to indicate a busy condition when the STORE (initiated by  
any means) is in progress.  
AutoStore Operation  
The CY14B256KA stores data to the nvSRAM using one of three  
storage operations. These three operations are: Hardware  
STORE, activated by the HSB; Software STORE, activated by  
an address sequence; AutoStore, on device power-down. The  
AutoStore operation is a unique feature of QuantumTrap  
technology and is enabled by default on the CY14B256KA.  
Note After each Hardware and Software STORE operation HSB  
is driven HIGH for a short time (tHHHD) with standard output high  
current and then remains HIGH by internal 100 kpull-up  
resistor.  
During normal operation, the device draws current from VCC to  
charge a capacitor connected to the VCAP pin. This stored  
charge is used by the chip to perform a single STORE operation.  
If the voltage on the VCC pin drops below VSWITCH, the part  
automatically disconnects the VCAP pin from VCC. A STORE  
operation is initiated with power provided by the VCAP capacitor.  
SRAM write operations that are in progress when HSB is driven  
LOW by any means are given time (tDELAY) to complete before  
the STORE operation is initiated. However, any SRAM write  
cycles requested after HSB goes LOW are inhibited until HSB  
returns HIGH. In case the write latch is not set, HSB is not driven  
LOW by the CY14B256KA. But any SRAM read and write cycles  
are inhibited until HSB is returned HIGH by MPU or other  
external source.  
Note If the capacitor is not connected to VCAP pin, AutoStore  
must be disabled using the soft sequence specified in Preventing  
AutoStore on page 6. In case AutoStore is enabled without a  
capacitor on VCAP pin, the device attempts an AutoStore  
operation without sufficient charge to complete the Store. This  
corrupts the data stored in nvSRAM.  
During any STORE operation, regardless of how it is initiated,  
the CY14B256KA continues to drive the HSB pin LOW, releasing  
Document Number: 001-55720 Rev. *I  
Page 4 of 28  
CY14B256KA  
it only when the STORE is complete. Upon completion of the  
STORE operation, the nvSRAM memory access is inhibited for  
tLZHSB time after HSB pin returns HIGH. Leave the HSB  
unconnected if it is not used.  
4. Read address 0x3C1F Valid READ  
5. Read address 0x303F Valid READ  
6. Read address 0x0FC0 Initiate STORE cycle  
The software sequence may be clocked with CE controlled reads  
or OE controlled reads, with WE kept HIGH for all the six READ  
sequences. After the sixth address in the sequence is entered,  
the STORE cycle commences and the chip is disabled. HSB is  
driven LOW. After the tSTORE cycle time is fulfilled, the SRAM is  
activated again for the read and write operation.  
Hardware RECALL (Power-Up)  
During power-up or after any low power condition  
(VCC< VSWITCH), an internal RECALL request is latched. When  
VCC again exceeds the VSWITCH on powerup, a RECALL cycle  
is automatically initiated and takes tHRECALL to complete. During  
this time, the HSB pin is driven LOW by the HSB driver and all  
reads and writes to nvSRAM are inhibited.  
Software RECALL  
Data is transferred from the nonvolatile memory to the SRAM by  
a software address sequence. A Software RECALL cycle is  
initiated with a sequence of read operations in a manner similar  
to the Software STORE initiation. To initiate the RECALL cycle,  
the following sequence of CE or OE controlled read operations  
must be performed:  
Software STORE  
Data is transferred from the SRAM to the nonvolatile memory by  
a software address sequence. The CY14B256KA Software  
STORE cycle is initiated by executing sequential CE or OE  
controlled read cycles from six specific address locations in  
exact order. During the STORE cycle, an erase of the previous  
nonvolatile data is first performed, followed by a program of the  
nonvolatile elements. After a STORE cycle is initiated, further  
input and output are disabled until the cycle is completed.  
1. Read address 0x0E38 Valid READ  
2. Read address 0x31C7 Valid READ  
3. Read address 0x03E0 Valid READ  
4. Read address 0x3C1F Valid READ  
5. Read address 0x303F Valid READ  
6. Read address 0x0C63 Initiate RECALL cycle  
Because a sequence of reads from specific addresses is used  
for STORE initiation, it is important that no other read or write  
accesses intervene in the sequence, or the sequence is aborted  
and no STORE or RECALL takes place.  
Internally, RECALL is a two step procedure. First, the SRAM data  
is cleared. Next, the nonvolatile information is transferred into the  
SRAM cells. After the tRECALL cycle time, the SRAM is again  
ready for read and write operations. The RECALL operation  
does not alter the data in the nonvolatile elements.  
To initiate the Software STORE cycle, the following read  
sequence must be performed:  
1. Read address 0x0E38 Valid READ  
2. Read address 0x31C7 Valid READ  
3. Read address 0x03E0 Valid READ  
Document Number: 001-55720 Rev. *I  
Page 5 of 28  
CY14B256KA  
Table 1. Mode Selection  
[3]  
Mode  
I/O  
Power  
A14–A0  
CE  
WE  
OE  
H
X
H
L
X
X
Not Selected  
Read SRAM  
Write SRAM  
Output High Z  
Output Data  
Input Data  
Standby  
Active  
L
L
L
L
X
L
X
X
Active  
Active[4]  
H
0x0E38  
0x31C7  
0x03E0  
0x3C1F  
0x303F  
0x0B45  
Read SRAM  
Read SRAM  
Read SRAM  
Read SRAM  
Read SRAM  
AutoStore  
Output Data  
Output Data  
Output Data  
Output Data  
Output Data  
Output Data  
Disable  
L
L
H
H
L
L
0x0E38  
0x31C7  
0x03E0  
0x3C1F  
0x303F  
0x0B46  
Read SRAM  
Read SRAM  
Read SRAM  
Read SRAM  
Read SRAM  
AutoStore Enable  
Output Data  
Output Data  
Output Data  
Output Data  
Output Data  
Output Data  
Active[4]  
[4]  
0x0E38  
0x31C7  
0x03E0  
0x3C1F  
0x303F  
0x0FC0  
Read SRAM  
Read SRAM  
Read SRAM  
Read SRAM  
Read SRAM  
Nonvolatile  
STORE  
Output Data  
Output Data  
Output Data  
Output Data  
Output Data  
Output High Z  
Active ICC2  
L
H
L
0x0E38  
0x31C7  
0x03E0  
0x3C1F  
0x303F  
0x0C63  
Read SRAM  
Read SRAM  
Read SRAM  
Read SRAM  
Read SRAM  
Nonvolatile  
RECALL  
Output Data  
Output Data  
Output Data  
Output Data  
Output Data  
Output High Z  
Active[4]  
1. Read address 0x0E38 Valid READ  
2. Read address 0x31C7 Valid READ  
3. Read address 0x03E0 Valid READ  
4. Read address 0x3C1F Valid READ  
5. Read address 0x303F Valid READ  
6. Read address 0x0B46 AutoStore Enable  
Preventing AutoStore  
The AutoStore function is disabled by initiating an AutoStore  
disable sequence. A sequence of read operations is performed  
in a manner similar to the Software STORE initiation. To initiate  
the AutoStore disable sequence, the following sequence of CE  
or OE controlled read operations must be performed:  
If the AutoStore function is disabled or re-enabled, a manual  
STORE operation (Hardware or Software) issued to save the  
AutoStore state through subsequent power-down cycles. The  
part comes from the factory with AutoStore enabled and 0x00  
written in all cells.  
1. Read address 0x0E38 Valid READ  
2. Read address 0x31C7 Valid READ  
3. Read address 0x03E0 Valid READ  
4. Read address 0x3C1F Valid READ  
5. Read address 0x303F Valid READ  
6. Read address 0x0B45 AutoStore Disable  
Data Protection  
The CY14B256KA protects data from corruption during low  
voltage conditions by inhibiting all externally initiated STORE  
and write operations. The low voltage condition is detected when  
The AutoStore is reenabled by initiating an AutoStore enable  
sequence. A sequence of read operations is performed in a  
manner similar to the Software RECALL initiation.  
VCC is less than VSWITCH. If the CY14B256KA is in a write mode  
(both CE and WE are LOW) at power-up, after a RECALL or  
STORE, the write is inhibited until the SRAM is enabled after  
tLZHSB (HSB to output active). This protects against inadvertent  
writes during power-up or brown out conditions.  
To initiate the AutoStore enable sequence, the following  
sequence of CE or OE controlled read operations must be  
performed:  
Notes  
3. While there are 15 address lines on the CY14B256KA, only the lower 14 are used to control software modes.  
4. The six consecutive address locations must be in the order listed. WE must be HIGH during all six cycles to enable a nonvolatile cycle.  
Document Number: 001-55720 Rev. *I  
Page 6 of 28  
CY14B256KA  
Software/Hardware STORE or AutoStore operation. While  
working in AutoStore disabled mode, perform a STORE  
operation after tRTCp time while writing into the RTC registers for  
the modifications to be correctly recorded.  
Real Time Clock Operation  
nvTIME Operation  
The CY14B256KA offers internal registers that contain clock,  
alarm, watchdog, interrupt, and control functions. RTC registers  
use the last 16 address locations of the SRAM. Internal double  
buffering of the clock and timer information registers prevents  
accessing transitional internal clock data during a read or write  
operation. Double buffering also circumvents disrupting normal  
timing counts or the clock accuracy of the internal clock when  
accessing clock data. Clock and alarm registers store data in  
BCD format.  
Backup Power  
The RTC in the CY14B256KA is intended for permanently  
powered operation. The VRTCcap or VRTCbat pin is connected  
depending on whether a capacitor or battery is chosen for the  
application. When the primary power, VCC, fails and drops below  
VSWITCH the device switches to the backup power supply.  
The clock oscillator uses very little current, which maximizes the  
backup time available from the backup source. Regardless of the  
clock operation with the primary source removed, the data stored  
in the nvSRAM is secure, having been stored in the nonvolatile  
elements when power was lost.  
RTC functionality is described in the following sections. The RTC  
register addresses for CY14B256KA range from 0x7FF0 to  
0x7FFF. Refer to Table 3 on page 12 and Table 4 on page 13 for  
a detailed Register Map description.  
During backup operation, the CY14B256KA consumes a  
0.35 µA (Typ) at room temperature. The user must choose  
capacitor or battery values according to the application.  
Clock Operations  
The clock registers maintain time up to 9,999 years in  
one-second increments. The time can be set to any calendar  
time and the clock automatically keeps track of days of the week  
and month, leap years, and century transitions. There are eight  
registers dedicated to the clock functions, which are used to set  
time with a write cycle and to read time with a read cycle. These  
registers contain the time of day in BCD format. Bits defined as  
‘0’ are currently not used and are reserved for future use by  
Cypress.  
Note: If a battery is applied to VRTCbat pin prior to VCC, the chip  
will draw high IBAK current. This occurs even if the oscillator is  
disabled. In order to maximize battery life, VCC must be applied  
before a battery is applied to VRTCbat pin.  
Backup time values based on maximum current specifications  
are shown in the following Table 2. Nominal backup times are  
approximately two times longer.  
Table 2. RTC Backup Time  
Reading the Clock  
Capacitor Value  
0.1 F  
Backup Time  
72 hours  
14 days  
The double buffered RTC register structure reduces the chance  
of reading incorrect data from the clock. Internal updates to the  
CY14B256KA time keeping registers are stopped when the read  
bit ‘R’ (in the flags register at 0x7FF0) is set to ‘1’ before reading  
clock data to prevent reading of data in transition. Stopping the  
register updates does not affect clock accuracy.  
0.47 F  
1.0 F  
30 days  
Using a capacitor has the obvious advantage of recharging the  
backup source each time the system is powered up. If a battery  
is used, a 3 V lithium is recommended and the CY14B256KA  
sources current only from the battery when the primary power is  
removed. However, the battery is not recharged at any time by  
the CY14B256KA. The battery capacity must be chosen for total  
anticipated cumulative down time required over the life of the  
system.  
When a read sequence of RTC device is initiated, the update of  
the user timekeeping registers stops and does not restart until a  
‘0’ is written to the read bit ‘R’ (in the flags register at 0x7FF0).  
After the end of read sequence, all the RTC registers are simul-  
taneously updated within 20 ms.  
Setting the Clock  
Stopping and Starting the Oscillator  
A write access to the RTC device stops updates to the time  
keeping registers and enables the time to be set when the write  
bit ‘W’ (in the flags register at 0x7FF0) is set to ‘1’. The correct  
day, date, and time is then written into the registers and must be  
in 24 hour BCD format. The time written is referred to as the  
“Base Time”. This value is stored in nonvolatile registers and  
used in the calculation of the current time. When the write bit ‘W’  
is cleared by writing ‘0’ to it, the values of timekeeping registers  
are transferred to the actual clock counters after which the clock  
resumes normal operation.  
The OSCEN bit in the calibration register at 0x7FF8 controls the  
enable and disable of the oscillator. This bit is nonvolatile and is  
shipped to customers in the “enabled” (set to ‘0’) state. To  
preserve the battery life when the system is in storage, OSCEN  
must be set to ‘1’. This turns off the oscillator circuit, extending  
the battery life. If the OSCEN bit goes from disabled to enabled,  
it takes approximately one second (two seconds maximum) for  
the oscillator to start.  
While system power is off, if the voltage on the backup supply  
(VRTCcap or VRTCbat) falls below their respective minimum level,  
the oscillator may fail.The CY14B256KA has the ability to detect  
oscillator failure when system power is restored. This is recorded  
in the Oscillator Fail Flag (OSCF) of the flags register at the  
address 0x7FF0. When the device is powered on (VCC goes  
above VSWITCH) the OSCEN bit is checked for the ‘enabled’  
status. If the OSCEN bit is enabled and the oscillator is not active  
If the time written to the timekeeping registers is not in the correct  
BCD format, each invalid nibble of the RTC registers continue  
counting to 0xF before rolling over to 0x0 after which RTC  
resumes normal operation.  
Note After ‘W’ bit is set to ‘0’, values written into the timekeeping,  
alarm, calibration, and interrupt registers are transferred to the  
RTC time keeping counters in tRTCp time. These counter values  
must be saved to nonvolatile memory either by initiating a  
Document Number: 001-55720 Rev. *I  
Page 7 of 28  
CY14B256KA  
within the first 5 ms, the OSCF bit is set to ‘1’. The system must  
check for this condition and then write ‘0’ to clear the flag.  
Alarm  
The alarm function compares user programmed values of alarm  
time and date (stored in the registers 0x7FF1-5) with the corre-  
sponding time of day and date values. When a match occurs, the  
alarm internal flag (AF) is set and an interrupt is generated on  
INT pin if Alarm Interrupt Enable (AIE) bit is set.  
Note that in addition to setting the OSCF flag bit, the time  
registers are reset to the ‘Base Time’, which is the value last  
written to the timekeeping registers. The control or calibration  
registers and the OSCEN bit are not affected by the ‘oscillator  
failed’ condition.  
There are four alarm match fields – date, hours, minutes, and  
seconds. Each of these fields has a match bit that is used to  
determine if the field is used in the alarm match logic. Setting the  
match bit to ‘0’ indicates that the corresponding field is used in  
the match process. Depending on the match bits, the alarm  
occurs as specifically as once a month or as frequently as once  
every minute. Selecting none of the match bits (all 1s) indicates  
that no match is required and therefore, alarm is disabled.  
Selecting all match bits (all 0s) causes an exact time and date  
match.  
The value of OSCF must be reset to ‘0’ when the time registers  
are written for the first time. This initializes the state of this bit  
which may have become set when the system was first powered  
on.  
To reset OSCF, set the write bit ‘W’ (in the flags register at  
0x7FF0) to a ‘1’ to enable writes to the flags register . Write a ‘0’  
to the OSCF bit and then reset the write bit to ‘0’ to disable writes.  
Calibrating the Clock  
The RTC is driven by a quartz controlled crystal with a nominal  
frequency of 32.768 kHz. Clock accuracy depends on the quality  
of the crystal and calibration. The crystals available in market  
typically have an error of +20 ppm to +35 ppm. However,  
CY14B256KA employs a calibration circuit that improves the  
accuracy to +1/–2 ppm at 25 °C. This implies an error of +2.5  
seconds to –5 seconds per month.  
There are two ways to detect an alarm event: by reading the AF  
flag or monitoring the INT pin. The AF flag in the flags register  
at 0x7FF0 indicates that a date or time match has occurred. The  
AF bit is set to ‘1’ when a match occurs. Reading the flags  
register clears the alarm flag bit (and all others). A hardware  
interrupt pin may also be used to detect an alarm event.  
To set, clear or enable an alarm, set the ‘W’ bit (in flags register  
– 0x7FF0) to ‘1’ to enable writes to Alarm Registers. After writing  
the alarm value, clear the ‘W’ bit back to ‘0’ for the changes to  
take effect.  
The calibration circuit adds or subtracts counts from the oscillator  
divider circuit to achieve this accuracy. The number of pulses that  
are suppressed (subtracted, negative calibration) or split (added,  
positive calibration) depends upon the value loaded into the five  
calibration bits found in Calibration register at 0x7FF8. The  
calibration bits occupy the five lower order bits in the Calibration  
register. These bits are set to represent any value between ‘0’  
and 31 in binary form. Bit D5 is a sign bit, where a ‘1’ indicates  
positive calibration and a ‘0’ indicates negative calibration.  
Adding counts speeds the clock up and subtracting counts slows  
the clock down. If a binary ‘1’ is loaded into the register, it  
corresponds to an adjustment of 4.068 or –2.034 ppm offset in  
oscillator error, depending on the sign.  
Note CY14B256KA requires the alarm match bit for seconds (bit  
‘D7’ in Alarm-Seconds register 0x7FF2) to be set to ‘0’ for proper  
operation of Alarm Flag and Interrupt..  
Watchdog Timer  
The watchdog timer is a free running down counter that uses the  
32 Hz clock (31.25 ms) derived from the crystal oscillator. The  
oscillator must be running for the watchdog to function. It begins  
counting down from the value loaded in the watchdog timer  
register.  
Calibration occurs within a 64-minute cycle. The first 62 minutes  
in the cycle may, once every minute, have one second shortened  
by 128 or lengthened by 256 oscillator cycles. If a binary ‘1’ is  
loaded into the register, only the first two minutes of the  
64-minute cycle are modified. If a binary 6 is loaded, the first 12  
are affected, and so on. Therefore, each calibration step has the  
effect of adding 512 or subtracting 256 oscillator cycles for every  
125,829,120 actual oscillator cycles, that is, 4.068 or –2.034 ppm  
of adjustment per calibration step in the Calibration register.  
The timer consists of a loadable register and a free running  
counter. On power-up, the watchdog time out value in register  
0x7FF7 is loaded into the counter load register. Counting begins  
on power-up and restarts from the loadable value any time the  
watchdog strobe (WDS) bit is set to ‘1’. The counter is compared  
to the terminal value of ‘0’. If the counter reaches this value, it  
causes an internal flag and an optional interrupt output. You can  
prevent the time out interrupt by setting WDS bit to ‘1’ prior to the  
counter reaching ‘0’. This causes the counter to reload with the  
watchdog time out value and to be restarted. As long as the user  
sets the WDS bit prior to the counter reaching the terminal value,  
the interrupt and WDT flag never occur.  
To determine the required calibration, the CAL bit in the flags  
register (0x7FF0) must be set to ‘1’. This causes the INT pin to  
toggle at a nominal frequency of 512 Hz. Any deviation  
measured from the 512 Hz indicates the degree and direction of  
the required correction. For example, a reading of 512.01024 Hz  
indicates a +20 ppm error. Hence, a decimal value of –10  
(001010b) must be loaded into the Calibration register to offset  
this error.  
New time out values are written by setting the watchdog write bit  
to ‘0’. When the WDW is ‘0’, new writes to the watchdog time out  
value bits D5–D0 are enabled to modify the time out value. When  
WDW is ‘1’, writes to bits D5–D0 are ignored. The WDW function  
enables a user to set the WDS bit without concern that the  
watchdog timer value is modified. A logical diagram of the  
watchdog timer is shown in Figure 3. Note that setting the  
watchdog time out value to ‘0’ disables the watchdog function.  
Note Setting or changing the Calibration register does not affect  
the test output frequency.  
To set or clear CAL, set the write bit ‘W’ (in the flags register at  
0x7FF0) to ‘1’ to enable writes to the flags register . Write a value  
to CAL, and then reset the write bit to ‘0’ to disable writes.  
The output of the watchdog timer is the flag bit WDF that is set if  
the watchdog is allowed to time out. If the watchdog interrupt  
enable (WIE) bit in the interrupt register is set, a hardware  
Document Number: 001-55720 Rev. *I  
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CY14B256KA  
interrupt on INT pin is also generated on watchdog timeout. The  
flag and the hardware interrupt are both cleared when user reads  
internally fixed at approximately 200 ms. This mode is intended  
to reset a host microcontroller. In the level mode, the pin goes to  
its active polarity until the flags register is read by the user. This  
mode is used as an interrupt to a host microcontroller. The  
control bits are summarized in the following section.  
the flags register.  
.
Figure 3. Watchdog Timer Block Diagram  
Interrupts are only generated while working on normal power and  
are not triggered when system is running in backup power mode.  
Clock  
Oscillator  
1 Hz  
Divider  
32,768 KHz  
32 Hz  
Note CY14B256KA generates valid interrupts only after the  
Powerup RECALL sequence is completed. All events on INT pin  
must be ignored for tHRECALL duration after powerup.  
Zero  
Compare  
WDF  
Counter  
Interrupt Register  
Load  
Watchdog Interrupt Enable (WIE). When set to ‘1’, the  
watchdog timer drives the INT pin and an internal flag when a  
watchdog time out occurs. When WIE is set to ‘0’, the watchdog  
timer only affects the WDF flag in flags register.  
WDS  
Register  
Q
D
WDW  
Alarm Interrupt Enable (AIE). When set to ‘1’, the alarm match  
drives the INT pin and an internal flag. When AIE is set to ‘0’, the  
alarm match only affects the AF flag in flags register.  
Q
Watchdog  
Register  
write to  
Watchdog  
Register  
Power Fail Interrupt Enable (PFE). When set to ‘1’, the power  
fail monitor drives the pin and an internal flag. When PFE is set  
to ‘0’, the power fail monitor only affects the PF flag in flags  
register.  
Power Monitor  
The CY14B256KA provides a power management scheme with  
power fail interrupt capability. It also controls the internal switch  
to backup power for the clock and protects the memory from low  
High/Low (H/L). When set to a ‘1’, the INT pin is active HIGH  
and the driver mode is push pull. The INT pin drives high only  
when VCC is greater than VSWITCH. When set to a ‘0’, the INT pin  
is active LOW and the drive mode is open drain. The INT pin  
must be pulled up to Vcc by a 10 k resistor while using the  
interrupt in active LOW mode.  
VCC access. The power monitor is based on an internal band gap  
reference circuit that compares the VCC voltage to VSWITCH  
threshold.  
As described in the AutoStore Operation on page 4, when  
VSWITCH is reached as VCC decays from power loss, a data  
STORE operation is initiated from SRAM to the nonvolatile  
elements, securing the last SRAM data state. Power is also  
switched from VCC to the backup supply (battery or capacitor) to  
operate the RTC oscillator.  
Pulse/Level (P/L). When set to a ‘1’ and an interrupt occurs, the  
INT pin is driven for approximately 200 ms. When P/L is set to a  
‘0’, the INT pin is driven high or low (determined by H/L) until the  
flags register is read.  
When an enabled interrupt source activates the INT pin, an  
external host reads the flags register to determine the cause. All  
flags are cleared when the register is read. If the INT pin is  
programmed for level mode, then the condition clears and the  
INT pin returns to its inactive state. If the pin is programmed for  
pulse mode, then reading the flag also clears the flag and the pin.  
The pulse does not complete its specified duration if the flags  
register is read. If the INT pin is used as a host reset, then the  
flags register is not read during a reset.  
When operating from the backup source, read and write  
operations to nvSRAM are inhibited and the RTC functions are  
not available to the user. The RTC clock continues to operate in  
the background. The updated RTC time keeping registers data  
are available to the user after VCC is restored to the device (see  
AutoStore/Power-Up RECALL on page 21).  
Interrupts  
The CY14B256KA has flags register, interrupt register and  
interrupt logic that can signal interrupt to the microcontroller.  
There are three potential sources for interrupt: watchdog timer,  
power monitor, and alarm timer. Each of these can be individually  
enabled to drive the INT pin by appropriate setting in the interrupt  
register (0x7FF6). In addition, each has an associated flag bit in  
the flags register (0x7FF0) that the host processor uses to  
determine the cause of the interrupt. The INT pin driver has two  
bits that specify its behavior when an interrupt occurs.  
Flags Register  
The flags register has three flag bits: WDF, AF, and PF, which  
can be used to generate an interrupt. These flags are set by the  
watchdog timeout, alarm match, or power fail monitor  
respectively. The processor can either poll this register or enable  
interrupts to be informed when a flag is set. These flags are  
automatically reset when the register is read. The flags register  
is automatically loaded with the value 0x00 on power-up (except  
for the OSCF bit; see Stopping and Starting the Oscillator on  
page 7).  
An interrupt is raised only if both a flag is raised by one of the  
three sources and the respective interrupt enable bit in interrupts  
register is enabled (set to ‘1’). After an interrupt source is active,  
two programmable bits, H/L and P/L, determine the behavior of  
the output pin driver on INT pin. These two bits are located in the  
interrupt register and can be used to drive level or pulse mode  
output from the INT pin. In pulse mode, the pulse width is  
Document Number: 001-55720 Rev. *I  
Page 9 of 28  
CY14B256KA  
Figure 4. Interrupt Block Diagram  
WDF - Watchdog Timer Flag  
WDF  
WIE  
PF  
WIE - Watchdog Interrupt  
Enable  
Watchdog  
Timer  
PF - Power Fail Flag  
PFE - Power Fail Enable  
V
CC  
P/L  
AF - Alarm Flag  
AIE - Alarm Interrupt Enable  
Power  
Monitor  
Pin  
Driver  
P/L - Pulse Level  
H/L - High/Low  
INT  
PFE  
VINT  
H/L  
V
SS  
AF  
Clock  
Alarm  
AIE  
load capacitances C1 and C2 are inclusive of parasitic of the  
printed circuit board (PCB). The PCB parasitic includes the  
capacitance due to land pattern of crystal pads/pins, Xin/Xout  
pads and copper traces connecting crystal and device pins.  
RTC External Components  
The RTC requires connecting an external 32.768 kHz crystal and  
C1, C2 load capacitance as shown in the Figure 5. The figure  
shows the recommnded RTC external component values. The  
Figure 5. RTC Recommended Component Configuration [5]  
Recommended Values  
= 32.768 kHz (12.5 pF)  
Y
1
C1 = 10 pF  
C2 = 67 pF  
Note: The recommended values for C1 and C2 include  
board trace capacitance.  
C1  
C2  
X
out  
Y1  
X
in  
Note  
5. For nonvolatile static random access memory (nvSRAM) real time clock (RTC) design guidelines and best practices, see application note AN61546.  
Document Number: 001-55720 Rev. *I  
Page 10 of 28  
CY14B256KA  
■ Keep Xin and Xout trace width lesser than 8 mils. Wider trace  
width leads to larger trace capacitance. The larger these bond  
pads and traces are, the more likely it is that noise can couple  
from adjacent signals.  
PCB Design Considerations for RTC  
RTC crystal oscillator is a low current circuit with high impedance  
nodes on their crystal pins. Due to lower timekeeping current of  
RTC, the crystal connections are very sensitive to noise on the  
board. Hence it is necessary to isolate the RTC circuit from other  
signals on the board.  
■ Shield the Xin and Xout signals by providing a guard ring around  
the crystal circuitry. This guard ring prevents noise coupling  
from neighboring signals.  
It is also critical to minimize the stray capacitance on the PCB.  
Stray capacitances add to the overall crystal load capacitance  
and therefore cause oscillation frequency errors. Proper  
bypassing and careful layout are required to achieve the  
optimum RTC performance.  
■ Take care while routing any other high speed signal in the  
vicinity of RTC traces. The more the crystal is isolated from  
other signals on the board, the less likely it is that noise is  
coupled into the crystal. Maintain a minimum of 200 mil  
separation between the Xin, Xout traces and any other high  
speed signal on the board.  
Layout requirements  
The board layout must adhere to (but not limited to) the following  
guidelines during routing RTC circuitry. Following these guide-  
lines help you achieve optimum performance from the RTC  
design.  
■ No signals should run underneath crystal components on the  
same PCB layer.  
Create an isolated solid copper plane on adjacent PCB layer and  
underneath the crystal circuitry to prevent unwanted noise  
coupled from traces routed on the other signal layers of the PCB.  
The local plane should be separated by at least 40 mils from the  
neighboring plane on the same PCB layer. The solid plane  
should be in the vicinity of RTC components only and its  
perimeter should be kept equal to the guard ring perimeter.  
Figure 6 shows the recommended layout for RTC circuit.  
■ It is important to place the crystal as close as possible to the  
Xin and Xout pins. Keep the trace lengths between the crystal  
and RTC equal in length and as short as possible to reduce the  
probability of noise coupling by reducing the length of the  
antenna.  
Figure 6. Recommended Layout for RTC  
Top component layer: L1  
Ground plane layer: L2  
System ground  
C1  
Y1  
C2  
Isolated ground plane on  
layer 2 : L2  
Guard ring - Top (Component)  
layer: L1  
Via: Via connects to isolated  
ground plane on L2  
Via: Via connects to system ground  
plane on L2  
Document Number: 001-55720 Rev. *I  
Page 11 of 28  
CY14B256KA  
Table 3. RTC Register Map [6, 7]  
Register  
BCD Format Data [6]  
Function/Range  
CY14B256KA  
0x7FFF  
D7  
D6  
D5  
D4  
D3  
D2  
D1  
Years  
Months  
D0  
10s years  
Years: 00–99  
0x7FFE  
0
0
0
10s  
Months: 01–12  
months  
0x7FFD  
0x7FFC  
0x7FFB  
0x7FFA  
0x7FF9  
0x7FF8  
0
0
0
0
0
0
0
0
10s day of month  
Day of month  
Day of week  
Day of month: 01–31  
Day of week: 01–07  
Hours: 00–23  
0
0
0
10s hours  
Hours  
Minutes  
Seconds  
10s minutes  
10s seconds  
Minutes: 00–59  
Seconds: 00–59  
Calibration values [8]  
OSCEN  
(0)  
0
Cal  
sign (0)  
Calibration (00000)  
0x7FF7  
WDS (0)  
WDW  
(0)  
WDT (000000)  
Watchdog [8]  
0x7FF6  
0x7FF5  
0x7FF4  
0x7FF3  
0x7FF2  
0x7FF1  
0x7FF0  
WIE (0) AIE (0) PFE (0)  
0
H/L (1) P/L (0)  
0
0
Interrupts [8]  
Alarm, Day of month: 01–31  
Alarm, hours: 00–23  
Alarm, minutes: 00–59  
Alarm, seconds: 00–59  
Centuries: 00–99  
M (1)  
M (1)  
M (1)  
M (1)  
0
0
10s alarm date  
10s alarm hours  
Alarm day  
Alarm hours  
Alarm minutes  
Alarm, seconds  
Centuries  
10s alarm minutes  
10s alarm seconds  
10s centuries  
WDF  
AF  
PF  
OSCF [9]  
0
CAL  
(0)  
W (0)  
R (0)  
Flags [8]  
Notes  
6. The unused bits of RTC registers are reserved for future use and should be set to ‘0’.  
7. ( ) designates values shipped from the factory.  
8. This is a binary value, not a BCD value.  
9. When the user resets OSCF flag bit, the flags register will be updated after t  
time.  
RTCp  
Document Number: 001-55720 Rev. *I  
Page 12 of 28  
CY14B256KA  
Table 4. Register Map Detail  
Register  
Description  
CY14B256KA  
Time Keeping - Years  
0x7FFF  
D7  
D6  
D5  
10s years  
D4  
D3  
D2  
D1  
D0  
Years  
Contains the lower two BCD digits of the year. Lower nibble (four bits) contains the value for years; upper nibble  
(four bits) contains the value for 10s of years. Each nibble operates from 0 to 9. The range for the register is 0–99.  
Time Keeping - Months  
0x7FFE  
0x7FFD  
D7  
D6  
D5  
D4  
D3  
D2  
D1  
D0  
0
0
0
10s month  
Months  
Contains the BCD digits of the month. Lower nibble (four bits) contains the lower digit and operates from 0 to 9;  
upper nibble (one bit) contains the upper digit and operates from 0 to 1. The range for the register is 1–12.  
Time Keeping - Date  
D7  
D6  
D5  
D4  
D3  
D2  
D1  
D0  
0
0
10s day of month  
Day of month  
Contains the BCD digits for the date of the month. Lower nibble (four bits) contains the lower digit and operates  
from 0 to 9; upper nibble (two bits) contains the 10s digit and operates from 0 to 3. The range for the register is  
1–31. Leap years are automatically adjusted for.  
Time Keeping - Day  
0x7FFC  
0x7FFB  
0x7FFA  
0x7FF9  
D7  
D6  
D5  
D4  
D3  
D2  
D1  
D0  
0
0
0
0
0
Day of week  
Lower nibble (three bits) contains a value that correlates to day of the week. Day of the week is a ring counter  
that counts from 1 to 7 then returns to 1. The user must assign meaning to the day value, because the day is not  
integrated with the date.  
Time Keeping - Hours  
D7  
D6  
D5  
D4  
D3  
D2  
D1  
D0  
0
0
10s hours  
Hours  
Contains the BCD value of hours in 24 hour format. Lower nibble (four bits) contains the lower digit and operates  
from 0 to 9; upper nibble (two bits) contains the upper digit and operates from 0 to 2. The range for the register  
is 0–23.  
Time Keeping - Minutes  
D7  
D6  
D5  
D4  
D3  
D2  
D1  
D0  
0
10s minutes  
Minutes  
Contains the BCD value of minutes. Lower nibble (four bits) contains the lower digit and operates from 0 to 9;  
upper nibble (three bits) contains the upper minutes digit and operates from 0 to 5. The range for the register is  
0–59.  
Time Keeping - Seconds  
D7  
D6  
D5  
D4  
D3  
D2  
D1  
D0  
0
10s seconds  
Seconds  
Contains the BCD value of seconds. Lower nibble (four bits) contains the lower digit and operates from 0 to 9;  
upper nibble (three bits) contains the upper digit and operates from 0 to 5. The range for the register is 0–59.  
Document Number: 001-55720 Rev. *I  
Page 13 of 28  
CY14B256KA  
Table 4. Register Map Detail (continued)  
Register  
Description  
CY14B256KA  
Calibration/Control  
0x7FF8  
D7  
D6  
D5  
D4  
D3  
D2  
D1  
D0  
OSCEN  
0
Calibration  
sign  
Calibration  
OSCEN  
Oscillator Enable. When set to ‘1’, the oscillator is stopped. When set to ‘0’, the oscillator runs. Disabling the  
oscillator saves battery or capacitor power during storage.  
Calibration Sign Determines if the calibration adjustment is applied as an addition (1) to or as a subtraction (0) from the time-base.  
Calibration  
These five bits control the calibration of the clock.  
WatchDog Timer  
D4 D3  
0x7FF7  
D7  
D6  
D5  
D2  
D1  
D0  
WDS  
WDW  
WDT  
WDS  
Watchdog strobe. Setting this bit to ‘1’ reloads and restarts the watchdog timer. Setting the bit to ‘0’ has no effect.  
The bit is cleared automatically after the watchdog timer is reset. The WDS bit is write only. Reading it always  
returns a 0.  
WDW  
Watchdog write enable. Setting this bit to ‘1’ disables any WRITE to the watchdog timeout value (D5–D0). This  
allows the user to set the watchdog strobe bit without disturbing the timeout value. Setting this bit to ‘0’ allows  
bits D5–D0 to be written to the watchdog register when the next write cycle is complete. This function is explained  
in more detail in Watchdog Timer on page 8.  
WDT  
Watchdog timeout selection. The watchdog timer interval is selected by the 6-bit value in this register. It  
represents a multiplier of the 32 Hz count (31.25 ms). The range of timeout value is 31.25 ms (a setting of 1) to  
2 seconds (setting of 3 Fh). Setting the watchdog timer register to 0 disables the timer. These bits can be written  
only if the WDW bit was set to 0 on a previous cycle.  
Interrupt Status/Control  
0x7FF6  
D7  
D6  
D5  
D4  
D3  
D2  
D1  
D0  
WIE  
AIE  
PFE  
0
H/L  
P/L  
0
0
WIE  
AIE  
Watchdog interrupt enable. When set to ‘1’ and a watchdog timeout occurs, the watchdog timer drives the INT  
pin and the WDF flag. When set to ‘0’, the watchdog timeout affects only the WDF flag.  
Alarm interrupt enable. When set to ‘1’, the alarm match drives the INT pin and the AF flag. When set to ‘0’, the  
alarm match only affects the AF flag.  
PFE  
Power fail enable. When set to ‘1’, the power fail monitor drives the INT pin and the PF flag. When set to ‘0’, the  
power fail monitor affects only the PF flag.  
0
Reserved for future use  
H/L  
P/L  
High/Low. When set to ‘1’, the INT pin is driven active HIGH. When set to ‘0’, the INT pin is open drain, active LOW.  
Pulse/Level. When set to ‘1’, the INT pin is driven active (determined by H/L) by an interrupt source for  
approximately 200 ms. When set to ‘0’, the INT pin is driven to an active level (as set by H/L) until the flags  
register is read.  
Alarm - Day  
0x7FF5  
D7  
D6  
D5  
D4  
D3  
D2  
D1  
Alarm date  
D0  
M
0
10s alarm date  
Contains the alarm value for the date of the month and the mask bit to select or deselect the date value.  
M
Match. When this bit is set to ‘0’, the date value is used in the alarm match. Setting this bit to ‘1’ causes the match  
circuit to ignore the date value.  
Document Number: 001-55720 Rev. *I  
Page 14 of 28  
CY14B256KA  
Table 4. Register Map Detail (continued)  
Register  
Description  
CY14B256KA  
Alarm - Hours  
0x7FF4  
D7  
D6  
D5  
D4  
D3  
D2  
D1  
D0  
M
0
10s alarm hours  
Alarm hours  
Contains the alarm value for the hours and the mask bit to select or deselect the hours value.  
M
Match. When this bit is set to ‘0’, the hours value is used in the alarm match. Setting this bit to ‘1’ causes the  
match circuit to ignore the hours value.  
Alarm - Minutes  
0x7FF3  
D7  
D6  
D5  
D4  
D3  
D2  
D1  
D0  
M
10s alarm minutes  
Alarm minutes  
Contains the alarm value for the minutes and the mask bit to select or deselect the minutes value.  
M
Match. When this bit is set to ‘0’, the minutes value is used in the alarm match. Setting this bit to ‘1’ causes the  
match circuit to ignore the minutes value.  
Alarm - Seconds  
0x7FF2  
D7  
D6  
D5  
D4  
D3  
D2  
D1  
D0  
M
10s alarm seconds  
Alarm seconds  
Contains the alarm value for the seconds and the mask bit to select or deselect the seconds’ value.  
M
Match. When this bit is set to ‘0’, the seconds value is used in the alarm match. Setting this bit to ‘1’ causes the  
match circuit to ignore the seconds value.  
Time Keeping - Centuries  
0x7FF1  
D7  
D6  
D5  
10s centuries  
D4  
D3  
D2  
D1  
Centuries  
D0  
Contains the BCD value of centuries. Lower nibble (four bits) contains the lower digit and operates from 0 to 9;  
upper nibble (four bits) contains the upper digit and operates from 0 to 9. The range for the register is 0–99  
centuries.  
Flags  
0x7FF0  
D7  
D6  
D5  
D4  
D3  
D2  
D1  
D0  
WDF  
AF  
PF  
OSCF  
0
CAL  
W
R
WDF  
AF  
Watchdog timer flag. This read only bit is set to ‘1’ when the watchdog timer is allowed to reach 0 without being  
reset by the user. It is cleared to ‘0’ when the flags register is read or on power-up.  
Alarm flag. This read only bit is set to ‘1’ when the time and date match the values stored in the alarm registers  
with the match bits = 0. It is cleared when the flags register is read or on power-up.  
PF  
Power fail flag. This read only bit is set to 1 when power falls below the power fail threshold VSWITCH. It is cleared  
to 0 when the flags register is read or on power-up.  
OSCF  
Oscillator fail flag. Set to ‘1’ on power-up if the oscillator is enabled and not running in the first 5 ms of operation.  
This indicates that RTC backup power failed and clock value is no longer valid. This bit survives the power cycle  
and is never cleared internally by the chip. The user must check for this condition and write '0' to clear this flag.  
When user resets OSCF flag bit, the bit will be updated after tRTCp time.  
CAL  
W
Calibration mode. When set to ‘1’, a 512 Hz square wave is output on the INT pin. When set to ‘0’, the INT pin  
resumes normal operation. This bit defaults to 0 (disabled) on power-up.  
Write enable: Setting the ‘W’ bit to ‘1’ freezes updates of the RTC registers. The user can then write to RTC  
registers, alarm registers, calibration register, interrupt register and flags register. Setting the ‘W’ bit to ‘0’ causes  
the contents of the RTC registers to be transferred to the time keeping counters if the time has changed. This  
transfer process takes tRTCp time to complete. This bit defaults to 0 on power-up.  
R
Read enable: Setting ‘R’ bit to ‘1’, stops clock updates to user RTC registers so that clock updates are not seen  
during the reading process. Set ‘R’ bit to ‘0’ to resume clock updates to the holding register. Setting this bit does  
not require ‘W’ bit to be set to ‘1’. This bit defaults to 0 on power-up.  
Document Number: 001-55720 Rev. *I  
Page 15 of 28  
CY14B256KA  
Transient voltage (< 20 ns) on  
any pin to ground potential ................. –2.0 V to VCC + 2.0 V  
Maximum Ratings  
Exceeding maximum ratings may shorten the useful life of the  
device. These user guidelines are not tested.  
Package power dissipation  
capability (TA = 25 °C) ................................................. 1.0 W  
Storage temperature ................................ –65 C to +150 C  
Maximum accumulated storage time  
Surface mount Pb soldering  
temperature (3 seconds) ......................................... +260 C  
DC output current (1 output at a time, 1s duration) .... 15 mA  
At 150 C ambient temperature ...................... 1000 h  
At 85 C ambient temperature ..................... 20 Years  
Maximum junction temperature ..................................150C  
Supply voltage on VCC relative to VSS ...........–0.5 V to 4.1 V  
Static discharge voltage  
(per MIL-STD-883, Method 3015) ......................... > 2001 V  
Latch up current .................................................... > 200 mA  
Voltage applied to outputs  
in High Z state ....................................–0.5 V to VCC + 0.5 V  
Operating Range  
Range  
Industrial  
Ambient Temperature  
VCC  
Input voltage .......................................–0.5 V to VCC + 0.5 V  
–40 C to +85 C  
2.7 V to 3.6 V  
DC Electrical Characteristics  
Over the Operating Range  
Parameter  
VCC  
Description  
Power supply voltage  
Average Vcc current  
Test Conditions  
Min  
2.7  
–
Typ [10]  
Max  
Unit  
3.0  
–
3.6  
V
ICC1  
tRC = 25 ns  
RC = 45 ns  
70  
52  
mA  
mA  
t
Values obtained without output loads  
(IOUT = 0 mA)  
ICC2  
Average VCC current during  
STORE  
All inputs don’t care, VCC = Max.  
Average current for duration tSTORE  
–
–
–
10  
–
mA  
mA  
[10]  
Average VCC current at  
All inputs cycling at CMOS levels.  
Values obtained without output loads  
(IOUT = 0 mA).  
35  
ICC3  
tRC= 200 ns, VCC(Typ), 25 °C  
ICC4  
ISB  
Average VCAP current during  
AutoStore cycle  
All inputs don’t care. Average current  
for duration tSTORE  
–
–
–
–
5
5
mA  
mA  
VCC standby current  
CE > (VCC – 0.2 V).  
VIN < 0.2 V or > (VCC – 0.2 V).  
W bit set to ‘0’.  
Standby current level after  
nonvolatile cycle is complete.  
Inputs are static. f = 0 MHz.  
[11]  
Input leakage current (except  
HSB)  
VCC = Max, VSS < VIN < VCC  
–1  
–
+1  
µA  
IIX  
Input leakage current (for HSB) VCC = Max, VSS < VIN < VCC  
–100  
–1  
–
–
+1  
+1  
µA  
µA  
IOZ  
Off state output leakage current  
VCC = Max, VSS < VOUT < VCC  
,
CE or OE > VIH or WE < VIL  
VIH  
VIL  
Input HIGH voltage  
Input LOW voltage  
Output HIGH voltage  
Output LOW voltage  
2.0  
VSS – 0.5  
2.4  
–
–
–
–
VCC + 0.5  
V
V
V
V
0.8  
–
VOH  
VOL  
IOUT = –2 mA  
IOUT = 4 mA  
–
0.4  
Notes  
10. Typical values are at 25 °C, V = V  
. Not 100% tested.  
CC(Typ)  
CC  
11. The HSB pin has I  
= –2 µA for V of 2.4 V when both active HIGH and low drivers are disabled. When they are enabled standard V and V are valid. This  
OUT  
O
H
O
H
O
L
parameter is characterized but not tested.  
Document Number: 001-55720 Rev. *I  
Page 16 of 28  
CY14B256KA  
DC Electrical Characteristics (continued)  
Over the Operating Range  
Parameter  
Description  
Storage capacitor  
Test Conditions  
Min  
Typ [10]  
Max  
Unit  
[12]  
Between VCAP pin and VSS  
61  
68  
180  
µF  
VCAP  
[13, 14]  
VVCAP  
Maximum voltage driven on VCAP VCC = Max  
pin by the device  
–
–
VCC  
V
Data Retention and Endurance  
Over the Operating Range  
Parameter  
Description  
Min  
Unit  
Years  
K
DATAR  
NVC  
Data retention  
20  
Nonvolatile STORE operations  
1,000  
Capacitance  
Parameter[14]  
Description  
Test Conditions  
Max  
Unit  
pF  
CIN  
Input capacitance (except HSB) TA = 25 C, f = 1 MHz, VCC = VCC(Typ)  
Input capacitance (for HSB)  
7
8
7
8
pF  
COUT  
Output capacitance (except HSB)  
pF  
Output capacitance (for HSB)  
pF  
Thermal Resistance  
Parameter[14]  
Description  
Test Conditions  
48-pin SSOP Unit  
JA  
Thermal resistance  
(Junction to ambient)  
Test conditions follow standard test methods and  
procedures for measuring thermal impedance, in  
accordance with EIA/JESD51.  
37.47  
C/W  
JC  
Thermal resistance  
(Junction to case)  
24.71  
C/W  
Notes  
12. Min V  
value guarantees that there is a sufficient charge available to complete a successful AutoStore operation. Max V  
value guarantees that the capacitor on  
CAP  
CAP  
V
is charged to a minimum voltage during a Power-Up RECALL cycle so that an immediate power-down cycle can complete a successful AutoStore. Therefore it  
CAP  
is always recommended to use a capacitor within the specified min and max limits. Refer application note AN43593 for more details on V  
options.  
CAP  
13. Maximum voltage on V  
pin (V  
) is provided for guidance when choosing the V  
capacitor. The voltage rating of the V capacitor across the operating  
CAP  
VCAP  
CAP  
CAP  
temperature range should be higher than the V  
voltage.  
VCAP  
14. These parameters are guaranteed by design and are not tested.  
Document Number: 001-55720 Rev. *I  
Page 17 of 28  
CY14B256KA  
AC Test Loads  
Figure 7. AC Test Loads  
3.0 V  
OUTPUT  
577  
577   
3.0 V  
OUTPUT  
R1  
R1  
R2  
789   
R2  
789   
5 pF  
30 pF  
AC Test Conditions  
Input pulse levels ...................................................0 V to 3 V  
Input rise and fall times (10%–90%) ............................ <3 ns  
Input and output timing reference levels ....................... 1.5 V  
RTC Characteristics  
Over the Operating Range  
Parameter  
Description  
Min  
1.8  
–
Typ [15]  
Max  
3.6  
0.35  
–
Units  
V
VRTCbat  
RTC battery pin voltage  
RTC backup current  
3.0  
–
[16]  
IBAK  
TA (Min)  
µA  
µA  
µA  
V
(Refer Figure 5 for the recommended external componets  
for RTC)  
25 °C  
–
0.35  
–
TA (Max)  
TA (Min)  
25 °C  
–
0.5  
3.6  
3.6  
3.6  
2
[17]  
VRTCcap  
RTC capacitor pin voltage  
1.6  
1.5  
1.4  
–
–
3.0  
–
V
TA (Max)  
V
tOCS  
RTC oscillator time to start  
1
sec  
s  
tRTCp  
RTC processing time from end of ‘W’ bit set to ‘0’  
RTC backup capacitor charge current-limiting resistor  
–
–
350  
850  
RBKCHG  
350  
–
Notes  
15. Typical values are at 25 °C, V = V  
. Not 100% tested.  
CC  
CC(Typ)  
16. From either V  
or V  
.
RTCcap  
RTCbat  
17. If V  
> 0.5 V or if no capacitor is connected to V  
pin, the oscillator starts in t  
time. If a backup capacitor is connected and V < 0.5 V, the capacitor  
RTCcap  
RTCcap  
RTCcap  
OCS  
must be allowed to charge to 0.5 V for oscillator to start.  
Document Number: 001-55720 Rev. *I  
Page 18 of 28  
CY14B256KA  
AC Switching Characteristics  
Over the Operating Range  
Parameters [18]  
25 ns  
45 ns  
Description  
Unit  
Max  
Cypress  
Alt Parameter  
Parameter  
Min  
Max  
Min  
SRAM Read Cycle  
tACE  
tACS  
tRC  
Chip enable access time  
Read cycle time  
–
25  
–
–
45  
–
ns  
ns  
[19]  
25  
45  
tRC  
[20]  
tAA  
tOE  
tOH  
tLZ  
Address access time  
–
–
3
3
–
0
–
0
–
25  
12  
–
–
–
3
3
–
0
–
0
–
45  
20  
–
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tAA  
tDOE  
Output enable to data valid  
Output hold after address change  
Chip enable to output active  
Chip disable to output Inactive  
Output enable to output active  
Output disable to output inactive  
Chip enable to power active  
Chip disable to power standby  
[20]  
tOHA  
[21, 22]  
[21, 22]  
[21, 22]  
[21, 22]  
–
–
tLZCE  
tHZCE  
tLZOE  
tHZOE  
tHZ  
tOLZ  
tOHZ  
tPA  
10  
–
15  
–
10  
–
15  
–
[21]  
tPU  
[21]  
tPS  
25  
45  
tPD  
SRAM Write Cycle  
tWC  
tPWE  
tSCE  
tSD  
tWC  
tWP  
tCW  
tDW  
tDH  
tAW  
tAS  
Write cycle time  
25  
20  
20  
10  
0
–
–
45  
30  
30  
15  
0
–
–
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
Write pulse width  
Chip enable to end of write  
Data setup to end of write  
Data hold after end of write  
Address setup to end of write  
Address setup to start of write  
Address hold after end of write  
Write enable to output disable  
–
–
–
–
tHD  
–
–
tAW  
tSA  
20  
0
–
30  
0
–
–
–
tHA  
tWR  
0
–
0
–
[21, 22, 23]  
[21, 22]  
tWZ  
–
10  
–
15  
tHZWE  
tLZWE  
tOW  
Output active after end of write  
3
–
3
–
ns  
Switching Waveforms  
Figure 8. SRAM Read Cycle #1 (Address Controlled) [19, 20, 24]  
tRC  
Address  
Address Valid  
tAA  
Output Data Valid  
Previous Data Valid  
tOHA  
Data Output  
Notes  
18. Test conditions assume signal transition time of 3 ns or less, timing reference levels of V /2, input pulse levels of 0 to V  
, and output loading of the specified  
CC(typ)  
CC  
I
/I and load capacitance shown in Figure 7 on page 18.  
OL OH  
19. WE must be HIGH during SRAM read cycles.  
20. Device is continuously selected with CE and OE LOW.  
21. These parameters are guaranteed by design and are not tested.  
22. Measured ±200 mV from steady state output voltage.  
23. If WE is low when CE goes low, the outputs remain in the high impedance state.  
24. HSB must remain HIGH during Read and Write cycles.  
Document Number: 001-55720 Rev. *I  
Page 19 of 28  
CY14B256KA  
Switching Waveforms (continued)  
Figure 9. SRAM Read Cycle #2 (CE and OE Controlled) [25, 26]  
Address  
CE  
Address Valid  
tRC  
tHZCE  
tACE  
tAA  
tLZCE  
tHZOE  
tDOE  
OE  
tLZOE  
High Impedance  
Standby  
Data Output  
Output Data Valid  
tPU  
tPD  
Active  
ICC  
Figure 10. SRAM Write Cycle #1 (WE Controlled) [26, 27, 28]  
tWC  
Address  
CE  
Address Valid  
tSCE  
tHA  
tAW  
tPWE  
WE  
Data Input  
Data Output  
tSA  
tHD  
tSD  
Input Data Valid  
tLZWE  
tHZWE  
High Impedance  
Previous Data  
Figure 11. SRAM Write Cycle #2 (CE Controlled) [26, 27, 28]  
tWC  
Address Valid  
Address  
tSA  
tSCE  
tHA  
CE  
tPWE  
WE  
tHD  
tSD  
Input Data Valid  
Data Input  
High Impedance  
Data Output  
Notes  
25. WE must be HIGH during SRAM read cycles.  
26. HSB must remain HIGH during Read and Write cycles.  
27. If WE is low when CE goes low, the outputs remain in the high impedance state.  
28. CE or WE must be >V during address transitions.  
IH  
Document Number: 001-55720 Rev. *I  
Page 20 of 28  
CY14B256KA  
AutoStore/Power-Up RECALL  
Over the Operating Range  
Parameter  
Description  
Min  
Max  
Unit  
[29]  
Power-Up RECALL duration  
STORE cycle duration  
–
20  
ms  
tHRECALL  
[30]  
–
–
8
25  
ms  
ns  
V
tSTORE  
[31]  
Time allowed to complete SRAM write cycle  
Low voltage trigger level  
tDELAY  
VSWITCH  
–
2.65  
–
[32]  
VCC rise time  
150  
–
µs  
V
tVCCRISE  
[32]  
HSB output disable voltage  
1.9  
VHDIS  
[32]  
tLZHSB  
HSB to output active time  
HSB high active time  
–
–
5
µs  
ns  
[32]  
tHHHD  
500  
Switching Waveforms  
Figure 12. AutoStore or Power-Up RECALL [33]  
VCC  
VSWITCH  
VHDIS  
30  
30  
tVCCRISE  
tSTORE  
tSTORE  
Note  
Note  
tHHHD  
tHHHD  
34  
34  
Note  
Note  
HSB OUT  
AutoStore  
tDELAY  
tLZHSB  
tLZHSB  
tDELAY  
POWER-  
UP  
RECALL  
tHRECALL  
tHRECALL  
Read & Write  
Inhibited  
(RWI)  
Read & Write  
Read & Write  
POWER-UP  
RECALL  
BROWN  
OUT  
AutoStore  
POWER  
DOWN  
AutoStore  
POWER-UP  
RECALL  
Notes  
29. t  
starts from the time V rises above V .  
SWITCH  
HRECALL  
CC  
30. If an SRAM write has not taken place since the last nonvolatile cycle, no AutoStore or Hardware STORE takes place  
31. On a Hardware STORE and AutoStore initiation, SRAM write operation continues to be enabled for time t  
32. These parameters are guaranteed by design and are not tested.  
.
DELAY  
33. Read and Write cycles are ignored during STORE, RECALL, and while V is below V  
.
CC  
SWITCH  
34. During power-up and power-down, HSB glitches when HSB pin is pulled up through an external resistor.  
Document Number: 001-55720 Rev. *I  
Page 21 of 28  
CY14B256KA  
Software Controlled STORE/RECALL Cycle  
Over the Operating Range  
25 ns  
45 ns  
Unit  
Parameter [35, 36]  
Description  
Min  
25  
0
20  
0
Max  
–
–
–
–
Min  
45  
0
30  
0
Max  
tRC  
tSA  
tCW  
tHA  
STORE/RECALL initiation cycle time  
Address setup time  
–
–
ns  
ns  
ns  
ns  
µs  
µs  
Clock pulse width  
Address hold time  
RECALL duration  
–
–
tRECALL  
–
–
200  
100  
–
–
200  
100  
[37, 38]  
Soft sequence processing time  
tSS  
Switching Waveforms  
Figure 13. CE & OE Controlled Software STORE/RECALL Cycle [36]  
tRC  
tRC  
Address  
Address #1  
tCW  
Address #6  
tCW  
tSA  
CE  
tSA  
tHA  
tHA  
tHA  
tHA  
OE  
tHHHD  
tHZCE  
HSB (STORE only)  
DQ (DATA)  
39  
Note  
tDELAY  
tLZCE  
tLZHSB  
High Impedance  
tSTORE/tRECALL  
RWI  
Figure 14. AutoStore Enable/Disable Cycle[36]  
tRC  
Address #1  
tCW  
tRC  
Address  
Address #6  
tCW  
tSA  
CE  
tSA  
tHA  
tHA  
tHA  
tHA  
OE  
tSS  
tHZCE  
39  
tLZCE  
tDELAY  
Note  
DQ (DATA)  
RWI  
Notes  
35. The software sequence is clocked with CE controlled or OE controlled reads.  
36. The six consecutive addresses must be read in the order listed in Table 1. WE must be HIGH during all six consecutive cycles.  
37. This is the amount of time it takes to take action on a soft sequence command. Vcc power must remain HIGH to effectively register command.  
38. Commands such as STORE and RECALL lock out I/O until operation is complete which further increases this time. See the specific command.  
39. DQ output data at the sixth read may be invalid since the output is disabled at t  
time.  
DELAY  
Document Number: 001-55720 Rev. *I  
Page 22 of 28  
CY14B256KA  
Hardware STORE Cycle  
Over the Operating Range  
Parameter  
Description  
Min  
–
Max  
25  
–
Unit  
ns  
tDHSB  
tPHSB  
HSB to output active time when write latch not set  
Hardware STORE pulse width  
15  
ns  
Switching Waveforms  
Figure 15. Hardware STORE Cycle [40]  
Write latch set  
tPHSB  
HSB (IN)  
tSTORE  
tHHHD  
tDELAY  
HSB (OUT)  
DQ (Data Out)  
RWI  
tLZHSB  
Write latch not set  
tPHSB  
HSB pin is driven high to VCC only by Internal  
100 kOhm resistor,  
HSB (IN)  
HSB driver is disabled  
SRAM is disabled as long as HSB (IN) is driven low.  
tDELAY  
tDHSB  
tDHSB  
HSB (OUT)  
RWI  
Figure 16. Soft Sequence Processing [41, 42]  
tSS  
tSS  
Soft Sequence  
Command  
Soft Sequence  
Command  
Address  
Address #1  
tSA  
Address #6  
tCW  
Address #1  
Address #6  
tCW  
CE  
VCC  
Notes  
40. If an SRAM write has not taken place since the last nonvolatile cycle, no AutoStore or Hardware STORE takes place.  
41. This is the amount of time it takes to take action on a soft sequence command. Vcc power must remain HIGH to effectively register command.  
42. Commands such as STORE and RECALL lock out I/O until operation is complete which further increases this time. See the specific command.  
Document Number: 001-55720 Rev. *I  
Page 23 of 28  
CY14B256KA  
Truth Table For SRAM Operations  
HSB must remain HIGH for SRAM operations.  
Table 5. Truth Table  
CE  
H
L
WE  
X
OE  
X
Inputs/Outputs  
Mode  
Deselect/Power-down  
Read  
Power  
High Z  
Standby  
H
L
Data out (DQ0–DQ7)  
High Z  
Active  
Active  
Active  
L
H
H
Output disabled  
Write  
L
L
X
Data in (DQ0–DQ7)  
Ordering Information  
Speed  
Ordering Code  
Package Diagram  
51-85061  
Package Type  
Operating Range  
(ns)  
25  
CY14B256KA-SP25XIT  
CY14B256KA-SP25XI  
CY14B256KA-SP45XIT  
CY14B256KA-SP45XI  
48-pin SSOP  
Industrial  
45  
All the above parts are Pb-free.  
Ordering Code Definitions  
CY 14 B 256 K A - SP 25 X I T  
Option:  
T - Tape and Reel  
Blank - Std.  
Temperature:  
I - Industrial (–40 °C to 85 °C)  
Pb-free  
Speed:  
25 - 25 ns  
45 - 45 ns  
Package:  
SP - 48-pin SSOP  
Die revision:  
Blank - No Rev  
A - 1st Rev  
Data Bus:  
K - × 8 + RTC  
Density:  
256 - 256 Kb  
Voltage:  
B - 3.0 V  
14 - nvSRAM  
Cypress  
Document Number: 001-55720 Rev. *I  
Page 24 of 28  
CY14B256KA  
Package Diagram  
Figure 17. 48-pin SSOP (300 Mils) Package Outline, 51-85061  
51-85061 *F  
Document Number: 001-55720 Rev. *I  
Page 25 of 28  
CY14B256KA  
Acronyms  
Document Conventions  
Units of Measure  
Acronym  
Description  
Binary Coded Decimal  
Chip Enable  
BCD  
Symbol  
Unit of Measure  
CE  
%
percent  
CMOS  
Complementary Metal Oxide Semiconductor  
Electronic Industries Alliance  
Hardware Store Busy  
°C  
F
degree celsius  
farad  
EIA  
HSB  
I/O  
Hz  
kHz  
k  
A  
mA  
F  
MHz  
s  
hertz  
Input/Output  
kilohertz  
nvSRAM  
OE  
non-volatile Static Random Access Memory  
Output Enable  
kilohm  
microampere  
milliampere  
microfarad  
megahertz  
microsecond  
millisecond  
nanosecond  
picofarad  
parts per million  
volt  
Printed Circuit Board  
PCB  
RoHS  
Restriction of Hazardous Substances  
Real Time Clock  
RTC  
RWI  
Read and Write Inhibited  
Static Random Access Memory  
Shrink Small Outline Package  
Write Enable  
SRAM  
SSOP  
WE  
ms  
ns  
pF  
ppm  
V
ohm  
W
watt  
Document Number: 001-55720 Rev. *I  
Page 26 of 28  
CY14B256KA  
Document History Page  
Document Title: CY14B256KA, 256-Kbit (32 K × 8) nvSRAM with Real Time Clock  
Document Number: 001-55720  
Orig. of  
Change  
Submission  
Date  
Rev.  
ECN No.  
Description of Change  
**  
2763469  
2829117  
GVCH  
GVCH  
09/14/09  
12/16/09  
New data sheet.  
Added data retention and endurance table  
*A  
Updated STORE cycles to QuantumTrap from 200K to 1 Million  
Updated IBAK RTC backup current spec unit from nA to A  
Added Contents. Moved to external web  
*B  
*C  
2922858  
3143855  
GVCH  
GVCH  
04/26/10  
Pin Definitions: Added more clarity on HSB pin operation  
Hardware STORE (HSB) Operation: Added more clarity on HSB pin operation  
Updated HSB pin operation in Figure 12 and updated footnote 34.  
Updated package diagram.  
01/17/2011 Updated Setting the Clock description  
Added footnote 7  
Updated ‘W’ bit description in Register Map Detail table  
Updated Maximum Ratings  
Added tRTCp parameter to RTC Characteristics table  
Figure 11: Typo error fixed  
Added Acronyms table and Units of Measure table  
*D  
*E  
3315247  
3587664  
GVCH  
GVCH  
07/15/2011 Updated DC Electrical Characteristics (Added Note 12 and referred the same  
note in VCAP parameter).  
Updated Capacitance (Included Input capacitance (for HSB) and Output  
capacitance (for HSB)).  
Updated AC Switching Characteristics (Added Note 18 and referred the same  
note in Parameters).  
04/16/2012 Updated Pin Definitions (Added Note 2 and referred the same note in VRTCcap  
RTCbat, Xout, Xin, INT pins).  
,
V
Added Note 5 and referred the same note in Figure .  
Updated Package Diagram.  
*F  
3660966  
3759143  
GVCH  
GVCH  
06/29/2012 Updated DC Electrical Characteristics (Added VVCAP parameter and its details,  
added Note 13 and referred the same note in VVCAP parameter, also referred  
Note 14 in VVCAP parameter).  
*G  
09/28/2012 Updated Real Time Clock Operation (description).  
Updated Maximum Ratings (Removed “Ambient temperature with power  
applied” and included “Maximum junction temperature”).  
Updated Package Diagram (spec 51-85061 (Changed revision from *E to *F)).  
*H  
4048849  
GVCH  
07/03/2013 Updated Pin Definitions:  
Updated HSB pin description (Added more clarity).  
Updated Device Operation:  
Updated AutoStore Operation (Removed sentence “The HSB signal is  
monitored by the system to detect if an AutoStore cycle is in progress.”).  
Updated Real Time Clock Operation:  
Updated Backup Power (Added Note).  
Added RTC External Components.  
Moved Figure 5 from Flags Register section to RTC External Components  
section.  
Added PCB Design Considerations for RTC.  
Updated in new template.  
*I  
4568935  
GVCH  
11/14/2014 Added documentation related hyperlink in page 1  
Document Number: 001-55720 Rev. *I  
Page 27 of 28  
CY14B256KA  
Sales, Solutions, and Legal Information  
Worldwide Sales and Design Support  
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office  
closest to you, visit us at Cypress Locations.  
®
Products  
PSoC Solutions  
Automotive  
cypress.com/go/automotive  
cypress.com/go/clocks  
cypress.com/go/interface  
cypress.com/go/powerpsoc  
cypress.com/go/plc  
psoc.cypress.com/solutions  
PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP  
Clocks & Buffers  
Interface  
Cypress Developer Community  
Lighting & Power Control  
Community | Forums | Blogs | Video | Training  
Technical Support  
Memory  
cypress.com/go/memory  
cypress.com/go/psoc  
cypress.com/go/support  
PSoC  
Touch Sensing  
USB Controllers  
Wireless/RF  
cypress.com/go/touch  
cypress.com/go/USB  
cypress.com/go/wireless  
© Cypress Semiconductor Corporation, 2009-2014. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of  
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for  
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as  
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems  
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.  
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),  
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,  
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress  
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without  
the express written permission of Cypress.  
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES  
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not  
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where  
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer  
assumes all risk of such use and in doing so indemnifies Cypress against all charges.  
Use may be limited by and subject to the applicable Cypress software license agreement.  
Document Number: 001-55720 Rev. *I  
Revised November 14, 2014  
Page 28 of 28  
All products and company names mentioned in this document may be the trademarks of their respective holders.  

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