CY15B108QSN-108BKXIT

CY15B108QSN, CY15V108QSN

8Mb EXCELON™ Ultra Ferroelectric RAM

(F-RAM)

Serial (Quad SPI), 1024K × 8, 108MHz, industrial

Features

• 8-Mbit ferroelectric random access memory (F-RAM) logically organized as 1024K  8

- Virtually unlimited endurance of 100 trillion (10¹⁴) read/write cycles

- 151-year data retention (see “Data retention and endurance” on page 94)

- Infineon instant non-volatile write technology

- Advanced high-reliability ferroelectric process

• Single and multi I/O serial peripheral interface (SPI)

- Serial bus interface SPI protocols

- Supports SPI mode 0 (0, 0) and mode 3 (1, 1) for all SDR mode transfers

- Supports SPI mode 0 (0, 0) for all DDR mode transfers

- Extended I/O SPI protocols

- Dual SPI (DPI) protocols

- Quad SPI (QPI) protocols

• SPI clock frequency

- Up to 108-MHz frequency SPI single data rate (SDR)

- Up to 46-MHz frequency SPI double data rate (DDR)

• eXecute-In-Place (XIP) for memory read/write

• Write protection, data security, and data integrity

• Hardware protection using the write protect (WP) pin

• Software block protection

• Embedded error correction code (ECC) and cyclic redundancy check (CRC) for enhanced data integrity

- ECC detects and corrects 2-bit error. If a 3-bit error occurs, it does not correct but reports through the ECC

Status Register

- CRC detects any accidental change to raw data

• Extended electronic signatures

- Device ID includes manufacturer ID and product ID

- Unique ID

- User programmable serial number

• Dedicated 256-byte special sector F-RAM

- Dedicated special sector write and read

- Content can survive up to three standard reflow cycles

• Low-power consumption at high speed

- 12 mA (typ) active current for 108 MHz SPI SDR

- 20 mA (typ) active current for 108 MHz QSPI SDR

- 15.5 mA (typ) active current for 46 MHz QSPI DDR

- 105 µA (typ) standby current

- 0.9 µA (typ) deep power down mode current

- 0.1 µA (typ) hibernate mode current

Datasheet

www.infineon.com

Please read the Important Notice and Warnings at the end of this document

page 1 of 109

002-30246 Rev. *D

2022-05-25

8Mb EXCELON™ Ultra Ferroelectric RAM (F-RAM)

Serial (Quad SPI), 1024K × 8, 108MHz, industrial

Functional description

• Low-voltage operation

- CY15V108QSN: V_DD= 1.71 V to 1.89 V

- CY15B108QSN: V_DD= 1.8 V to 3.6 V

• Operating temperature: –40 °C to +85 °C

• Packages

- 24-ball fine pitch ball grid array (FBGA)

• Restriction of hazardous substances (RoHS) compliant

Functional description

The EXCELON™ Ultra CY15x108QSN is a high-performance, 8-Mbit non-volatile memory employing an advanced

ferroelectric process. A ferroelectric random access memory or F-RAM is non-volatile and performs reads and

writes similar to a RAM. It provides reliable data retention for 151 years while eliminating the complexities,

overhead, and system-level reliability problems caused by serial flash and other non-volatile memories.

Unlike serial flash, the CY15x108QSN performs write operations at bus speed. No write delays are incurred. Data

is written to the memory array immediately after each byte is successfully transferred to the device. The next bus

cycle can commence without the need for data polling. In addition, the product offers substantial write

endurance compared to other non-volatile memories. The CY15x108QSN is capable of supporting 10¹⁴read/write

cycles, or 100 million times more write cycles than EEPROM. These capabilities make the CY15x108QSN ideal for

non-volatile memory applications, requiring frequent or rapid writes. Examples range from data collection,

where the number of write cycles may be critical, to demanding industrial controls where the long write time of

serial flash can cause data loss.

The CY15x108QSN combines a 8-Mbit F-RAM with the high-speed quad SPI (QPI) SDR and DDR interfaces which

enhances the non-volatile write capability of F-RAM technology. The device incorporates a read-only device ID

and unique ID features which allow the SPI bus master to determine the manufacturer, product density, product

revision and unique ID for each part. The device is also offered with a unique serial number that is read-only and

can be used to identify a board or a system.

The device supports on-die ECC logic which can detect and correct 2-bit error in every 8-byte unit data. The device

also extends capability to report 3-bit error in 8-byte unit data. The CY15x108QSN also supports the cyclic

redundancy check (CRC) feature which can be used to check the data integrity of the stored data in the memory

array.

For a complete list of related resources, click here.

Datasheet

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8Mb EXCELON™ Ultra Ferroelectric RAM (F-RAM)

Serial (Quad SPI), 1024K × 8, 108MHz, industrial

Logic block diagram

V_DD

Power Control Block

256-Byte

Special Sector

F-RAM

SI (I/O0)

SO (I/O1)

Instruction Decoder

SPI Control Logic

Reset Logic

F-RAM and

Non-volatile Registers

Access Control

WP (I/O2)

RESET (I/O3)

CS

1024K x 8

F-RAM Array

Write Protect

Status Registers

SCK

Configuration

Registers

Device ID

Unique ID

Serial Number

Registers

Datasheet

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8Mb EXCELON™ Ultra Ferroelectric RAM (F-RAM)

Serial (Quad SPI), 1024K × 8, 108MHz, industrial

Table of contents

Features ...........................................................................................................................................1

Functional description.......................................................................................................................2

Logic block diagram ..........................................................................................................................3

Table of contents...............................................................................................................................4

1 Pinouts ..........................................................................................................................................6

2 Pin definitions ................................................................................................................................7

3 Functional overview .......................................................................................................................8

3.1 Memory architecture ..............................................................................................................................................8

3.2 Serial peripheral interface (SPI) bus ......................................................................................................................8

3.2.1 Single channel SPI ...............................................................................................................................................9

3.2.2 Extended SPI ........................................................................................................................................................9

3.2.3 Dual SPI (DPI) .......................................................................................................................................................9

3.2.4 Quad SPI (QPI)....................................................................................................................................................10

3.3 Terms used in SPI protocol ..................................................................................................................................10

3.3.1 SPI master ..........................................................................................................................................................10

3.3.2 SPI slave .............................................................................................................................................................10

3.3.3 Chip Select (CS)..................................................................................................................................................10

3.3.4 Serial Select (SCK)..............................................................................................................................................10

3.3.5 Data transmission (SI/SO) .................................................................................................................................11

3.3.6 Most significant bit.............................................................................................................................................11

3.3.7 Serial opcode .....................................................................................................................................................11

3.3.8 Invalid opcode....................................................................................................................................................12

3.3.9 Instruction..........................................................................................................................................................12

3.3.10 Mode byte.........................................................................................................................................................12

3.3.11 Wait states or dummy cycles...........................................................................................................................12

3.4 SPI modes..............................................................................................................................................................13

3.4.1 SDR .....................................................................................................................................................................13

3.4.2 DDR .....................................................................................................................................................................13

3.5 Power-up to first access .......................................................................................................................................14

4 CY15x108QSN registers .................................................................................................................15

4.1 Status Registers ....................................................................................................................................................15

4.1.1 Status Register 1 (SR1).......................................................................................................................................15

4.1.2 Status Register 2 (SR2).......................................................................................................................................19

4.2 Configuration registers.........................................................................................................................................20

4.2.1 Configuration Register 1 (CR1) ..........................................................................................................................20

4.2.2 Configuration Register 2 (CR2) ..........................................................................................................................24

4.2.3 Configuration Register 4 (CR4) ..........................................................................................................................26

4.2.4 Configuration Register 5 (CR5) ..........................................................................................................................28

5 Functional description ..................................................................................................................30

5.1 Command structure..............................................................................................................................................30

5.1.1 Write Enable Control commands ......................................................................................................................32

5.1.2 Register Access commands ...............................................................................................................................35

5.1.3 Memory operation .............................................................................................................................................46

5.1.4 Memory Write Operation commands................................................................................................................46

5.1.5 Memory Read Operation commands................................................................................................................57

5.1.6 Special Sector Memory commands ..................................................................................................................66

5.1.7 Identification and Serial Number commands ..................................................................................................78

5.1.8 Low power modes and resets ...........................................................................................................................83

6 Electrical characteristics ...............................................................................................................91

6.1 Maximum ratings ..................................................................................................................................................91

6.2 Operating range ....................................................................................................................................................91

Datasheet

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8Mb EXCELON™ Ultra Ferroelectric RAM (F-RAM)

Serial (Quad SPI), 1024K × 8, 108MHz, industrial

Table of contents

6.3 DC electrical characteristics.................................................................................................................................92

6.4 Data retention and endurance.............................................................................................................................94

6.5 Capacitance...........................................................................................................................................................94

6.6 Thermal resistance ...............................................................................................................................................94

6.7 AC test conditions .................................................................................................................................................95

6.8 SDR AC switching characteristics.........................................................................................................................96

6.9 DDR AC switching characteristics.........................................................................................................................99

6.10 Write protect (WP) timing parameters.............................................................................................................101

6.11 Reset (RESET) timing parameters ....................................................................................................................101

6.12 Power cycle timing............................................................................................................................................102

7 Ordering information .................................................................................................................. 104

7.1 Ordering code definitions...................................................................................................................................104

8 Package diagram ........................................................................................................................ 105

9 Acronyms................................................................................................................................... 106

10 Document conventions.............................................................................................................. 107

10.1 Units of measure ...............................................................................................................................................107

Revision history ............................................................................................................................ 108

Datasheet

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8Mb EXCELON™ Ultra Ferroelectric RAM (F-RAM)

Serial (Quad SPI), 1024K × 8, 108MHz, industrial

Pinouts

1

Pinouts

5

1

2

3

4

NC

A

B

NC

SCK

VSS

VDD

IO2/

WP

NC

CS

NC

C

D

IO1/

SO

IO0/

SI

IO3/

RESET

NC

E

Figure 1

24-ball BGA pinout

Datasheet

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8Mb EXCELON™ Ultra Ferroelectric RAM (F-RAM)

Serial (Quad SPI), 1024K × 8, 108MHz, industrial

Pin definitions

2

Pin definitions

Table 1

Pin definitions

I/O type

Pin name

Description

ChipSelect.ThisactiveLOWinputactivatesthedevice.WhenHIGH,thedeviceenters

low-power standby mode, ignores other inputs, and the output is tristated. When

LOW, the device internally activates the SCK signal. A falling edge on CS must occur

before a new opcode is issued.

CS

Input

Serial Clock. All I/O activity is synchronized to the serial clock. Inputs are latched on

the rising edge and outputs occur on the falling edge. Because the device is

synchronous, the clock frequency can vary between 0 and 108 MHz and may be

interrupted at any time.

SCK

Input

Serial Input. All data is input to the device on this pin. The pin is sampled on the rising

edge of SCK and is ignored at other times.

SI / (I/O0)

I/O0: When the part is either in dual mode or quad mode, the SI pin becomes

Input/output input/output (I/O0) pin and acts as input during command and address cycles and

output during the data output cycle.

Serial Output. This is the data output pin. It is driven during a read and remains

tristated at all other times including when RESET is LOW. Data transitions are driven

on the falling edge of the serial clock.

Output

SO / (I/O1)

I/O1: When the part is either in dual mode or quad mode, the SO pin becomes

Input/output input/output (I/O1) pin and acts as input during command and address cycles and

output during the data output cycle.

Write Protect. This active LOW pin prevents write operation to the Status and

Configuration registers when SRWD bit (SR1[7]) is set to ‘1’. A complete explanation of

Input

write protection is provided in “Status Register 1 (SR1)” on page 15. This pin must

be tied to V if not used.

WP / (I/O2)

DD

I/O2: When the part is in quad mode, the WP pin becomes input/output (I/O2) pin and

Input/output acts as input during command and address cycles and output during the data output

cycle.

Hardware Reset Pin. This active LOW pin resets the device. When RESET is LOW, the

device will self-initialize and will return to either standby state or active state

Input

depending on CS HIGH or LOW status after the RESET input is released to HIGH. This

pin must be tied to V if not used. RESET / (I/O3) behavior is described in Table 21.

RESET / (I/O3)

DD

I/O3: When the part is in quad mode, the RESET pin becomes input/output (I/O3) pin

Input/output and acts as input during command and address cycles and output during the data

output cycle.

V

Power supply Ground for the device. Must be connected to the system ground.

Power supply Power supply input to the device.

SS

V^DD

Datasheet

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8Mb EXCELON™ Ultra Ferroelectric RAM (F-RAM)

Serial (Quad SPI), 1024K × 8, 108MHz, industrial

Functional overview

3

Functional overview

The CY15x108QSN is a serial F-RAM memory. The memory array is logically organized as 1,048,576 × 8 bits and is

accessed using an industry-standard serial peripheral interface (SPI) bus. The functional operation of the F-RAM

is similar to single SPI EEPROM or single/dual/quad SPI flash. The key differences between the CY15x108QSN and

a serial flash, with the same pinout, is the F-RAM’s superior write performance, high endurance, and lower power

consumption.

3.1

Memory architecture

When accessing the CY15x108QSN, the user addresses 1024K locations of eight data bits each. These eight data

bits are shifted in or out serially either on single, dual, or quad I/Os. The addresses are accessed using the SPI

protocol, which includes a chip select (to permit multiple devices on the bus), an opcode, and a three-byte

(24-bit) address. However, since CY15x108QSN requires only 20 bits to address its entire 1024K byte locations,

the upper four bits of the most significant address byte are ‘don’t care’ values. The 20-bit address uniquely

identifies each data byte location in the 1024K memory array.

The access time for the memory operation is essentially zero, beyond the time needed for the serial protocol.

That is, the memory is read or written at the speed of the SPI bus. Unlike a serial flash or EEPROM, it is not

necessary to poll the device for a ready condition before initiating a new command. This is explained in more

detail in “Functional description” on page 30.

3.2

Serial peripheral interface (SPI) bus

The SPI is a synchronous serial interface, which uses clock and data pins for memory access and supports

multiple devices on the data bus. A device on the SPI bus is activated using the CS pin. The relationship between

chip select, clock, and data is dictated by the SPI mode. This device supports SPI modes 0 and 3. In both of these

modes, data is clocked into the F-RAM on the rising edge of SCK starting from the first rising edge after CS goes

active. The SPI protocol is controlled by opcodes. The CS must go inactive after an operation is complete and

before a new opcode can be issued.

The CY15x108QSN is an SPI slave device and operates at speeds up to 108 MHz in single data rate (SDR) mode and

at speeds up to 46 MHz in DDR mode. This high-speed serial bus provides high-performance serial

communication to an SPI master. The CY15x108QSN supports four different SPI interface/protocol options:

Single channel SPI, Extended SPI, Dual SPI, Quad SPI.

Refer to Table 2 for I/O signaling details during opcode, address, and data phase in various SPI modes discussed

above.

Table 2

SPI modes and signal details

Single

[1]

Extended SPI

Multi-channel SPI

Interface

channel SPI

Dual data

Quad data

Dual I/O

Quad I/O

DPI

QPI

CS, SCK, I/O0,

I/O1, I/O2,

I/O3

CS, SCK, I/O0,

I/O1, I/O2,

I/O3

CS, SCK, I/O0,

I/O1, I/O2,

I/O3

CS, SCK, SI,

SO

CS, SCK,

CS, SCK, I/O0,

I/O1

CS, SCK, I/O0,

I/O1

Signals

I/O0, I/O1

I/O0, I/O1,

I/O2, I/O3

Opcode

Address

Data

SI

I/O0

I/O0, I/O1

I/O0, I/O1,

I/O2, I/O3

I/O0, I/O1,

I/O2, I/O3

I/O0, I/O1

I/O0, I/O1,

I/O2, I/O3

I/O0, I/O1,

I/O2, I/O3

I/O0, I/O1,

I/O2, I/O3

SI/SO

I/O0, I/O1

Note

1. There is no user setting for the extended SPI modes. Device always starts with SPI mode and then changes to the

respective extended SPI mode based on the opcode received.

Datasheet

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8Mb EXCELON™ Ultra Ferroelectric RAM (F-RAM)

Serial (Quad SPI), 1024K × 8, 108MHz, industrial

Functional overview

3.2.1

Single channel SPI

The single channel SPI is a four-pin interface with chip select (CS), serial input (SI), serial output (SO), and serial

clock (SCK) pins. After CS is activated, the first byte transferred from the bus master is the opcode. Following the

opcode, any addresses and data are then transferred. The CS must go HIGH (inactive) after an operation is

complete and before a new opcode can be issued. This mode uses SI and SO pins for input and output

respectively. Opcode and address is transferred by the master on the SI line, while data is read by the master on

SO.

3.2.2

Extended SPI

The CY15x108QSN has the capability to reconfigure the standard SPI pins to work in dual or quad I/O modes

called extended SPI modes. The extended SPI mode provides: Dual Data, Dual Input/Output (I/O), Quad Data, and

Quad Input/Output (I/O) modes. The CS going HIGH after extended SPI command or device reset (either POR or

hardware/software reset) brings the device back to the single channel SPI mode. Extended SPI mode has the

following I/O configurations:

• When the part is in dual output or dual I/O mode, the SI pin and SO pin become I/O0 pin and I/O1 pin respectively.

• When the part is in quad output or quad I/O mode, the SI pin, SO pin, WP pin, and RESET pin become I/O0 pin,

I/O1 pin, I/O2 pin, I/O3 pin respectively.

• Dual or Quad Data commands and addresses are sent to the memory only on the SI signal. Data will be returned

to the host as a sequence of bit pairs on I/O0 and I/O1 or four bit (nibble) groups on I/O0, I/O1, I/O2, and I/O3.

• Dual or Quad Input/Output (I/O) commands are sent to the memory only on SI signal while an address is sent

from the host as bit pairs on I/O0 and I/O1 or, four bit (nibble) groups on I/O0, I/O1, I/O2, and I/O3 respectively.

Data is returned to the host similarly as bit pairs on I/O0 and I/O1 or, four bit (nibble) groups on I/O0, I/O1, I/O2,

and I/O3.

3.2.3

Dual SPI (DPI)

The CY15x108QSN DPI mode is enabled by writing ‘1’ at bit 4 of “Configuration Register 2 (CR2)” on page 24,

CR2[4] = 1. Since “Configuration Register 2 (CR2)” on page 24 has both volatile and non-volatile space, user

setting in the non-volatile register will survive power and hardware reset cycles. Therefore, once the dual SPI

(DPI) mode is set in the non-volatile CR2, it always returns to the DPI mode until the host clears the DPI bit by

writing ‘0’ in the non-volatile CR2[4]. The host can change the device interface to DPI mode by writing ‘1’ to the

volatile register CR2[4]; but this volatile setting will not survive the power and hardware reset cycles, and the

volatile CR2[4] setting will be overwritten with default settings stored at associated non-volatile location at

power up or after the hardware reset cycle.

When the part is in Dual SPI mode, the SI pin and SO pin become I/O0 pin and I/O1 pin respectively. Command,

Address, and Data bits are sent to the memory from the host as bit pairs on I/O0 and I/O1. Data bits are returned

to the host similarly as bit pairs on I/O0 and I/O1.

Datasheet

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002-30246 Rev. *D

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8Mb EXCELON™ Ultra Ferroelectric RAM (F-RAM)

Serial (Quad SPI), 1024K × 8, 108MHz, industrial

Functional overview

3.2.4

Quad SPI (QPI)

The CY15x108QSN multichannel QPI mode is enabled by writing ‘1’ at bit 6 of “Configuration Register 2 (CR2)”

on page 24, CR2[6] = 1. Since “Configuration Register 2 (CR2)” on page 24 has both volatile and non-volatile

space, user setting in the non-volatile register will survive power and hardware reset cycles. Therefore, once the

Quad SPI (QPI) mode is set in the non-volatile CR2, it always returns to the QPI mode until the host clears the QPI

bit by writing ‘0’ in the non-volatile CR2[6]. The host can change the device interface to QPI mode by writing ‘1’

to the volatile register CR2[6]; but this volatile setting will not survive the power and hardware reset cycles, and

the volatile CR2[6] setting will be overwritten with default settings stored at associated non-volatile location at

power up or after the hardware reset cycle.

When the part is in Quad SPI mode, the SI pin, SO pin, WP pin, and RESET pins become I/O0 pin, I/O1 pin, I/O2 pin,

I/O3 pin respectively. Command, Address, and Data bits are sent to the memory from the host as four bit (nibble)

groups on I/O0, I/O1, I/O2, and I/O3. Data bits are returned to the host similarly as four bit (nibble) groups on I/O0,

I/O1, I/O2, and I/O3.

The QPI mode also supports DDR through special opcodes where byte transfer occurs on both edges of the clock

for address, mode, and data bytes. There is no DDR mode during the opcode phase; that is, opcodes are always

transmitted in SDR mode. The device enters DDR mode after a specific command is transmitted in SDR mode,

which then determines the address, mode, and data cycles in DDR. There is no setting for enabling the DDR mode.

The Quad SPI DDR mode is only supported for memory write and read operations with special opcodes.

3.3

Terms used in SPI protocol

The commonly used terms in the SPI protocol are as follows:

3.3.1

SPI master

The SPI master device controls the operations on the SPI bus. An SPI bus may have only one master with one or

more slave devices. All the slaves share the same SPI bus lines and the master may select any of the slave devices

using the CS pin. All of the operations must be initiated by the master activating a slave device by pulling the CS

pin of the slave LOW. The master also generates the SCK and all the data transmission on SI and SO lines are

synchronized with this clock.

3.3.2

SPI slave

The SPI slave device is activated by the master through the Chip Select line. A slave device gets the SCK as an

input from the SPI master and all the communication is synchronized with this clock. An SPI slave never initiates

a communication on the SPI bus and acts only on the instruction from the master.

The CY15x108QSN operates as an SPI slave and may share the SPI bus with other SPI slave devices.

3.3.3

Chip Select (CS)

To select any slave device, the master needs to pull down the corresponding CS pin. Any instruction can be issued

to a slave device only while the CS pin is LOW. When the device is not selected, data through the SI pin is ignored

and the serial output pin (SO) remains in a high-impedance state.

Note A new instruction must begin with the falling edge of CS. Therefore, only one opcode can be issued for each

active CS HIGH to LOW transition.

3.3.4

Serial Select (SCK)

The serial clock is generated by the SPI master and the communication is synchronized with this clock after CS

goes LOW.

The CY15x108QSN enables SPI modes 0 and 3 for data communication. In both of these modes, the inputs are

latched by the slave device on the rising edge of SCK and outputs are issued on the falling edge. Therefore, the

first rising edge of SCK signifies the arrival of the first most significant bit (MSb) of an SPI instruction on the SI pin.

Further, all data inputs and outputs are synchronized with SCK.

Datasheet

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8Mb EXCELON™ Ultra Ferroelectric RAM (F-RAM)

Serial (Quad SPI), 1024K × 8, 108MHz, industrial

Functional overview

3.3.5

Data transmission (SI/SO)

The SPI data bus consists of two lines, SI and SO, for serial data communication. SI is also referred to as

master-out-slave-in (MOSI) and SO is referred to as master-in-slave-out (MISO). The master issues instructions to

the slave through the SI pin, while the slave responds through the SO pin. Multiple slave devices may share the

SI and SO lines as described earlier.

The CY15x108QSN has two separate pins for SI and SO, which can be connected with the master as shown in

Figure 2. When in dual or quad I/O modes, these pins are configured as I/O pins. Figure 3 shows such a system

interface with a QSPI port.

SCK

MOSI

MISO

(I/O0) (I/O1)

SI SO

(I/O0) (I/O1)

SI SO

SCK

SPI

Hostcontroller

or

CY15X108QSN

SPI Master

WP RESET

CS (I/O2) (I/O3)

CS1

GPIO1

CS2

GPIO 2

Optional connection;

leave floating if not used

Figure 2

System configuration with SPI port

SCK

I/O0

I/O1

(I/O0) (I/O1)

SI SO

(I/O0) (I/O1)

SI SO

SCK

QSPI

Hostcontroller

CY15X108QSN

or

QSPI Master

WP RESET

CS (I/O2) (I/O3)

CS1

CS2

I/O2

I/O3

Figure 3

System configuration with QSPI port

3.3.6

Most significant bit

The SPI protocol requires that the first bit to be transmitted is the most significant bit (MSb). This is valid for both

address and data transmission.

The 8-Mbit serial F-RAM requires a 3-byte address for any read or write operation. Because the address is only 20

bits, the five bits, which are fed in are ignored by the device. Although these five bits are ‘don’t care’, Infineon

recommends that these bits be set to 0s to enable seamless transition to higher memory densities.

3.3.7

Serial opcode

After the slave device is selected with CS going LOW, the first byte received is treated as the opcode for the

intended operation. CY15x108QSN uses the standard opcodes (refer to Table 32) for memory accesses.

Datasheet

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002-30246 Rev. *D

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8Mb EXCELON™ Ultra Ferroelectric RAM (F-RAM)

Serial (Quad SPI), 1024K × 8, 108MHz, industrial

Functional overview

3.3.8

Invalid opcode

If a reserved opcode is received, the opcode may internally trigger unintended operation and start driving the I/O

pin(s) with a non-deterministic data output. Hence, all opcodes under the reserved category should be avoided

to transmit over SI pin when CY15x108QSN chip select CS is LOW.

3.3.9

Instruction

Instruction is the combination of the opcode, address, mode and/or dummy bytes/cycles used to access the

memory and registers.

3.3.10

Mode byte

The mode byte is applicable for all write and read commands that support eXecute-In-Place (XIP). The XIP is a

method of executing the program (code) directly from an external memory rather than copying or shadowing the

code into RAM. When the XIP is set for a write or read command, the device stays in XIP mode after the command

cycle is terminated (CS toggles HIGH) so that the subsequent command cycle with CS LOW directly starts with the

Address phase (opcode phase is skipped). When in XIP, the device executes the same operation as in previous

cycle. To initiate a new operation while in XIP, for example to switch from memory write to memory read or vice

versa, the device should first exit the XIP for the current command cycle and initiate the next command cycle with

opcode phase. Opcodes with the mode phase only support the XIP. See Table 32 for the list of opcodes that

require mode phase.

Following the opcode and 3-byte address cycles, the mode byte 0xAX (X don’t care bits) or 0xA5 (depending on

the opcode) transmitted during the mode phase keeps the device in XIP for the next command cycle. The XIP must

be set during every command cycle to remain in XIP for the next command cycle. Any other value than 0xAX or

0xA5 (!0xAX or !0xA5) transmitted during the mode phase will exit the XIP for the current operation. In this case,

the next command cycle must always start with the opcode phase to start the same operation or a new operation.

Depending upon the SPI mode and the interface type, the number of clocks to transmit the mode byte will vary

from one clock (Quad, DDR) to eight clocks (SPI, SDR).

3.3.11

Wait states or dummy cycles

The wait states, also called dummy cycles, are appended after the address bits and mode bits (if applicable). The

number of wait state cycles are programmable through “Configuration Register 1 (CR1)” on page 20 and

“Configuration Register 2 (CR2)” on page 24 for both memory and registers reads respectively. A valid data is

driven on the output bus only after specific number of dummy cycles are elapsed following memory and register

read commands that support wait state. A dummy cycle is a full clock cycle irrespective of the SPI modes and

data rates (SDR or DDR). The status of I/Os are don’t care during dummy cycle.

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Functional overview

3.4

SPI modes

CY15x108QSN may be driven by a microcontroller with its SPI peripheral running in either of the following two

modes:

• SPI mode 0 (CPOL = 0, CPHA = 0)

• SPI mode 3 (CPOL = 1, CPHA = 1)

The device detects the SPI mode from the status of the SCK pin when the device is selected by bringing the CS

pin LOW. If the SCK pin is LOW when the device is selected, SPI Mode 0 is assumed and if the SCK pin is HIGH, it

works in SPI mode 3. The two SPI modes are shown in Figure 4 and Figure 5. The status of the clock SCK when

the bus master is not transferring data is:

• SCK remains at 0 for Mode 0

• SCK remains at 1 for Mode 3

SPI mode 0 and SPI mode 3 are supported for all SDR mode commands. While, all DDR mode commands support

only SPI mode 0.

CS

0

1

2

3

4

5

6

7

SCK

SI

7

6

5

4

3

2

1

0

Figure 4

SPI mode 0

CS

0

1

2

3

4

5

6

7

SCK

7

6

5

4

3

2

1

0

SI

Figure 5

SPI mode 3

3.4.1

SDR

The input data bits (includes instruction, address, and data) are always latched in on the rising edge of SCK

starting from the first rising edge after CS goes active. If the clock starts from a HIGH state (in mode 3), the first

rising edge after the clock toggles is considered. The output data is available on the falling edge of SCK.

3.4.2

DDR

The instruction bits are always latched on the rising edge of SCK starting from the first rising edge after CS goes

active. If the clock starts from a HIGH state (in mode 3), the first rising edge after the clock toggles is considered.

However, the address and input data that follow the instruction are latched on both the rising and falling edges

of SCK. The first address bit is latched on the first rising edge of SCK following the falling edge at the end of the

last instruction bit. The first bit of output data is driven on the falling edge of SCK at the end of the last access

latency (dummy) cycle.

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Functional overview

3.5

Power-up to first access

When the CY15x108QSN power supply (V_DD) falls below V_DD(low), the power-up cycle starts. CY15x108QSN waits

for the V_DDpower supply to rise above the minimum V_DD(min), after which the device stars its internal boot-up

sequence. The boot-up sequence for CY15x108QSN includes internal power-on-reset (POR) followed by loading

the internal device configuration and trim registers as well as setting the user accessible registers. All user

accessible registers (Status and Configuration, Mode, ID, ECC, and CRC) are set to their default values after a

successful boot-up cycle. Table 3 shows the status of each register of CY15x108QSN after a successful power-up

(or POR) sequence.

CY15x108QSN ignores all instructions until a time delay of t_PUhas elapsed after the moment V_DDrises above

V_DD(min). No instruction should be sent to the device until the end of t_PU. After the t_PU, if CS is HIGH, the device

enters Standby mode and draws standby current (I_SB). The device enters deep power-down mode after t_PUif the

deep power-down mode upon POR (DPDPOR) in “Configuration Register 4 (CR4)” on page 26 is set to ‘1’

(CR4 [2] = 1).

The WIP bit of Status Register 1 (SR1[0]) cannot be used to poll the device readiness after the POR event because

device is still not accessible for executing any command including RDSR1 until the t_PUtime is over. However, if

the WIP status remains HIGH even after t_PUtime or device remains inaccessible, indicates device did not boot up

correctly (boot error). Once the boot error occurs, the device enters the following default states:

• The interface mode is set to Single SPI (SDR)

• IO3R bit of CR2 (CR2[5]) is internally set ‘1’ to enable the hardware reset (RESET) on IO3

• Register latency is set to three-clock cycle (max value)

• Output impedance is set to 45 

• Only RDSR1 and RDAR commands are allowed (in SPI SDR mode only) to read the SR1. All other commands will

remain disabled and will return undefined data if executed.

• Reading the SR1 returns 0x61 as boot error signature

CY15x108QSN will require power cycle or hardware reset to restart the boot-up again. The above default settings

will be replaced with actual user configurations after a successful boot-up.

Table 3

CY15x108QSN registers status after POR

Function

Register type

CY15x108QSN registers status after POR

Default to corresponding non-volatile bits

0x00

Status Register 1 (SR1)

Device status

Status Register 2 (SR2)

Configuration Register 1 (CR1)

Configuration Register 2 (CR2)

Configuration Register 4 (CR4)

Configuration Register 5 (CR5)

Identification Register

Default to corresponding non-volatile bits

Default to corresponding non-volatile bits (factory set)

[2]

Device configuration

Unique Identification Register

Identification

Default to corresponding non-volatile bits (factory set to

0x0000000000000000)

Serial Number Register

ECC Status Register

0x00

Error correction

ECC Count Register

0x0000

ECC Address Trap Register

0x00000000

Cyclic redundancy check CRC Register

Note

2. Configuration Register 3 (CR3) is reserved for future use.

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CY15x108QSN registers

4

CY15x108QSN registers

CY15x108QSN supports various status and configuration registers for device status update and configuration

settings. CY15x108QSN registers and their access details are discussed in follow on sections.

4.1

Status Registers

The CY15x108QSN supports two status registers - Status Register 1 (SR1) and Status Register 2 (SR2) to provide

the write protect settings as well ready/CRC status of the device. The SR1 register has a volatile and an associated

non-volatile register space in the F-RAM. The non-volatile register retains the device configuration during power

down which is then copied to the respective volatile register during power up or after the hardware reset (JEDEC

reset or RESET pin). The CY15x108QSN state machine uses only the volatile register settings to change the device

configuration during normal access. Since the CY15x108QSN provides independent space for both volatile and

non-volatile configuration registers, the host can program the volatile register only to make the configuration

effective for the current power cycle. The non-volatile write changes the content of both volatile and non-volatile

registers. Therefore, the new configurations become effective immediately for the current power cycle as well as

subsequent power cycles or hardware reset cycles. The SR2 is a read only register.

Read from status registers either uses dedicated status register read opcodes (RDSR1, RDSR2) or RDAR followed

status register address. The status register read always returns the volatile register content. Individual status

register details are provided in follow on sections.

4.1.1

Status Register 1 (SR1)

The Status Register 1 (SR1), as shown in Table 4, contains both status and write protect control bits. The SR1 is

accessible by WRSR and WRAR command for write and the RDSR1 or the RDAR command for read operations. The

SR1 access details are provided in “Register Access commands” on page 35.

WRAR non-volatile write address - 0x000000

WRAR volatile write address - 0x070000

RDAR read address - 0x000000 or 0x070000

The default state shown after each bit in Table 4 is the factory programmed value.

Table 4

Status Register 1 (SR1)

SR1[7]

SRWD (0)

SR1[6]

SR1[5]

SR1[4]

SR1[3]

SR1[2]

SR1[1]

SR1[0]

RFU (0)

TBPROT (0)

BP2 (0)

BP1 (0)

BP0 (0)

WEL (0)

WIP (0)

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Table 5

Bit

Status Register 1 (SR1) - Non-volatile

Bit name

Bit function

Type Read/write

Description

1 = Locks state of Status and Configuration registers

when WP is LOW

0 = No register protection irrespective of the status of

WP pin

Status register write

disable

SR1[7]

SRWD

RFU

NV

R/W

SR1[6]

Reserved (0)

Reserved for future use

1 = Protection starts at memory array bottom

0 = Protection starts at memory array top

Top/bottom relative

SR1[5] TBPROT

NV

R/W

protection

SR1[4]

SR1[3]

SR1[2]

BP2

BP1

BP0

NV

Block protect bit

Protects the selected address range of memory array

WEL indicates if the device is write enabled. This bit

defaults to ‘0’ (disabled) on power-up.

WEL = 1 --> write enabled

SR1[1]

WEL

Write enable latch

Work in progress

V

R

WEL = 0 --> write disabled

1 = Device Busy

0 = Device Ready

SR1[0]

WIP

NV - Non-volatile; V - Volatile

Table 6

Bit

Status Register 1 (SR1) - Volatile

Bit name

Bit function

Type Read/write

Description

1 = Locks state of Status and Configuration registers

when WP is LOW

0 = No register protection irrespective of the status of

WP pin

Status register write

disable

SR1[7]

SRWD

V

R/W

SR1[6]

SR1[5]

RFU

Reserved (0)

Reserved for future use

1 = Protection starts at memory array bottom

0 = Protection starts at memory array top

Top/bottom relative

TBPROT

V

R/W

protection

SR1[4]

SR1[3]

SR1[2]

BP2

BP1

BP0

V

Block protect bit

Protects the selected address range of memory array

WEL indicates if the device is write enabled. This bit

defaults to ‘0’ (disabled) on power-up.

WEL = 1 --> write enabled

SR1[1]

WEL

WIP

Write enable latch

Work in progress

V

R

WEL = 0 --> write disabled

1 = Device Busy

0 = Device Ready

SR1[0]

V - Volatile

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4.1.1.1

Status register protect (SRWD) SR1 [7]

This bit enables write protect for the Status and Configuration Registers when set to ‘1’ and the write protect (WP)

pin is driven LOW. In this mode, any instruction that changes the status registers or configuration registers

content is ignored, effectively locking the state of the device. If the SRWD is set to ‘0’, irrespective of the WP status

(LOW or HIGH), status and configuration registers write protection remains disabled. Refer to Table 9 for the

memory and status register protection options.

4.1.1.2

Top or bottom protection (TBPROT) SR1 [5]

This bit defines the operation of the block protection bits BP2, BP1, and BP0. This bit controls the starting point

of the memory array (from top or bottom) memory that gets protected by the block protection bits.

Table 7

Start of protection from top (TBPROT = 0)

Status register content

Protected fraction of memory array

Protected address range

BP2

0

BP1

0

BP0

0

None

th

0

1

Upper 1/64 of memory array

0x0FC000–0x0FFFFF

0x0F8000–0x0FFFFF

0x0F0000–0x0FFFFF

0x0E0000–0x0FFFFF

0x0C0000–0x0FFFFF

0x080000–0x0FFFFF

0x000000–0x0FFFFF

nd

0

1

0

Upper 1/32 of memory array

th

0

1

Upper 1/16 of memory array

th

1

0

Upper 1/8 of memory array

th

1

0

1

Upper 1/4 of memory array

1

0

Upper half of memory array

Full memory

1

Table 8

Start of protection from bottom (TBPROT = 1)

Status register content

Protected fraction of memory array

Protected address range

BP2

0

BP1

0

BP0

0

None

th

0

1

Lower 1/64 of memory array

0x000000–0x003FFF

0x000000–0x007FFF

0x000000–0x00FFFF

0x000000–0x01FFFF

0x000000–0x03FFFF

0x000000–0x07FFFF

0x000000–0x0FFFFF

nd

0

1

0

Lower 1/32 of memory array

th

0

1

Lower 1/16 of memory array

th

1

0

Lower 1/8 of memory array

th

1

0

1

Lower 1/4 of memory array

1

0

Lower half of memory array

Full memory

1

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4.1.1.3

Block protection (BP2, BP1 and BP0) SR1 [4:2]

These bits define the memory array to be write-protected against memory write commands. When one or more

of the BP bits is set to ‘1’, the respective memory address is protected from write. The block protect bits (BP2,

BP1, and BP0) in combination with the TBPROT bit can be used to protect an address range of the memory array.

The size of the range is determined by the value of the BP bits and the upper or lower starting point of the range

which is selected by the TBPROT. Table 7 and Table 8 show CY15x108QSN protected address range for BP[2:0]

bits setting.

4.1.1.4

Write enable latch (WEL) SR1 [1]

The WEL bit must be set to 1 to enable write operations to memory array or registers, as shown in Table 9. This

bit is set to ‘1’ only by executing the write enable (WREN) command. The WEL bit (SR1[1]) automatically clears to

‘0’ on the rising edge of CS following opcodes including: WRDI (04h), WRSR (01h), SSWR (42h), WRAR (71h), and

WRSN (C2h). The WEL bit (SR1[1]) does not clear to ‘0’ on the rising edge of CS following memory write opcodes.

The WEL bit is volatile and returns to its default ‘0’ state after POR and all reset events.

Table 9

SRWD

Write protection

[3]

WP

X

WEL

Protected blocks

Unprotected blocks

Protected

Status and Configuration registers

X

0

1

0

1

Protected

Writable

Protected

Writable

X

Writable

0

Writable

1

Writable

4.1.1.5

Work-in-progress (WIP) SR1 [0]

This is a read-only bit and indicates device ready or busy status during normal operation. The CY15x108QSN sets

this bit to ‘1’ while executing the CRC calculation. No other command (s) and event (s) set the WIP to ‘1’ in

CY15xQSN. When WIP is ‘1’, the CY15x108QSN can execute only read status registers using RDSR1/RDSR2 or Read

Any Register (RDAR followed by status register address), CRC suspend (EPCS), and software reset (RSTEN

followed by RST) commands. Other commands will be ignored while WIP is ‘1’. The WIP bit cannot be used to poll

the device ready status during power up or reset cycles. This bit is volatile and returns to its default state after

POR and all reset events.

Note

3. All bits except read only and reserved bits.

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4.1.2

Status Register 2 (SR2)

The Status Register 2 (SR2), as shown in Table 10, provides the device status on CRC operations. The SR2 is a

read-only volatile register and is accessible by RDSR2 or the RDAR command for read operations. The SR1 access

details are provided in “Register Access commands” on page 35.

RDAR read address - 0x000001 or 0x070001

The default state shown after each bit in Table 10 is the factory programmed value.

Table 10

SR2[7]

Status Register 2 (SR2)

SR2[6]

SR2[5]

SR2[4]

SR2[3]

SR2[2]

SR2[1]

SR2[0]

RFU (0)

CRCS (0)

CRCA (0)

RFU (0)

Table 11

Bit

Status Register 2 (SR2) - volatile only

Bit name

RFU

Bit function

Type

Read/write

Description

SR2[7]

SR2[6]

SR2[5]

Reserved (0)

Reserved for future use

RFU

1 = In CRC suspend mode

SR2[4]

SR2[3]

CRCS

CRCA

CRC suspend

CRC abort

V

R

0 = Not in CRC suspend mode

1 = CRC command aborted

0 = CRC command not aborted

SR2[2]

SR2[1]

RFU

Reserved (0)

Reserved for future use

SR2[0]

V - Volatile

4.1.2.1

CRC suspend (CRCS) SR2 [4]

The CRC suspend (CRCS) bit is used to determine whether the device is in CRC suspend mode. When the device

CRC calculation is in progress, executing the CRC suspend command (EPCS) will set this bit to ‘1’ to indicate the

CRC suspend status. The CRC resume (EPCR) command clears the CRCS bit to ‘0’, indicates device exited the CRC

suspend mode. This is a read only bit. This bit also gets cleared after resets (POR, hardware, and software).

4.1.2.2

CRC abort (CRCA) SR2 [3]

This bit indicates whether the CRC calculation (CRCC) operation is aborted. The CRC calculation is aborted when

end address and start address criteria (EA < SA + 3), which is ending address should be at least 32-bit aligned word

higher than the starting address, does not meet. This bits gets clears when subsequent CRC calculation starts

successfully. This bit also gets cleared after reset (POR, hardware, and software).

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4.2

Configuration registers

The CY15x108QSN supports four user Configuration Registers - CR1, CR2, CR4, and CR5 to program various

controls in the device. Each Configuration Register has a volatile and an associated non-volatile register space in

the F-RAM. The non-volatile registers retain the device configuration during power down which are then copied

to their respective volatile registers during power up or after the hardware reset (JEDEC reset or RESET pin). The

CY15x108QSN state machine uses only the volatile register settings to change the device configuration during

normal access. Since the CY15x108QSN provides independent space for both volatile and non-volatile

Configuration Registers, the host can program volatile register only to make the configuration effective for the

current power cycle. The non-volatile write changes the content of both volatile and non-volatile registers.

Therefore, new configurations become effective immediately for the current power cycle as well as subsequent

power cycles or hardware reset cycles.

Read from Configuration Registers either using dedicated configuration register read opcodes (RDCR1, RDCR2,

RDCR3, RDCR4) or RDAR always returns the volatile register content. Individual configuration register details are

provided in follow on sections.

4.2.1

Configuration Register 1 (CR1)

The Configuration Register 1 (CR1), as shown in Table 12, configures the latency (dummy) cycles for memory and

special sector reads and enables the quad I/O during extended SPI access. The CR1 is accessible by the WRAR

command for write and the RDCR1 or the RDAR command for read operations. The CR1 access details are

provided in “Register Access commands” on page 35.

WRAR non-volatile write address - 0x000002

WRAR volatile write address - 0x070002

RDAR read address - 0x000002 or 0x070002

The default state shown after each bit in Table 12 is the factory programmed value.

Table 12

Configuration Register 1 (CR1)

CR1[7]

MLC3 (0)

CR1[6]

CR1[5]

CR1[4]

CR1[3]

CR1[2]

CR1[1]

CR1[0]

MLC2 (0)

MLC1 (0)

MLC0 (0)

RFU (0)

QUAD (0)

RFU (0)

Table 13

Configuration Register 1 (CR1) - Non-volatile

Bit

Bit name

MLC3

Bit function

Type

NV

Read/write

Description

CR1[7]

CR1[6]

CR1[5]

Configures number of latency (dummy)

cycles for the memory as well as special

sector read opcodes.

Example:

NV

MLC2

Memory latency

code

MLC1

NV

R/W

0000 - 0 cycle

0110 - 6 cycles

NV

CR1[4]

MLC0

1111 - 15 cycles

CR1[3]

CR1[2]

RFU

Reserved (0)

Reserved for future use

1 = Quad

0 = Dual or Serial

CR1[1]

QUAD

Quad

NV

R/W

CR1[0]

RFU

Reserved (0)

Reserved for future use

NV - Non-volatile

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Table 14

Bit

Configuration Register 1 (CR1) - Volatile

Bit name

MLC3

Bit function

Type

Read/write

Description

CR1[7]

CR1[6]

CR1[5]

V

Configures number of latency (dummy) cycles

for the memory as well as special sector read

MLC2

opcodes.

Memory

MLC1

R/W

Example-

latency code

0000 - 0 cycle

0110 - 6 cycles

1111 - 15 cycles

CR1[4]

MLC0

V

CR1[3]

CR1[2]

RFU

Reserved (0)

V

Reserved for future use

1 = Quad

0 = Dual or Serial

CR1[1]

QUAD

RFU

Quad

R/W

CR1[0]

Reserved (0)

Reserved for future use

V - Volatile

4.2.1.1

Memory latency code (MLC) CR1 [7:4]

These four bits configure the latency (dummy) cycles for all variable latency memory read instructions. It enables

the user to adjust the memory read latency during normal operation to optimize the latency for different

instructions at different operating frequencies. Dummy cycles are full clock cycles on SCK irrespective of the SPI

modes and data rates (SDR and DDR).

Some read opcodes support dummy cycles following address cycles. These dummy cycles provide additional

latency that is needed to complete the initial read access of the memory array before data can be returned to the

host system. As the SPI clock (SCK) frequency increase, number of dummy cycles need to increase to meet the

latency.

Table 15 to Table 19 show the max SPI clock frequency versus clock latency for each opcodes that support

dummy cycles. The host controller can determine to optimize the timing by setting individual latency cycle for

each opcode or can set the worst case latency which meets the latency requirement of all opcodes for a desired

operating frequency. The memory read latency set for a higher frequency also applies for all lower frequencies.

Hence, when the host lowers the SPI clock (SCK) from higher frequency to a lower frequency, adjusting the clock

latency becomes optional.

The format (CMD, ADD, DATA) in Table 15 header represents the transmission of these bytes over number of I/Os

in different SPI modes. For example: (2, 2, 2) represents all command (CMD), address (ADDR), and data (DATA)

bytes are transmitted over two I/Os (I/O0 and I/O1) in DPI mode. Similarly, (1, 2, 2) represents CMD byte is

transmitted over a single I/O (I/O0), while ADDR and DATA bytes are transmitted over two I/Os (I/O0, I/O1) in dual

I/O mode. (1, 1, 4) represents CMD and ADDR bytes are transmitted over a single I/O (I/O0), while DATA bytes are

transmitted over four I/Os (I/O0, I/O1, I/O2, I/O3) in Quad Data mode.

Mode represents number of clock cycles required in various SPI interface modes to transmit the mode byte after

address bits. Since mode bits are transmitted after the address cycles, clock cycles required to transmit mode

bits are internally added to the latency calculation.

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Table 15

Latency (Dummy) cycles for memory read commands - With XIP mode (SDR)

Dual data

(SDR)

Dual I/O

(SDR)

Quad data

(SDR)

Quad I/O

(SDR)

SPI (SDR)

DPI (SDR)

QPI (SDR)

Latency

(Dummy)

cycles -

FAST_READ,

QIOR

FAST_READ

DOR

DIOR

QOR

QIOR

decimal

(1, 1, 1, 1, 1)

Mode = 8

108 MHz

(2, 2, 2, 2 , 2)

Mode = 4

(4, 4, 4, 4, 4)

Mode = 2

(1, 1, 1, 1, 2)

Mode = 8

108 MHz

(1, 2, 2, 2, 2)

Mode = 4

(1, 1, 1, 1, 4)

Mode = 8

108 MHz

(1, 4, 4, 4, 4)

Mode = 2

[4]

0

45 MHz

10 MHz

45 MHz

10 MHz

[4]

1

55 MHz

20 MHz

55 MHz

20 MHz

[4]

2

70 MHz

35 MHz

70 MHz

35 MHz

[4]

3

80 MHz

45 MHz

80 MHz

45 MHz

[4]

4

5

90 MHz

55 MHz

90 MHz

55 MHz

[4]

105 MHz

70 MHz

105 MHz

70 MHz

[4]

6

108 MHz

80 MHz

108 MHz

80 MHz

[4]

7

90 MHz

[4]

8

105 MHz

9–15

108 MHz

Table 16

Latency (Dummy) cycles for memory read commands - With XIP mode (DDR)

QPI (DDR)

DDRFR, DDRQIOR

(4, 4, 4, 4, 4)

Mode = 1

NA

Quad I/O (DDR)

DDRQIOR

(1, 4, 4, 4, 4)

Mode = 1

NA

Latency (Dummy)

cycles - decimal

0

1

NA

[4]

2

3

10 MHz

[4]

15 MH

[4]

4

25 MHz

[4]

5

33 MHz

[4]

6

40 MHz

[4]

7–15

46 MHz

Note

4. This parameter is guaranteed by characterization; not tested in production.

Datasheet

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CY15x108QSN registers

Table 17

Latency (Dummy) cycles for memory read commands - Without XIP mode

SPI (SDR)

DPI (SDR)

READ, ECCRD, SSRD

(2, 2, 2, 2, 2)

Mode = NA

NA

QPI (SDR)

Latency (Dummy)

cycles - decimal

(1, 1, 1, 1, 1)

Mode = NA

(4, 4, 4, 4, 4)

Mode = NA

NA

[5]

0

35 MHz

[5]

1

45 MHz

NA

[5]

2

55 MHz

20 MHz

10 MHz

[5]

3

70 MHz

35 MHz

20 MHz

[5]

4

80 MHz

45 MHz

35 MHz

[5]

5

90 MHz

55 MHz

45 MHz

[5]

6

7

105 MHz

70 MHz

55 MHz

[5]

108 MHz

80 MHz

70 MHz

[5]

8

90 MHz

80 MHz

[5]

9

105 MHz

90 MHz

[5]

10

11-15

108 MHz

105 MHz

108 MHz

4.2.1.2

Quad data width (QUAD) CR1 [1]

When set to ‘1’, this bit switches the data width of the device to four I/Os – quad mode, that is WP becomes I/O2

and RESET / (I/O3) becomes I/O3. If the alternate function is enabled on I/O3 by setting IO3R bit in Configuration

Register 2 (CR2[5]), RESET / (I/O3) works as I/O3 when CS is low and RESET input when CS is HIGH. The WP input

is disabled and is internally set to ‘1’. The QUAD bit must be set to ‘1’ when executing the extended SPI read

commands: quad output read, and quad I/O Read, and DDR quad I/O Read. The impact of “QUAD” bit setting on

various SPI interfaces are shown in Table 21.

Note

5. This parameter is guaranteed by characterization; not tested in production.

Datasheet

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CY15x108QSN registers

4.2.2

Configuration Register 2 (CR2)

The Configuration Register 2 (CR2), as shown in Table 18, controls the serial interface settings. The CR2 is

accessible by the WRAR command for write and the RDCR2 or the RDAR command for read operations. The CR2

access details are provided in “Register Access commands” on page 35.

WRAR non-volatile write address - 0x000003

WRAR volatile write address - 0x070003

RDAR read address - 0x000003 or 0x070003

The default state shown after each bit in Table 18 is the factory programmed value.

Table 18

CR2[7]

Configuration Register 2 (CR2)

CR2[6]

CR2[5]

CR2[4]

CR2[3]

CR2[2]

CR2[1]

CR2[0]

RFU (0)

QPI (0)

IO3R (0)

DPI (0)

RFU (0)

Table 19

Bit

Configuration Register 2 (CR2) - Non-volatile

Bit name Bit function

Type

Read/write

Description

CR2[7]

RFU

Reserved (0)

Reserved for future use

1 = Enable QPI protocol

Quad SPI

CR2[6]

CR2[5]

CR2[4]

QPI

NV

R/W

enable

0 = Enable SPI protocol, if DPI bit is set to ‘0’

1 = I/O3 is used as RESET input when CS is HIGH

0 = I/O3 has no alternate function

IO3R

DPI

IO3 reset

1 = Enable DPI protocol

0 = Enable SPI protocol, if QPI bit is set to ‘0’

Dual SPI

enable

CR2[3]

CR2[2]

CR2[1]

CR2[0]

RFU

Reserved (0)

Reserved for future use

NV - Non-volatile

Table 20

Configuration Register 2 (CR2) - Volatile

Bit

Bit name Bit function

Type

Read/Write

Description

CR2[7]

RFU

Reserved (0)

Reserved for future use

1 = Enable QPI protocol

Quad SPI

enable

CR2[6]

CR2[5]

CR2[4]

QPI

V

R/W

0 = Enable SPI protocol, if DPI bit is set to ‘0’

1 = I/O3 is used as RESET input when CS is HIGH

0 = I/O3 has no alternate function

IO3R

DPI

IO3 reset

1 = Enable DPI protocol

0 = Enable SPI protocol, if QPI bit is set to ‘0’

Dual SPI

enable

CR2[3]

CR2[2]

CR2[1]

CR2[0]

RFU

Reserved (0)

Reserved for future use

NV - Non-volatile

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4.2.2.1

Quad SPI (QPI) CR2 [6]

This bit controls the instruction and data widths in quad SPI mode. In this mode, all transfers between the host

system and memory are 4 bits wide on I/O0 to I/O3, including all instructions. The QUAD bit set ‘1’ in CR1 [1] is not

necessary, hence ignored for the QPI mode. Refer to Table 22 for details.

4.2.2.2

IO3 reset (IO3R) CR2 [5]

This bit controls the RESET / (I/O3) pin behavior. When this bit is set ‘1’, enables the RESET input during normal

operation. Table 21 shows the RESET / (I/O3) functionality based on the interface mode.

4.2.2.3

Dual (DPI) CR2 [4]

This bit controls the instruction and data widths in dual SPI mode. In this mode, all transfers between the host

system and memory are 2 bits wide on I/O0 to I/O1, including all instructions (see Table 22).

Table 21

RESET / (I/O3) pin function

IO3R (CR2[5]) = 0

(IO3 reset disable)

IO3R (CR2[5]) = 1

(IO3 reset enable)

[6]

Interface mode

Quad bit (CR1[1] )

CS = 0

CS = 1

CS = 0

CS = 1

RESET

SPI

DPI

QPI

QUAD = 0

QUAD = 1

No function

RESET

[7]

I/O3

QUAD = 0

No function

I/O3

RESET

No function

I/O3

QUAD = 1

QUAD = x (Don’t care)

Table 22

QUAD

SPI operation modes setting

[8]

DPI

QPI

Operational mode

CR1[1]

CR2[4]

CR2[6]

0

1

X

0

1

0

1

0

1

0

1

SPI, extended SPI (Dual)

SPI, extended SPI (Dual/Quad)

DPI

QPI

[9]

SPI , extended SPI (Dual) – not a recommended configuration

[9]

SPI , extended SPI (Dual/Quad) - not a recommended configuration

Notes

6. All extended SPIs start in the SPI mode.

7. No function in SPI and DPI modes. I/O3 in quad data or quad I/O mode.

8. QUAD = 1 reconfigures I/O to QUAD mode and affects WP and RESET operations, refer to Table 21 for details.

9. Register reads will always return what is written to them, even though not a recommended configuration.

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CY15x108QSN registers

4.2.3

Configuration Register 4 (CR4)

The Configuration Register 4 (CR4), as shown in Table 23, controls the output drive impedance and the

deep-power-down (DPD) mode settings. The CR4 is accessible by the WRAR command for write and the RDCR4

or the RDAR command for read operations. The CR4 access details are provided in “Register Access commands”

on page 35.

WRAR non-volatile write address - 0x000005

WRAR volatile write address - 0x070005

RDAR read address - 0x000005 or 0x070005

The default state shown after each bit in Table 23 is the factory programmed value.

Table 23

CR4[7]

OI (0)

Configuration Register 4 (CR4)

CR4[6]

CR4[5]

CR4[4]

CR4[3]

CR4[2]

CR4[1]

CR4[0]

OI (0)

RFU (0)

RFU (1)

DPDPOR (0)

RFU (0)

Table 24

Bit

Configuration Register 4 (CR4) - Non-volatile

Bit name

Bit function

Type

NV

Read/write

R/W

Description

CR4[7]

CR4[6]

CR4[5]

CR4[4]

CR4[3]

OI

Output impedance

NV

R/W

Output impedance selection

Reserved for future use

NV

R/W

RFU

Reserved (0)

Reserved (1)

[10]

Reserved for future use

1 = Deep power-down is entered upon

completion of POR or hardware reset

(including JEDEC reset) when CS is HIGH.

0 = Standby mode is entered upon completion

of power-up or POR or hardware reset

(including JEDEC reset) when CS is HIGH.

Deep power-down

mode on POR

CR4[2]

DPDPOR

NV

R/W

CR4[1]

CR4[0]

RFU

Reserved (0)

Reserved for future use

NV - Non-volatile

Table 25

Configuration Register 4 (CR4) - Volatile

Bit

CR4[7]

CR4[6]

CR4[5]

CR4[4]

CR4[3]

Bit name

Bit function

Type

Read/Write

R/W

Description

V

OI

Output impedance

V

R/W

Output impedance selection

R/W

RFU

Reserved (0)

Reserved (1)

Reserved for future use

1 = Deep Power-Down is entered upon

completion of POR or Hardware reset

(including JEDEC reset) when CS is HIGH.

0 = Standby mode is entered upon completion

of Power-up or POR or Hardware reset

(including JEDEC reset) when CS is HIGH

Deep power-down

mode on POR

CR4[2]

DPDPOR

V

R/W

CR4[1]

RFU

Reserved (0)

Reserved for future use

CR4[0]

V - Volatile

Note

10. The SPI bus master must make sure bit CR4 [3] remains ‘1’ when writing to this configuration register. Writing a ‘0’ to

this bit may impact device functionality.

Datasheet

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4.2.3.1

Output impedance (OI) CR4 [7:5]

These three bits control the output impedance (drive strength) of the I/O pins. The output impedance

configuration bits enable the user to adjust the drive strength for a better signal integrity on the printed circuit

board.

Table 26

Impedance selection

[11]

Impedance selection

Typical impedance (Ω)

Comments

000

001

010

011

100

101

110

111

45

120

90

45 Ωis the factory default configuration.

Other drive strength can be

programmedbywriting into impedance

selection bits in CR4[7:5].

60

45

30

20

4.2.3.2

Deep-power-down mode on POR (DPDPOR) CR4 [2]

This bit controls whether the device enters the deep-power-down (DPD) or the standby mode after the

completion of power-on-reset (POR), hardware reset (RESET pin or JEDEC reset), or exit the hibernate mode. The

DPDPOR configuration bit enables the device to start in DPD mode, instead of standby mode when CS is HIGH. A

CS pulse-width of t_CSDPD, or hardware reset will exit the DPD mode after t_EXTDPDtime. The CS pulse-width can be

generated by toggling CS alone while SCK and I/Os are don’t care. The DPDPOR bit status is ignored during the

software reset and the device always enters standby after the software reset.

Note

11. Typical impedance measured at V /2.

DD

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CY15x108QSN registers

4.2.4

Configuration Register 5 (CR5)

The Configuration Register 5 (CR5), as shown in Table 27, configures the read latency (dummy) cycles for register

read. The CR5 is accessible by the WRAR command for write and the RDCR5 or the RDAR command for read

operations. The CR5 access details are provided in “Register Access commands” on page 35.

WRAR non-volatile write address - 0x000006

WRAR volatile write address - 0x070006

RDAR read address - 0x000006 or 0x070006

The default state shown after each bit in Table 27 is the factory programmed value.

Table 27

CR5[7]

Configuration Register 5 (CR5)

CR5[6]

CR5[5]

CR5[4]

CR5[3]

CR5[2]

CR5[1]

CR5[0]

RLC1 (0)

RLC0 (0)

RFU (0)

Table 28

Bit

Configuration Register 5 (CR5) - Non-volatile

Bit name

Bit function

Type

Read/write

Description

CR5[7]

RLC1

R/W

Selects number of register read latency cycles

between 0 to 3 clock cycles for register

accesses

Register

NV

latency code

CR5[6]

RLC0

R/W

CR5[5]

CR5[4]

CR5[3]

CR5[2]

CR5[1]

CR5[0]

RFU

Reserved (0)

Reserved for future use

NV - Non-volatile

Table 29

Configuration Register 5 (CR5) - volatile

Bit

CR5[7]

CR5[6]

CR5[5]

CR5[4]

CR5[3]

CR5[2]

CR5[1]

CR5[0]

V - Volatile

Bit name

Bit function

Type

Read/write

R/W

Description

RLC1

RLC0

RFU

Selects number of register read latency cycles

between 0 to 3 clock cycles for register accesses

Register

V

latency code

R/W

Reserved (0)

Reserved for future use

Datasheet

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CY15x108QSN registers

4.2.4.1

Register latency code (RLC [1:0]) CR5 [7:6]

These two bits control the read latency (dummy cycle) delay in all variable latency register read instructions. It

enables users to adjust the read latency during normal operation to optimize the latency for different register

read instructions at different operating frequencies. Table 30 shows latency cycles for register read command.

Table 30

Dummy cycles for register read commands

SPI (SDR)

DPI (SDR)

QPI (SDR)

Latency (dummy cycles)

RDSR1, RDSR2, RDCR1, RDCR2, RDCR4, RDCR5, RDAR, RUID, RDID2, RDSN

[12]

0

50 MHz

108 MHz

50 MHz

108 MHz

50 MHz

108 MHz

1–3

Note

12. This parameter is guaranteed by characterization; not tested in production.

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Functional description

5

Functional description

The CY15x108QSN has an 8-bit instruction register. All instructions and their opcodes are listed in Table 32. All

instructions, addresses, and data are transferred with a HIGH to LOW CS transition. Furthermore, the WP and

RESET pins provide additional hardware controlled functions.

5.1

Command structure

The CY15x108QSN command cycle consists of up to five different command phases - opcode, address, mode,

dummy (latency), and data. The number of command phases per command cycle varies from one to five

depending on the opcode sent in the opcode phase. The opcode, address, mode, and data phases are configu-

rable in terms of number of lines 1, 2, or 4 needed to transmit them in SPI, DPI, or QPI interface, respectively.

Table 31 shows the command phases for each command cycle in different SPI interfaces.

Table 31

Command transmission over I/Os in different SPI modes

Command transmission on I/Os

Command

Extended SPI

Multi-channel SPI

Single

phases

channel SPI

Dual data

Quad data

Dual I/O

Quad I/O

DPI

QPI

I/O0, I/O1,

I/O2, I/O3

Opcode

Address

Mode

SI

I/O0

I/O0, I/O1

I/O0, I/O1,

I/O2, I/O3

I/O0, I/O1,

I/O2, I/O3

I/O0

I/O0, I/O1

I/O0, I/O1,

I/O2, I/O3

I/O0, I/O1,

I/O2, I/O3

Fixed number of dummy SPI clocks, independent of SPI interface.

0 to 15 clocks for memory access (configurable via CR1[7:4])

0 to 3 clocks for register access (configurable via CR5[7:6])

Dummy

(Latency)

I/O0, I/O1,

I/O2, I/O3

I/O0, I/O1,

I/O2, I/O3

I/O0, I/O1,

I/O2, I/O3

Data

SI/SO

I/O0, I/O1

There are 44 commands, called opcodes that can be issued by the bus master to the CY15xQSN as shown in

Table 32. These opcodes control the functions performed by the memory.

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Functional description

Table 32

Opcode commands

Data

Command

SPI bus interface

Latency

XIP

transfer

Opcode

(HEX)

Dual Quad Dual Quad

Register Memory Execute

Command

SPI

DPI QPI SDR DDR

data data I/O

I/O

latency

latency -in-place

Write enable control

WREN

WRDI

06

04

Yes

NA

Yes Yes Yes NA

NA

Register access

WRSR

01

05

07

35

3F

45

5E

71

65

Yes

NA

Yes Yes Yes NA

NA

Yes

NA

RDSR1

RDSR2

RDCR1

RDCR2

RDCR4

RDCR5

WRAR

RDAR

Yes

Memory read

READ

03

0B

Yes

NA

Yes Yes Yes NA

Yes NA

NA

Yes

NA

FAST_

READ

Yes

DOR

DIOR

3B

BB

6B

EB

0D

ED

NA Yes

NA

Yes

NA

Yes NA

QOR

NA

Yes

NA

QIOR

NA

Yes

NA Yes Yes NA

Yes NA Yes

DDRFR

NA

DDRQIOR

Memory write

WRITE

NA

Yes

NA Yes NA Yes

02

Yes

NA

Yes Yes Yes NA

Yes NA

NA

FAST_

WRITE

DA

Yes

DIW

DIOW

QIW

A2

A1

32

D2

NA Yes

NA

Yes

NA

Yes NA

NA

Yes

NA

QIOW

NA

Yes

NA

DDR_FAST

_WRITE

DD

NA

Yes NA Yes

NA

Yes

DDRWRITE

DDRQIOW

DE

D1

Yes NA Yes

NA Yes

NA

Yes

Special sector memory access

SSWR

SSRD

42

4B

Yes

NA

Yes Yes Yes NA

NA

Yes

ECC and CRC

CLECC

1B

Yes

NA

Yes Yes Yes NA

NA

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Functional description

Table 32

Opcode commands (continued)

SPI bus interface

Data

Command

Latency

XIP

transfer

Opcode

(HEX)

Dual Quad Dual Quad

Register Memory Execute

Command

SPI

DPI QPI SDR DDR

data data I/O

I/O

latency

NA

latency -in-place

ECCRD

CRCC

EPCS

EPCR

19

5B

75

7A

Yes

NA

Yes Yes Yes NA

Yes

NA

Identification and serial number

RUID

RDID

4C

9F

C2

C3

Yes

NA

Yes Yes Yes NA

Yes

NA

WRSN

RDSN

Power modes and reset

DPD

HBN

B9

BA

66

99

Yes

NA

Yes Yes Yes NA

NA

RSTEN

RST

5.1.1

Write Enable Control commands

These commands set or clear the write enable latch bit in the Status Register 1 (SR1[1]).

Table 33 Write Enable Control commands

Command Opcode (Hex)

Command description

WREN

WRDI

06

04

Write enable – sets the WEL bit of Status Register 1 to ‘1’

Write disable – clears the WEL bit of Status Register 1 to ‘0’

Table 34

Write Enable Control command details

SPI bus interface

Data

XIP

Latency

transfer

Opcode Address

Max. clock

frequency

(Hex)

length

Dual Quad Dual Quad

Execute Dummy

SPI

DPI QPI SDR DDR

data data

I/O

IO

-in-place

NA

cycles

NA

06

04

0

Yes

NA

Yes Yes Yes

NA

108 MHz

NA

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Functional description

5.1.1.1

Set Write Enable Latch (WREN, 06h)

The WREN command sets the WEL bit of Status Register 1 (SR1[1]) to a ‘1’. CY15x108QSN requires WEL bit set to

a ‘1’ prior to issuing any write command. The CY15x108QSN commands requiring WEL set to ‘1’ prior to their

execution are WRSR, WRAR, WRITE, FAST_WRITE, DIW, DIOW, QIW, QIOW, DDR_FAST_WRITE, DDRWRITE,

DDRQIOW, SSWR, and WRSN.

CS must be driven to the logic HIGH state after the eighth bit of the instruction byte has been latched in on SI.

CY15x108QSN executes the WREN command and sets the WEL bit (SR1[1]) to ‘1’ after CS is driven HIGH after 8-bit

WREN opcode is successfully latched in.

CS

SCK

0

1

0

X

SI (IO0)

hi-Z

Opcode (06h)

hi-Z

SO (IO1)

Figure 6

WREN bus configuration in SPI mode

CS

SCK

hi-Z

0

1

0

1

SI (IO0)

hi-Z

SO (IO1)

Opcode (06h)

Figure 7

WREN bus configuration in DPI mode

CS

SCK

hi-Z

0

1

0

SI (IO0)

SO (IO1)

hi-Z

WP (IO2)

RESET (IO3)

Opc.

(06h)

Figure 8

WREN bus configuration in QPI mode

Datasheet

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Functional description

5.1.1.2

Reset Write Enable Latch (WRDI, 04h)

The WRDI instruction clears the write enable latch (WEL) bit of the Status Register 1 (SR1[1]) to a ‘0’. This disables

Write Status Register (WRSR), Write Any Register (WRAR), Special Sector Write (SSWR), and other instructions that

require WEL to be set to ‘1’ prior to the execution. The WRDI instruction can be used to protect the memory and

the SPI registers against inadvertent writes. The WRDI command is ignored during an embedded operation while

WIP bit = 1.

CS must be driven to the logic HIGH state after the eighth bit of the instruction byte has been latched in on SI.

CY15x108QSN executes the WRDI command and clears the WEL bit (SR1[1]) to ‘0’ after CS is driven HIGH after 8-bit

WRDI opcode is successfully latched in.

CS

SCK

0

1

0

X

SI (IO0)

hi-Z

Opcode (04h)

hi-Z

SO (IO1)

Figure 9

WRDI bus configuration in SPI mode

CS

SCK

hi-Z

0

1

0

SI (IO0)

hi-Z

SO (IO1)

Opcode (04h)

Figure 10

WRDI bus configuration in DPI mode

CS

SCK

hi-Z

0

1

0

SI (IO0)

SO (IO1)

hi-Z

WP (IO2)

RESET (IO3)

Opc.

(04h)

Figure 11

WRDI bus configuration in QPI mode

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Functional description

5.1.2

Register Access commands

CY15x108QSN provides various configuration and status registers. These registers are user-writable, which can

be programmed to enable or disable certain configurations/features in the part as well as can be polled to know

the device status. These registers are accessed by specific commands, called opcodes.

The individual register bits can be one of multiple types: write/read, read only, or reserved for future use (RFU).

The specific type of each bit is specified in their respective register section. Register bits can be either volatile or

non-volatile in nature. All volatile (V) bits are set to their default values after power-on reset (POR), or any reset

event (via hardware or software resets); while all non-volatile (NV) bits resume to user configured values after

power-on reset (POR), or any reset event (via hardware or software resets).

Table 35

Register Access commands

Opcode (Hex)

Command

Command description

WRSR

RDSR1

RDSR2

RDCR1

RDCR2

RDCR4

RDCR5

01

05

07

35

3F

45

5E

Write Status Register 1

Read Status Register 1

Read Status Register 2

Read Configuration Register 1

Read Configuration Register 2

Read Configuration Register 4

Read Configuration Register 5

Write Any Register - Including Status registers, Configurations registers, Serial Number

registers

WRAR

RDAR

71

65

Read Any Register - Including Status registers, Configurations registers, CRC registers,

ECC registers, Serial Number registers, and ID registers

Table 36

Register Access command details

SPI bus interface

Data

Register

latency

transfer

Opcode Address

Max. clock Register

(Hex)

length

frequency

latency

Dual Quad Dual Quad

Dummy

cycle

SPI

DPI QPI SDR DDR

data data I/O

I/O

01

05

07

35

3F

45

5E

71

65

0

Yes

NA

Yes Yes Yes NA

NA

Yes

NA

108 MHz

NA

Yes

NA

3 bytes Yes

Yes

Datasheet

35 of 109

002-30246 Rev. *D

2022-05-25

8Mb EXCELON™ Ultra Ferroelectric RAM (F-RAM)

Serial (Quad SPI), 1024K × 8, 108MHz, industrial

Functional description

5.1.2.1

Write Status Register (WRSR, 01h)

The Write Status Register (WRSR) instruction allows new values to be programmed in Status Register 1 (SR1). This

instruction writes to the non-volatile SR1, thus survives the power cycle. The WRSR command is ignored when

the SRWD bit in SR1 (SR1[7]) is set ‘1’ and the WP pin is asserted LOW.

Notes

• The WRSR instruction executes only when WEL bit in SR1 is set to ‘1’; otherwise, the WRSR instruction will be

ignored.

• The WEL bit of the Status Register 1 (SR1[1]) is automatically cleared to ‘0’ after WRSR command is terminated

(at the rising edge of CS).

CS

SCK

hi-Z

0

1

D7

D6

D5

D4

D3

D2

D1

D0

X

SI (IO0)

hi-Z

SO (IO1)

Opcode (01h)

SR1

Figure 12

WRSR in SPI mode (WREN not shown)

CS

SCK

hi-Z

0

1

0

D6 D4

D2

D0

D1

SI (IO0)

hi-Z

D7

D5

D3

SO (IO1)

Opcode (01h)

SR1

Figure 13

WRSR in DPI mode (WREN not shown)

CS

SCK

hi-Z

0

1

0

D4

D5

D6

D7

D0

D1

D2

D3

SI (IO0)

hi-Z

0

SO (IO1)

hi-Z

0

WP (IO2)

hi-Z

RESET (IO3)

Opc.

(01h)

SR1

Figure 14

WRSR in QPI mode (WREN not shown)

Datasheet

36 of 109

002-30246 Rev. *D

2022-05-25

8Mb EXCELON™ Ultra Ferroelectric RAM (F-RAM)

Serial (Quad SPI), 1024K × 8, 108MHz, industrial

Functional description

5.1.2.2

Read Status Register 1 (RDSR1, 05h)

The RDSR1 command allows the bus master to verify the contents of the Status Register 1 (SR1). Reading SR1

provides information about the current state of the write-protection features, WEL, and WIP status. Following the

RDSR1 opcode, the CY15x108QSN will return one byte SR1 content.

Notes

• The RDSR1 returns the volatile content of SR1.

• The dummy cycles shown are a configuration option through register latency code bits (RLC0, RLC1) in CR5.

CS

SCK

hi-Z

SI (IO0)

X

0

1

0

1

DM7 DM6 DM5 DM4 DM3 DM2 DM1 DM0

X

hi-Z

SO (IO1)

D7

D6

D5

D4

D3

D2

D1

D0

Opcode (05h)

Dummy Cycles

Status Register 1

Figure 15

Read SR1 (RDSR1) in SPI mode

CS

SCK

hi-Z

SI (IO0)

0

1

0

1

0

DM7 DM6

DM1 DM0 D6

D4

D5

D2

D3

D0

D1

hi-Z

SO (IO1)

DM1 DM0 D7

Status

Register 1

Opcode (05h)

ummy Cycles

D

Figure 16

Read SR1 (RDSR1) in DPI mode

CS

SCK

hi-Z

0

1

0

1

0

DM7 DM6

DM1 DM0 D4

DM1 DM0 D5

DM1 DM0 D6

DM1 DM0 D7

D0

SI (IO0)

hi-Z

0

D1

SO (IO1)

hi-Z

0

D2

WP (IO2)

hi-Z

0

D3

RESET (IO3)

Opc.

(05h)

Status

Reg. 1

Dummy Cycles

Figure 17

Read SR1 (RDSR1) in QPI mode

Datasheet

37 of 109

002-30246 Rev. *D

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8Mb EXCELON™ Ultra Ferroelectric RAM (F-RAM)

Serial (Quad SPI), 1024K × 8, 108MHz, industrial

Functional description

5.1.2.3

Read Status Register 2 (RDSR2, 07h)

The RDSR2 command allows the bus master to verify the contents of the Status Register 2 (SR2). This is a read

only register and provides information about the CRC suspend and CRC abort status. The SR2 bits indicate the

correct status (CRCS and CRCA) only when the WIP bit of SR1 is ‘0’. Reading SR2 while WIP is ‘1’ will return an

undetermined status.

Notes

• The RDSR2 returns the volatile content of SR2.

• The dummy cycles shown are a configuration option through register latency code bits (RLC0, RLC1) in CR5.

CS

SCK

hi-Z

SI (IO0)

X

0

1

DM7 DM6 DM5 DM4 DM3 DM2 DM1 DM0

X

hi-Z

SO (IO1)

D7

D6

D5

D4

D3

D2

D1

D0

Opcode (07h)

Dummy Cycles

Status Register 2

Figure 18

Read SR2 (RDSR2) in SPI mode

CS

SCK

hi-Z

0

1

0

DM7 DM6

DM1 DM0 D4

DM1 DM0 D5

DM1 DM0 D6

DM1 DM0 D7

D0

D1

D2

D3

SI (IO0)

hi-Z

0

SO (IO1)

WP (IO2)

0

RESET (IO3)

Opc.

(07h)

Status

Reg. 2

Dummy Cycles

Figure 19

Read SR2 (RDSR2) in DPI mode

CS

SCK

hi-Z

0

1

0

DM7 DM6

DM1 DM0 D4

D0

D1

D2

D3

SI (IO0)

hi-Z

0

DM1 DM0 D5

DM1 DM0 D6

DM1 DM0 D7

SO (IO1)

WP (IO2)

0

RESET (IO3)

Opc.

(07h)

Status

Reg. 2

Dummy Cycles

Figure 20

Read SR2 (RDSR2) in QPI mode

Datasheet

38 of 109

002-30246 Rev. *D

2022-05-25

8Mb EXCELON™ Ultra Ferroelectric RAM (F-RAM)

Serial (Quad SPI), 1024K × 8, 108MHz, industrial

Functional description

5.1.2.4

Read Configuration Register 1 (RDCR1, 35h)

The RDCR1 command allows the bus master to verify the contents of the Configuration Register 1 (CR1). Reading

CR1 provides information about the current state of the memory latency code and QUAD bit status. Following the

RDCR1 opcode, the CY15x108QSN will return one byte content of CR1.

Notes

• The RDCR1 returns the volatile content of CR1.

• The dummy cycles shown are a configuration option through register latency code bits (RLC0, RLC1) in CR5.

CS

SCK

hi-Z

SI (IO0)

X

0

1

0

1

0

1

DM7 DM6 DM5 DM4 DM3 DM2 DM1 DM0

X

hi-Z

SO (IO1)

D7

D6

D5

D4

D3

D2

D1

D0

Opcode (35h)

Dummy Cycles

Config Register 1

Figure 21

Read CR1 (RDCR1) in SPI mode

CS

SCK

hi-Z

SI (IO0)

0

1

0

1

0

DM7 DM6

DM1 DM0 D6

DM1 DM0 D7

D4

D5

D2

D3

D0

hi-Z

SO (IO1)

D1

Config

Register 1

Opcode (35h)

Dummy Cycles

Figure 22

Read CR1 (RDCR1) in DPI mode

CS

SCK

hi-Z

1

DM7 DM6

DM1 DM0 D4

DM1 DM0 D5

DM1 DM0 D6

DM1 DM0 D7

D0

D1

D2

D3

SI (IO0)

hi-Z

1

0

1

0

SO (IO1)

hi-Z

0

WP (IO2)

hi-Z

0

RESET (IO3)

Opc.

(35h)

Config

Reg. 1

Dummy Cycles

Figure 23

Read CR1 (RDCR1) in QPI mode

Datasheet

39 of 109

002-30246 Rev. *D

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8Mb EXCELON™ Ultra Ferroelectric RAM (F-RAM)

Serial (Quad SPI), 1024K × 8, 108MHz, industrial

Functional description

5.1.2.5

Read Configuration Register 2 (RDCR2, 3Fh)

The RDCR2 command allows the bus master to verify the contents of the Configuration Register 2 (CR2). Reading

CR2 provides information about the current SPI interface option (SPI vs DPI vs QPI) and RESET / (I/O3) status.

Following the RDCR2 opcode, the CY15x108QSN will return one byte content of CR2.

Notes

• The RDCR2 returns the volatile content of CR2.

• The dummy cycles shown are a configuration option through register latency code bits (RLC0, RLC1) in CR5.

CS

SCK

hi-Z

SI (IO0)

X

0

1

DM7 DM6 DM5 DM4 DM3 DM2 DM1 DM0

X

hi-Z

SO (IO1)

D7

D6

D5

D4

D3

D2

D1

D0

Opcode (3Fh)

Dummy Cycles

Config Register 2

Figure 24

Read CR2 (RDCR2) in SPI mode

CS

SCK

hi-Z

SI (IO0)

0

1

DM7 DM6

DM1 DM0 D6

DM1 DM0 D7

D4

D5

D2

D3

D0

hi-Z

SO (IO1)

D1

Config

Register 2

Opcode (3Fh)

Dummy Cycles

Figure 25

Read CR2 (RDCR2) in DPI mode

CS

SCK

hi-Z

1

DM7 DM6

DM1 DM0 D4

DM1 DM0 D5

DM1 DM0 D6

DM1 DM0 D7

D0

D1

D2

D3

SI (IO0)

hi-Z

1

SO (IO1)

hi-Z

0

WP (IO2)

hi-Z

0

RESET (IO3)

Opc.

(3Fh)

Config

Reg. 2

Dummy Cycles

Figure 26

Read CR2 (RDCR2) in QPI mode

Datasheet

40 of 109

002-30246 Rev. *D

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8Mb EXCELON™ Ultra Ferroelectric RAM (F-RAM)

Serial (Quad SPI), 1024K × 8, 108MHz, industrial

Functional description

5.1.2.6

Read Configuration Register 4 (RDCR4, 45h)

The RDCR4 command allows the bus master to verify the contents of the Configuration Register 4 (CR4). Reading

CR4 provides information about the output impedance setting and device power mode status after POR

(deep-power-down vs standby). Following the RDCR4 opcode, the CY15x108QSN will return one byte content of

CR4.

Notes

• The RDCR4 returns the volatile content of CR4.

• The dummy cycles shown are a configuration option through register latency code bits (RLC0, RLC1) in CR5.

CS

SCK

hi-Z

SI (IO0)

X

0

1

0

1

0

1

DM7 DM6 DM5 DM4 DM3 DM2 DM1 DM0

X

hi-Z

SO (IO1)

D7

D6

D5

D4

D3

D2

D1

D0

Opcode (45h)

Dummy Cycles

Config Register 4

Figure 27

Read CR4 (RDCR4]) in SPI mode

CS

SCK

hi-Z

SI (IO0)

1

0

1

0

1

0

DM7 DM6

DM1 DM0 D6

DM1 DM0 D7

D4

D5

D2

D0

hi-Z

SO (IO1)

D3

D1

Config

Register 4

Opcode (45h)

Dummy Cycles

Figure 28

Read CR4 (RDCR4) in DPI mode

CS

SCK

hi-Z

0

1

0

1

0

DM7 DM6

DM1 DM0 D4

DM1 DM0 D5

DM1 DM0 D6

DM1 DM0 D7

D0

SI (IO0)

hi-Z

0

D1

SO (IO1)

hi-Z

1

D2

WP (IO2)

hi-Z

0

D3

RESET (IO3)

Opc.

(45h)

Config

Reg. 4

Dummy Cycles

Figure 29

Read CR4 (RDCR4) in QPI mode

Datasheet

41 of 109

002-30246 Rev. *D

2022-05-25

8Mb EXCELON™ Ultra Ferroelectric RAM (F-RAM)

Serial (Quad SPI), 1024K × 8, 108MHz, industrial

Functional description

5.1.2.7

Read Configuration Register 5 (RDCR5, 5Eh)

The RDCR5 command allows the bus master to verify the contents of the Configuration Register 5 (CR5). Reading

CR5 provides information about the register read latency cycles (RLC0, RLC1) setting. Following the RDCR5

opcode, the CY15x108QSN will return one byte content of CR5.

Notes

• The RDCR5 returns the volatile content of CR5.

• The dummy cycles shown are a configuration option through register latency code bits (RLC0, RLC1) in CR5.

CS

SCK

hi-Z

SI (IO0)

X

0

1

0

1

0

DM7 DM6 DM5 DM4 DM3 DM2 DM1 DM0

X

hi-Z

SO(IO1)

D7

D6

D5

D4

D3

D2

D1

D0

Opcode (5Eh)

Dummy Cycles

Config Register 5

Figure 30

Read CR5 (RDCR5) in SPI mode

CS

SCK

hi-Z

SI (IO0)

1

0

1

0

1

0

1

DM7 DM6

DM1 DM0 D6

DM1 DM0 D7

D4

D2

D0

hi-Z

SO (IO1)

D5

D3

D1

Config

Register 5

Opcode (5Eh)

Dummy Cycles

Figure 31

Read CR5 (RDCR5) in DPI mode

CS

SCK

hi-Z

1

0

1

DM7 DM6

DM1 DM0 D4

DM1 DM0 D5

DM1 DM0 D6

DM1 DM0 D7

D0

SI (IO0)

hi-Z

0

D1

D2

D3

SO (IO1)

hi-Z

1

WP (IO2)

hi-Z

0

RESET (IO3)

Opc.

(5Eh)

Config

Reg. 5

Dummy Cycles

Figure 32

Read CR5 (RDCR5) in QPI mode

Datasheet

42 of 109

002-30246 Rev. *D

2022-05-25

8Mb EXCELON™ Ultra Ferroelectric RAM (F-RAM)

Serial (Quad SPI), 1024K × 8, 108MHz, industrial

Functional description

5.1.2.8

Write Any Register (WRAR, 71h)

The WRAR instruction allows writing into CY15xQSN registers, one register at a time, addressable by their 3-byte

addressing. The WRAR opcode is followed by the three-byte address of the register, as shown in Table 38,

followed by one byte register data to be written. The WREN command precedes the WRAR command to set the

WEL bit ‘1’ prior to WRAR. The WEL bit is automatically cleared to ‘1’ after WRAR command is terminated (at the

rising edge of CS). The WRAR command is ignored when the SRWD bit in SR1 (SR1[7]) is set to ‘1’ and the WP pin

is driven LOW.

Notes

• The WRAR command supports only one byte write per WRAR command at the given register address. The WRAR

command format is shown in Table 37.

• The register address sent in 3-byte address field after the WRAR opcode determines whether new configuration

will be programmed into the Volatile Status/Configuration Register only, or will be programmed into both

volatile and Non-volatile Status/Configuration Register. Table 38 shows register addresses for both volatile and

non-volatile registers.

Table 37

Registers with generic write instructions

Instruction name

WRAR

Instruction description

Opcode

Address bytes

Data bytes

Write Any Register

71h

3

1

CS

SCK

OP7 OP6

OP1 OP0 A23 A22

A1

A0

D7

D6

D5

D4

D3

D2

D1

D0

X

SI (IO0)

hi-Z

SO (IO1)

Opcode

(71h)

Address

(3 Bytes)

Data

(1 Byte)

Figure 33

Write Any Register (WRAR) in SPI mode

CS

SCK

hi-Z

OP6 OP4 OP2 OP0 A22 A20

A2

A0

D6

D4

D2

D3

D0

D1

SI (IO0)

hi-Z

OP7 OP5 OP3 OP1 A23 A21

A3

A1

D7

D5

SO (IO1)

Opcode

(71h)

Address

(3 Bytes)

Data

(1 Byte)

Figure 34

Write Any Register (WRAR) in DPI mode

Datasheet

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002-30246 Rev. *D

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8Mb EXCELON™ Ultra Ferroelectric RAM (F-RAM)

Serial (Quad SPI), 1024K × 8, 108MHz, industrial

Functional description

CS

SCK

hi-Z

OP4 OP0 A20

OP5 OP1 A21

OP6 OP2 A22

OP7 OP3 A23

A0

D4

D5

D6

D7

D0

D1

D2

D3

SI (IO0)

hi-Z

A1

A2

A3

SO (IO1)

WP (IO2)

RESET (IO3)

Opc.

(71h)

Address

(3 Bytes)

Data

(1 Byte)

Figure 35

Table 38

Write Any Register (WRAR) in QPI mode

Register address for generic register access

Register

[13]

Register address

[14]

Function

Register type

WRAR RDAR

[14]

content

Volatile

Non-volatile

Volatile and

Non-volatile

Status Register 1

Yes

0x070000

0x000000

Device status

Yes

Status Register 2

Volatile only

NA

0x070001 or 0x000001

Configuration Register 1

Configuration Register 2

Configuration Register 4

Configuration Register 5

ECC Status Register

0x070002

0x070003

0x070005

0x070006

0x000002

0x000003

0x000005

0x000006

Device

configuration

Volatile and

Non-volatile

Yes

0x070089 or 0x000089

0x07008A or 0x00008A

0x07008B or 0x00008B

0x07008E or 0x00008E

0x07008F or 0x00008F

0x070040 or 0x000040

0x070041 or 0x000041

0x070095 or 0x000095

0x070096 or 0x000096

0x070097 or 0x000097

0x070098 or 0x000098

ECC Count Register [7:0]

ECC Count Register [15:8]

Error correction ECC Address Trap Register [7:0]

ECC Address Trap Register [15:8]

ECC Address Trap Register [23:16]

ECC Address Trap Register [31:24]

CRC Register [7:0]

Volatile only

NA

Yes

Cyclic

CRC Register [15:8]

redundancy

CRC Register [23:16]

check

CRC Register [31:24]

Notes

13. The volatile registers return to their default state after POR or hardware Reset. Refer to Table 59 for the volatile register

status after any POR or Reset event.

14. The RDAR command always returns content from the volatile register. Therefore, RDAR followed by either volatile

register address or non-volatile register address will return identical values (from respective volatile register only). The

volatile only register does not have associated non-volatile register.

Datasheet

44 of 109

002-30246 Rev. *D

2022-05-25

8Mb EXCELON™ Ultra Ferroelectric RAM (F-RAM)

Serial (Quad SPI), 1024K × 8, 108MHz, industrial

Functional description

5.1.2.9

Read Any Register (RDAR, 65h)

The RDAR instruction allows reading CY15x108QSN registers, one register at a time, addressable by their 3-byte

addressing. The RDAR opcode is followed by the three-byte address of the register and dummy cycle (per register

latency set in CR5), after which CY15x108QSN returns one byte register content on its output bus. The host should

terminate the RDAR command by pulling CS HIGH after one register byte is received. Keeping CS LOW after the

first data byte received will return undefined data byte(s). The RDAR instruction timing diagrams are shown in

Figure 36 to Figure 38.

Notes

• Since the status and configuration register read always returns the register content from its volatile space, hence

the 3-byte address following the WRAR opcode can be the register address of either volatile register or its

associated non-volatile register. Table 38 shows register addresses for both volatile and non-volatile registers.

• The dummy cycles shown are a configuration option through register latency code bits (RLC0, RLC1) in CR5.

CS

SCK

OP7 OP6

OP1 OP0 A23 A22

A1

A0 DM7 DM6

DM1 DM0

X

SI (IO0)

hi-Z

D7

D6

D5

D4

D3

D2

D1

D0

SO (IO1)

Address

(3 Bytes)

Opcode

Dummy Cycles

Read data

Figure 36

Read Any Register (RDAR) in SPI mode

CS

SCK

hi-Z

OP6 OP4 OP2 OP0 A22 A20

A2

A3

A0 DM7 DM6

A1 DM7 DM6

DM1 DM0 D6

DM1 DM0 D7

D4

D5

D2

D3

D0

D1

SI (IO0)

hi-Z

OP7 OP5 OP3 OP1 A23 A21

SO (IO1)

Address

(3 Bytes)

Opcode

Dummy Cycles

Read data

Figure 37

Read Any Register (RDAR) in DPI mode

CS

SCK

hi-Z

OP4 OP0 A20

OP5 OP1 A21

OP6 OP2 A22

OP7 OP3 A23

A0 DM7 DM6

DM1 DM0 D4

D0

D1

D2

D3

SI (IO0)

hi-Z

A1 DM7 DM6

DM1 DM0 D5

DM1 DM0 D6

DM1 DM0 D7

SO (IO1)

A2 DM7 DM6

A3 DM7 DM6

WP (IO2)

RESET (IO3)

Address

(3 Bytes)

Read

data

Opc.

DMY Cycles

Figure 38

Read Any Register (RDAR) in QPI mode

Datasheet

45 of 109

002-30246 Rev. *D

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8Mb EXCELON™ Ultra Ferroelectric RAM (F-RAM)

Serial (Quad SPI), 1024K × 8, 108MHz, industrial

Functional description

5.1.3

Memory operation

The SPI interface, which is capable of a high clock frequency, highlights the fast write capability of the F-RAM

technology. Unlike serial flash, the CY15x108QSN can perform sequential writes at bus speed. No page register is

needed and any number of sequential writes can be performed.

5.1.4

Memory Write Operation commands

The memory write instruction is sent after the CS pin is pulled LOW. The write opcode is followed by a three-byte

address and mode byte for XIP (as applicable). The CY15x108QSN has a 20-bit address space for 8-Mbit (1024K ×

8) density. The most significant address byte contains A16, A17, A18, and A19 active bits while the remaining

A[23:20] bits are considered ‘don’t care’. Address bits A19 to A0 are transmitted in three bytes over the SPI bus,

following the (XIP) mode byte, if supported. Immediately after the last address bit or the last mode bit (if XIP is

supported) is transmitted, the data byte(s) ([D7:0]) is (are) transmitted through the input line(s). The memory

write operations are allowed in SPI, extended SPI, DPI or QPI Modes in SDR and DDR bus interfaces and some of

them support eXecute-In-Place (XIP). Table 39 shows the list of memory write commands supported in

CY15x108QSN in various SPI bus interface and data transfer modes.

Notes

• When a burst write reaches a protected block address, it continues incrementing the address into the protected

space but does not write any data to the protected memory. If the address rolls over and takes the burst write

to unprotected space, it resumes writes. The same operation is true if a burst write is initiated within a

write-protected block.

• If the power is lost in the middle of the byte transfer during the write operation, only the last completed byte

will be written.

Table 39

Memory Write commands

Opcode (Hex)

Command

Command description

Memory Write - write to F-RAM array

DDR Write - memory write in QPI DDR mode

WRITE

DDRWRITE

02

DE

DA

DD

FAST_WRITE

DDR_FAST_WRITE

Memory Fast Write - memory write with Execute-In-Place

DDR Fast Write - memory fast write in DDR mode

Dual Input Write - command, address and mode byte are sent on single SI line,

data bytes are sent on dual input lines I/O1 (SO), I/O0 (SI)

DIW

A2

A1

DDR Dual I/O Write - command is sent on single SI line, address and mode byte

and data bytes are sent on dual input lines I/O1 (SO), I/O0 (SI)

DIOW

Quad Input Write - command, address and mode bytes are sent on single SI

line, data bytes are sent on quad input lines I/O3 (RESET), I/O2 (WP), I/O1 (SO),

I/O0 (SI)

QIW

32

Quad I/O Write - command is sent on single SI line, address and mode byte and

QIOW

D2

D1

data bytes are sent on quad input lines I/O3 (RESET), I/O2 (WP), I/O1 (SO), I/O0

(SI)

DDRQIOW

DDR Quad I/O Write - quad I/O write in DDR mode

Datasheet

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8Mb EXCELON™ Ultra Ferroelectric RAM (F-RAM)

Serial (Quad SPI), 1024K × 8, 108MHz, industrial

Functional description

Table 40

Memory Write command details

Data

Command

SPI bus interface

XIP

transfer

Max. Clock

frequency

Execute-

in-place

(Mode

Opcode Address

Dual Quad Dual Quad

Command

SPI

DPI QPI SDR DDR

(Hex)

length

data data I/O

IO

byte)

WRITE

02

3 bytes Yes

3 bytes

NA

Yes Yes Yes

Yes NA

NA

108 MHz

46 MHz

DDRWRITE

DE

Yes

FAST_WRIT

E

DA

DD

3 bytes Yes

3 bytes

NA

Yes Yes Yes

NA

Yes

108 MHz

46 MHz

DDR_FAST_

WRITE

Yes NA

Yes

DIW

DIOW

A2

A1

32

D2

D1

3 bytes NA Yes

NA

Yes

108 MHz

46 MHz

3 bytes

NA

Yes

NA

Yes

NA

QIW

NA

Yes

NA

QIOW

Yes

NA

DDRQIOW

5.1.4.1

Write (WRITE, 02h)

Write operations are performed when the WRITE opcode, along with write data, are transmitted on the SI pin for

SPI mode, or I/O1 and I/O0 pins for DPI mode, or I/O3, I/O2, I/O1, and I/O0 pins for QPI mode. The burst writes can

be used to write consecutive addresses without issuing a new WRITE instruction. If only one byte is to be written,

the CS pin must be driven HIGH after the D0 (LSb of data) is transmitted. However, if more bytes are to be written,

CS pin must be held LOW and the address is incremented automatically. The data bytes on the input pin(s) are

written in successive addresses. When the internal address counter reaches to 0x0FFFFF, the address rolls over

to 0x00000 and the device continues to write.

Notes

• The WRITE instruction will only execute if the WEL bit (SR1[1]) is set to ‘1’.

• The WEL bit (SR1[1]) does not clear to ‘0’ on completion of the WRITE operation. Therefore, any write command

following the WRITE operation does not require preceding WREN command to set the WEL bit to ‘1’.

CS

SCK

0

1

0

A23 A22 A21 Am-3 A3

A2

A1

A0

D7

D6

D5

D4

D3

D2

D1

D0

X

SI (IO0)

Data Byte 1

hi-Z

SO (IO1)

Address

(3 Bytes)

Opcode (02h)

Write data

CS

SCK

D7

D6

D5

D4

D3

D2

D1

D0

D7

D6

D5

D4

D3

D2

D1

D0

X

SI (IO0)

Data Byte 2

Data Byte N

hi-Z

SO (IO1)

Write data

Figure 39

Memory write (WRITE) in SPI mode

Datasheet

47 of 109

002-30246 Rev. *D

2022-05-25

8Mb EXCELON™ Ultra Ferroelectric RAM (F-RAM)

Serial (Quad SPI), 1024K × 8, 108MHz, industrial

Functional description

CS

SCK

hi-Z

0

1

A22 A20

A23 A21

A2

A3

A0

A1

D6

D7

D4

D5

D2

D3

D0

D1

D6

D7

D4

D5

D2

D3

D0

D1

D6

D7

D4

D5

D2

D3

D0

D1

SI (IO0)

hi-Z

SO (IO1)

Data Byte 1

Data Byte 2

Data Byte N

Address

(3 Bytes)

Opcode (02h)

Write data

Figure 40

Memory write (WRITE) in DPI mode

CS

SCK

hi-Z

0

1

0

A20

A21

A22

A23

A0

D4

D5

D6

D7

D0

D1

D2

D3

D4

D0

D4

D5

D6

D7

D0

D1

D2

D3

SI (IO0)

hi-Z

A1

A2

A3

D5

D6

D7

D1

D2

D3

SO (IO1)

WP (IO2)

RESET (IO3)

Data

Byte 1

Data

Byte 2

Data

Byte N

Opc.

(02h)

Address

(3 Bytes)

Write data

Figure 41

Memory write (WRITE) in QPI mode

Datasheet

48 of 109

002-30246 Rev. *D

2022-05-25

8Mb EXCELON™ Ultra Ferroelectric RAM (F-RAM)

Serial (Quad SPI), 1024K × 8, 108MHz, industrial

Functional description

5.1.4.2

DDR Write (DDRWRITE, DEh)

The DDRWRITE instruction improves bandwidth by transferring address and data bits on both edges of SCK. The

address can start at any byte location of the memory array. The address is automatically incremented to the next

higher address in sequential order after each byte of data is shifted out. The entire memory can therefore be

written with one single write opcode and the start address provided. When the highest address 0x0FFFFF is

reached, the address counter will wrap around and roll back to 0x000000, allowing the read sequence to be

continued indefinitely. This opcode does not support SPI Mode 3.

Notes

• DDRWRITE instruction can only be executed by the device if the WEL bit is set to ‘1’ to enable write operations.

• The WEL bit does not reset to ‘0’ on completion of the DDRWRITE operation.

CS

SCK

A

2

0

A

1

6

hi-Z

A

4

A

0

D

4

D

0

D

4

D

0

1

0

1

0

1

SI(IO0)

SO(IO1)

A

2

1

A

1

7

A

5

A

1

D

5

D

1

D

5

D

1

A

2

A

1

8

A

6

A

2

D

6

D

2

D

6

D

2

WP(IO2)

A

2

3

A

1

9

A

7

A

3

D

7

D

3

D

7

D

3

RESET(IO3)

Opc.

(DEh)

Address

( 3Bytes)

Write Data

(N Bytes)

Figure 42

DDR write (DDRWRITE) in QPI mode

Datasheet

49 of 109

002-30246 Rev. *D

2022-05-25

8Mb EXCELON™ Ultra Ferroelectric RAM (F-RAM)

Serial (Quad SPI), 1024K × 8, 108MHz, industrial

Functional description

5.1.4.3

Fast Write (FAST_WRITE, DAh)

The FAST_WRITE instruction is similar to WRITE instruction except for it allows for XIP operation set through

mode byte. Mode bits allow a series of fast write instructions to eliminate the 8-bit opcode after the first

instruction sends an Axh mode bit (“1010XXXX”) pattern. This feature, called eXecute-In-Place (XIP), reduces

initial access times (improves performance). The mode bits control the length of the next fast write operation

through the inclusion or exclusion of the first byte instruction opcode. If the mode bits are Axh, the device

transitions to continuous fast write mode and the next address can be entered (after CS is raised HIGH and then

asserted LOW) without requiring the DAh opcode thus eliminating 8-cycles from the instruction sequence.

Otherwise, opcode is required once CS transitions from HIGH to LOW.

Notes

• Mode bits with !Axh (logical NOT of Axh byte) will exit the FAST_WRITE XIP mode.

• FAST_WRITE instruction can only be executed by the device if the write enable latch (WEL) in the status register

is set to ‘1’ to enable write operations.

• The WEL bit does not reset to ‘0’ on completion of the FAST_WRITE operation.

CS

SCK

hi-Z

SI (IO0)

1

0

A23 A22

A1

A0

M7

M6

M1

M0

D7

D6

D5

D0

D7

D0

X

hi-Z

SO (IO1)

Address

(3 Bytes)

Write Data

(N Bytes)

Opcode (DAh)

Mode Byte

Figure 43

Fast write (FAST_WRITE) in SPI mode

CS

SCK

hi-Z

1

0

1

0

1

A22 A20

A23 A21

A2

A3

A0

A1

M6

M7

M4

M5

M2

M0

M1

D6

D4

D5

D2

D3

D0

D1

D6

D7

D4

D5

D2

D3

D0

SI (IO0)

M3

D7

D1

SO (IO1)

Address

(3 Bytes)

Write Data

(N Bytes)

Opcode (DAh)

Mode Byte

Figure 44

Fast write (FAST_WRITE) in DPI mode

Datasheet

50 of 109

002-30246 Rev. *D

2022-05-25

8Mb EXCELON™ Ultra Ferroelectric RAM (F-RAM)

Serial (Quad SPI), 1024K × 8, 108MHz, industrial

Functional description

CS

SCK

hi-Z

1

0

1

0

1

0

1

A20

A21

A22

A23

A0

A1

A2

A3

M4

M5

M6

M7

M0

M1

M2

M3

D4

D5

D6

D7

D0

D1

D2

D3

D4

D5

D6

D7

D0

D1

D2

D3

SI (IO0)

hi-Z

SO (IO1)

WP (IO2)

RESET (IO3)

Opc.

(DAh)

Address

(3 Bytes)

Mode

Byte

Write Data

(N Bytes)

Figure 45

Fast write (FAST_WRITE) in QPI mode

5.1.4.4

DDR Fast Write (DDR_FAST_WRITE, DDh)

The DDR_FAST_WRITE instruction is similar to the DDRWRITE instruction, except that it allows XIP operation.

Mode bits allow a series of DDR_FAST_WRITE instructions to eliminate the 8-bit opcode after the first instruction

sends an A5h mode bit (“10100101”) pattern. This feature, called eXecute-In-Place (XIP), significantly reduces

initial access times (improves performance). The mode bits control the length of the next DDR_FAST_WRITE

operation through the inclusion or exclusion of the first byte instruction opcode. If the mode bits are A5h, the

device transitions to continuous DDR_FAST_WRITE Mode and the next address can be entered (after CS is raised

HIGH and then asserted LOW) without requiring the DDh opcode, thus eliminating 8 cycles from the instruction

sequence. Otherwise, opcode is required once CS transitions from HIGH to LOW. This opcode doesn’t support SPI

Mode 3.

Notes

• Mode bits with !A5h (logical NOT of A5h byte) will exit the DDR_FAST_WRITE XIP mode.

• DDR_FAST_WRITE instruction can only be executed by the device if the WEL bit is set to ‘1’ to enable write

operations.

The WEL bit does not reset to ‘0’ on completion of the DDR_FAST_WRITE operation.

C S

SC K

A

2

0

A

1

6

hi-Z

A

4

A

0

M

4

M

0

D

4

D

0

D

4

D

0

hi-Z

1

0

1

0

1

SI (IO 0)

SO (IO 1)

A

2

1

A

1

7

A

5

A

1

M

5

M

1

D

5

D

1

D

5

D

1

A

2

A

1

8

A

6

A

2

M

6

M

2

D

6

D

2

D

6

D

2

W P (IO 2)

A

2

3

A

1

9

A

7

A

3

M

7

M

3

D

7

D

3

D

7

D

3

R ESET (IO 3)

Opc.

(D D h)

Address

(3 Bytes )

W rite D ata

(N Bytes)

M

Figure 46

DDR fast write (DDR_FAST_WRITE) in QPI mode

Datasheet

51 of 109

002-30246 Rev. *D

2022-05-25

8Mb EXCELON™ Ultra Ferroelectric RAM (F-RAM)

Serial (Quad SPI), 1024K × 8, 108MHz, industrial

Functional description

5.1.4.5

Dual Input Write (DIW, A2h)

The DIW instruction can be used in dual data mode which is part of the Extended SPI Write instructions. In dual

data mode, opcode, address and mode bytes are transmitted through SI pin, one bit per clock cycle. Immediately

after the last address bit is transmitted, the pins are reconfigured as SO becoming I/O1, and SI becoming I/O0,

and the data (D[7:0]) is transmitted into the I/O1, and I/O0 pins, 2 bits per clock cycle, starting with D7 on I/O1 and

D6 on I/O0.

Mode bits allow a series of DIW instructions to eliminate the 8-bit opcode after the first instruction sends an Axh

mode bit (“1010XXXX”) pattern. This feature, called eXecute-In-Place (XIP), and reduces initial access times

(improves performance). The mode bits control the length of the next DIW operation through the inclusion or

exclusion of the first byte instruction opcode. If the mode bits are Axh, the device transitions to continuous DIW

mode and the next address can be entered (after CS is raised HIGH and then asserted LOW) without requiring the

A2h opcode thus eliminating 8-cycles from the instruction sequence. Otherwise, opcode is required once CS

transitions from HIGH to LOW.

Notes

• Mode bits with !Axh (logical NOT of Axh byte) will exit the DIW XIP mode.

• DIW instruction can only be executed by the device when the WEL bit is set to ‘1’ to enable write operations.

• The WEL bit does not reset to ‘0’ on completion of the DIW operation.

CS

SCK

hi-Z

1

0

1

0

A23 A22

A1

A0

M7

M6

M1

M0

D6

D7

D4

D5

D2

D3

D0

D1

D6

D7

D4

D5

D2

D3

D0

D1

SI (IO0)

hi-Z

SO (IO1)

Address

(3 Bytes)

Write Data

(N Bytes)

Opcode (A2h)

Mode Byte

Figure 47

Dual input write (DIW)

Datasheet

52 of 109

002-30246 Rev. *D

2022-05-25

8Mb EXCELON™ Ultra Ferroelectric RAM (F-RAM)

Serial (Quad SPI), 1024K × 8, 108MHz, industrial

Functional description

5.1.4.6

Dual I/O Write (DIOW, A1h)

The DIOW instruction can be used in dual addr/data mode, which is part of Extended SPI Write instructions. In

dual addr/data mode, the opcode is transmitted through the SI pin, one bit per clock cycle. Immediately after the

last opcode bit is transmitted, the pins are reconfigured as SO becoming I/O1, and SI becoming I/O0, and the

address along with the mode byte are transmitted into the part through I/O1 and I/O0 pins, 2 bits per clock cycle,

starting with address A23 on I/O1, A22 on I/O0, until the three-byte address is input. After the last address bits are

transmitted, the data (D[7:0]) is transmitted into the part through I/O1 and I/O0 two bits per clock cycle starting

with D7 on I/O1 and D6 on I/O0.

Mode bits allow a series of DIOW instructions to eliminate the 8-bit opcode after the first instruction sends an Axh

mode bit (“1010XXXX”) pattern. This feature, called eXecute-In-Place (XIP), significantly reduces initial access

times (improves performance). The mode bits control the length of the next DIOW operation through the

inclusion or exclusion of the first byte instruction opcode. If the mode bits are Axh the device transitions to

continuous DIOW mode and the next address can be entered (after CS is raised HIGH and then asserted LOW)

without requiring the A1h opcode thus eliminating 8-cycles from the instruction sequence. Otherwise, opcode is

required once CS transitions from HIGH to LOW.

Notes

• Mode bits with !Axh (logical NOT of Axh byte) will exit the DIOW XIP mode.

• The DIOW instruction can only be executed by the device when the WEL bit set to ‘1’ to enable write operations.

• The WEL bit does not reset to ‘0’ on completion of the DIOW operation.

CS

SCK

hi-Z

1

0

1

A22 A20

A23 A21

A2

A3

A0

A1

M6

M7

M4

M5

M2

M3

M0

M1

D6

D7

D4

D5

D2

D3

D0

D1

D6

D7

D4

D5

D2

D3

D0

D1

SI (IO0)

SO (IO1)

Address

(3 Bytes)

Write Data

(N Bytes)

Opcode (A1h)

Mode Byte

Figure 48

Dual I/O write (DIOW)

Datasheet

53 of 109

002-30246 Rev. *D

2022-05-25

8Mb EXCELON™ Ultra Ferroelectric RAM (F-RAM)

Serial (Quad SPI), 1024K × 8, 108MHz, industrial

Functional description

5.1.4.7

Quad Input Write (QIW, 32h)

The QIW instruction is used in Quad Data mode which is part of Extended SPI Write instructions. In Quad Data

mode, opcode, address, and mode bytes are transmitted through the SI pin, one bit per clock cycle. Immediately

after the last address bit is transmitted, the pins are reconfigured as RESET becoming I/O3, WP becoming I/O2,

SO becoming I/O1, and SI becoming I/O0, and the data (D7–D0) is transmitted into the I/O3 I/O2, I/O1, and I/O0

pins, 4 bits per clock cycle, starting with D7 on I/O3 and D6 on I/O2, D5 on I/O1, and D4 on I/O0.

Mode bits allow a series of QIW instructions to eliminate the 8-bit opcode after the first instruction sends an Axh

mode bit (“1010XXXX”) pattern. This feature, called eXecute-In-Place (XIP), significantly reduces initial access

times (improves performance). The mode bits control the length of the next QIW operation through the inclusion

or exclusion of the first byte instruction opcode. If the mode bits are Axh, the device transitions to continuous

QIW mode and the next address can be entered (after CS is raised HIGH and then asserted LOW) without requiring

the 32h opcode thus eliminating 8-cycles from the instruction sequence. Otherwise, opcode is required once CS

transitions from HIGH to LOW.

Notes

• Mode bits with !Axh (logical NOT of Axh byte) will exit the QIW XIP mode.

• The QIW instruction can only be executed by the device if the write enable latch (WEL) in the status register is

set to ‘1’ to enable write operations.

• The WEL bit does not reset to ‘0’ on completion of the QIW operation.

CS

SCK

hi-Z

X

0

1

0

A23 A22

A1

A0

M7

M6

M1

M0

D4

D5

D6

D7

D0

D1

D2

D3

D4

D5

D6

D7

D0

D1

D2

D3

SI (IO0)

SO (IO1)

hi-Z

WP (IO2)

RESET (IO3)

Address

(3 Bytes)

Write Data

(N Bytes)

Opcode (32h)

Mode Byte

Figure 49

Quad input write (QIW)

Datasheet

54 of 109

002-30246 Rev. *D

2022-05-25

8Mb EXCELON™ Ultra Ferroelectric RAM (F-RAM)

Serial (Quad SPI), 1024K × 8, 108MHz, industrial

Functional description

5.1.4.8

Quad I/O Write (QIOW, D2h)

The QIOW instruction can be used in quad addr/data mode which is part of Extended SPI Write instructions. In

quad addr/data Mode, opcode is transmitted through SI pin, one bit per clock cycle. Immediately after the last

opcode bit is transmitted, the pins are reconfigured as RESET becoming I/O3, WP becoming I/O2, SO becoming

I/O1, and SI becoming I/O0, and the address is transmitted into the part through I/O3, I/O2, I/O1 and I/O0 pins,

4 bits per clock cycle, starting with address A23 on I/O3, A22 in I/O2, A21 on I/O1 and A20 on I/O0, until the

three-byte address is input. After the last address bits are transmitted, the data (D7–D0) is transmitted into the

part through I/O3, I/O2, I/O1, and I/O0 four bits per clock cycle starting with D7 on I/O3, D6 on I/O2, D5 on I/O1

and D4 on I/O0.

Mode bits allow a series of QIOW instructions to eliminate the 8-bit opcode after the first instruction sends an Axh

mode bit (“1010XXXX”) pattern. This feature, called eXecute-In-Place (XIP), significantly reduces initial access

times (improves performance). The mode bits control the length of the next QIOW operation through the

inclusion or exclusion of the first byte instruction opcode. If the mode bits are Axh the device transitions to

continuous DIOW mode and the next address can be entered (after CS is raised HIGH and then asserted LOW)

without requiring the D2h opcode thus eliminating 8-cycles from the instruction sequence. Otherwise, opcode is

required once CS transitions from HIGH to LOW.

Notes

• Mode bits with !Axh (logical NOT of Axh byte) will exit the QIOW XIP mode.

• The QIOW instruction can only be executed by the device if the write enable latch (WEL) in the status register is

set to ‘1’ to enable write operations.

• The WEL bit does not reset to ‘0’ on completion of the QIOW operation.

CS

SCK

hi-Z

1

0

A20

A21

A22

A23

A0

A1

A2

A3

M4

M5

M6

M7

M0

M1

M2

M3

D4

D5

D6

D7

D0

D1

D2

D3

D4

D5

D6

D7

D0

D1

D2

D3

SI (IO0)

SO (IO1)

WP (IO2)

RESET (IO3)

Address

(3 Bytes)

Mode

Byte

Opcode (D2h)

Write data

Figure 50

Quad I/O write (QIOW)

Datasheet

55 of 109

002-30246 Rev. *D

2022-05-25

8Mb EXCELON™ Ultra Ferroelectric RAM (F-RAM)

Serial (Quad SPI), 1024K × 8, 108MHz, industrial

Functional description

5.1.4.9

DDR Quad I/O Write (DDRQIOW, D1h)

Double data rate quad I/O write is similar to quad I/O except that the address and data are sent on every edge of

the clock and the mode bit pattern in DDRQIOW is A5h (“10100101”). This opcode does not support SPI mode 3.

Note Mode bits with !A5h (logical NOT of A5h byte) will exit the DDRQIOW XIP mode.

CS

SCK

A

2

0

A

1

6

hi-Z

X

A

4

A

0

M

4

M

0

D

4

D

0

D

4

D

0

hi-Z

1

0

1

SI (IO0)

SO (IO1)

A

2

1

A

1

7

hi-Z

A

5

A

1

M

5

M

1

D

5

D

1

D

5

D

1

A

2

A

1

8

A

6

A

2

M

6

M

2

D

6

D

2

D

6

D

2

WP (IO2)

A

2

3

A

1

9

A

7

A

3

M

7

M

3

D

7

D

3

D

7

D

3

RESET (IO3)

Address

(3 Bytes)

Write Data

(N Bytes)

Opcode (D1h)

M

Figure 51

Quad I/O write (QIOW)

Datasheet

56 of 109

002-30246 Rev. *D

2022-05-25

8Mb EXCELON™ Ultra Ferroelectric RAM (F-RAM)

Serial (Quad SPI), 1024K × 8, 108MHz, industrial

Functional description

5.1.5

Memory Read Operation commands

The memory read instruction is sent after the CS pin is pulled LOW to select a device. The read opcode is followed

by a three-byte address and mode byte for XIP (as applicable). The CY15x108QSN has a 20-bit address space for

8-Mbit (1024K × 8) density. The most significant address byte contains A16, A17, A18, and A19 active bits while the

remaining bits are considered ‘don’t care’. Address bits A19 to A0 are transmitted as three bytes over the SPI bus

followed by the mode byte and dummy cycles as applicable.

The memory read supports SPI, Extended SPI, DPI, or QPI Modes in SDR and DDR bus interface and includes

eXecute-In-Place (XIP) support. Table 41 shows the list of memory read commands supported in CY15x108QSN

in various SPI bus interface and data transfer modes.

Table 41

Memory Read commands

Opcode

(Hex)

Command

Command description

Memory read - Reads up to 50 MHz without memory latency cycle in SPI SDR mode and up to

108 MHz with memory latency cycles in SPI, DPI, QPI SDR modes

READ

03

FAST_READ

DDRFR

0B

0D

Memory fast read - Reads up to 108 MHz with memory latency cycles in SPI, DPI, QPI SDR modes

DDR fast read - Fast read instruction in QPI DDR mode

Dual output read - Command and address bytes are sent on single SI line and data on dual

output lines I/O1 (SO), I/O0 (SI)

DOR

DIOR

QOR

3B

BB

6B

Dual I/O read - Command sent on single SI line, address input and data output on dual output

lines I/O1 (SO), I/O0 (SI)

Quad output read - Command and address sent on single SI line, data on quad output lines I/O3

(RESET), I/O2 (WP), I/O1 (SO), I/O0 (SI)

Quad I/O read - Command sent on single SI line, address input and data output on quad output

lines I/O3 (RESET), I/O2 (WP), I/O1 (SO), I/O0 (SI). This opcode executes in Extended SPI (Quad

I/O) SDR and in QPI SDR mode

QIOR

EB

ED

Quad I/O read in SDR and DDR modes. This opcode executes in extended SPI (quad I/O) SDR and

in QPI DDR mode.

DDRQIOR

Table 42

Memory Read command details

SPI bus interface

Data trans-

fer

Memory

latency

XIP

Opcode Address

Max. clock

frequency

(Hex)

length

Dual Quad Dual Quad

Execute- Dummy

SPI

DPI QPI SDR DDR

data data I/O

I/O

in-place

NA

cycles

Yes

03

0B

0D

3B

BB

6B

EB

ED

3 bytes Yes

3 bytes

NA

Yes Yes Yes NA

Yes NA Yes

Yes NA

108 MHz

46 MHz

Yes

3 bytes

NA Yes

NA

Yes

108 MHz

46 MHz

Yes

NA

Yes NA

Yes

NA

Yes

NA

Yes

NA

Yes

NA Yes Yes NA

NA Yes NA Yes

Yes

Datasheet

57 of 109

002-30246 Rev. *D

2022-05-25

8Mb EXCELON™ Ultra Ferroelectric RAM (F-RAM)

Serial (Quad SPI), 1024K × 8, 108MHz, industrial

Functional description

5.1.5.1

Memory Read (READ, 03h)

The READ instruction reads out the memory contents at the given address. The address can start at any byte

location of the 8-Mbit memory array determined by the three-byte address. The address is automatically

incremented to the next higher address in sequential order after each byte of data is shifted out. The entire 8-Mbit

memory can therefore be read out with one single read opcode and address provided. When the highest address

0x0FFFFF is reached, the address counter will wrap around and roll back to 0x000000, allowing the read sequence

to continue indefinitely. This command executes in SPI, DPI, or QPI modes.

Note The dummy cycles are a configuration option through the memory latency code bits (MLC0 to MLC3) in CR1.

CS

SCK

0

1

A23 A22

A1

A0 DM7 DM6

DM1 DM0

X

SI(IO0)

hi-Z

D7

D6

D5

D4

D3

D2

D1

D0

SO(IO1)

Address

(3 Bytes)

Opcode (03h)

Dummy Cycles

Read data

Figure 52

READ in SPI mode

CS

SCK

hi-Z

0

1

A22 A20

A23 A21

A2

A3

A0 DM7 DM6

DM1 DM0 D6

DM1 DM0 D7

D4

D2

D0

D6

D7

D4

D2

D0

SI (IO0)

hi-Z

A1 DM7 DM6

D5

D3

D1

D5

D3

D1

SO (IO1)

Address

3 Bytes

Opcode (03h)

Dummy Cycles

Read data

Figure 53

READ in DPI mode

CS

SCK

hi-Z

0

1

0

A20

A21

A22

A23

A0 DM7 DM6

A1 DM7 DM6

A2 DM7 DM6

A3 DM7 DM6

DM1 DM0 D4

DM1 DM0 D5

DM1 DM0 D6

DM1 DM0 D7

D0

D1

D2

D3

D4

D5

D6

D7

D0

D1

D2

D3

SI (IO0)

hi-Z

SO (IO1)

hi-Z

WP (IO2)

hi-Z

RESET (IO3)

Opc.

(03h)

Address

3 Bytes

DMY Cycles

Read data

Figure 54

READ in QPI mode

Datasheet

58 of 109

002-30246 Rev. *D

2022-05-25

8Mb EXCELON™ Ultra Ferroelectric RAM (F-RAM)

Serial (Quad SPI), 1024K × 8, 108MHz, industrial

Functional description

5.1.5.2

Fast Read (FAST_READ, 0Bh)

The FAST_READ instruction reads out the memory contents at the given address. The address can start at any

byte location of the 8-Mbit memory array determined by the three-byte address. The address is automatically

incremented to the next higher address in sequential order after each byte of data is shifted out. The entire

memory can therefore be read out with one single read opcode and address provided. When the highest address

0x0FFFFF is reached, the address counter will wrap around and roll back to 0x000000, allowing the read sequence

to continue indefinitely. This command executes in SPI, DPI or QPI modes.

Mode bits allow a series of fast read instructions to eliminate the 8-bit opcode after the first instruction sends an

Axh mode bit (“1010XXXX”) pattern. This feature, called eXecute-In-Place (XIP), significantly reduces initial access

times (improves performance). The mode bits control the length of the next FAST_READ operation through the

inclusion or exclusion of the first byte instruction opcode. If the mode bits are Axh, the device transitions to

continuous FAST_READ Mode and the next address can be entered (after CS is raised HIGH and then asserted

LOW) without requiring the 0Bh opcode thus eliminating 8-cycles from the instruction sequence. Otherwise,

opcode is required once CS transitions from HIGH to LOW.

Notes

• Mode bits with !Axh (logical NOT of Axh byte) will exit the FAST_READ XIP mode.

• The dummy cycles are a configuration option through the memory latency code bits (MLC0 to MLC3) in CR1.

CS

SCK

0

1

A23 A22

A1

A0 M7 M6

M1 M0 DM7 DM6

DM1 DM0

X

SI (IO0)

hi-Z

D7

D6

D5

D4

D3

D2

D1

D0

SO (IO1)

Address

(3 Bytes)

Opcode (0Bh)

Mode Byte

Dummy Cycles

Read data

Figure 55

FAST_READ in SPI mode

CS

SCK

hi-Z

0

1

A22 A20

A23 A21

A2 A0 M6 M4 M2 M0 DM7 DM6

A3 A1 M7 M5 M3 M1 DM7 DM6

DM1 DM0 D6 D4 D2 D0

DM1 DM0 D7 D5 D3 D1

D6 D4 D2 D0

D7 D5 D3 D1

SI (IO0)

hi-Z

SO (IO1)

Address

3 Bytes

Opcode (0Bh)

Mode Byte

Dummy Cycles

Read data

Figure 56

FAST_READ in DPI mode

Datasheet

59 of 109

002-30246 Rev. *D

2022-05-25

8Mb EXCELON™ Ultra Ferroelectric RAM (F-RAM)

Serial (Quad SPI), 1024K × 8, 108MHz, industrial

Functional description

CS

SCK

hi-Z

0

1

0

1

A20

A21

A22

A23

A0

A1

A2

A3

M4

M5

M6

M7

M0 DM7 DM6

M1 DM7 DM6

M2 DM7 DM6

M3 DM7 DM6

DM1 DM0 D4

DM1 DM0 D5

DM1 DM0 D6

DM1 DM0 D7

D0

D1

D2

D3

D4

D5

D6

D7

D0

D1

D2

D33

SI (IO0)

hi-Z

SO (IO1)

WP (IO2)

RESET (IO3)

Opc.

(0Bh)

Address

3 Bytes

Mode

Byte

DMY Cycles

Read data

Figure 57

FAST_READ in QPI mode

5.1.5.3

DDR Fast Read (DDRFR, 0Dh)

The DDRFR instruction improves bandwidth by transferring address, dummy bits and data bits on every edge of

the clock. The address can start at any byte location of the 8-Mbit memory array determined by the three-byte

address. The address is automatically incremented to the next address in sequential order after each byte of data

is shifted out. The entire memory can therefore be read out with one single read opcode and the start address

provided. When the highest address 0x0FFFFF is reached, the address counter wraps around and rolls back to

0x000000, allowing the read sequence to continue indefinitely. CS should remain LOW during the dummy

cycle(s). This command executes in QPI mode.

Mode bits allow a series of fast read DDR instructions to eliminate the 8-bit opcode after the first instruction sends

an A5h mode bit (“10100101”) pattern. This feature, called eXecute-In-Place (XIP), significantly reduces initial

access times (improves XIP performance). The mode bits control the length of the next DDRFR operation through

the inclusion or exclusion of the first byte instruction opcode. If the mode bits are A5h, the device transitions to

continuous DDR fast read mode and the next address can be entered (after CS is raised HIGH and then asserted

LOW) without requiring the 0Dh opcode thus eliminating 8-cycles from the instruction sequence. Otherwise,

opcode is required once CS transitions from HIGH to LOW. This opcode does not support SPI mode 3.

Notes

• Mode bits with !A5h (logical NOT of A5h byte) will exit the DDRFR XIP mode.

• The dummy cycles are a configuration option through the memory latency code bits (MLC0 to MLC3) in CR1.

CS

SCK

hi-Z

0

1

0

1

SI (IO0)

SO (IO1)

WP (IO2)

RESET (IO3)

Opc.

(0Dh)

Address

(3 Bytes)

Dummy

Cycle

M

Read Data (N Bytes)

Figure 58

DDRFR in QPI mode

Datasheet

60 of 109

002-30246 Rev. *D

2022-05-25

8Mb EXCELON™ Ultra Ferroelectric RAM (F-RAM)

Serial (Quad SPI), 1024K × 8, 108MHz, industrial

Functional description

5.1.5.4

Dual Output Read (DOR, 3Bh)

The DOR instruction is used in dual data mode which is the part of extended SPI read instructions. In dual data

mode, opcode, address, and mode byte (Axh) and dummy cycles are transmitted through SI pin, one bit per clock

cycle. At the falling edge of SCK of the last dummy cycle, the pins are reconfigured as SO becoming I/O1, and SI

becoming I/O0. The data (D7–D0) from the specified address is shifted out on I/O1, and I/O0 pins two bits per clock

cycle starting with D7 on I/O1, and D6 on I/O. The address can start at any byte location of the memory array. The

address is automatically incremented to the next higher address in sequential order after each byte of data is

shifted out. The entire memory can therefore be read out. When the highest address 0x0FFFFF is reached, the

address counter will wrap around and roll back to 0x000000, allowing the read sequence to continue indefinitely.

Mode bits allow a series of DOR instruction to eliminate the 8-bit opcode after the first instruction sends an Axh

mode bit (“1010XXXX”) pattern. This feature, called eXecute-In-Place (XIP), significantly reduces initial access

times (improves XIP performance). The mode bits control the length of the next DOR operation through the

inclusion or exclusion of the first byte instruction opcode. If the mode bits are Axh, the device transitions to

continuous DOR Mode and the next address can be entered (after CS is raised HIGH and then asserted LOW)

without requiring the 3Bh opcode thus eliminating 8-cycles from the instruction sequence. Otherwise, opcode is

required once CS transitions from HIGH to LOW.

Notes

• Mode bits with !Axh (logical NOT of Axh byte) will exit the DOR XIP mode.

• The dummy cycles are a configuration option through the memory latency code bits (MLC0 to MLC3) in CR1.

CS

SCK

hi-Z

0

1

A23 A22

A1 A0 M7 M6

M1 M0 DM7 DM6

DM1 DM0 D6 D4 D2 D0

D7 D5 D3 D1

D6 D4 D2 D0

D7 D5 D3 D1

SI (IO0)

hi-Z

SO (IO1)

Address

(3 Bytes)

Read Data

(NBytes)

Opcode (3Bh)

Mode Byte

Dummy Cycles

Figure 59

Double output read (DOR)

5.1.5.5

Dual I/O Read (DIOR, BBh)

The DIOR instruction is used in dual addr/data mode which is part of extended SPI read instructions. In dual

addr/data mode, opcode is transmitted through SI pin, one bit per clock cycle. After the last bit of the opcode,

the pins are reconfigured as SO becoming I/O1, and SI becoming I/O0. The address is then transmitted into the

part through I/O1 and I/O0 pins, 2 bits per clock cycle, starting with address A23 on I/O1 and A22 on I/O0, until

the three-byte address is input. The data (D7–D0) at the specific address is shifted out on I/O1, and I/O0 pins two

bits per clock cycle starting with D7 on I/O1, and D6 on I/O0. The address is automatically incremented to the next

higher address in sequential order after each byte of data is shifted out. The entire memory can, therefore, be

read out. When the highest address 0x0FFFFF is reached, the address counter will wrap around and roll back to

0x000000, allowing the read sequence to continue indefinitely.

Mode bits allow a series of DIOR instruction to eliminate the 8-bit opcode after the first instruction sends an Axh

mode bit (“1010XXXX”) pattern. This feature, called eXecute-In-Place (XIP), significantly reduces initial access

times (improves XIP performance). The mode bits control the length of the next DIOR operation through the

inclusion or exclusion of the first byte instruction opcode. If the mode bits are Axh the device transitions to

continuous DIOR Mode and the next address can be entered (after CS is raised HIGH and then asserted LOW)

without requiring the BBh opcode thus eliminating 8-cycles from the instruction sequence. Otherwise, opcode is

required once CS transitions from HIGH to LOW.

Notes

• Mode bits with !Axh (logical NOT of Axh byte) will exit the FAST_READ XIP mode.

• The dummy cycles are a configuration option through the memory latency code bits (MLC0 to MLC3) in CR1.

Datasheet

61 of 109

002-30246 Rev. *D

2022-05-25

8Mb EXCELON™ Ultra Ferroelectric RAM (F-RAM)

Serial (Quad SPI), 1024K × 8, 108MHz, industrial

Functional description

CS

SCK

hi-Z

1

0

1

A22 A20

A23 A21

A2

A3

A0

A1

M6

M7

M4

M5

M2

M3

M0 DM7 DM6

M1 DM7 DM6

DM1 DM0 D6

DM1 DM0 D7

D4

D5

D2

D3

D0

D1

D6

D7

D4

D5

D2

D3

D0

D1

SI(IO0)

hi-Z

SO(IO1)

Address

(3 Bytes)

Read Data

(N Bytes)

Opcode (BBh)

Mode Byte

Dummy Cycles

Figure 60

Double I/O read (DIOR)

5.1.5.6

Quad Output Read (QOR, 6Bh)

The QOR instruction is used in Quad Data mode which is the part of extended SPI read instructions. In Quad Data

mode, opcode, address, mode byte (Axh) and dummy cycles are transmitted through SI pin, one bit per clock

cycle. At the falling edge of SCK of the last mode cycle, the pins are reconfigured as RESET becoming I/O3, WP

becoming I/O2, SO becoming I/O1, and SI becoming I/O0. The data (D7–D0) from the specified address is shifted

out on I/O3, I/O2, I/O1, and I/O0 pins four bits per clock cycle starting with D7 on I/O3 and D6 on I/O2, D5 on I/O1,

and D4 on I/O0. The address is automatically incremented to the next higher address in sequential order after

each byte of data is shifted out. The entire memory can, therefore, be read out. When the highest address

0x0FFFFF is reached, the address counter will wrap around and roll back to 0x000000, allowing the read sequence

to continue indefinitely.

Mode bits allow a series of DOR instruction to eliminate the 8-bit opcode after the first instruction sends an Axh

mode bit (“1010XXXX”) pattern. This feature, called eXecute-In-Place (XIP), significantly reduces initial access

times (improves XIP performance). The mode bits control the length of the next QOR operation through the

inclusion or exclusion of the first byte instruction opcode. If the mode bits are Axh the device transitions to

continuous QOR mode and the next address can be entered (after CS is raised HIGH and then asserted LOW)

without requiring the 6Bh opcode thus eliminating 8-cycles from the instruction sequence. Otherwise, opcode is

required once CS transitions from HIGH to LOW.

Notes

• The QUAD bit CR1[1] must be set to ‘1’ in the Configuration Register 1.

• Mode bits with !Axh (logical NOT of Axh byte) will exit the DOR XIP mode.

• The dummy cycles are a configuration option through the memory latency code bits (MLC0 to MLC3) in CR1.

CS

SCK

hi-Z

X

0

1

A23 A22

A1

A0

M7

M6

M1

M0 DM7 DM6

DM1 DM0 D4

D0

D1

D2

D3

D4

D5

D6

D7

D0

D1

D2

D3

SI (IO0)

SO (IO1)

hi-Z

D5

D6

D7

hi-Z

WP (IO2)

RESET (IO3)

Address

(3 Bytes)

Read Data

(N Bytes)

Opcode (6Bh)

Mode Byte

Dummy Cycles

Figure 61

Quad output read (QOR)

Datasheet

62 of 109

002-30246 Rev. *D

2022-05-25

8Mb EXCELON™ Ultra Ferroelectric RAM (F-RAM)

Serial (Quad SPI), 1024K × 8, 108MHz, industrial

Functional description

5.1.5.7

Quad I/O Read (QIOR, EBh) – In extended SPI mode

The QIOR instruction is used in quad addr/data mode which is part of extended SPI read instructions. In quad

addr/data mode, opcode is transmitted through SI pin, one bit per clock cycle. After the last bit of the opcode,

the pins are reconfigured as RESET becoming I/O3, WP becoming I/O2, SO becoming I/O1, and SI becoming I/O0.

The address is then transmitted into the part through I/O3, I/O2, I/O1, and I/O0 pins, 4 bits per clock cycle, starting

with address A23 on I/O3, A22 on I/O2, A21 on I/O1 and A20 on I/O0, until the three-byte address is input. The data

(D7–D0) at the specific address is shifted out on I/O3, I/O2, I/O1, and I/O0 pins four bits per clock cycle starting

with D7 on I/O3 and D6 on I/O2, D5 on I/O1, and D4 on I/O0. The entire memory can therefore be read out. When

the highest address 0x0FFFFF is reached, the address counter will wrap around and roll back to 0x000000,

allowing the read sequence to continue indefinitely.

Mode bits allow a series of QIOR instruction to eliminate the 8-bit opcode after the first instruction sends an Axh

mode bit (“1010XXXX”) pattern. This feature, called eXecute-In-Place (XIP), significantly reduces initial access

times (improves XIP performance). The mode bits control the length of the next QIOR operation through the

inclusion or exclusion of the first byte instruction opcode. If the mode bits are Axh, the device transitions to

continuous QIOR mode and the next address can be entered (after CS is raised HIGH and then asserted LOW)

without requiring the EBh opcode thus eliminating 8-cycles from the instruction sequence. Otherwise, opcode is

required once CS is raised HIGH and then asserted LOW.

Notes

• The QUAD bit CR1[1] must be set to ‘1’ in configuration register 1.

• Mode bits with !Axh (logical NOT of Axh byte) will exit the QIOR XIP mode.

• The dummy cycles are a configuration option through the memory latency code bits (MLC0 to MLC3) in CR1.

CS

SCK

hi-Z

1

A20

A21

A22

A23

A0

A1

A2

A3

M4

M5

M6

M7

M0 DM7 DM6

M1 DM7 DM6

M2 DM7 DM6

M3 DM7 DM6

DM1 DM0 D4

DM1 DM0 D5

DM1 DM0 D6

DM1 DM0 D7

D0

D1

D2

D3

D4

D5

D6

D7

D0

D1

D2

D3

SI (IO0)

SO (IO1)

WP (IO2)

RESET (IO3)

Address

(3 Bytes)

Mode

Byte

Read Data

(N Bytes)

Opcode (EBh)

Dummy Cycles

Figure 62

Quad I/O read (QIOR) in extended SPI mode

Datasheet

63 of 109

002-30246 Rev. *D

2022-05-25

8Mb EXCELON™ Ultra Ferroelectric RAM (F-RAM)

Serial (Quad SPI), 1024K × 8, 108MHz, industrial

Functional description

5.1.5.8

Quad I/O Read (QIOR, EBh) – In QPI mode

The opcode for QIOR can be executed in the QSPI mode as well. As the device is in QSPI mode, the opcode,

address, and mode bytes are transmitted over all four I/Os. The data (D7–D0) at the specific address is shifted out

on I/O3, I/O2, I/O1, and I/O0 pins four bits per clock cycle starting with D7 on I/O3 and D6 on I/O2, D5 on I/O1, and

D4 on I/O0.

Notes

• Mode bits with !Axh (logical NOT of Axh byte) will exit the QIOR mode.

• The dummy cycles are a configuration option through the memory latency code bits (MLC0 to MLC3) in CR1.

CS

SCK

hi-Z

1

A20

A21

A22

A23

A0

A1

A2

A3

M4

M5

M6

M7

M0 DM7 DM6

M1 DM7 DM6

M2 DM7 DM6

M3 DM7 DM6

DM1 DM0 D4

DM1 DM0 D5

DM1 DM0 D6

DM1 DM0 D7

D0

D1

D2

D3

D4

D5

D6

D7

D0

D1

D2

D3

SI (IO0)

SO (IO1)

WP (IO2)

RESET (IO3)

Opc.

(EBh)

Address

(3 Bytes)

Mode

Byte

Read Data

(N Bytes)

Dummy Cycles

Figure 63

Quad I/O read (QIOR) in QPI mode

5.1.5.9

DDR Quad I/O Read (DDRQIOR EDh) – In extended SPI mode

The DDRQIOR instruction improves bandwidth with four I/O signals SI (I/O0), SO (I/O1), WP (I/O2) and RESET

(I/O3). It is similar to the quad I/O read instruction but transfers address, mode, dummy or data bits on every edge

of the clock. The address can start at any byte location of the memory array. The address is automatically

incremented to the next higher address’s in sequential order after each byte of data is shifted out. The entire

memory can therefore be read out with one single read opcode and address provided. When the highest address

0x0FFFFF is reached, the address counter will wrap around and roll back to 0x000000, allowing the read sequence

to be continued indefinitely. CS should not be driven HIGH during dummy bits as this may make the bits

indeterminate.

Mode bits allow a series of QIOR DDR instructions to eliminate the 8-bit opcode after the first instruction sends

an A5h mode bit pattern. This feature, called eXecute-In-Place (XIP), significantly reduces initial access times

(improves XIP performance). The mode bits control the length of the next DDR QIOR operation through the

inclusion or exclusion of the first byte instruction opcode. If the mode bits are Axh the device transitions to

continuous QIOR DDR mode and the next address can be entered (after CS is raised HIGH and then asserted LOW)

without requiring the EDh opcode thus eliminating 8-cycles from the instruction sequence. Otherwise, opcode is

required once CS is raised HIGH and then asserted LOW. This opcode does not support SPI mode 3.

Notes

• The QUAD bit CR1[1] must be set to ‘1’ in configuration register 1.

• Mode bits with !A5h (logical NOT of A5h byte) will exit the DDRQIOR XIP mode.

• The dummy cycles are a configuration option through the memory latency code bits (MLC0 to MLC3) in CR1.

Datasheet

64 of 109

002-30246 Rev. *D

2022-05-25

8Mb EXCELON™ Ultra Ferroelectric RAM (F-RAM)

Serial (Quad SPI), 1024K × 8, 108MHz, industrial

Functional description

CS

SCK

hi-Z

1

0

1

0

1

SI (IO0)

hi-Z

SO (IO1)

WP (IO2)

RESET (IO3)

Opc.

(EDh)

Address

3 Bytes

Dummy

Cycle

M

Read Data (N Bytes)

Figure 64

Quad I/O read in DDR (DDRQIOR) – In extended SPI mode

5.1.5.10

DDR Quad I/O Read (DDRQIOR EDh) – In QPI mode

The opcode for DDRQIOR can be executed in QSPI mode as well. For DDR quad in/out read (DDRQIOR) in QPI

mode, the data is read over (I/O0, I/O1, I/O2, I/O3) in DDR and address and mode bits are also sent over (I/O0, I/O1,

I/O2, I/O3) in DDR while the opcode is sent over (I/O0, I/O1, I/O2, I/O3) in SDR.

Notes

• Mode bits with !A5h (logical NOT of A5h byte) will exit the DDRQIOR XIP mode.

• The dummy cycles are a configuration option through the memory latency code bits (MLC0 to MLC3) in CR1.

CS

SCK

hi-Z

0

1

0

1

SI (IO0)

SO (IO1)

WP (IO2)

RESET (IO3)

Opc.

(EDh)

Address

(3 Bytes)

Dummy

Cycle

M

Read Data (N Bytes)

Figure 65

Quad I/O read in DDR (DDRQIOR) – In QPI mode

Datasheet

65 of 109

002-30246 Rev. *D

2022-05-25

8Mb EXCELON™ Ultra Ferroelectric RAM (F-RAM)

Serial (Quad SPI), 1024K × 8, 108MHz, industrial

Functional description

5.1.6

Special Sector Memory commands

The CY15x108QSN also provides an additional special sector memory region that is 256 bytes in length. This

special sector region design for a higher thermal reliability for stored content. Data stored into this special sector

can survive up to three standard reflow cycles. This special sector location can be used to store the PCB module

details, serial number details, and so on. The special sector memory access commands support the SPI, DPI, and

QPI modes of operation.

Table 43

Special Sector Memory Access commands

Opcode

Command

Command description

(Hex)

42

SSWR

SSRD

Special sector write - dedicated command to write 256 bytes special sector memory

Special sector read - dedicated command to read 256 bytes from the special sector memory

4B

Table 44

Special Sector Memory Access command details

SPI bus interface

Data

Memory

latency

XIP

transfer

Opcode Address

Max clock

frequency

(Hex)

length

Dual Quad Dual Quad

Dummy Execute-

SPI

DPI QPI SDR DDR

data data I/O

I/O

cycles

NA

in-place

NA

42

4B

3 bytes Yes

NA

Yes Yes Yes NA

108 MHz

Yes

NA

CS

SCK

0

1

0

1

0

A23 A22 A21 D4

A3

A2

A1

A0

D7

D6

D5

D4

D3

D2

D1

D0

X

SI (IO0)

hi-Z

Opcode (42h)

hi-Z

SO (IO1)

Address

(3 Bytes)

Write Data

Figure 66

Special sector write (SSWR) in SPI mode (WREN is not shown)

CS

SCK

hi-Z

1

0

1

A22 D4

A23 D5

A2

A3

A0

A1

D6

D7

D4

D5

D2

D3

D0

D1

SI (IO0)

hi-Z

SO (IO1)

Address

(3 Bytes)

Opcode (42h)

Write Data

Figure 67

Special sector write (SSWR) in DPI mode (WREN is not shown)

Datasheet

66 of 109

002-30246 Rev. *D

2022-05-25

8Mb EXCELON™ Ultra Ferroelectric RAM (F-RAM)

Serial (Quad SPI), 1024K × 8, 108MHz, industrial

Functional description

CS

SCK

hi-Z

0

1

0

1

0

A20

A21

A22

A23

A0

A1

A2

A3

D4

D5

D6

D7

D0

D1

D2

D3

SI (IO0)

hi-Z

SO (IO1)

WP (IO2)

RESET (IO3)

Opc.

(42h)

Address

(3 Bytes)

Write

Data

Figure 68

Special sector write (SSWR) in QPI mode (WREN is not shown)

5.1.6.1

Special Sector Read (SSRD, 4Bh)

The SSRD instruction reads out the memory contents at the given address. The address can start at any byte

location of the 256-byte special sector memory determined by the three-byte address. The address is

automatically incremented to the next higher address in sequential order after each byte of data is shifted out.

The entire 256-byte special sector can therefore be read out with one single special sector read opcode and

address provided. Once the internal address counter auto increments to 0xFF and if the host continues clocking

on SCK, the device will return undefined data byte(s).

Notes

• The three-byte address contains the lower 8-bit for sector address (A7–A0). While the remaining 16 most

significant bits of the three-byte address should be set to ‘0’.

• The dummy cycles are a configuration option through the memory latency code bits (MLC0 to MLC3) in CR1.

• The special sector F-RAM guarantees to retain user data up to three cycles of standard reflow soldering.

CS

SCK

hi-Z

0

1

A23 A22

A1

A0 DM7 DM6

DM1 DM0

X

SI (IO0)

hi-Z

D7 D6 D5 D4 D3 D2 D1 D0

SO (IO1)

Opcode (4Bh)

Address

Dummy Cycles

Read data

Figure 69

Special sector read (SSRD) in SPI mode

CS

SCK

hi-Z

1

0

1

A22 A20

A23 A21

A2

A3

A0 DM7 DM6

A1 DM7 DM6

DM1 DM0 D6 D4 D2 D0

DM1 DM0 D7 D5 D3 D1

D6 D4 D2 D0

D7 D5 D3 D1

SI (IO0)

hi-Z

SO (IO1)

Opcode (4Bh)

Address

Dummy Cycles

Read data

Figure 70

Special sector read (SSRD) in DPI mode

Datasheet

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8Mb EXCELON™ Ultra Ferroelectric RAM (F-RAM)

Serial (Quad SPI), 1024K × 8, 108MHz, industrial

Functional description

CS

SCK

hi-Z

0

1

0

1

0

1

A20

A21

A22

A23

A0 DM7 DM6

A1 DM7 DM6

A2 DM7 DM6

A3 DM7 DM6

DM1 DM0 D4

DM1 DM0 D5

DM1 DM0 D6

DM1 DM0 D7

D0

D1

D2

D3

D4

D5

D6

D7

D0

D1

D2

D33

SI (IO0)

hi-Z

SO (IO1)

WP (IO2)

RESET (IO3)

Opc.

(4Bh)

Address

DMY Cycles

Read data

Figure 71

Special sector read (SSRD) in QPI mode

5.1.6.2

Error Correction Code (ECC) and Cyclic Redundancy Check commands

5.1.6.2.1 Error Correction Code (ECC)

The CY15x108QSN provides an in-built hardware error correction code (ECC) with 3-bit error detection and

reporting on an 8-byte (64 bits) unit data. Since every F-RAM read follows a write cycle (refresh cycle), the 2-bit

error detected is automatically corrected and written back to the F-RAM array during the refresh cycle. Hence,

does not report 2-bit error detection because the subsequent ECC check on the same data unit will not reproduce

the same 2-bit error.

CY15x108QSN ECC is always enabled and observes the following behavior in run time:

• Whenever there is a 3-bit error detected during F-RAM read, CY15x108QSN‘3BD’

• The first three least significant bytes of ADDRTRAP register will hold the 3-byte unit data address of the very first

2-bit error detected in an 8-byte unit data after POR, reset, or CLECC. Any subsequent occurrence of a 3-bit error

will not overwrite the ADDRTRAP register with the most recent data unit address.

• CY15x108QSN provides a 2-byte ECC detection count (ECCDC) register which increments by ‘1’ every time a 3-bit

error is detected. The ECCDC register is cleared after POR, any reset event, or after CLECC command execution.

• User can read either ADDRTRAP register for its non-zero value (with an exception to where the 3-bit error

detected at address 0x00000) or read ‘3BD’ flag bit of ECCSR register, or read the non-zero value in the ECCDC

register to determine the occurrence of a 3-bit error detection.

• In addition, CY15x108QSN also supports the ECCRD (19h) command which returns the 3-bit error detection

status in 8-byte unit data by setting the ‘3BD’ error flag to ‘1’ in the ECCSR at the unit address sent with the

ECCRD command.

ECC is not supported on the 256-byte special sector memory, status and configuration registers.

Datasheet

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8Mb EXCELON™ Ultra Ferroelectric RAM (F-RAM)

Serial (Quad SPI), 1024K × 8, 108MHz, industrial

Functional description

5.1.6.3

ECC Status Register

The status of ECC is presented in the ECC Status Register (ECCSR). The ECCSR details are shown in Table 46. The

ECCSR content can be read only by using the RDAR commands as described in “Read Any Register (RDAR, 65h)”

on page 45. The ECCRD command returns the ECCSR status for the unit data. The unit data is defined as the

number of bytes over which the ECC is calculated. CY15x108QS has 8-bytes unit data.

Table 45

ECC Status Register

ECCSR[7]

ECCSR[6]

ECCSR[5]

RFU (0)

ECCSR[4]

ECCSR[3]

ECCSR[2]

ECCSR[1]

ECCSR[0]

RFU (0)

3BD (0)

RFU (0)

Table 46

ECC Status Register - Volatile only

Bit

Bit name Bit function

Type

Read/write

Description

ECCSR[7]

ECCSR[6]

ECCSR[5]

RFU

Reserved (0)

Reserved for future use

1 = 3-bit error detection occurred since last

ECCSR clear command (CLECC)

0 = 3-bit error detection has not occurred since

last ECCSR clear command (CLECC)

3-bit ECC

3BD

ECCSR[4]

V

R

Detection

ECCSR[3]

ECCSR[2]

ECCSR[1]

ECCSR[0]

V - Volatile

RFU

Reserved (0)

Reserved for future use

5.1.6.4

3-Bit ECC Detection (3BD) ECCSR [4]

This bit indicates that a 3-bit ECC detection has occurred on the read data since the last clear ECC Status Register.

The CLECC instruction resets 3BD bit to ‘0’.

5.1.6.4.1 ECC Detection Counter (ECCDC)

The ECC Detection Counter (ECCDC) register is a 2-byte volatile register, which stores the number of times 3-bit

error detections have occurred during the memory read operations since the last POR, any reset event, or after

CLECC command. The ECCDC register content can be read by using RDAR commands as described in “Read Any

Register (RDAR, 65h)” on page 45.

Notes

• Once the ECCDC count reaches 0xFFFF, the ECCDC will stop incrementing.

• The ECCDC loses its content when in deep power-down (DPD) mode and returns with 0x0000 upon DPD exit.

Table 47

Bits

ECC Detection Counter Register (ECCDC)

Name

Function Type Read/write

Default state

Description

ECC 3-bit

error

Total count of 3-bit ECC detections since the

last POR or any reset event. CLECC command

does not clear this register.

15:0

ECCDC

V

R

0x0000

detection

count

V - Volatile

Datasheet

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8Mb EXCELON™ Ultra Ferroelectric RAM (F-RAM)

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Functional description

5.1.6.5

Address Trap Register (ADDTRAP)

The Address Trap Register (ADDTRAP) is a 4-byte volatile register which stores the ECC unit data address where

a 3-bit error detection has occurred during a read operation. The ADDTRAP register stores the address of very first

ECC data unit in which 3-bit error detected since the last clear ECC instruction (CLECC), POR, or any reset event.

The address of subsequent data unit with 3-bit error detected will not be captured into ADDTRAP. In this case,

only ECCDC count will increment. The ADDTRAP register content can be read by using the RDAR command as

described in “Read Any Register (RDAR, 65h)” on page 45.

Note The ADDTRAP register loses its content when in deep power down (DPD) mode and returns with 0x00000000

upon DPD exit.

Table 48

Address Trap Register

Bits

Name

Function

Type

Read/write

Default state

Description

Store address of unit data where 3-bit ECC

detection occurred

Stores ECC

address

31:0

ADDTRAP

V

R

0x00000000

V - Volatile

5.1.6.6

ECC commands

The CY15x108QSN ECC commands are described in the following section.

Table 49

ECC commands

Command

(Hex)

Opcode

Command description

ECCRD

CLECC

19

1B

ECC status read - determines the ECC status of the addressed unit data

Clear ECC register(s) - ECC Flags and Address Trap Registers

Table 50

ECC command details

Data

Memory

latency

SPI bus interface

XIP

transfer

Opcode Address

Max clock

frequency

(Hex)

length

Dual Quad Dual Quad

Dummy Execute-

SPI

3 bytes Yes

NA Yes

DPI QPI SDR DDR

data data I/O

I/O

cycles

Yes

in-place

NA

19

1B

NA

Yes Yes Yes NA

108 MHz

NA

Datasheet

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8Mb EXCELON™ Ultra Ferroelectric RAM (F-RAM)

Serial (Quad SPI), 1024K × 8, 108MHz, industrial

Functional description

5.1.6.7

ECC Status Read (ECCRD, 19h)

The ECCRD instruction is used to determine the 3-bit error detection status of the addressed unit data. To do so,

CS is pulled LOW and the ECCRD instruction is followed by the ECC data unit address in which the three least

significant bits (LSb) of address should be set to zero. Even if the least three significant bits of address are not set

to zero, they will be ignored internally and the start address for the data unit is determined by the rest of the MS

bits.

The address bytes are followed by the number of dummy cycles selected by the read latency value for the

memory read. The 8-bit ECC Status is shifted out on output lines. CS must be pulled high after 8-bit ECC status is

read out.

Notes

• If CS remains LOW after 8-bit ECC status is read out, the subsequent ECC status data will be indeterminate. It is

necessary to send the new ECCRD command with next unit address to read the ECC status of next data unit.

• The dummy cycles are a configuration option through the memory latency code bits (MLC0 to MLC3) in CR1.

Table 51

Unit data ECC status byte details

Bits

Name

Function

Reserved

Read/write

Default state

Description

Reserved for future use

7

6

5

4

RFU

0

1 = 3-bit error detected in ECC unit

0 = No error

3

EECC3D

3-bit error in ECC unit

R

0

2

1

0

RFU

Reserved

0

Reserved for future use

CS

SCK

0

1

A23 A22

A1

A0 DM7 DM6

DM1 DM0

X

SI (IO0)

hi-Z

D7

D6

D5

D4

D3

D2

D1

D0

SO (IO1)

Address

(3 Bytes)

Opcode (19h)

Dummy Cycles

ECC Read Data

Figure 72

ECC read (ECCRD) in SPI mode

CS

SCK

hi-Z

0

1

0

1

A22 A20

A23 A21

A2

A3

A0 DM7 DM6

A1 DM7 DM6

DM1 DM0 D6

DM1 DM0 D7

D4

D5

D2

D3

D0

D1

D6

D7

D4

D5

D2

D3

D0

D1

SI (IO0)

hi-Z

SO (IO1)

Address

(3 Bytes)

Opcode (19h)

Dummy Cycles

ECC Read Data

Figure 73

ECC read (ECCRD) in DPI mode

Datasheet

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8Mb EXCELON™ Ultra Ferroelectric RAM (F-RAM)

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Functional description

CS

SCK

hi-Z

1

0

1

0

1

A20

A21

A22

A23

A0 DM7 DM6

A1 DM7 DM6

A2 DM7 DM6

A3 DM7 DM6

DM1 DM0 D4

DM1 DM0 D5

DM1 DM0 D6

DM1 DM0 D7

D0

D1

D2

D3

D4

D5

D6

D7

D0

D1

D2

D3

SI (IO0)

hi-Z

SO (IO1)

WP (IO2)

RESET (IO3)

Opc.

(19h)

Address

(3 Bytes)

Dummy Cycles

ECC Read Data

Figure 74

ECC read (ECCRD) in QPI mode

5.1.6.8

Clear ECC (CLECC, 1Bh)

The CLECC instruction clears all ECC flags, ADDTRAP, and ECCDC registers. It is not necessary to set the WEL bit

before a CLECC instruction is executed.

CS

SCK

0

1

0

1

X

SI (IO0)

hi-Z

Opcode (1Bh)

hi-Z

SO (IO1)

Figure 75

Clear ECC (CLECC) in SPI mode

CS

SCK

hi-Z

0

1

0

1

SI (IO0)

hi-Z

SO (IO1)

Opcode (1Bh)

Figure 76

Clear ECC (CLECC) in DPI mode

Datasheet

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8Mb EXCELON™ Ultra Ferroelectric RAM (F-RAM)

Serial (Quad SPI), 1024K × 8, 108MHz, industrial

Functional description

CS

SCK

hi-Z

0

1

0

SI (IO0)

hi-Z

SO (IO1)

WP (IO2)

RESET (IO3)

Opc.

(1Bh)

Figure 77

Clear ECC (CLECC) in QPI mode

5.1.6.9

Cyclic Redundancy Check (CRC)

CY15x108QSN provides an in-built cyclic redundancy check (CRC) engine that computes the check sequence on

the stored data in the memory array. CRC is not supported on 256-byte special sector memory, status and

configurations registers.

The CY15x108QSN supports CRC with the following opcodes.

Table 52

CRC Access commands

Opcode

(Hex)

Command

Command description

CRCC

EPCS

5B

75

7A

CRC calculation - performs a CRC calculation over a user defined address range

CRC suspend - interrupts the CRCC operation and allow other accesses

CRC resume - resumes suspended CRCC operation

EPCR1

Table 53

CRC Access command description

SPI bus interface

Data

Memory

latency

XIP

transfer

Opcode Address

Max clock

frequency

(Hex)

length

Dual Quad Dual Quad

Dummy Execute-

SPI

DPI QPI SDR DDR

data data I/O

I/O

cycle

NA

in-place

NA

5B

75

7A

NA

Yes

NA

Yes Yes Yes NA

108 MHz

NA

Datasheet

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8Mb EXCELON™ Ultra Ferroelectric RAM (F-RAM)

Serial (Quad SPI), 1024K × 8, 108MHz, industrial

Functional description

5.1.6.10

Data CRC Calculation (CRCC, 5Bh)

The CRCC instruction sequence causes CY15x108QSN to perform a cyclic redundancy check calculation (CRCC)

over a user-defined address range. A data CRC-enabled CY15x108QSN device calculates a fixed-length binary

sequence, known as the CRC checksum, for each block of data and sends them both together to the host. When

the host device receives the data block, it recalculates the CRC checksum. If the new CRC checksum does not

match the original checksum sent with the data, then the block contains a data error and the host device may

take corrective action such as requesting the data block to be sent again.

The CRCC process calculates the check-value on the data contained at the starting address through the ending

address.

The CRC calculation instruction starts by entering the opcode followed by the starting address and ending

address. CS must be driven HIGH after the ending address has been latched in. This will initiate the beginning of

internal CRC process that calculates the check-value on the data contained at the starting address through the

ending address. If CS is not driven HIGH after the last bit of address, the CRC calculation operation will not be

executed. The CRCC command does not check the WEL status. However, if the WEL is set prior to the CRC

command, the WEL gets cleared to after the CRC operation is complete.

The ending address (EA) should be at least a 32-bit aligned word higher than the starting address (SA). If

EA < SA + 3, the CRC calculation will abort and the device will return to the standby mode. The CRC abort (CRCA)

bit (SR2[3] = 1) is set to indicate the aborted condition and the CRC register (CRCR) will hold indeterminate data.

When the CRC calculation is in progress, CY15x108QSN sets the WIP bit of SR1 (SR1[0]) to ‘1’. User can poll the WIP

status to determine when the ongoing CRCC operation is complete and device is ready for access. The WIP bit will

be ‘1’ when the CRC calculation is in progress and a ‘0’ when it has been completed. The CRC register (CRCR)

stores the results of the CRC process that calculates the Check-value on the data contained at the starting address

through the ending address. The details of the CRC register is described in Table 54. The CRC check-value bits

0–31 can be read by reading the CRC register using Read Any Register (RDAR) command as described in “Read

Any Register (RDAR, 65h)” on page 45.

The CRC register bits are initialized with all 0s (0x00000000) every time CRC calculation is initiated. A POR or any

reset event will also initialize the CRC register value to all 0s.

The check-value calculation can be suspended with the CRC suspend command (EPCS, B0h) to read data from

the memory array or registers. During the suspended state, the CRC suspend (CRCS) status bit in status register-2

will be set (SR2[4] = 1). Once suspended, the host can read the status register, read data from the array and can

resume the CRC calculation by using the CRC Resume command (EPCR, 30h). CY15x108QSN takes t_CRCCto

calculate the CRC checksum on data between the SA and EA (including data at SA and EA).

The 32-bit CRC (CRC-32C) polynomial (0x1EDC6F41) is defined as follows:

32X + 28X + 27X + 26X + 25X + 23X + 22X + 20X+ 19X + 18X + 14X + 13X + 11X + 10X + 9X + 8X + 6X + 1X

Note 4-byte memory data are internally read as {data[7:0], data[15:8], data[23:16], data[31:24]} and are assigned

to CRC[31:0] for the CRC calculation.

Table 54

Bits

CRC register description

Name

Function

Default state

Description

Volatile register to store the CRC checksum value resulted

after the CRC calculation (CRCC command).

31:0

CRCR

Check CRC value

0x00000000

Datasheet

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8Mb EXCELON™ Ultra Ferroelectric RAM (F-RAM)

Serial (Quad SPI), 1024K × 8, 108MHz, industrial

Functional description

t_CRCC

CS

SCK

0

1

0

1

0

1

A23 A22 A21 D4

A3

A2

A1

A0 A23 A22 A21 D4

A3

A2

A1

A0

X

SI (IO0)

hi-Z

Opcode (5Bh)

hi-Z

SO (IO1)

Start Address

(3 Bytes)

End Address

(3 Bytes)

Figure 78

CRC calculation (CRCC) in SPI mode

CS

SCK

hi-Z

1

0

1

0

1

A22 A20 D2

A23 A21 D3

A0 A22 D4

A1 A23 D5

A2

A3

0

SI (IO0)

hi-Z

SO (IO1)

Start Addr

(3 Bytes)

End Addr

(3 Bytes)

Opcode (5Bh)

Figure 79

CRC calculation (CRCC) in DPI mode

CS

SCK

hi-Z

1

0

1

0

1

0

1

A20 D0

A21 D1

A22 D2

A23 D3

A20 D0

A21 D1

A22 D2

A23 D3

A0

A1

A2

A3

0

SI (IO0)

SO (IO1)

hi-Z

A2

A3

WP (IO2)

RESET (IO3)

Opc.

(5Bh)

Start Addr

(3 Bytes)

End Addr

(3 Bytes)

Figure 80

CRC calculation (CRCC) in QPI mode

Datasheet

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8Mb EXCELON™ Ultra Ferroelectric RAM (F-RAM)

Serial (Quad SPI), 1024K × 8, 108MHz, industrial

Functional description

5.1.6.11

CRC Suspend (EPCS, 75h)

EPCS allows the system to interrupt the ongoing CRCC operation and allow other accesses while the current CRC

operation is suspended. Commands which can execute while CRC is suspended are: READ, RDSR1, RDSR2,

FAST_READ, DDRFR, ECCRD, CLECC, RDCR1, DOR, RDCR2, RDCR4, SSRD, RDCR5, RDAR, RSTEN, QOR, EPCR, RST,

RDID, DIOR, RDSN, QIOR, DDRQIOR.

The CRC suspend is valid only during a CRC calculation operation. The Status Register 2 (SR2) can be checked to

determine if the CRCC operation has been suspended or completed. The CRC status bit shows if a CRCC operation

is suspended or was completed at the time WIP status bit in Status Register 1 changes to ‘0’. EPCS takes t_CRCS

time to process the CRC suspend operation and keeps the WIP bit status ‘1’. In the case CRCC calculation

completes before the EPCS command is fully processed, the CRCS bit in SR2 (SR2 [4]) will not set to ‘1’, indicating

EPCS did not execute.

t_CRCS

CS

SCK

0

1

0

1

0

1

X

SI (IO0)

hi-Z

Opcode (75h)

hi-Z

SO (IO1)

Figure 81

CRC suspend (EPCS) in SPI mode

CS

SCK

hi-Z

1

0

1

SI (IO0)

hi-Z

0

SO (IO1)

Opcode (75h)

Figure 82

CRC suspend (EPCS) in DPI mode

Datasheet

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8Mb EXCELON™ Ultra Ferroelectric RAM (F-RAM)

Serial (Quad SPI), 1024K × 8, 108MHz, industrial

Functional description

CS

SCK

hi-Z

1

0

1

0

1

0

SI (IO0)

hi-Z

SO (IO1)

WP (IO2)

RESET (IO3)

Opc.

(75h)

Figure 83

Suspend (EPCS) in QPI mode

5.1.6.12

CRC Resume (EPCR, 7Ah)

EPCR resumes a suspended CRCC operation. After the CRC resume instruction is issued, the WIP bit is set to ‘1’.

The CRCC operation can be interrupted as often as necessary. The EPCR resumes a suspended CRCC operation

only when CRCS bit of SR2 (SR2[4]) is set ‘1’, otherwise EPCR command will be ignored. After the EPCR instruction

is issued, the WIP bit is set to ‘1’. The CRCC operation can be interrupted and resumed as often as necessary.

EPCR takes t_CRCRtime to process the command and resumes the CRC calculation on the remaining data bytes,

until the end address (EA) reaches.

t_CRCR

CS

SCK

0

1

0

1

0

X

SI (IO0)

hi-Z

Opcode (7Ah)

hi-Z

SO (IO1)

Figure 84

CRC resume (EPCR) in SPI mode

CS

SCK

hi-Z

1

0

1

0

1

SI (IO0)

hi-Z

0

SO (IO1)

Opcode (7Ah)

Figure 85

CRC resume (EPCR) in DPI mode

Datasheet

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8Mb EXCELON™ Ultra Ferroelectric RAM (F-RAM)

Serial (Quad SPI), 1024K × 8, 108MHz, industrial

Functional description

CS

SCK

hi-Z

1

0

1

0

1

SI (IO0)

hi-Z

SO (IO1)

WP (IO2)

RESET (IO3)

Opc.

(7Ah)

Figure 86

CRC resume (EPCR) in QPI mode

5.1.7

Identification and Serial Number commands

The CY15x108QSN device offers three different types of identification features that include device ID and

unique ID which are 8-byte read only registers and 8-byte writable serial number registers. Details of each is

described in the following section.

5.1.7.1

Read Device ID (RDID, 9Fh)

The CY15x108QSN device can be interrogated for its manufacturer, product identification, and die revision. The

RDID opcode 9Fh allows the user to read the 8-byte manufacturer ID and product ID, both of which are read-only

bytes. The device ID field is described in the device ID field register table. The device ID of the corresponding part

number is shown in the “Ordering information” on page 104.

Notes

• The dummy cycles shown are a configuration option through register latency code bits (RLC0, RLC1) in CR5.

• RDID data preference - LSb shifts out first, MSb shifts out last. No wrap is allowed for the RDID command. After

the 8th byte, if the host continues to clock the device will return undefined data byte/s.

Table 55

Device ID field

Bits (number of

bits)

63–32 (32 bits)

31–21 (11 bits) 20–8 (13 bits) 7–3 (5 bits) 2–0 (3 bits)

00000110100

00000000000000000000000000000000

(reserved)

Description

(Manufacturer

ID)

Product ID

Density ID

Die Rev

CS

SCK

SI(IO0)

X

1

0

1

DM7 DM6

DM1 DM0

X

hi-Z

SO(IO1)

ID7 ID6

ID1 ID0 ID15 ID14

ID9 ID8

ID63 ID62

ID57 ID56

Byte0

Byte1

Byte7

Opcode(9Fh)

Dummy Byte

ID data

Figure 87

Read device ID (RDID) in SPI mode

Datasheet

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8Mb EXCELON™ Ultra Ferroelectric RAM (F-RAM)

Serial (Quad SPI), 1024K × 8, 108MHz, industrial

Functional description

CS

SCK

hi-Z

SI (IO0)

0

1

0

1

DM7 DM6

DM1 DM0 ID6

DM1 DM0 ID7

D0

D1

ID0 Sn14 D0

ID8

ID9

ID62 D0 ID56

hi-Z

SO (IO1)

ID1 ID15 D1

ID63 D1 ID57

Byte 0

Byte 1

Byte 7

Opcode (9Fh)

Dummy Cycles

ID data

Figure 88

Read device ID (RDID) in DPI mode

CS

SCK

hi-Z

1

0

1

DM7 DM6

DM1 DM0 ID4 ID0 ID0 ID28 ID24 ID60 ID60 ID56

DM1 DM0 ID5 ID1 ID1 ID29 ID25 ID61 ID61 ID57

DM1 DM0 ID6 ID2 ID2 ID30 ID26 ID62 ID62 ID58

DM1 DM0 ID7 ID3 ID3 ID31 ID27 ID63 ID63 ID59

SI (IO0)

hi-Z

SO (IO1)

WP (IO2)

HOLD (IO3)

Byte 0

Byte 3

ID data

Byte 7

Opc.

(9Fh)

DMY Cycles

Figure 89

Read device ID (RDID) in QPI mode

Datasheet

79 of 109

002-30246 Rev. *D

2022-05-25

8Mb EXCELON™ Ultra Ferroelectric RAM (F-RAM)

Serial (Quad SPI), 1024K × 8, 108MHz, industrial

Functional description

5.1.7.2

Read Unique ID (RUID, 4Ch)

The CY15x108QSN device can be interrogated for unique ID which is a factory programmed, 64-bit number unique

to each device. The RUID opcode, 4Ch allows to read the 8-byte, read only unique ID.

Notes

• The dummy cycles shown are a configuration option through register latency code bits (RLC0, RLC1) in CR5.

• RUID data preference - LSb shifts out first, MSb shifts out last. No wrap is allowed for the RDID command. After

the 8th byte, if the host continues to clock, the device will return undefined data byte(s).

• The unique ID registers guarantee to retain user data up to three cycles of standard reflow soldering.

CS

SCK

SI (IO0)

X

0

1

0

1

0

DM7 DM6

DM1 DM0

X

hi-Z

SO (IO1)

ID7 ID6

ID1 ID0 ID15 ID14

ID9 ID8

ID63 ID62

ID57 ID56

Byte0

Byte 1

Byte7

Opcode (4Ch)

Dummy Byte

Unique ID

Figure 90

Read unique ID in SPI mode

CS

SCK

hi-Z

SI (IO0)

1

0

1

0

DM7 DM6

DM1 DM0 ID6

DM1 DM0 ID7

D0

ID0 Sn14 D0

ID1 ID15 D1

ID8

ID62 D0 ID56

hi-Z

SO (IO1)

DM7 DM6

D1

ID9

ID63 D1 ID57

Byte 0

Byte 7

Opcode (4Ch)

Dummy Cycles

Unique ID

Figure 91

Read unique ID in DPI mode

CS

SCK

hi-Z

0

1

0

1

DM7 DM6

DM1 DM0 ID4 ID0 ID0 ID28 ID24 ID60 ID60 ID56

DM1 DM0 ID5 ID1 ID1 ID29 ID25 ID61 ID61 ID57

DM1 DM0 ID6 ID2 ID2 ID30 ID26 ID62 ID62 ID58

DM1 DM0 ID7 ID3 ID3 ID31 ID27 ID63 ID63 ID59

SI (IO0)

hi-Z

SO (IO1)

WP (IO2)

HOLD (IO3)

Byte 0

Byte 7

Opc.

(4Ch)

DMY Cycles

Unique ID

Figure 92

Read unique ID in QPI mode

Datasheet

80 of 109

002-30246 Rev. *D

2022-05-25

8Mb EXCELON™ Ultra Ferroelectric RAM (F-RAM)

Serial (Quad SPI), 1024K × 8, 108MHz, industrial

Functional description

5.1.7.3

Write Serial Number (WRSN, C2h)

The serial number is an 8-byte programmable memory space provided to the user to uniquely identify a PC board

or a system. A serial number typically consists of a two byte customer ID, followed by five bytes of unique serial

number and one byte of CRC check. However, end application can define their own format for 8-byte serial

number. All writes to the serial number register begin with a WREN opcode with CS being asserted and

de-asserted. The next opcode is WRSN. The WRSN instruction can be used in burst mode to write all the 8 bytes

of serial number. After the last byte of serial number is shifted in, CS must be driven HIGH to complete the WRSN

operation.

Notes

• The WRSN instruction can only be executed by the device if the write enable latch (WEL) in the status register

is set to ‘1’ to enable write operations. When the WRSN operation is completed, the write enable latch (WEL) is

reset to a ‘0’.

• WRSN data preference - LSb shifts in first, MSb shifts in last.

• The CRC checksum on the 7-byte ID is not calculated by the device. The system firmware must calculate the

CRC checksum and append the checksum to the 7-byte user defined serial number before programming the

entire 8-byte serial number into the serial number register. Factory default value for the 8-byte serial number

is ‘0x0000000000000000’.

• The WEL bit is automatically cleared to ‘0’ after WRSN command is terminated (at the rising edge of CS).

• Exactly 8 bytes must be entered, otherwise the serial number write (WRSN) will not execute.

Table 56

8-Byte serial number

16-bit customer identifier

SN[63:56] SN[55:48]

40-bit unique number

8-bit CRC

SN[47:40]

SN[39:32]

SN[31:24]

SN[23:16]

SN[15:8]

SN[7:0]

CS

SCK

1

0

1

0

SN7 SN6 D4 SN1 SN0 SN7 SN6 D4 SN1 SN0

SN7 SN6 D4 SN1 SN0

X

SI (IO0)

Byte 0

Byte 7

hi-Z

SO (IO1)

Opcode (C2h)

SN write data

Figure 93

Write serial number in SPI mode (WREN not shown)

CS

SCK

hi-Z

1

0

1

SN6 D4

SN0 SN6 D4

SN1 SN7 D5

SN0

SN1

SN6 D4

SN0

SN1

SI (IO0)

hi-Z

SN7 D5

SO (IO1)

Byte 0

Byte 7

Opcode (C2h)

SN write data

Figure 94

Write serial number in DPI mode (WREN not shown)

Datasheet

81 of 109

002-30246 Rev. *D

2022-05-25

8Mb EXCELON™ Ultra Ferroelectric RAM (F-RAM)

Serial (Quad SPI), 1024K × 8, 108MHz, industrial

Functional description

CS

SCK

hi-Z

0

1

0

SN4 SN0

SN5 SN1

SN6 SN2

SN12 SN8

SN13 SN9

SN14 SN 10

SN15 SN 11

SN60 SN56

SN61 SN57

SN62 SN58

SI (IO0)

hi-Z

0

SO (IO1)

1

WP (IO2)

SN7 SN3

SN63 SN59

RESET (IO3)

Byte 0

Byte 7

Opc.

(C2h)

SN write data

Figure 95

Write serial number in QPI mode (WREN not shown)

5.1.7.4

Read Serial Number (RDSN, C3h)

The CY15x108QSN device incorporates an 8-byte serial space provided to the user to uniquely identify the device.

The serial number is read using the RDSN instruction. A serial number read may be performed in burst mode to

read all the eight bytes at once. After the last byte of serial number is read, the host must stop clocking and drive

the CS HIGH to terminate the RDSN command. An RDSN instruction can be issued by shifting the opcode for RDSN

after CS goes LOW.

Notes

• The dummy cycles shown are a configuration option through register latency code bits (RLC0, RLC1) in CR5.

• LSb shifts out first, MSb shifts out last. If the host continues clocking after 8th byte, the device may return

undefined data byte/s.

CS

SCK

SI (IO0)

1

0

1

DM7 DM6

DM1 DM0

X

hi-Z

SO (IO1)

SN7 SN6

SN1 SN0 SN15 SN14

SN9 SN8

SN63 SN62

SN57 SN56

Byte 0

Byte 1

Byte 7

Opcode (C3h)

Dummy Byte

SN read data

Figure 96

Read serial number (RDSN) in SPI mode

CS

SCK

hi-Z

SI (IO0)

1

0

1

DM7 DM6

DM1 DM0 SN 6 D0 SN 0 SN14 D0 SN 8

DM1 DM0 SN 7 D1 SN 1 SN15 D1 SN 9

SN62 D0 SN56

hi-Z

SO (IO1)

SN63 D1 SN57

Byte 0

Byte 7

Opcode (C3h)

Dummy Cycles

SN read data

Figure 97

Read serial number (RDSN) in DPI mode

Datasheet

82 of 109

002-30246 Rev. *D

2022-05-25

8Mb EXCELON™ Ultra Ferroelectric RAM (F-RAM)

Serial (Quad SPI), 1024K × 8, 108MHz, industrial

Functional description

CS

SCK

hi-Z

0

1

0

DM7 DM6

DM1 DM0 SN 4 SN 0 SN 0 SN28 SN24 SN60 SN60 SN56

DM1 DM0 SN 5 SN 1 SN 1 SN29 SN25 SN61 SN61 SN57

DM1 DM0 SN 6 SN 2 SN 2 SN30 SN26 SN62 SN62 SN58

DM1 DM0 SN 7 SN 3 SN 3 SN31 SN27 SN63 SN63 SN59

SI (IO0)

hi-Z

SO (IO1)

WP (IO2)

HOLD (IO3)

Byte 0

Byte 7

Opc.

(C3h)

DMY Cycles

SN read data

Figure 98

Read serial number (RDSN) in QPI mode

5.1.8

Low power modes and resets

Table 57

Command

DPD

Low Power Mode and Reset commands

Opcode (Hex)

Command description

B9

BA

66

99

Deep power down - enters deep-power-down power mode

Hibernate mode - enters hibernate power mode

HBN

RSTEN

RST

Reset enable - pre command to enable software reset

Software reset - command to initiate software reset

Table 58

Low Power Mode and Reset command description

SPI bus interface

Data

Latency

(None)

XIP

transfer

Opcode Address

Max clock

frequency

(Hex)

length

Dual Quad Dual Quad

Dummy Execute-

SPI

DPI QPI SDR DDR

data data I/O

I/O

cycles

NA

in-place

NA

B9

BA

66

99

NA

Yes

NA

Yes Yes Yes NA

108 MHz

NA

Datasheet

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002-30246 Rev. *D

2022-05-25

8Mb EXCELON™ Ultra Ferroelectric RAM (F-RAM)

Serial (Quad SPI), 1024K × 8, 108MHz, industrial

Functional description

5.1.8.1

Deep Power-down Mode (DPD, B9h)

The device enters deep power-down mode when the DPD opcode B9 is clocked in and a rising edge of CS is

applied. When in deep power-down mode, the SCK and SI pins are ignored and SO goes to hi-Z, but the device

continues to monitor the CS pin.

A CS pulse-width of t_CSDPDor hardware reset exits the DPD mode after t_EXTDPDtime. The CS pulse-width can be

generated either by sending a dummy command cycle or toggling CS alone while SCK and I/Os are don’t care.

The I/Os remain in hi-Z state during the wakeup from deep power-down. Refer to Figure 99 for DPD entry and

Figure 102 for DPD exit timing.

Notes

• The timing details shown in Figure 99 are applicable as is in DPI and QPI modes.

• CRC register (CRCR) and ECC registers (ECCDC and ADDRTRAP) will lose their content in the DPD mode and will

return to their default values, 0x00.

• The WEL bit (SR0[1]) status is not retained in the DPD mode. If the WEL status was before entering DPD, it will

clear to after the DPD mode exits.

Enters

Deep-Power-Down Mode

t_ENTDPD

CS

0

1

2

3

4

5

6

7

SCK

SI

1

0

1

0

1

hi-Z

SO

Opcode (B9h)

Figure 99

DPD entry in SPI mode

CS

SCK

hi-Z

0

1

0

1

0

SI (IO0)

hi-Z

SO (IO1)

Opcode (B9h)

Figure 100

Deep power-down mode operation in DPI mode

Datasheet

84 of 109

002-30246 Rev. *D

2022-05-25

8Mb EXCELON™ Ultra Ferroelectric RAM (F-RAM)

Serial (Quad SPI), 1024K × 8, 108MHz, industrial

Functional description

CS

SCK

hi-Z

1

0

1

SI (IO0)

hi-Z

SO (IO1)

0

WP (IO2)

1

RESET (IO3)

Opc.

(B9h)

Figure 101

Deep power-down mode operation in QPI mode

tEXTDPD

t_CSDPD

CS

0

1

2

SCK

t_SU

X

I/Os

Figure 102

DPD exit in SPI mode

Datasheet

85 of 109

002-30246 Rev. *D

2022-05-25

8Mb EXCELON™ Ultra Ferroelectric RAM (F-RAM)

Serial (Quad SPI), 1024K × 8, 108MHz, industrial

Functional description

5.1.8.2

Hibernate Mode (HBN, BAh)

The device enters hibernate mode when the HBN opcode BAh is clocked in and a rising edge of CS is applied.

When in hibernate mode, the SCK and SI pins are ignored and SO will be hi-Z, but the device continues to monitor

the CS pin. On the next falling edge of CS, the device will return to normal operation within t_EXTHIBtime. The SO

pin remains in a hi-Z state during the wakeup from hibernate period. The device does not necessarily respond to

an opcode within the wakeup period. To exit the hibernate mode, the controller may send a “dummy” read, for

example, and wait for the remaining t_EXTHIBtime.

Notes

• The timing details shown in the SPI mode timing diagram are applicable as is in the DPI and QPI modes.

• Return from hibernate reloads all registers to their default POR values. Refer to Table 3 for details on registers

default values after POR.

Enters

Hibernate Mode

Recovers from

Hibernate Mode

t_ENTHIB

t_EXTHIB

CS

0

1

2

3

4

5

6

7

0

1

2

SCK

t_SU

SI

1

0

1

0

1

0

hi-Z

SO

Opcode (BAh)

Figure 103

Hibernate mode operation in SPI mode

CS

SCK

hi-Z

0

1

0

1

0

1

SI (IO0)

hi-Z

1

SO (IO1)

Opcode (BAh)

Figure 104

Hibernate mode operation in DPI mode

Datasheet

86 of 109

002-30246 Rev. *D

2022-05-25

8Mb EXCELON™ Ultra Ferroelectric RAM (F-RAM)

Serial (Quad SPI), 1024K × 8, 108MHz, industrial

Functional description

CS

SCK

hi-Z

1

0

1

0

1

SI (IO0)

hi-Z

SO (IO1)

0

WP (IO2)

1

RESET (IO3)

Opc.

(BAh)

Figure 105

Hibernate mode operation in QPI mode

5.1.8.3

Software Reset

The software reset operation combines two instructions: reset-enable (RSTEN) instruction followed by a reset

(RST) instruction. It resets the whole device and makes it ready to receive instructions only after t_SRESETtime.

Notes

• Any instruction other than RST following the RSTEN instruction will clear the reset enable condition and prevent

a later RST instruction from being recognized.

• During software reset, only RDSR1 and RDAR (to access RDSR1) commands are supported. Other commands

will be ignored.

• The timing details shown in the SPI mode timing diagram are applicable as is in the DPI and QPI modes.

Software reset

starts

t_SRESET

t_CS

CS

SCK

hi-Z

SI(IO0)

0

1

0

1

0

1

0

1

0

1

X

hi-Z

Opcod(e66h)

hi-Z

Opcod(e99h)

SO(IO1)

Figure 106

Software reset timing in SPI mode

CS

SCK

hi-Z

SI (IO0)

1

0

1

0

1

0

1

0

1

0

hi-Z

SO (IO1)

1

Opcode (66h)

Opcode (99h)

Figure 107

Software reset timing in DPI mode

Datasheet

87 of 109

002-30246 Rev. *D

2022-05-25

8Mb EXCELON™ Ultra Ferroelectric RAM (F-RAM)

Serial (Quad SPI), 1024K × 8, 108MHz, industrial

Functional description

CS

SCK

hi-Z

SI (IO0)

SO (IO1)

0

1

0

1

0

1

0

1

0

1

WP (IO2)

RESET (IO3)

Opc.

(66h)

Opc.

(99h)

Figure 108

Software reset timing in QPI mode

5.1.8.4

Hardware Reset (RESET)

The hardware reset input (RESET) is multiplexed on (RESET / (I/O3) and is an active LOW signal in CY15x108QSN

device. Refer to Table 21 for hardware reset (RESET) pin configurations across various SPI interfaces. When

RESET is pulled LOW, CY15x108QSN self initializes and brings its configuration back to the power up status. Refer

to Table 59 for different registers configuration after RESET cycle. Once RESET is issued, CY15x108QSN takes

t_RPH/t_HRESETtime from RESET rising edge to complete the reset cycle. CY15x108QSN becomes inaccessible during

t_RPHtime. Figure 109 and Figure 110 show the RESET timings in different reset mode.

Notes

• The RESET pin is multiplexed on I/O3 in the QPI mode. When using the hardware (RESET) in QPI mode, the CR2

[5] bit must be set to ‘1’ to enable to use I/O3 as RESET input when CS is HIGH. Figure 109 shows the RESET /

(I/O3) timing in QPI mode.

• QUAD bit CR1 [1] in configuration register 1 must be set to ‘0’ to enable the hardware reset feature on the RESET

pin.

• In a shared bus configuration in QPI mode, if the RESET function is enabled, the device will reset every time

(RESET / (I/O3)) toggles due to any ongoing communication between the master another QSPI slave on the same

bus. Hence, it is recommended to disable RESET pin functionality in a shared bus configuration.

CS

t_RS

t_RP

t_RPH/t_HRESET

RESET

Figure 109

RESET timing - SPI with QUAD set (CR1[1] = 1) or QPI enabled (CR2[6] = 1)

Datasheet

88 of 109

002-30246 Rev. *D

2022-05-25

8Mb EXCELON™ Ultra Ferroelectric RAM (F-RAM)

Serial (Quad SPI), 1024K × 8, 108MHz, industrial

Functional description

Don’t Care

CS

t_RP

t_RPH/t_HRESET

New

Reset

RESET

Reset

Figure 110

RESET timing - SPI with QUAD clear (CR1[1] = 0) and QPI disabled (CR2[6] = 0)

5.1.8.4.1 JEDEC SPI reset

JEDEC SPI reset is a signaling protocol which initiates a hardware reset independent of the device’s operating I/O

mode. It brings the device to its default mode as selected in the status and configuration registers. Table 59

shows the device status after the default recovery is initiated.

The default recovery steps are as follows:

1. CS toggles active LOW to select the SPI slave.

2. SCK remains stable either in a HIGH or in a LOW state.

3. SI (I/O0) toggles HIGH to LOW, simultaneously with CS going LOW. Other I/Os (I/O1, I/O2, and I/O3) remain don’t

care.

4. CS is driven HIGH while I/O0 remain LOW.

5. Repeat the above steps 1 to 4 each time alternating the state of SI (I/O0) at the falling edge of CS for a total of

four times.

6. Reset occurs after the 4^thCS goes HIGH (inactive).

Figure 111 illustrates the timing details.

Start next valid access

t_{CSH_R}

t_CSL

t_HRESET

CS

SCK @ ‘1’ - Mode 3

SCK @ ‘0’ - Mode 0

SCK

SI (IO0)

SO (IO1)

t_{HD_R}

t_SU

hi-Z

Figure 111

JEDEC SPI reset

Datasheet

89 of 109

002-30246 Rev. *D

2022-05-25

8Mb EXCELON™ Ultra Ferroelectric RAM (F-RAM)

Serial (Quad SPI), 1024K × 8, 108MHz, industrial

Functional description

Table 59

Status of registers after various types of reset

Status

Registers

(SRx)

Configuration

Register

ECC Count ADDR Trap

Reset

I/O

ECC

I/O

CRC reg

Reg

function

requirements

status

modes

(CRx)

(ECCDC)

(ADDTRAP)

CS = 1

Other inputs -

ignored

SR1 - Load

default

CR1, CR2, CR4,

CR5

Power-on

reset

Load -

0x00

Load -

0x00

No

values

Load - 0x00 Load - 0x00

Load default

values

change

All outputs -

tristated

SR2 - 0x00

CS = 1

Other inputs -

ignored

SR1 - Load

default

CR1, CR2, CR4,

CR5

Hardware

reset

Load -

0x00

Load -

0x00

No

values

Load default

values

change

All outputs -

tristated

SR2 - 0x00

SR1 - No

change

except the

WEL bit

Software

reset

Instruction

CR1, CR2, CR4,

Load -

0x00

Load -

0x00

No

which will

clearto‘0’if

set ‘1’.

Load - 0x00 Load - 0x00

(RSTEN, RST)

CR5 - No change

change

SR2 - 0x00

CS and SI (IO0) =

Toggle

SR1 - Load

default

JEDEC

reset

CR1, CR2, CR4,

CR5

Other inputs -

Ignored

Load -

0x00

Load -

0x00

No

values

(default

recovery)

Load default

values

change

All outputs -

tristated

SR2 - 0x00

The SPI host can issue hardware RESET or JEDEC SPI reset if CY15x108QSN goes into an undefined state and stops

responding to any SPI command. The CY15x108QSN enters into an internal test mode or any undefined mode

either due to wrong opcode or any glitch on the SPI signals which can internally cause latching of a wrong opcode,

or part didn’t boot up successfully (keep showing busy status WIP = 1 after t_PU).

Note ECC (ECCDC and ADDRTRAP) registers lose their content while in DPD and return to their default values 0x00

for ECC registers. Return from hibernate reloads all registers to their default values at power up as shown in

Table 3.

Datasheet

90 of 109

002-30246 Rev. *D

2022-05-25

8Mb EXCELON™ Ultra Ferroelectric RAM (F-RAM)

Serial (Quad SPI), 1024K × 8, 108MHz, industrial

Electrical characteristics

6

Electrical characteristics

6.1

Maximum ratings

Exceeding the maximum ratings may impair the useful life of the device. User guidelines are not tested.

Storage temperature

–65 °C to +125 °C

Maximum accumulated storage time

At 125 °C ambient temperature

1000 h

10 Years

125 °C

At 85°C ambient temperature

Maximum junction temperature

Supply voltage on V relative to V

:

SS

DD

CY15V108QSN

CY15B108QSN

–0.5 V to +2.4 V

–0.5 V to +4.1 V

Input voltage

V  V + 0.5 V

IN DD

DC voltage applied to outputs in High-Z state

–0.5 V to V + 0.5 V

DD

Transient voltage (< 20 ns) on any pin to ground potential

–2.0 V to V + 2.0 V

DD

Package power dissipation capability (T = 25°C)

1.0 W

A

Surface mount lead soldering temperature (3 seconds)

DC output current (1 output at a time, 1s duration)

+260°C

15 mA

Electrostatic discharge voltage

human body model (JEDEC Std JESD22-A114-B)

2 kV

Charged device model (JEDEC Std JESD22-C101-A)

Latch-up current

500 V

>140 mA

6.2

Operating range

Table 60

Operating range

Device

Ambient temperature

V

DD

CY15V108QSN

CY15B108QSN

1.71 V to 1.89 V

1.8 V to 3.6 V

Industrial,

–40 °C to +85 °C

Datasheet

91 of 109

002-30246 Rev. *D

2022-05-25

8Mb EXCELON™ Ultra Ferroelectric RAM (F-RAM)

Serial (Quad SPI), 1024K × 8, 108MHz, industrial

Electrical characteristics

6.3

DC electrical characteristics

Table 61

DC electrical characteristics

Over the Operating range

[15]

Parameter

Description

Test conditions

CY15V108QSN

CY15B108QSN

= 1.71 V to 1.89 V; SCK

Min

1.71

1.8

–

Max

1.89

3.6

Unit

V

Typ

1.8

V

Power supply

DD

3.0

6

V

f

= 50 MHz

= 108 MHz

= 50 MHz

= 108 MHz

7.5

mA

DD

SCK

toggling between V

–

DD

0.2 V and V , other

SS

inputs

–

12

7

14.5

8.5

16

mA

V

or V – 0.2 V.

DD

SS

No output loads.

V

supply current in

DD

I

DD1

SPI SDR mode

V

= 1.8 V to 3.6 V;

DD

SCK toggling between

– 0.2 V and V , other

V

DD

SS

inputs

or V – 0.2 V.

–

13

V

SS

DD

No output loads.

V

= 1.71 V to 1.89 V; SCK

DD

toggling between V

–

DD

0.2 V and V , other

SS

f

= 108 MHz

= 46 MHz

14.5

16

18

19.5

24.5

27.5

19

mA

SCK

inputs

V

or V – 0.2 V.

DD

SS

No output loads.

VDD supply current in

DPI SDR mode

I

DD2

V

= 1.8 V to 3.6 V;

DD

SCK toggling between

– 0.2 V and V , other

V

DD

SS

–

inputs

or V – 0.2 V.

V

SS

DD

No output loads.

V

= 1.71 V to 1.89 V; SCK

DD

toggling between V

–

DD

0.2 V and V , other

SS

20

inputs

V

or V – 0.2 V.

DD

SS

No output loads.

V

supply current in

DD

QPI SDR mode

V

= 1.8 V to 3.6 V;

DD

SCK toggling between

– 0.2 V and V , other

V

DD

SS

21.5

15.5

16.5

inputs

or V – 0.2 V.

V

SS

DD

No output loads.

I

DD3

V

= 1.71 V to 1.89 V; SCK

DD

toggling between V

–

DD

0.2 V and V , other

SS

inputs

V

or V – 0.2 V.

DD

SS

No output loads.

V

supply current in

DD

QPI DDR mode

V

= 1.8 V to 3.6 V;

DD

SCK toggling between

– 0.2 V and V , other

V

DD

SS

21

inputs

or V – 0.2 V.

V

SS

DD

No output loads.

Note

15. Typical values are at 25 °C, V = V (Typ). Not 100% tested.

DD

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8Mb EXCELON™ Ultra Ferroelectric RAM (F-RAM)

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Electrical characteristics

Table 61

DC electrical characteristics (continued)

Over the Operating range

[15]

Parameter

Description

Test conditions

= 1.71 V to 1.89 V; CS T = 25 °C

Min

Max

Unit

Typ

105

V

–

µA

DD

A

= V . All other inputs V

DD

SS

T = 85 °C

–

295

–

µA

A

or V

.

DD

I

V

standby current

DD

SB

V

= 1.8 V to 3.6 V;

T = 25 °C

195

–

DD

A

CS = V . All other inputs

DD

T = 85 °C

435

–

A

V

or V .

SS

DD

V

= 1.71 V to 1.89 V; CS T = 25 °C

0.9

–

DD

A

= V . All other inputs V

DD

SS

T = 85 °C

17.2

–

A

or V

.

Deep power-down

current

DD

DPD

HBN

V

= 1.8 V to 3.6 V;

T = 25 °C

1.0

–

DD

A

CS = V . All other inputs

DD

T = 85 °C

18.5

–

A

V

or V .

SS

DD

V

= 1.71 V to 1.89 V; CS T = 25 °C

0.1

–

DD

A

= V . All other inputs V

DD

SS

T = °C

0.9

–

A

or V

.

Hibernate mode

current

DD

V

= 1.8 V to 3.6 V;

T = 25 °C

0.1

–

DD

A

CS = V . All other inputs

DD

T = °C

1.6

A

V

or V .

SS

DD

Input leakage current

on I/O pins

–1

–100

–1

–

1

µA

Input leakage current

on WP and RESET

(when I/O2 and I/O3

functions disabled)

I

V

< V < V

IN DD

LI

SS

Output leakage

current

V

< V

OUT DD

LO

SS

V

Input HIGH voltage

Input LOW voltage

Output HIGH voltage

Output LOW voltage

–

I

0.7 × V

–0.3

2.4

–

V + 0.3

DD

V

IH

DD

0.3 × V

IL

DD

= –1 mA, V = 2.7 V.

–

OH1

OH2

OL1

OL2

OH

OL

DD

I

= –100 µA

V

– 0.2

–

DD

= 2 mA, V = 2.7 V

–

0.4

0.2

DD

= 150 µA

Note

15. Typical values are at 25 °C, V = V (Typ). Not 100% tested.

DD

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Electrical characteristics

6.4

Data retention and endurance

Table 62

Data retention and endurance

Parameter

Description

Test conditions

Min

10

Max

Unit

Years

Cycles

T = 85 C

–

A

T = 75 C

38

A

T

Data retention

DR

T = 65 C

151

A

14

NV

Endurance

Over operating temperature

10

C

6.5

Capacitance

Table 63

Parameter

Capacitance

[16]

Description

Test conditions

T = 25 °C, f = 1 MHz, V = V (typ)

Max

Unit

pF

C

Output pin capacitance (SO)

Input pin capacitance

6

5

O

I

A

DD

pF

6.6

Thermal resistance

Table 64

Parameter

Thermal resistance

[16]

Description

Test conditions

24-ball FBGA Unit

Thermal resistance



46.4

31.7

°C/W

Test conditions follow standard test methods

and procedures for measuring thermal

impedance, per EIA/JESD51.

JA

(junction to ambient)

Thermal resistance

(junction to case)



JC

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Electrical characteristics

6.7

AC test conditions

Table 65

AC test conditions

Value

Parameter

CY15V108QSN

0 V to V

CY15B108QSN

0 V to V

Input pulse levels (0 V to V

)

DD

Input rise and fall times (10% to 90%)

Input timing reference voltages

≤ 1.8 ns

0.3 × V to 0.7 × V

≤ 2.0 ns

0.3 × V to 0.7 × V

DD

Output timing reference voltages (V )

V

/2

V /2

DD

T

DD

Load capacitance (C )

30 pF

L

All I/Os in hi-Z state

All I/Os in output state except hi-Z

V_T= V_DD/2

50 Ω

Output

30pF

5pF

Figure 112

Figure 113

AC test loads

V_DD

Input levels

0V

0.7V_DD

0.3V_DD

Input timing

reference levels

AC timing input voltage reference levels

Note

16. This parameter is guaranteed by characterization; not tested in production.

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8Mb EXCELON™ Ultra Ferroelectric RAM (F-RAM)

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Electrical characteristics

6.8

SDR AC switching characteristics

Table 66

SDR AC switching characteristics

[17]

Parameters

Description

Min

Max

Unit

Alt.

Parameter

f

–

t

SCK clock frequency

Clock HIGH time

Clock LOW time

0

108

–

MHz

ns

SCK

t

0.45 × 1/f

CH

SCK

t

0.45 × 1/f

–

ns

CL

SCK

t

Chip select (CS) setup time

5

4

9

–

ns

CSS

CSU

CSH

t

Chip select (CS) hold time - SPI mode 0

Chip select (CS) hold time - SPI mode 3

Output disable time - CY15B108QSN

Output disable time - CY15V108QSN

–

ns

CSH

t

–

ns

CSH1

10

11

ns

18 19

[ ]

,

t

HZCS

OD

ns

Output data valid time with 15-pF load (Output driver

set to 45 Ω. Over the Operating range.)

–

7

ns

Clock low to output valid – 15-pF load (Output driver

set to 45 Ω.

–

6.7

ns

For V = 2.7 V to 3.6 V; over the Operating range.)

DD

t

–

CO

Clock low to output valid – 30-pF load (Output driver

set to 45 Ω.

–

7

ns

For V = 2.7 V to 3.6 V; over the Operating range.)

DD

Clock low to output valid – 30-pF load (Output driver

set to default 30 Ω. Over the Operating range.)

–

1

7

–

ns

Output hold time

OH

Chip deselect (CS HIGH) time before the command

cycle in SPI mode; all accesses (memory array and

registers)

40

105

70

–

ns

Chip deselect (CS HIGH) time before the command

cycle in DPI mode; all accesses except memory array

access

Chip deselect (CS HIGH) time before the command

cycle in DPI mode (including dual mode in extended

SPI); memory array access (non XIP mode)

20

[

]

t

D

CS

Chip deselect (CS HIGH) time before the command

cycle in DPI mode (including dual mode in extended

SPI); memory array access (XIP mode)

105

145

Chip deselect (CS HIGH) time before the command

cycle in QPI mode; all accesses except memory array

access

Notes

17. These parameters are tested per “AC test conditions” on page 95.

18. t and t are specified with a load capacitance of 5 pF. Transition is measured when the outputs enter a high

OD

HZ

impedance state.

19. Characterized but not 100% tested in production.

20. t is the minimum chip deselect (CS HIGH) time before the new command cycle starts in a specific SPI mode (SPI, DPI,

CS

or QPI). This parameter ensures that previous operation is successfully completed before the host starts a new

command cycle. Refer to Figure 116.

21. Guaranteed by design.

Datasheet

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8Mb EXCELON™ Ultra Ferroelectric RAM (F-RAM)

Serial (Quad SPI), 1024K × 8, 108MHz, industrial

Electrical characteristics

Table 66

SDR AC switching characteristics (continued)

[17]

Parameters

Description

Min

Max

Unit

Alt.

Parameter

Chip deselect (CS HIGH) time before the command

cycle in QPI mode (including quad mode in extended

SPI); memory array access (non XIP mode)

125

145

–

ns

20

]

[

t

CS

D

Chip deselect (CS HIGH) time before the command

cycle in QPI mode (including quad mode in extended

SPI); memory array access (XIP mode)

t

Data in setup time (with respect to SCK)

Data in hold time (with respect to SCK)

Clock Low to Output low-Z

2

3

–

ns

ms

µs

SD

SU

H

HD

CLZ

21

[

]

0

–

CRC calculation time (100 µs + (0.8 µs/byte of data))

CS high to CRC calculation suspends

CS high to CRC calculation resumes

0.10

–

440

100

CRCC

CRCS

CRCR

–

Notes

17. These parameters are tested per “AC test conditions” on page 95.

18. t and t are specified with a load capacitance of 5 pF. Transition is measured when the outputs enter a high

OD

HZ

impedance state.

19. Characterized but not 100% tested in production.

20. t is the minimum chip deselect (CS HIGH) time before the new command cycle starts in a specific SPI mode (SPI, DPI,

CS

or QPI). This parameter ensures that previous operation is successfully completed before the host starts a new

command cycle. Refer to Figure 116.

21. Guaranteed by design.

t_CS

CS

t_CSS

t_CH

t_CL

t_CSH1

t_CSH

Mode 3

Mode 0

SCK

SI

t_SD

t_HD

X

VALID DATA IN

t_CO

t_OH

t_HZCS

t_CLZ

Hi-Z

SO

X

DATA OUT

X

Figure 114

SPI switching timing - single IO, SDR (Mode 0 and Mode 3)

t_CS

CS

t_CSS

t_CH

t_CL

t_CSH1

t_CSH

Mode 3

Mode 0

t_CO

SCK

IO

t_CLZ

t_SD

t_HD

t_OH

t_HZCS

Hi-Z

X

VALID DATA IN

X

DATA OUT

X

Figure 115

SPI switching timing - multiple I/O, SDR (Mode 0 and Mode 3)

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8Mb EXCELON™ Ultra Ferroelectric RAM (F-RAM)

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Electrical characteristics

t_CS

CS

SCK

new command cycle

previous command cycle

I/Os

Figure 116

Chip deselect (CS HIGH) - t_CStiming

Datasheet

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8Mb EXCELON™ Ultra Ferroelectric RAM (F-RAM)

Serial (Quad SPI), 1024K × 8, 108MHz, industrial

Electrical characteristics

6.9

DDR AC switching characteristics

Table 67

DDR AC switching characteristics

Over the Operating range

[22]

Parameters

Description

SCK clock frequency

Min

Max

Unit

Alt.

Parameter

f

–

t

0

46

–

MHz

ns

SCK

t

Clock HIGH time

0.45 × 1/f

CH

SCK

Clock LOW time

0.45 × 1/f

–

ns

CL

SCK

Chip select (CS) setup time

Chip select (CS) hold time

CY15B108QSN

5

–

ns

CSS

CSH

CSU

t

–

ns

CSH

23 24

]

10

11

ns

[

,

t

HZCS

OD

CY15V108QSN

ns

Output data valid time with 15-pF load

(Output driver set to 45 Ω.

1

7

ns

Over the Operating range)

Clock low to output valid – 15-pF load

(Output driver set to 45 Ω.

1

6.7

For V = 2.7 V to 3.6 V;

DD

over the Operating range)

t

CO

Clock low to output valid – 30-pF load

(Output driver set to 45 Ω.

1

7

ns

For V = 2.7 V to 3.6 V;

DD

over the Operating range)

Clock low to output valid – 30-pF load

(Output driver set to default 30 Ω.

Over the Operating range)

1

7

–

ns

–

Output hold time

OH

Chip deselect (CS HIGH) time before the

command cycle in SPI mode; all accesses

(memory array and registers)

105

Chip deselect (CS HIGH) time before the

command cycle in QPI mode; all accesses

except memory array access

145

125

–

ns

[25]

Chip deselect (CS HIGH) time before the

command cycle in QPI mode (including

quad mode in extended SPI); memory

array access (non XIP mode)

t

CS

D

Chip deselect (CS HIGH) time before the

command cycle in QPI mode (including

quad mode in extended SPI); memory

array access (XIP mode)

145

4

–

ns

Data in setup time (with respect to SCK)

SD

SU

Notes

22. These parameters are tested per “AC test conditions” on page 95.

23. t and t are specified with a load capacitance of 5 pF. Transition is measured when the outputs enter a high

OD

HZ

impedance state.

24. Characterized but not 100% tested in production.

25. t is the minimum chip deselect (CS HIGH) time before the new command cycle starts in a specific SPI mode (SPI or

CS

QPI). This parameter ensures that previous operation is successfully completed before the host starts a new command

cycle. Refer to Figure 116.

26. Guaranteed by design.

Datasheet

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8Mb EXCELON™ Ultra Ferroelectric RAM (F-RAM)

Serial (Quad SPI), 1024K × 8, 108MHz, industrial

Electrical characteristics

Table 67

DDR AC switching characteristics (continued)

Over the Operating range

[22]

Parameters

Description

Min

Max

Unit

Alt.

Parameter

t

Data in hold time (with respect to SCK)

Clock low to output low-Z

4

0

–

ns

HD

H

[26]

CLZ

Notes

22. These parameters are tested per “AC test conditions” on page 95.

23. t and t are specified with a load capacitance of 5 pF. Transition is measured when the outputs enter a high

OD

HZ

impedance state.

24. Characterized but not 100% tested in production.

25. t is the minimum chip deselect (CS HIGH) time before the new command cycle starts in a specific SPI mode (SPI or

CS

QPI). This parameter ensures that previous operation is successfully completed before the host starts a new command

cycle. Refer to Figure 116.

26. Guaranteed by design.

t_CS

CS

t_CSS

t_CH

t_CL

t_CSH

SCK

SI

t_SDt_HDt_SDt_HD

t_SDt_HD

DATA IN

X

DATA IN

X

DATA1 IN

t_CO

t_CLZ

t_HZCS

t_OH

hi-Z

SO

X

DATA OUT DATA OUT

X

Figure 117

SPI switching timing - single I/O, DDR

t_CS

CS

t_CSS

t_CH

t_CL

t_CSH

SCK

t_CO

t_SDt_HD

DATA IN

t_SDt_HD

DATA IN

t_HZCS

t_OH

hi-Z

IO

X

DATA OUT DATA OUT

DATA1 IN

X

Figure 118

SPI switching timing - multiple I/O, DDR^[27]

Note

27. The DDR mode input timing, capturing data input on both the clock edge, is applicable to address and data input cycles

only. The DDR opcodes are always transmitted in SDR mode during the opcode cycle.

Datasheet

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8Mb EXCELON™ Ultra Ferroelectric RAM (F-RAM)

Serial (Quad SPI), 1024K × 8, 108MHz, industrial

Electrical characteristics

6.10

Write protect (WP) timing parameters

Table 68

Write protect (WP) timing parameters

Over the Operating range

[28]

Parameters

Description

Min

Max

Unit

Parameter

Alt. Parameter

t

WP setup time (with respect to CS)

WP hold time (with respect to CS)

20

–

ns

WPS

WPH

SW

HW

t

t_WPS

t_WPH

CS

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

SCK

SI

0

1

D7 D6 D5 D4 D3 D2 D1 D0

MSb LSb

hi-Z

SO

Opcode (01h)

Write Data

Figure 119

Write protect setup and hold timing

6.11

Reset (RESET) timing parameters

Table 69

Reset (RESET) timing parameters

Over the Operating range

[

]

28

Parameters

Description

Hardware RESET setup time

Min

Max

Unit

Alt.

Parameter

t

–

50

450

200

–

ns

µs

ns

µs

ns

RS

tRHSL, tRH

Hardware RESET hold time

Hardware RESET pulse width

Hardware RESET time

RPH

t

–

RLRH

RP

–

450

100

–

HRESET

SRESET

CSL

Software RESET time

–

Chip select (CS) LOW time for JEDEC reset

Chip select (CS) HIGH time for JEDEC reset

500

–

CSH_R

SI (I/O0) setup time (with respect to CS HIGH) for JEDEC

reset

t

–

5

–

ns

SU

SI (I/O0) hold time (with respect to CS HIGH) for JEDEC

reset

t

HD_R

Note

28. These parameters are tested per “AC test conditions” on page 95.

Datasheet

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8Mb EXCELON™ Ultra Ferroelectric RAM (F-RAM)

Serial (Quad SPI), 1024K × 8, 108MHz, industrial

Electrical characteristics

6.12

Power cycle timing

Table 70

Power cycle timing

Over the Operating range

[29]

Parameter

Description

Min

Max

Unit

Alt.

Parameter

t

–

Power-up V (min) to first access (CS LOW)

450

30

–

µs

PU

DD

30]

[

V

power-up ramp rate

µs/V

DD

VR

[

power-down ramp rate

20

VF

CS HIGH to enter deep power-down

(CS HIGH to hibernate mode current)

31]

[

–

0.015

–

3

µs

t

DP

ENTDPD

[31]

–

CS pulse width to wake up from deep power-down mode

4  1/f

CSDPD

SCK

Recovery time from deep power-down mode

(CS LOW to ready for access)

[32]

13

t

EXTDPD

ENTHIB

EXITHIB

RDP

HBN

REC

Time to enter hibernate

(CS HIGH to hibernate mode current)

–

3

µs

t

Recovery time from hibernate mode

(CS LOW to ready for access)

[33]

450

V

t

(low)

–

Low V where initialization must occur

0.6

130

70

–

V

DD

V

(low) time when V (low) at 0.6 V

µs

DD

PD

(low) time when V (low) at V

DD

SS

Notes

29. These parameters are tested per “AC test conditions” on page 95.

30. Slope measured at any point on the V waveform.

DD

31. Guaranteed by design. Refer to Figure 99 and Figure 102 for deep sleep mode timing.

32. Guaranteed by design. Refer to Figure 103 for hibernate mode timing.

33. This parameter is guaranteed by characterization; not tested in production.

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8Mb EXCELON™ Ultra Ferroelectric RAM (F-RAM)

Serial (Quad SPI), 1024K × 8, 108MHz, industrial

Electrical characteristics

V_DD

V_{DD (max)}

V_{DD (min)}

Device Access

t_VR

Allowed

t_PU

Time

V_DD

V_{DD (max)}

No Device Access

Allowed

V_{DD (min)}

Device Access

Allowed

t_VFt_VR

t_PU

V_{DD (low)}

t_PD

Time

Figure 120

Power cycle timing

Datasheet

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8Mb EXCELON™ Ultra Ferroelectric RAM (F-RAM)

Serial (Quad SPI), 1024K × 8, 108MHz, industrial

Ordering information

7

Ordering information

Table 71

Ordering information

Ordering code

Device ID

Package diagram

001-97209

Package type

24-ball FBGA

Operating range

Industrial

CY15B108QSN-108BKXI

CY15V108QSN-108BKXI

0000000006825158

0000000006805158

001-97209

Industrial

All these parts are Pb-free. Contact your local Infineon sales representative for availability of these parts.

7.1

Ordering code definitions

CY 15

B

108 QS

- 108 BK

X

I

T

N

Options:

Blank = Standard; T = Tape and reel

Temperature range:

I = Industrial (-40 °C to +85 °C)

X = Pb-free

Package type:

BK = 24-ball FBGA

Frequency:

108 = 108 MHz

N = No Inrush current control

Interface:

QS = Quad SPI F-RAM

Density:

108 = 8-Mbit

Voltage:

V = 1.71 V to 1.89 V (1.8 V typical)

B = 1.8 V to 3.6 V (3.0 V typical)

15 = F-RAM

CY = CYPRESS™ (An Infineon company)

Datasheet

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8Mb EXCELON™ Ultra Ferroelectric RAM (F-RAM)

Serial (Quad SPI), 1024K × 8, 108MHz, industrial

Package diagram

8

Package diagram

TOP VIEW

8.00 BSC

BOTTOM VIEW

4.00 BSC

SIDE VIEW

4.00 BSC

6.00 BSC

1.00 BSC

Ø0.40 0.0ꢀ

0.20 MIN

PIN A1

CORNER

PIN A1

CORNER

1.20 MAX

0.10

C

NOTES:

001-97209 *A

1. REFERENCE JEDEC # MO-216

2. ALL DIMENSIONS ARE IN MILLIMETERS

Figure 121

24-pin FBGA (8 × 6 × 1.2 mm) package outline, 001-97209

Datasheet

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8Mb EXCELON™ Ultra Ferroelectric RAM (F-RAM)

Serial (Quad SPI), 1024K × 8, 108MHz, industrial

Acronyms

9

Acronyms

Table 72

Acronyms used in this document

Acronym

Description

CPHA

CPOL

CRC

Clock phase

Clock polarity

Cyclic redundancy check

Dual SPI

DPI

ECC

Error correction code

EEPROM

EIA

Electrically erasable programmable read-only memory

Electronic Industries Alliance

Ferroelectric random access memory

Input/Output

F-RAM

I/O

JEDEC

JESD

LSb

Joint Electron Devices Engineering Council

JEDEC standards

Least significant bit

MSb

Most significant bit

RoHS

SPI

Restriction of Hazardous Substances

Serial peripheral interface

SOIC

Small outline integrated circuit

Datasheet

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8Mb EXCELON™ Ultra Ferroelectric RAM (F-RAM)

Serial (Quad SPI), 1024K × 8, 108MHz, industrial

Document conventions

10

Document conventions

10.1

Units of measure

Table 73

Symbol

°C

Units of measure

Unit of measure

degree Celsius

hertz

Hz

kHz

k

kilohertz

kilohm

Mbit

MHz

µA

megabit

megahertz

microampere

microfarad

microsecond

milliampere

millisecond

nanosecond

ohm

µF

µs

mA

ms

ns



%

percent

pF

picofarad

volt

V

W

watt

Datasheet

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8Mb EXCELON™ Ultra Ferroelectric RAM (F-RAM)

Serial (Quad SPI), 1024K × 8, 108MHz, industrial

Revision history

Document

Date of release

Description of changes

version

*D

2022-05-25

Publish to web.

Datasheet

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Trademarks

All referenced product or service names and trademarks are the property of their respective owners.

IMPORTANT NOTICE

For further information on the product, technology,

delivery terms and conditions and prices please

contact your nearest Infineon Technologies office

(www.infineon.com).

The information given in this document shall in no

event be regarded as a guarantee of conditions or

characteristics (“Beschaffenheitsgarantie”).

Edition 2022-05-25

Published by

Infineon Technologies AG

81726 Munich, Germany

With respect to any examples, hints or any typical

values stated herein and/or any information

regarding the application of the product, Infineon

Technologies hereby disclaims any and all

warranties and liabilities of any kind, including

without limitation warranties of non-infringement of

intellectual property rights of any third party.

WARNINGS

Due to technical requirements products may contain

dangerous substances. For information on the types

in question please contact your nearest Infineon

Technologies office.

Except as otherwise explicitly approved by Infineon

Technologies in a written document signed by

In addition, any information given in this document

is subject to customer’s compliance with its

obligations stated in this document and any

applicable legal requirements, norms and standards

concerning customer’s products and any use of the

product of Infineon Technologies in customer’s

applications.

Do you have a question about this

document?

Go to www.infineon.com/support

authorized

representatives

of

Infineon

Technologies, Infineon Technologies’ products may

not be used in any applications where a failure of the

product or any consequences of the use thereof can

reasonably be expected to result in personal injury.

Document reference

002-30246 Rev. *D

The data contained in this document is exclusively

intended for technically trained staff. It is the

responsibility of customer’s technical departments

to evaluate the suitability of the product for the

intended application and the completeness of the

product information given in this document with

respect to such application.


型号：	CY15B108QSN-108BKXIT
厂家：	Infineon
描述：	8Mb 3.0V Industrial 108MHz QSPI EXCELON™ F-RAM in 24-ball FBGA
文件：	总109页 (文件大小：997K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

CY15B108QSN-108BKXIT [INFINEON]

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