CY15E004Q-SXET [CYPRESS]
4-Kbit (512 Ã 8) Serial (SPI) Automotive F-RAM;
| 型号： | CY15E004Q-SXET |
| 厂家： | 
CYPRESS |
| 描述： | 4-Kbit (512 Ã 8) Serial (SPI) Automotive F-RAM |
| 文件： | 总22页 (文件大小：686K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY15E004Q
4-Kbit (512 × 8) Serial (SPI) Automotive
F-RAM
4-Kbit (512
× 8) Serial (SPI) Automotive F-RAM
Features
Functional Description
■ 4-Kbit ferroelectric random access memory (F-RAM) logically
organized as 512 × 8
❐ High-endurance 10 trillion (1013) read/writes
❐ 121-year data retention (See the Data Retention and
Endurance table)
❐ NoDelay™ writes
❐ Advanced high-reliability ferroelectric process
The CY15E004Q is a 4-Kbit nonvolatile memory employing an
advanced ferroelectric process. A ferroelectric random access
memory or F-RAM is nonvolatile and performs reads and writes
similar to a RAM. It provides reliable data retention for 121 years
while eliminating the complexities, overhead, and system level
reliability problems caused by serial flash, EEPROM, and other
nonvolatile memories.
■ Very fast serial peripheral interface (SPI)
❐ Up to 16 MHz frequency
❐ Direct hardware replacement for serial flash and EEPROM
❐ Supports SPI mode 0 (0, 0) and mode 3 (1, 1)
Unlike serial flash and EEPROM, the CY15E004Q performs
write operations at bus speed. No write delays are incurred. Data
is written to the memory array immediately after each byte is
successfully transferred to the device. The next bus cycle can
commence without the need for data polling. In addition, the
product offers substantial write endurance compared with other
nonvolatile memories. The CY15E004Q is capable of supporting
1013 read/write cycles, or 10 million times more write cycles than
EEPROM.
■ Sophisticated write protection scheme
❐ Hardware protection using the Write Protect (WP) pin
❐ Software protection using Write Disable instruction
❐ Software block protection for 1/4, 1/2, or entire array
These capabilities make the CY15E004Q ideal for nonvolatile
memory applications requiring frequent or rapid writes.
Examples range from data collection, where the number of write
cycles may be critical, to demanding industrial controls where the
long write time of serial flash or EEPROM can cause data loss.
■ Low power consumption
❐ 300 μA active current at 1 MHz
❐ 10 μA (typ) standby current at +85 °C
■ Voltage operation: VDD = 4.5 V to 5.5 V
■ Automotive-E temperature: –40 °C to +125 °C
■ 8-pin small outline integrated circuit (SOIC) package
■ AEC Q100 Grade 1 compliant
The CY15E004Q provides substantial benefits to users of serial
EEPROM or flash as a hardware drop-in replacement. The
CY15E004Q uses the high-speed SPI bus, which enhances the
high-speed write capability of F-RAM technology. The device
specifications are guaranteed over an automotive-e temperature
range of –40 °C to +125 °C.
■ Restriction of hazardous substances (RoHS) compliant
Logic Block Diagram
WP
Instruction Decoder
CS
Clock Generator
Control Logic
HOLD
Write Protect
SCK
512 x 8
F-RAM Array
Instruction Register
9
8
Address Register
Counter
SI
SO
Data I/O Register
2
Nonvolatile Status
Register
Errata: The Write Enable Latch (WEL) bit in the Status Register of CY15E004Q part doesn’t clear after executing the memory write (WRITE) operation at memory
location(s) from 0x100 to 0x1FF. For more information, see Errata on page 19. Details include errata trigger conditions, scope of impact, available workarounds, and
silicon revision applicability.
Cypress Semiconductor Corporation
Document Number: 002-10031 Rev. *B
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised April 5, 2017
CY15E004Q
Contents
Pinout ................................................................................3
Pin Definitions ..................................................................3
Functional Overview ........................................................4
Memory Architecture ........................................................4
Serial Peripheral Interface – SPI Bus ..............................4
SPI Overview ...............................................................4
SPI Modes ...................................................................5
Power Up to First Access ............................................6
Command Structure ....................................................6
WREN - Set Write Enable Latch .................................6
WRDI - Reset Write Enable Latch ...............................6
Status Register and Write Protection .............................6
RDSR - Read Status Register .....................................7
WRSR - Write Status Register ....................................7
Memory Operation ............................................................8
Write Operation ...........................................................8
Read Operation ...........................................................8
HOLD Pin Operation ...................................................9
Endurance .................................................................10
Maximum Ratings ...........................................................11
Operating Range .............................................................11
DC Electrical Characteristics ........................................11
Data Retention and Endurance .....................................12
Example of an F-RAM Life Time
Capacitance ....................................................................12
Thermal Resistance ........................................................12
AC Test Conditions ........................................................12
AC Switching Characteristics .......................................13
Power Cycle Timing .......................................................15
Ordering Information ......................................................16
Ordering Code Definitions .........................................16
Package Diagram ............................................................17
Acronyms ........................................................................18
Document Conventions .................................................18
Units of Measure .......................................................18
Errata ...............................................................................19
Part Numbers Affected ..............................................19
Qualification Status ...................................................19
Errata Summary ........................................................19
Document History Page .................................................21
Sales, Solutions, and Legal Information ......................22
Worldwide Sales and Design Support .......................22
Products ....................................................................22
PSoC® Solutions ......................................................22
Cypress Developer Community .................................22
Technical Support .....................................................22
in an AEC-Q100 Automotive Application .....................12
Document Number: 002-10031 Rev. *B
Page 2 of 22
CY15E004Q
Pinout
Figure 1. 8-pin SOIC pinout
8
7
6
5
V
CS
SO
1
2
3
DD
HOLD
SCK
SI
Top View
not to scale
WP
V
4
SS
Pin Definitions
Pin Name
I/O Type
Description
CS
Input
Chip Select. This active LOW input activates the device. When HIGH, the device enters low-power
standby mode, ignores other inputs, and tristates the output. When LOW, the device internally
activates the SCK signal. A falling edge on CS must occur before every opcode.
SCK
Input
Serial Clock. All I/O activity is synchronized to the serial clock. Inputs are latched on the rising edge
and outputs occur on the falling edge. Because the device is synchronous, the clock frequency may
be any value between 0 and 16 MHz and may be interrupted at any time.
SI[1]
SO[1]
WP
Input
Output
Input
Serial Input. All data is input to the device on this pin. The pin is sampled on the rising edge of SCK
and is ignored at other times. It should always be driven to a valid logic level to meet IDD specifications.
Serial Output. This is the data output pin. It is driven during a read and remains tristated at all other
times including when HOLD is LOW. Data transitions are driven on the falling edge of the serial clock.
Write Protect. This active LOW pin prevents all write operation, including Status Register. If HIGH,
write access is determined by the other write protection features, as controlled through the Status
Register. A complete explanation of write protection is provided in Status Register and Write Protection
on page 7. This pin must be tied to VDD if not used.
HOLD
Input
HOLD Pin. The HOLD pin is used when the host CPU must interrupt a memory operation for another
task. When HOLD is LOW, the current operation is suspended. The device ignores any transition on
SCK or CS. All transitions on HOLD must occur while SCK is LOW. This pin must be tied to VDD if not
used.
VSS
VDD
Power supply Ground for the device. Must be connected to the ground of the system.
Power supply Power supply input to the device.
Note
1. SI may be connected to SO for a single pin data interface.
Document Number: 002-10031 Rev. *B
Page 3 of 22
CY15E004Q
the data bus. A device on the SPI bus is activated using the CS
pin.
Functional Overview
The CY15E004Q is a serial F-RAM memory. The memory array
is logically organized as 512 × 8 bits and is accessed using an
industry standard serial peripheral interface (SPI) bus. The
functional operation of the F-RAM is similar to serial flash and
serial EEPROMs. The major difference between the
CY15E004Q and a serial flash or EEPROM with the same pinout
is the F-RAM's superior write performance, high endurance, and
low power consumption. The CY15E004Q differs from Cypress’s
FM25040 by increasing its performance to 16 MHz and adding
support for SPI Mode 3. This makes the FM25040B a drop-in
replacement for most 4-Kbit SPI EEPROMs that support Modes
0 & 3.
The relationship between chip select, clock, and data is dictated
by the SPI mode. This device supports SPI modes 0 and 3. In
both of these modes, data is clocked into the F-RAM on the rising
edge of SCK starting from the first rising edge after CS goes
active.
The SPI protocol is controlled by opcodes. These opcodes
specify the commands from the bus master to the slave device.
After CS is activated, the first byte transferred from the bus
master is the opcode. Following the opcode, any addresses and
data are then transferred. The CS must go inactive after an
operation is complete and before a new opcode can be issued.
The commonly used terms in the SPI protocol are as follows:
Memory Architecture
SPI Master
When accessing the CY15E004Q, the user addresses 512
locations of eight data bits each. These eight data bits are shifted
in or out serially. The addresses are accessed using the SPI
protocol, which includes a chip select (to permit multiple devices
on the bus), an opcode including the upper address bit, and a
word address. The word address consist of the lower 8-address
bits. The complete address of 9 bits specifies each byte address
uniquely.
The SPI master device controls the operations on a SPI bus. An
SPI bus may have only one master with one or more slave
devices. All the slaves share the same SPI bus lines and the
master may select any of the slave devices using the CS pin. All
of the operations must be initiated by the master activating a
slave device by pulling the CS pin of the slave LOW. The master
also generates the SCK and all the data transmission on SI and
SO lines are synchronized with this clock.
Most functions of the CY15E004Q are either controlled by the
SPI interface or handled by on-board circuitry. The access time
for the memory operation is essentially zero, beyond the time
needed for the serial protocol. That is, the memory is read or
written at the speed of the SPI bus. Unlike a serial flash or
EEPROM, it is not necessary to poll the device for a ready
condition because writes occur at bus speed. By the time a new
bus transaction can be shifted into the device, a write operation
is complete. This is explained in more detail in the interface
section.
SPI Slave
The SPI slave device is activated by the master through the Chip
Select line. A slave device gets the SCK as an input from the SPI
master and all the communication is synchronized with this
clock. An SPI slave never initiates a communication on the SPI
bus and acts only on the instruction from the master.
The CY15E004Q operates as an SPI slave and may share the
SPI bus with other SPI slave devices.
Chip Select (CS)
Note The CY15E004Q contains no power management circuits
other than a simple internal power-on reset circuit. It is the user’s
responsibility to ensure that VDD is within datasheet tolerances
to prevent incorrect operation. It is recommended that the part is
not powered down with chip enable active.
To select any slave device, the master needs to pull down the
corresponding CS pin. Any instruction can be issued to a slave
device only while the CS pin is LOW. When the device is not
selected, data through the SI pin is ignored and the serial output
pin (SO) remains in a high-impedance state.
Serial Peripheral Interface – SPI Bus
Note A new instruction must begin with the falling edge of CS.
Therefore, only one opcode can be issued for each active Chip
Select cycle.
The CY15E004Q is a SPI slave device and operates at speeds
up to 16 MHz. This high-speed serial bus provides
high-performance serial communication to a SPI master. Many
common microcontrollers have hardware SPI ports allowing a
direct interface. It is quite simple to emulate the port using
ordinary port pins for microcontrollers that do not. The
CY15E004Q operates in SPI Mode 0 and 3.
Serial Clock (SCK)
The Serial Clock is generated by the SPI master and the
communication is synchronized with this clock after CS goes
LOW.
The CY15E004Q enables SPI modes 0 and 3 for data
communication. In both of these modes, the inputs are latched
by the slave device on the rising edge of SCK and outputs are
issued on the falling edge. Therefore, the first rising edge of SCK
signifies the arrival of the first bit (MSB) of a SPI instruction on
the SI pin. Further, all data inputs and outputs are synchronized
with SCK.
SPI Overview
The SPI is a four-pin interface with Chip Select (CS), Serial Input
(SI), Serial Output (SO), and Serial Clock (SCK) pins.
The SPI is a synchronous serial interface, which uses clock and
data pins for memory access and supports multiple devices on
Document Number: 002-10031 Rev. *B
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CY15E004Q
Data Transmission (SI/SO)
the slave responds through the SO pin. Multiple slave devices
may share the SI and SO lines as described earlier.
The SPI data bus consists of two lines, SI and SO, for serial data
communication. SI is also referred to as Master Out Slave In
(MOSI) and SO is referred to as Master In Slave Out (MISO). The
master issues instructions to the slave through the SI pin, while
The CY15E004Q has two separate pins for SI and SO, which can
be connected with the master as shown in Figure 2.
For a microcontroller that has no dedicated SPI bus, a
general-purpose port may be used. To reduce hardware
resources on the controller, it is possible to connect the two data
pins (SI, SO) together and tie off (HIGH) the HOLD and WP pins.
Figure 3 shows such a configuration, which uses only three pins.
Figure 2. System Configuration with SPI port
SCK
MOSI
MISO
SCK
CY15E004Q
HOLD WP
SCK
CY15E004Q
HOLD WP
SI SO
SI SO
SPI
Microcontroller
CS
CS
C S 1
H O LD 1
W P 1
C S 2
H O LD 2
W P 2
Figure 3. System Configuration without SPI port
P1.0
P1.1
SCK
CY15E004Q
HOLD WP
SI SO
Microcontroller
CS
P1.2
Most Significant Bit (MSB)
Invalid Opcode
The SPI protocol requires that the first bit to be transmitted is the
Most Significant Bit (MSB). This is valid for both address and
data transmission.
If an invalid opcode is received, the opcode is ignored and the
device ignores any additional serial data on the SI pin until the
next falling edge of CS, and the SO pin remains tristated.
The 4-Kbit serial F-RAM requires an opcode including the upper
address bit, and a word address for any read or write operation.
Status Register
CY15E004Q has an 8-bit Status Register. The bits in the Status
Register are used to configure the device. These bits are
described in Table 3 on page 7.
The word address consist of the lower 8-address bits. The
complete address of 9 bits specifies each byte address uniquely.
Serial Opcode
SPI Modes
After the slave device is selected with CS going LOW, the first
byte received is treated as the opcode for the intended operation.
CY15E004Q uses the standard opcodes for memory accesses.
CY15E004Q may be driven by a microcontroller with its SPI
peripheral running in either of the following two modes:
■ SPI Mode 0 (CPOL = 0, CPHA = 0)
■ SPI Mode 3 (CPOL = 1, CPHA = 1)
Document Number: 002-10031 Rev. *B
Page 5 of 22
CY15E004Q
For both these modes, the input data is latched in on the rising
edge of SCK starting from the first rising edge after CS goes
active. If the clock starts from a HIGH state (in mode 3), the first
rising edge after the clock toggles is considered. The output data
is available on the falling edge of SCK.
WREN - Set Write Enable Latch
The CY15E004Q will power up with writes disabled. The WREN
command must be issued before any write operation. Sending
the WREN opcode allows the user to issue subsequent opcodes
for write operations. These include writing the Status Register
(WRSR) and writing the memory (WRITE).
The two SPI modes are shown in Figure 4 and Figure 5. The
status of the clock when the bus master is not transferring data is:
Sending the WREN opcode causes the internal Write Enable
Latch to be set. A flag bit in the Status Register, called WEL,
indicates the state of the latch. WEL = ‘1’ indicates that writes are
permitted. Attempting to write the WEL bit in the Status Register
has no effect on the state of this bit – only the WREN opcode can
set this bit. The WEL bit will be automatically cleared on the rising
edge of CS following a WRDI, a WRSR, or a WRITE operation.
This prevents further writes to the Status Register or the F-RAM
array without another WREN command. Figure 6 illustrates the
WREN command bus configuration.
■ SCK remains at 0 for Mode 0
■ SCK remains at 1 for Mode 3
The device detects the SPI mode from the status of the SCK pin
when the device is selected by bringing the CS pin LOW. If the
SCK pin is LOW when the device is selected, SPI Mode 0 is
assumed and if the SCK pin is HIGH, it works in SPI Mode 3.
Figure 4. SPI Mode 0
Note: The Write Enable Latch (WEL) bit in the Status Register
of CY15E004Q part doesn’t clear after executing the memory
write (WRITE) operation at memory location(s) from 0x100 to
0x1FF. For more information, see Errata on page 19.
CS
0
1
2
3
4
5
6
7
SCK
SI
Figure 6. WREN Bus Configuration
7
6
5
4
3
2
1
0
CS
MSB
LSB
0
1
2
3
4
5
6
7
SCK
SI
Figure 5. SPI Mode 3
0
0
0
0
0
1
1
0
CS
0
1
2
3
4
5
6
7
HI-Z
SO
SCK
WRDI - Reset Write Enable Latch
The WRDI command disables all write activity by clearing the
Write Enable Latch. The user can verify that writes are disabled
by reading the WEL bit in the Status Register and verifying that
WEL is equal to ‘0’. Figure 7 illustrates the WRDI command bus
configuration.
SI
7
6
5
4
3
2
1
0
MSB
LSB
Power Up to First Access
The CY15E004Q is not accessible for a tPU time after power up.
Users must comply with the timing parameter tPU, which is the
minimum time from VDD (min) to the first CS LOW.
Figure 7. WRDI Bus Configuration
Command Structure
CS
There are six commands, called opcodes, that can be issued by
the bus master to the CY15E004Q. They are listed in Table 1.
These opcodes control the functions performed by the memory.
0
1
2
3
4
5
6
7
SCK
SI
0
0
0
0
0
0
1
0
Table 1. Opcode commands
Name
WREN
Description
Set write enable latch
Write disable
Opcode
HI-Z
SO
0000 0110b
0000 0100b
0000 0101b
0000 0001b
0000 A011b
0000 A010b
WRDI
RDSR
WRSR
READ
WRITE
Read Status Register
Write Status Register
Read memory data
Write memory data
Document Number: 002-10031 Rev. *B
Page 6 of 22
CY15E004Q
LOW, the entire part is write-protected. When WP is HIGH, the
memory protection is subject to the Status Register. Writes to the
Status Register are performed using the WREN and WRSR
commands and subject to the WP pin. The Status Register is
organized as follows. (The default value shipped from the factory
for bits in the Status Register is ‘0’.)
Status Register and Write Protection
The write protection features of the CY15E004Q are multi-tiered
and are enabled through the status register. First, a WREN
opcode must be issued prior to any write operation. Assuming
that writes are enabled using WREN, writes to memory are
controlled by the WP pin and the Status Register. When WP is
Table 2. Status Register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
X (0)
X (0)
X (0)
X (0)
BP1 (0)
BP0 (0)
WEL (0)
X (0)
Table 3. Status Register Bit Definition
Bit Definition
Don’t care
Description
Bit 0
This bit is non-writable and always returns ‘0’ upon read.
Bit 1 (WEL)
Write Enable Latch
WEL indicates if the device is write enabled. This bit defaults to ‘0’ (disabled) on power-up.
WEL = ‘1’ --> Write enabled
WEL = ‘0’ --> Write disabled
Bit 2 (BP0)
Bit 3 (BP1)
Bit 4-7
Block Protect bit ‘0’
Block Protect bit ‘1’
Don’t care
Used for block protection. For details, see Table 4.
Used for block protection. For details, see Table 4.
These bits are non-writable and always return ‘0’ upon read.
Bits 0 and 4–7 are fixed at ‘0’; none of these bits can be modified.
Note that bit 0 (“Ready or Write in progress” bit in serial flash and
EEPROM) is unnecessary, as the F-RAM writes in real-time and
is never busy, so it reads out as a ‘0’. The BP1 and BP0 control
the software write-protection features and are nonvolatile bits.
The WEL flag indicates the state of the Write Enable Latch.
Attempting to directly write the WEL bit in the Status Register has
no effect on its state. This bit is internally set and cleared via the
WREN and WRDI commands, respectively.
Table 5 summarizes the write protection conditions.
Table 5. Write Protection
Protected
Blocks
Unprotected
Blocks
Status
WEL
WP
Register
0
1
1
X
0
1
Protected
Protected
Protected
Protected
Protected
Protected
Protected
Unprotected
Unprotected
BP1 and BP0 are memory block write protection bits. They
specify portions of memory that are write-protected as shown in
Table 4.
RDSR - Read Status Register
The RDSR command allows the bus master to verify the
contents of the Status Register. Reading the status register
provides information about the current state of the
write-protection features. Following the RDSR opcode, the
CY15E004Q will return one byte with the contents of the Status
Register.
Table 4. Block Memory Write Protection
BP1
BP0
Protected Address Range
None
0
0
1
1
0
1
0
1
180h to 1FFh (upper 1/4)
100h to 1FFh (upper 1/2)
000h to 1FFh (all)
WRSR - Write Status Register
The WRSR command allows the SPI bus master to write into the
Status Register and change the write protect configuration by
setting the BP0 and BP1 bits as required. Before issuing a
WRSR command, the WP pin must be HIGH or inactive. Note
that on the CY15E004Q, WP prevents writing to the Status
Register and the memory array. Before sending the WRSR
command, the user must send a WREN command to enable
writes. Executing a WRSR command is a write operation and
therefore, clears the Write Enable Latch.
The BP1 and BP0 bits and the Write Enable Latch are the only
mechanisms that protect the memory from writes. The remaining
write protection features protect inadvertent changes to the block
protect bits.
The BP1 and BP0 bits allow software to selectively write protect
the array. These settings are only used when the WP pin is
inactive and the WREN command has been issued.
Document Number: 002-10031 Rev. *B
Page 7 of 22
CY15E004Q
Figure 8. RDSR Bus Configuration
CS
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
SCK
Opcode
SI
0
0
0
0
0
1
0
1
Data
D7 D6 D5 D4 D3 D2 D1 D0
MSB LSB
HI-Z
SO
Figure 9. WRSR Bus Configuration (WREN not shown)
CS
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
SCK
Data
Opcode
SI
0
0
0
0
0
0
0
1
X
X
X
X
D3 D2
X
X
MSB
LSB
HI-Z
SO
operations. F-RAM memories do not have page buffers because
each byte is written to the F-RAM array immediately after it is
clocked in (after the eighth clock). This allows any number of
bytes to be written without page buffer delays.
Memory Operation
The SPI interface, which is capable of a high clock frequency,
highlights the fast write capability of the F-RAM technology.
Unlike serial flash and EEPROMs, the CY15E004Q can perform
sequential writes at bus speed. No page register is needed and
any number of sequential writes may be performed.
Note If the power is lost in the middle of the write operation, only
the last completed byte will be written.
Read Operation
Write Operation
After the falling edge of CS, the bus master can issue a READ
opcode. The READ opcode includes the upper bit of the memory
address. Bit 3 in the opcode corresponds to the upper address
bit (A8). The next byte is the lower 8-bits of the address (A7–A0).
In total, the 9-bits specify the address of the first byte of the read
operation. After the opcode and address are issued, the device
drives out the read data on the next eight clocks. The SI input is
ignored during read data bytes. Subsequent bytes are data
bytes, which are read out sequentially. Addresses are
incremented internally as long as the bus master continues to
issue clocks and CS is LOW. If the last address of 1FFh is
reached, the counter will roll over to 000h. Data is read MSB first.
The rising edge of CS terminates a read operation and tristates
the SO pin. A read operation is shown in Figure 11 on page 9.
All writes to the memory begin with a WREN opcode. The WRITE
opcode includes the upper bit of the memory address. Bit 3 in the
opcode corresponds to the upper address bit (A8). The next byte
is the lower 8-bits of the address (A7–A0). In total, the 9-bits
specify the address of the first byte of the write operation.
Subsequent bytes are data bytes, which are written sequentially.
Addresses are incremented internally as long as the bus master
continues to issue clocks and keeps CS LOW. If the last address
of 1FFh is reached, the counter will roll over to 000h. Data is
written MSB first. The rising edge of CS terminates a write
operation. A write operation is shown in Figure 10 on page 9.
Note When a burst write reaches a protected block address, the
automatic address increment stops and all the subsequent data
bytes received for write will be ignored by the device.
EEPROMs use page buffers to increase their write throughput.
This compensates for the technology's inherently slow write
Document Number: 002-10031 Rev. *B
Page 8 of 22
CY15E004Q
Figure 10. Memory Write (WREN not shown)
CS
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
SCK
Opcode
0
Byte Address
A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
MSB LSB MSB LSB
Data
SI
0
0
0
A8
0
1
0
HI-Z
SO
Figure 11. Memory Read
CS
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
SCK
Opcode
Byte Address
SI
0
0
0
0
A8
0
1
1 A7 A6 A5 A4 A3 A2 A1 A0
MSB
LSB
Data
D7 D6 D5 D4 D3 D2 D1 D0
MSB LSB
HI-Z
SO
HIGH while SCK is LOW will resume an operation. The
transitions of HOLD must occur while SCK is LOW, but the SCK
and CS can toggle during a hold state.
HOLD Pin Operation
The HOLD pin can be used to interrupt a serial operation without
aborting it. If the bus master pulls the HOLD pin LOW while SCK
is LOW, the current operation will pause. Taking the HOLD pin
Figure 12. HOLD Operation[2]
CS
SCK
HOLD
SI
VALID IN
VALID IN
SO
Note
2. Figure shows HOLD operation for input mode and output mode.
Document Number: 002-10031 Rev. *B
Page 9 of 22
CY15E004Q
address, and a sequential 64-byte data stream. This causes
each byte to experience one endurance cycle through the loop.
Endurance
The CY15E004Q devices are capable of being accessed at least
1013 times, reads or writes. An F-RAM memory operates with a
read and restore mechanism. Therefore, an endurance cycle is
applied on a row basis for each access (read or write) to the
memory array. The F-RAM architecture is based on an array of
rows and columns of 64 rows of 64-bits each. The entire row is
internally accessed once whether a single byte or all eight bytes
are read or written. Each byte in the row is counted only once in
an endurance calculation. Table 6 shows endurance calculations
for a 64-byte repeating loop, which includes an opcode, a starting
Table 6. Time to Reach Endurance Limit for Repeating
64-byte Loop
SCK Freq Endurance
Endurance
Years to Reach
Limit
(MHz)
Cycles/sec Cycles/year
10
5
18,660
9,330
1,870
5.88 × 1011
2.94 × 1011
5.88 × 1010
17.0
34.0
1
170.1
Document Number: 002-10031 Rev. *B
Page 10 of 22
CY15E004Q
Package power
dissipation capability (TA = 25 °C) ............................... 1.0 W
Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the
device. These user guidelines are not tested.
Surface mount lead
soldering temperature (3 seconds) .......................... +260°C
Storage temperature ................................ –55 °C to +150 °C
DC output current (1 output at a time, 1s duration) .... 15 mA
Maximum accumulated storage time
Electrostatic Discharge Voltage [3]
Human Body Model (AEC-Q100-002 Rev. E) ................... 2 kV
At 150 °C ambient temperature ................................. 1000 h
At 125 °C ambient temperature ................................11000 h
At 85 °C ambient temperature .............................. 121 Years
Charged Device Model (AEC-Q100-011 Rev. B) .............. 500 V
Latch-up current ....................................................> 140 mA
Ambient temperature
with power applied ................................... –55 °C to +125 °C
Operating Range
Supply voltage on VDD relative to VSS .........–1.0 V to +7.0 V
Input voltage ............. –1.0 V to +7.0 V and VIN < VDD+1.0 V
Range
Ambient Temperature (TA)
VDD
Automotive-E
–40 °C to +125 °C
4.5 V to 5.5 V
DC voltage applied to outputs
in High Z state ....................................–0.5 V to VDD + 0.5 V
Transient voltage (< 20 ns)
on any pin to ground potential ............–2.0 V to VDD + 2.0 V
DC Electrical Characteristics
Over the Operating Range
Parameter
VDD
Description
Power supply
Test Conditions
Min
4.5
–
Typ [4]
Max
5.5
0.3
3
Unit
V
5.0
–
IDD
VDD supply current
SCK toggling between fSCK = 1 MHz
mA
mA
mA
VDD – 0.3 V and VSS
other inputs
VSS or VDD – 0.3 V.
SO = Open.
,
fSCK = 14 MHz
fSCK = 16 MHz
–
–
–
–
3.2
ISB
VDD standby current
CS = VDD. All other TA = 85 °C
–
–
–
–
–
–
–
–
–
–
10
μA
μA
μA
μA
V
inputs VSS or VDD
.
TA = 125 °C
–
30
ILI
Input leakage current
Output leakage current
Input HIGH voltage
Input LOW voltage
Output HIGH voltage
Output LOW voltage
VSS < VIN < VDD
–
–
±1
ILO
VIH
VIL
VOH
VOL
VSS < VOUT < VDD
±1
0.75 × VDD
– 0.3
VDD + 0.3
0.25 × VDD
V
IOH = –1 mA
IOL = 2 mA
VDD – 0.8
–
–
0.4
–
V
V
[5]
VHYS
Input Hysteresis (CS and SCK
pin)
0.05 × VDD
V
Notes
3. Electrostatic Discharge voltages specified in the datasheet are the AEC-Q100 standard limits used for qualifying the device. To know the maximum value device passes
for, please refer to the device qualification report available on the website.
4. Typical values are at 25 °C, V = V (typ). Not 100% tested.
DD
DD
5. This parameter is characterized but not 100% tested.
Document Number: 002-10031 Rev. *B
Page 11 of 22
CY15E004Q
Data Retention and Endurance
Parameter
TDR
Description
Data retention
Test condition
Min
11000
11
Max
Unit
Hours
Years
TA = 125 °C
TA = 105 °C
TA = 85 °C
–
–
–
–
121
1013
NVC
Endurance
Over operating temperature
Cycles
Example of an F-RAM Life Time in an AEC-Q100 Automotive Application
An application does not operate under a steady temperature for the entire usage life time of the application. Instead, it is often expected
to operate in multiple temperature environments throughout the application’s usage life time. Accordingly, the retention specification
for F-RAM in applications often needs to be calculated cumulatively. An example calculation for a multi-temperature thermal profiles
is given below.
AccelerationFactorwithrespecttoTmax
A [6]
Profile Factor
P
Profile Life Time
L (P)
Tempeature
T
Time Factor
t
1
1
Ea 1
-------------------------------------------------------
P =
L(P) = P × L(Tmax)
---------------
------- --- –
Tmax
k
T
t1
t2
t3
t4
L(T)
------- ------- ------- -------
+
+
+
------------------------
A =
= e
A1 A2 A3 A4
L(Tmax)
T1 = 125 °C
T2 = 105 °C
T3 = 85 °C
T4 = 55 °C
t1 = 0.1
t2 = 0.15
t3 = 0.25
t4 = 0.50
A1 = 1
A2 = 8.67
8.33
> 10.46 Years
A3 = 95.68
A4 = 6074.80
Capacitance
Parameter [7]
Description
Test Conditions
Max
8
Unit
CO
CI
Output pin capacitance (SO)
Input pin capacitance
TA = 25 °C, f = 1 MHz, VDD = VDD(typ)
pF
pF
6
Thermal Resistance
Parameter [7]
Description
Test Conditions
8-pin SOIC
Unit
ΘJA
Thermal resistance
(junction to ambient)
Test conditions follow standard test methods and
procedures for measuring thermal impedance, per
EIA/JESD51.
148
°C/W
ΘJC
Thermal resistance
(junction to case)
48
°C/W
AC Test Conditions
Input pulse levels .................................10% and 90% of VDD
Input rise and fall times ...................................................5 ns
Input and output timing reference levels ................0.5 × VDD
Output load capacitance .............................................. 30 pF
Notes
-5
6. Where k is the Boltzmann constant 8.617 × 10 eV/K, Tmax is the highest temperature specified for the product, and T is any temperature within the F-RAM product
specification. All temperatures are in Kelvin in the equation.
7. This parameter is characterized but not 100% tested.
Document Number: 002-10031 Rev. *B
Page 12 of 22
CY15E004Q
AC Switching Characteristics
Over the Operating Range
Parameters [8]
Description
Min
Max
Min
Max
Unit
Cypress
Alt. Parameter
Parameter
fSCK
tCH
–
SCK Clock frequency
0
30
30
10
10
–
14
–
0
25
25
10
10
–
16
–
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
–
Clock HIGH time
Clock LOW time
Chip select setup
Chip select hold
Output disable time
Output data valid time
Output hold time
Deselect time
tCL
–
–
–
tCSU
tCSH
tCSS
tCSH
tHZCS
tCO
–
–
–
–
–
[9, 10]
tOD
tODV
tOH
tD
25
30
–
20
25
–
–
–
0
0
–
80
–
–
60
–
–
[11, 12]
tR
–
Data in rise time
Data in fall time
50
50
–
50
50
–
[11, 12]
tF
–
–
–
tSU
tH
tHS
tHH
tSD
tHD
tSH
tHH
tHHZ
tHLZ
Data setup time
5
5
Data hold time
5
–
5
–
HOLD setup time
HOLD hold time
HOLD LOW to HI-Z
HOLD HIGH to data active
10
10
–
–
10
10
–
–
–
–
[9, 10]
tHZ
25
25
20
20
[10]
tLZ
–
–
Notes
8. Test conditions assume a signal transition time of 5 ns or less, timing reference levels of 0.5 × V , input pulse levels of 10% to 90% of V , and output loading of
DD
DD
the specified I /I and 30 pF load capacitance shown in AC Test Conditions on page 12.
OL OH
9.
t
and t are specified with a load capacitance of 5 pF. Transition is measured when the outputs enter a high impedance state.
OD HZ
10. This parameter is characterized but not 100% tested.
11. Rise and fall times measured between 10% and 90% of waveform.
12. These parameters are guaranteed by design and are not tested.
Document Number: 002-10031 Rev. *B
Page 13 of 22
CY15E004Q
Figure 13. Synchronous Data Timing (Mode 0)
t
D
CS
SCK
SI
t
t
t
CSU
CH
CL
t
CSH
t
t
SU
H
VALID IN
VALID IN
VALID IN
t
t
t
OD
OH
ODV
HI-Z
HI-Z
SO
Figure 14. HOLD Timing
CS
SCK
t
t
HH
HH
t
t
HS
HS
HOLD
SI
t
SU
t
VALID IN
VALID IN
t
HZ
LZ
SO
Document Number: 002-10031 Rev. *B
Page 14 of 22
CY15E004Q
Power Cycle Timing
Over the Operating Range
Parameter
Description
Min
Max
Unit
Power-up VDD(min) to first access (CS LOW)
Last access (CS HIGH) to power-down (VDD(min))
VDD power-up ramp rate
1
–
ms
tPU
tPD
tVR
tVF
0
–
–
–
µs
[13]
[13]
30
20
µs/V
µs/V
VDD power-down ramp rate
Figure 15. Power Cycle Timing
V
V
DD(min)
DD(min)
t
t
VR
V
VF
DD
t
t
PU
PD
CS
Note
13. Slope measured at any point on V waveform.
DD
Document Number: 002-10031 Rev. *B
Page 15 of 22
CY15E004Q
Ordering Information
Package
Diagram
Operating
Range
Ordering Code
Package Type
CY15E004Q-SXE
CY15E004Q-SXET
51-85066 8-pin SOIC
51-85066 8-pin SOIC
Automotive-E
All these parts are Pb-free. Contact your local Cypress sales representative for availability of these parts.
Ordering Code Definitions
CY 15
E
004 Q - S
X
E
X
Option: X = blank or T
blank = Standard; T = Tape and Reel
Temperature Range:
E = Automotive-E (–40 °C to +125 °C)
X = Pb-free
Package Type: S = 8-pin SOIC
Q = SPI F-RAM
Density: 004 = 4-kbit
Voltage: E = 4.5 V to 5.5 V
F-RAM
Company ID: CY = Cypress
Document Number: 002-10031 Rev. *B
Page 16 of 22
CY15E004Q
Package Diagram
Figure 16. 8-pin SOIC (150 Mils) Package Outline, 51-85066
51-85066 *H
Document Number: 002-10031 Rev. *B
Page 17 of 22
CY15E004Q
Acronyms
Document Conventions
Units of Measure
Acronym
Description
AEC
Automotive Electronics Council
Clock Phase
Symbol
°C
Unit of Measure
CPHA
CPOL
degree Celsius
hertz
Clock Polarity
Hz
kHz
KΩ
Kbit
kV
MHz
μA
μs
EEPROM Electrically Erasable Programmable Read-Only
Memory
kilohertz
kilohm
EIA
Electronic Industries Alliance
Input/Output
kilobit
I/O
kilovolt
JEDEC
JESD
LSB
Joint Electron Devices Engineering Council
JEDEC Standards
megahertz
microampere
microsecond
milliampere
millisecond
nanosecond
ohm
Least Significant Bit
MSB
F-RAM
RoHS
SPI
Most Significant Bit
mA
ms
ns
Ferroelectric Random Access Memory
Restriction of Hazardous Substances
Serial Peripheral Interface
Small Outline Integrated Circuit
Ω
SOIC
%
percent
pF
V
picofarad
volt
W
watt
Document Number: 002-10031 Rev. *B
Page 18 of 22
CY15E004Q
Errata
This section describes the errata for the 4Kb SPI F-RAM (512 × 8, SPI) products. Details include errata trigger conditions, scope of
impact, available workarounds, and silicon revision applicability. Compare this document with the device datasheet for complete
functional differences.
Contact your local Cypress Sales Representative if you have questions. You can also send your related queries directly to
FRAM@cypress.com.
Part Numbers Affected
Part Number
Device Characteristics
CY15E004Q
512 × 8, 4.5 V to 5.5 V, single power supply, serial (SPI) interface F-RAM in 8-pin SOIC package.
Qualification Status
Production parts.
Errata Summary
The following table defines the errata applicability.
Items
Part Number
Silicon Revision
Fix Status
The Write Enable Latch (WEL) bit in the CY15E004Q-SXE
Status Register of CY15E004Q part doesn’t
clear after executing the memory write
(WRITE) operation at memory location(s)
from 0x100 to 0x1FF.
Rev *A
None. This behavior is applicable
to all listed parts in the production.
1. The Write Enable Latch (WEL) bit in the Status Register of CY15E004Q part doesn’t clear after executing the memory write (WRITE)
operation at memory location(s) from 0x100 to 0x1FF.
■ Problem Definition
As per the CY15E004Q datasheet “sending the WREN opcode causes the internal Write Enable Latch (WEL) to be set. A flag bit
in the status register, called WEL, indicates the state of the latch. WEL = 1 indicates that writes are permitted. Attempting to write
the WEL bit in the status register has no effect. Completing any write operation will automatically clear the write-enable latch and
will prevent further writes without another WREN command”.
However, in the CY15E004Q part, the WEL bit doesn’t clear automatically after writing at any memory location(s) from 0x100 to
0x1FF. That means, after completing the write cycle with the opcode byte 0x0A, WEL bit in status register is still set and hence a
further write can be issued without sending the WREN opcode.
Document Number: 002-10031 Rev. *B
Page 19 of 22
CY15E004Q
Status Register
Status Register Bit Definition
The internal state machine of CY15E004Q is intended to clear the WEL bit after executing write opcodes (WRITE and WRSR).
However, as explained above, the WEL doesn’t clear when executing the memory write (WRITE) at location/s from 0x100 to 0x1FF.
The 4Kb memory requires 9 address bits to map the entire memory array (512 × 8). To optimize the command cycle and to maintain
the compatibility with the industry standard 4Kb SPI EEPROMs, the MSB of the address (9th bit) in the 4Kb device is embedded
into write (WRITE) and read (READ) opcodes as shown below.
For address range – 0x00 to 0xFF:
WRITE opcode – 0000 A010 = 0x0000 0010 (or 0x02 in hex, A = ‘0’)
READ opcode – 0000 A011 = 0x0000 0011 (or 0x03 in hex, A = ‘0’)
For address range – 0x100 to 0x1FF:
WRITE opcode – 0000 A010 = 0x0000 1010 (or 0x0A in hex, A = ‘1’)
READ opcode – 0000 A011 = 0x0000 1011 (or 0x0B in hex, A = ‘1’)
Due to a logic bug in the CY15E004Q state machine, the opcode byte 0x0A does not trigger clearing of WEL bit, hence the WEL
bit remains set even after executing the memory write at address location/s from 0x100 to 0x1FF.
■ Parameters Affected
None.
■ Trigger Condition(S)
Execute the Write Enable command (WREN) followed by the write command (WRITE) to memory address range 0x100 to 0x1FF.
■ Scope of Impact
None. It only allows a subsequent write (WRITE or WRSR) without sending a prior WREN command.
■ Workaround
To ensure that the WEL bit is cleared after every write, the SPI host controller can issue the Write Disable (WRDI) opcode at the
end of every write cycle (after CS goes high). The WRDI command clears the WEL (if set) and disables all writes until the WEL is
set by sending the WREN opcode before initiating a new write operation.
■ Fix Status
There is no fix planned and all the CY15E004Q part in production will continue with the above errata.
Document Number: 002-10031 Rev. *B
Page 20 of 22
CY15E004Q
Document History Page
Document Title: CY15E004Q, 4-Kbit (512 × 8) Serial (SPI) Automotive F-RAM
Document Number: 002-10031
Orig. of
Change
Submission
Date
Rev.
ECN No.
Description of Change
**
5032342
5573964
GVCH
GVCH
12/02/2015 New data sheet.
*A
01/23/2017 Changed status from Summary to Final.
Updated Serial Peripheral Interface – SPI Bus:
Updated WREN - Set Write Enable Latch:
Updated description (Added note regarding Errata).
Updated Maximum Ratings:
Updated Electrostatic Discharge Voltage:
Changed value of “Human Body Model” from 3.5 kV to 2 kV.
Changed value of “Charged Device Model” from 1.25 kV to 500 V.
Removed “Machine Model” related information.
Updated Ordering Information:
Updated part numbers.
Added Errata.
Updated to new template.
*B
5685431
GVCH
04/05/2017 Updated Maximum Ratings:
Added Note 3 and referred the same note in “Electrostatic Discharge Voltage”.
Updated to new template.
Document Number: 002-10031 Rev. *B
Page 21 of 22
CY15E004Q
Sales, Solutions, and Legal Information
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Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
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© Cypress Semiconductor Corporation, 2015–2017. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document,
including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other
intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress
hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to
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(either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as
provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation
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the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress products
are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or
systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the
device or system could cause personal injury, death, or property damage ("Unintended Uses"). A critical component is any component of a device or system whose failure to perform can be reasonably
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damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other
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Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in
the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
Document Number: 002-10031 Rev. *B
Revised April 5, 2017
Page 22 of 22
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