CY223931FXI_技术文档

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CY22393/CY223931

CY22394

CY22395

Three-PLL, Serial-Programmable,

Flash-Programmable Clock Generator

Three-PLL, Serial-Programmable, Flash-Programmable Clock Generator

Features

Advanced Features

■ Three integrated phase-locked loops (PLLs)

■ Two-wire serial interface for in-system configurability

■ Ultra wide divide counters (8-bit Q, 11-bit P, and 7-bit post

■ Configurable output buffer

divide)

■ Digital VCXO

■ Improved linear crystal load capacitors

■ Flash programmability with external programmer

■ Field-programmable

■ High frequency LVPECL output (CY22394 only)

■ 3.3/2.5 V outputs (CY22395 only)

■ NiPdAu lead finish (CY223931)

■ Low jitter, high accuracy outputs

■ Power management options (Shutdown, OE, Suspend)

■ Configurable crystal drive strength

■ Frequency select through three external LVTTL inputs

■ 3.3 V operation

Functional Description

The CY22393, CY22394, and CY22395 are a family of parts

designed as upgrades to the existing CY22392 device. These

parts have similar performance to the CY22392, but provide

advanced features to meet the needs of more demanding

applications.

■ 16-pin TSSOP package

The clock family has three PLLs which, when combined with the

reference, allow up to four independent frequencies to be output

on up to six pins. These three PLLs are completely

programmable.

■ CyClocksRT™ software support

The CY223931 is the CY22393 with NiPdAu lead finish.

For a complete list of related documentation, click here.

Selection Guide

Part Number

Outputs

6 CMOS

Input Frequency Range

Output Frequency Range

Specifics

CY22393_C

8 MHz–30 MHz (external crystal)

1 MHz–166 MHz (reference clock)

Up to 200 MHz

Commercial temperature

CY22393_I

CY223931_I

CY22394_C

CY22394_I

CY22395_C

CY22395_I

6 CMOS

8 MHz–30 MHz (external crystal)

1 MHz–166 MHz (reference clock)

Up to 166 MHz

Industrial temperature

Commercial temperature

Industrial temperature

Commercial temperature

Industrial temperature

8 MHz–30 MHz (external crystal)

1 MHz–166 MHz (reference clock)

Up to 166 MHz

1 PECL/

4 CMOS

8 MHz–30 MHz (external crystal)

100 MHz–400 MHz (PECL)

1 MHz–166 MHz (reference clock) Up to 200 MHz (CMOS)

8 MHz–30 MHz (external crystal) 125 MHz–375 MHz (PECL)

1 MHz–150 MHz (reference clock) Up to 166 MHz (CMOS)

Up to 200 MHz (3.3 V)

1 MHz–166 MHz (reference clock) Up to 133 MHz (2.5 V)

4LVCMOS/1 8 MHz–30 MHz (external crystal) Up to 166 MHz (3.3 V)

CMOS 1 MHz–150 MHz (reference clock) Up to 133 MHz (2.5 V)

1 PECL/

4 CMOS

4LVCMOS/1 8 MHz–30 MHz (external crystal)

CMOS

Cypress Semiconductor Corporation

Document Number: 38-07186 Rev. *N

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised March 27, 2019

CY22393/CY223931

CY22394

CY22395

Logic Block Diagram – CY22393 and CY223931

XTALIN

XBUF

CLKE

OSC.

XTALOUT

CONFIGURATION

PLL1

FLASH

Divider

/2, /3, or /4

11-Bit P

8-Bit Q

SHUTDOWN/OE

PLL2

Divider

7-Bit

SCLK

CLKD

CLKC

11-Bit P

8-Bit Q

4x4

Crosspoint

SDAT

Switch

S2/SUSPEND

Divider

7-Bit

PLL3

11-Bit P

8-Bit Q

Divider

7-Bit

CLKB

CLKA

Divider

7-Bit

Logic Block Diagram – CY22394

XTALIN

XBUF

OSC.

XTALOUT

CONFIGURATION

FLASH

0º

PLL1

P+CLK

P-CLK

PECL

OUTPUT

11-Bit P

8-Bit Q

180º

SHUTDOWN/OE

SCLK

PLL2

Divider

7-Bit

4x4

Crosspoint

Switch

CLKC

CLKB

CLKA

SDAT

11-Bit P

8-Bit Q

S2/SUSPEND

Divider

7-Bit

PLL3

11-Bit P

8-Bit Q

Divider

7-Bit

Document Number: 38-07186 Rev. *N

Page 2 of 26

CY22393/CY223931

CY22394

CY22395

Logic Block Diagram – CY22395

XTALIN

OSC.

XTALOUT

Divider

/2, /3, or /4

LCLKE

LCLKD

CONFIGURATION

FLASH

PLL1

11-Bit P

8-Bit Q

Divider

7-Bit

SHUTDOWN/OE

SCLK

4x4

Crosspoint

Switch

SDAT

Divider

7-Bit

CLKC

S2/SUSPEND

PLL2

11-Bit P

8-Bit Q

Divider

7-Bit

LCLKB

LCLKA

PLL3

Divider

7-Bit

11-Bit P

8-Bit Q

LCLKA, LCLKB, LCLKD, LCLKE referenced to LVDD

Document Number: 38-07186 Rev. *N

Page 3 of 26

CY22393/CY223931

CY22394

CY22395

Contents

Pinouts ..............................................................................5

Pin Definitions ..................................................................5

Functional Overview ........................................................6

Configurable PLLs .......................................................6

General Purpose Inputs ..............................................6

Crystal Input ................................................................6

Crystal Drive Level and Power ....................................6

Digital VCXO ...............................................................6

Output Configuration ...................................................6

Power-Saving Features ...............................................7

Improving Jitter ............................................................7

Power Supply Sequencing ..........................................7

CyClocksRT Software ......................................................7

Junction Temperature Limitations ...............................7

Dynamic Updates ........................................................7

Memory Bitmap Definitions .............................................8

Clk{A–D}_Div[6:0] ........................................................8

ClkE_Div[1:0] ...............................................................8

Clk*_FS[2:0] ................................................................8

Xbuf_OE ......................................................................8

PdnEn ..........................................................................8

Clk*_ACAdj[1:0] ...........................................................8

Clk*_DCAdj[1:0] ..........................................................8

PLL*_Q[7:0] .................................................................8

PLL*_P[9:0] .................................................................8

PLL*_P ........................................................................8

PLL*_LF[2:0] ...............................................................9

PLL*_En ......................................................................9

DivSel ..........................................................................9

OscCap[5:0] ................................................................9

OscDrv[1:0] .................................................................9

Reserved .....................................................................9

Serial Programming Bitmaps — Summary Tables ......10

Serial Bus Programming Protocol and Timing ............11

Default Startup Condition

Data Frame ...............................................................12

Acknowledge Pulse ...................................................12

Write Operations .............................................................13

Writing Individual Bytes .............................................13

Writing Multiple Bytes ................................................13

Read Operations .............................................................13

Current Address Read ...............................................13

Random Read ...........................................................13

Sequential Read ........................................................13

Serial Programming Interface Timing ...........................14

Serial Programming Interface

Timing Specifications ....................................................14

Absolute Maximum Conditions .....................................15

Operating Conditions .....................................................15

Recommended Crystal Specifications .........................15

3.3 V Electrical Characteristics .....................................16

2.5 V Electrical Characteristics .....................................16

Thermal Resistance ........................................................16

3.3 V Switching Characteristics ....................................17

2.5 V Switching Characteristics ....................................17

Switching Waveforms ....................................................18

Test Circuit ......................................................................19

Ordering Information ......................................................20

Possible Configurations .............................................20

Ordering Code Definitions .........................................21

Package Diagram ............................................................22

Acronyms ........................................................................23

Document Conventions .................................................23

Units of Measure .......................................................23

Document History Page .................................................24

Sales, Solutions, and Legal Information ......................26

Worldwide Sales and Design Support .......................26

Products ....................................................................26

PSoC® Solutions ......................................................26

Cypress Developer Community .................................26

Technical Support .....................................................26

for the CY22393/931/94/95 ..............................................11

Device Address .........................................................11

Data Valid ..................................................................12

Document Number: 38-07186 Rev. *N

Page 4 of 26

CY22393/CY223931

CY22394

CY22395

Pinouts

Figure 1. 16-pin TSSOP pinout (for CY22393/CY223931/CY22394/CY22395)

SHUTDOWN

/OE

SHUTDOWN

/OE

SHUTDOWN

/OE

1

CLKC

V_DD

CLKC

V_DD

16

CLKC

16

S2/

SUSPEND

S2/

SUSPEND

S2/

SUSPEND

V_DD

AGND

2

3

4

5

6

2

3

4

5

6

2

3

4

5

6

15

14

13

12

11

15

14

13

12

11

CY22393

CY223931

15

14

13

12

11

CY22395

CY22394

AGND

XTALIN

AV_DD

AGND

XTALIN

AV_DD

SCLK(S1)

XTALIN

XTALOUT

LV_DD

SDAT(S0)

XTALOUT

XBUF

SDAT(S0)

GND

XTALOUT

XBUF

SDAT(S0)

GND

GND/

LGND

LCLKD

LCLKE

P-CLK

7

8

7

8

LCLKA

LCLKB

CLKD

CLKA

CLKB

7

8

CLKA

CLKB

10

9

10

9

10

9

P+CLK

CLKE

Pin Definitions

Pin Number

CY22393

CY223931

Pin Number Pin Number

Name

Description

CY22394

CY22395

CLKC

1

2

1

2

1

2

Configurable clock output C

Power supply

V_DD

AGND

3

Analog Ground

XTALIN

4

Reference crystal input or external reference clock input

Reference crystal feedback

XTALOUT

XBUF

5

6

N/A

6

Buffered reference clock output

LV_DD

N/A

7

N/A

7

Low voltage clock output power supply

Configurable clock output D; LCLKD referenced to LVDD

LV PECL output^[1]

CLKD or LCLKD

P– CLK

7

N/A

8

N/A

8

CLKE or LCLKE

P+ CLK

N/A

8

Configurable clock output E; LCLKE referenced to LVDD

LV PECL output^[1]

N/A

9

N/A

9

CLKB or LCLKB

CLKA or LCLKA

GND/LGND

SDAT (S0)

SCLK (S1)

AV_DD

9

Configurable clock output B; LCLKB referenced to LVDD

Configurable clock output A; LCLKA referenced to LVDD

Ground

10

11

12

13

14

10

11

12

13

14

10

11

12

13

14

Serial port data. S0 value latched during start up

Serial port clock. S1 value latched during start up

Analog power supply

S2/

SUSPEND

General purpose input for frequency control; bit 2. Optionally,

Suspend mode control input

15

Places outputs in tristate condition and shuts down chip when

LOW. Optionally, only places outputs in tristate condition and

does not shut down chip when LOW

SHUTDOWN/

OE

16

Note

1. LVPECL outputs require an external termination network.

Document Number: 38-07186 Rev. *N

Page 5 of 26

CY22393/CY223931

CY22394

CY22395

The value of the load capacitors is determined by six bits in a

programmable register. The load capacitance can be set with a

resolution of 0.375 pF for a total crystal load range of 6 pF to

30 pF. Typical crystals have a C_Lspecification in the range of

12 pF to 18 pF.

Functional Overview

Configurable PLLs

PLL1 generates a frequency that is equal to the reference

divided by an 8-bit divider (Q) and multiplied by an 11-bit divider

in the PLL feedback loop (P). The output of PLL1 is sent to two

locations: the cross point switch and the PECL output

(CY22394). The output of PLL1 is also sent to a /2, /3, or /4

synchronous post-divider that is output through CLKE. The

frequency of PLL1 can be changed using serial programming or

by external CMOS inputs, S0, S1, and S2. See the following

section on General Purpose Inputs for more detail.

For driven clock inputs, the input load capacitors can be

completely bypassed. This allows the clock chip to accept driven

frequency inputs up to 166 MHz. If the application requires a

driven input, leave XTALOUT floating.

Crystal Drive Level and Power

Crystals are specified to accept a maximum drive level.

Generally, larger crystals can accept more power. For a given

voltage swing, power dissipation in the crystal is proportional to

ESR and proportional to the square of the crystal frequency.

(Note that actual ESR is sometimes much less than the value

specified by the crystal manufacturer.) Power is also almost

proportional to the square of C_L.

PLL2 generates a frequency that is equal to the reference

divided by an 8-bit divider (Q) and multiplied by an 11-bit divider

in the PLL feedback loop (P). The output of PLL2 is sent to the

cross point switch. The frequency of PLL2 is changed using

serial programming.

PLL3 generates a frequency that is equal to the reference

divided by an 8-bit divider (Q) and multiplied by an 11-bit divider

in the PLL feedback loop (P). The output of PLL3 is sent to the

cross point switch. The frequency of PLL3 is changed using

serial programming.

Power can be reduced to less than the DL specification in the

table below by selecting a reduced frequency crystal with low C_L

and low R₁(ESR).

Digital VCXO

General Purpose Inputs

The serial programming interface is used to dynamically change

the capacitor load value on the crystal. A change in crystal load

capacitance corresponds with a change in the reference

frequency.

S2 is a general purpose input that is programmed to allow for two

different frequency settings. Options that switches with this

general purpose input are as follows: the frequency of PLL1, the

output divider of CLKB, and the output divider of CLKA.

For special pullable crystals specified by Cypress, the

capacitance pull range is +150 ppm to –150 ppm from midrange.

The two frequency settings are contained within an eight-row

frequency table. The values of SCLK (S1) and SDAT (S0) pins

are latched during start up and used as the other two indexes

into this array.

Be aware that adjusting the frequency of the reference affects all

frequencies on all PLLs in a similar manner since all frequencies

are derived from the single reference.

CLKA and CLKB have seven-bit dividers that point to one of the

two programmable settings (register 0 and register 1). Both

clocks share a single register control and both must be set to

register 0, or both must be set to register 1.

Output Configuration

Under normal operation there are four internal frequency

sources that are routed through a programmable cross point

switch to any of the four programmable 7-bit output dividers. The

four sources are: reference, PLL1, PLL2, and PLL3. The

following is a description of each output.

For example, the part may be programmed to use S0, S1, and

S2 (0,0,0 to 1,1,1) to control eight different values of P and Q on

PLL1. For each PLL1 P and Q setting, one of the two CLKA and

CLKB divider registers can be chosen. Any divider change as a

result of switching S2 is guaranteed to be glitch free.

CLKA’s output originates from the cross point switch and goes

through a programmable 7-bit post divider. The 7-bit post divider

derives its value from one of the two programmable registers.

See the section on General Purpose Inputs for more information.

Crystal Input

The input crystal oscillator is an important feature of this family

of parts because of its flexibility and performance features.

CLKB’s output originates from the cross point switch and goes

through a programmable 7-bit post divider. The 7-bit post divider

derives its value from one of the two programmable registers.

See the section on General Purpose Inputs for more information.

The oscillator inverter has programmable drive strength. This

allows for maximum compatibility with crystals from various

manufacturers. Parallel resonant, fundamental mode crystals

should be used.

CLKC’s output originates from the cross point switch and goes

through a programmable 7-bit post divider. The 7-bit post divider

derives its value from one programmable register.

The input load capacitors are placed on-die to reduce external

component cost. These capacitors are true parallel-plate

capacitors for ultra-linear performance. These were chosen to

reduce the frequency shift that occurs when nonlinear load

capacitance interacts with load, bias, supply, and temperature

changes. Nonlinear (FET gate) crystal load capacitors must not

be used for MPEG, communications, or other applications that

are sensitive to absolute frequency requirements.

CLKD’s output originates from the cross point switch and goes

through a programmable 7-bit post divider. The 7-bit post divider

derives its value from one programmable register. For the

CY22394, CLKD is brought out as the complimentary version of

a LV PECL Clock referenced to CLKE, bypassing both the cross

point switch and 7-bit post divider.

CLKE’s output originates from PLL1 and goes through a post

divider that may be programmed to /2, /3, or /4. For the CY22394,

Document Number: 38-07186 Rev. *N

Page 6 of 26

CY22393/CY223931

CY22394

CY22395

CLKE is brought out as a low voltage PECL Clock, bypassing the

post divider.

CyClocksRT Software

CyClocksRT is our second generation software application that

allows users to configure this family of devices. The easy-to-use

interface offers complete control of the many features of this

family including, but not limited to, input frequency, PLL and

output frequencies, and different functional options. It checks

data sheet frequency range limitations and automatically applies

performance tuning. CyClocksRT also has a power estimation

feature that allows the user to see the power consumption of a

specific configuration. You can download a free copy of

CyberClocks that includes CyClocksRT for free on Cypress’s

web site at www.cypress.com.

XBUF is the buffered reference.

The Clock outputs have been designed to drive a single point

load with a total lumped load capacitance of 15 pF. While driving

multiple loads is possible with the proper termination it is

generally not recommended.

Power-Saving Features

The SHUTDOWN/OE input tristates the outputs when pulled

LOW. If system shutdown is enabled, a LOW on this pin also

shuts off the PLLs, counters, reference oscillator, and all other

active components. The resulting current on the V_DDpins is less

than 5 mA (typical). Relock the PLLs after leaving shutdown

mode.

CyClocksRT is used to generate P, Q, and divider values used

in serial programming. There are many internal frequency rules

that are not documented in this data sheet, but are required for

proper operation of the device. Check these rules by using the

latest version of CyClocksRT.

The S2/SUSPEND input is configured to shut down a

customizable set of outputs and/or PLLs, when LOW. All PLLs

and any of the outputs are shut off in nearly any combination.

The only limitation is that if a PLL is shut off, all outputs derived

from it must also be shut off. Suspending a PLL shuts off all

associated logic, while suspending an output simply forces a

tristate condition.

Junction Temperature Limitations

It is possible to program this family such that the maximum

Junction Temperature rating is exceeded. The package _JAis

115 °C/W. Use the CyClocksRT power estimation feature to

verify that the programmed configuration meets the Junction

Temperature and Package Power Dissipation maximum ratings.

With the serial interface, each PLL and/or output is individually

disabled. This provides total control over the power savings.

Dynamic Updates

Improving Jitter

The output divider registers are not synchronized with the output

clocks. Changing the divider value of an active output is likely

cause a glitch on that output.

Jitter Optimization Control is useful for mitigating problems

related to similar clocks switching at the same moment, causing

excess jitter. If one PLL is driving more than one output, the

negative phase of the PLL can be selected for one of the outputs

(CLKA–CLKD). This prevents the output edges from aligning,

allowing superior jitter performance.

PLL P and Q data is spread between three bytes. Each byte

becomes active on the acknowledge for that byte, so changing

P and Q data for an active PLL is likely cause the PLL to try to

lock on an out-of-bounds condition. For this reason, turn off the

PLL being programmed during the update. Do this by setting the

PLL*_En bit LOW.

Power Supply Sequencing

For parts with multiple V_DDpins, there are no power supply

sequencing requirements. The part is not fully operational until

all V_DDpins have been brought up to the voltages specified in

the Operating Conditions Table on page 15.

PLL1, CLKA, and CLKB each have multiple registers supplying

data. To program these resources safely, always program an

inactive register, and then transition to that register. This allows

these resources to stay active during programming.

All grounds must be connected to the same ground plane.

The serial interface is active even with the SHUTDOWN/OE pin

LOW as the serial interface logic uses static components and is

completely self timed. The part does not meet the I_DDScurrent

limit with transitioning inputs.

Document Number: 38-07186 Rev. *N

Page 7 of 26

CY22393/CY223931

CY22394

CY22395

Xbuf_OE

Memory Bitmap Definitions

This bit enables the XBUF output when HIGH. For the CY22395,

Xbuf_OE = 0.

Clk{A–D}_Div[6:0]

Each of the four main output clocks (CLKA–CLKD) features a

7-bit linear output divider. Any divider setting between 1 and 127

may be used by programming the value of the desired divider

into this register. Odd divide values are automatically duty cycle

corrected. Setting a divide value of zero powers down the divider

and forces the output to a tristate condition.

PdnEn

This bit selects the function of the SHUTDOWN/OE pin. When

this bit is HIGH, the pin is an active LOW shutdown control. When

this bit is LOW, this pin is an active HIGH output enable control.

Clk*_ACAdj[1:0]

CLKA and CLKB have two divider registers, selected by the

DivSel bit (which in turn is selected by S2, S1, and S0). This

allows the output divider value to change dynamically. For the

CY22394 device, ClkD_Div = 000001.

These bits modify the output predrivers, changing the duty cycle

through the pads. These are nominally set to 01, with a higher

value shifting the duty cycle higher. The performance of the

nominal setting is guaranteed.

ClkE_Div[1:0]

Clk*_DCAdj[1:0]

CLKE has a simpler divider (see Table 1). For the CY22394, set

ClkE_Div = 01.

These bits modify the DC drive of the outputs. The performance

of the nominal setting is guaranteed.

Table 1. ClkE Divider

Table 3. Output Drive Strength

ClkE_Div[1:0]

ClkE Output

Off

Clk*_DCAdj[1:0]

Output Drive Strength

–30% of nominal

00

01

10

11

00

01

10

11

PLL1 0 Phase/4

PLL1 0 Phase/2

PLL1 0 Phase/3

Nominal

+15% of nominal

+50% of nominal

Clk*_FS[2:0]

PLL*_Q[7:0]

Each of the four main output clocks (CLKA–CLKD) has a

three-bit code that determines the clock sources for the output

divider. The available clock sources are: Reference, PLL1, PLL2,

and PLL3. Each PLL provides both positive and negative phased

outputs, for a total of seven clock sources (see Table 2). Note

that the phase is a relative measure of the PLL output phases.

No absolute phase relation exists at the outputs.

PLL*_P[9:0]

PLL*_P

These are the 8-bit Q value and 11-bit P values that determine

the PLL frequency. The formula is:

P_T









------

F_PLL= F_REF



Table 2. Clock Source

Q_T

Equation 1

Clk*_FS[2:0]

000

Clock Source

Reference Clock

P_T= 2  P + 3 + PO

Q_T= Q + 2

001

Reserved

010

PLL1 0 Phase

PLL1 180 Phase

PLL2 0 Phase

PLL2 180 Phase

PLL3 0 Phase

PLL3 180 Phase

011

100

101

110

111

Document Number: 38-07186 Rev. *N

Page 8 of 26

CY22393/CY223931

CY22394

CY22395

PLL*_LF[2:0]

OscDrv[1:0]

These bits adjust the loop filter to optimize the stability of the PLL.

Table 4 can be used to guarantee stability. However,

CyClocksRT uses a more complicated algorithm to set the loop

filter for enhanced jitter performance. Use the Print Preview

function in CyClocksRT to determine the charge pump settings

for optimal jitter performance.

These bits control the crystal oscillator gain setting. These must

always be set according to Table 5. The parameters are the

Crystal Frequency, Internal Crystal Parasitic Resistance

(equivalent series resistance), and the OscCap setting during

crystal start up, which occurs when power is applied, or after

shutdown is released. If in doubt, use the next higher setting.

Table 4. Loop Filter Settings

Table 5. Crystal Oscillator Gain Settings

PLL*_LF[2:0]

P_TMin

16

P_TMax

231

OscCap

00H–20H

20H–30H

30H–40H

000

001

010

011

100

Crystal Freq\R 30  60  30  60  30  60 

232

626

8–15 MHz

15–20 MHz

20–25 MHz

25–30 MHz

00

01

10

01

10

01

10

11

01

10

11

10

11

627

834

835

1043

1600

1044

NA

For external reference, the use Table 6.

PLL*_En

This bit enables the PLL when HIGH. If PLL2 or PLL3 are not

enabled, then any output selecting the disabled PLL must have

a divider setting of zero (off). Since the PLL1_En bit is dynamic,

internal logic automatically turns off dependent outputs when

PLL1_En goes LOW.

Table 6. Osc Drv for External Reference

External Freq (MHz) 1–25 25–50 50–90

90–166

OscDrv[1:0]

00

01

10

11

DivSel

Reserved

This bit controls which register is used for the CLKA and CLKB

dividers.

These bits must be programmed LOW for proper operation of the

device.

OscCap[5:0]

This controls the internal capacitive load of the oscillator. The

approximate effective crystal load capacitance is:

Equation 2

C_LOAD= 6pF + OscCap  0.375pF

Set to zero for external reference clock.

Document Number: 38-07186 Rev. *N

Page 9 of 26

CY22393/CY223931

CY22394

CY22395

Serial Programming Bitmaps — Summary Tables

Addr DivSel

b7

b6

b5

b4

b3

b2

b1

b0

08H

09H

0AH

0BH

0CH

0DH

0EH

0FH

10H

11H

12H

13H

14H

15H

16H

17H

0

1

0

1

–

ClkA_FS[0]

ClkB_FS[0]

ClkC_FS[0]

ClkD_FS[0]

ClkA_Div[6:0]

ClkB_Div[6:0]

ClkC_Div[6:0]

ClkD_Div[6:0]

ClkD_FS[2:1]

ClkC_FS[2:1]

ClkB_FS[2:1]

ClkA_FS[2:1]

Clk{C,X}_ACAdj[1:0]

ClkX_DCAdj[1]

Clk{A,B,D,E}_ACAdj[1:0]

Clk{D,E}_DCAdj[1]

PdnEn

Xbuf_OE

ClkE_Div[1:0]

ClkC_DCAdj[1]

Clk{A,B}_DCAdj[1]

PLL2_Q[7:0]

PLL2_P[7:0]

PLL2_LF[2:0]

Reserved

PLL2_En

PLL3_En

PLL2_PO

PLL3_PO

PLL2_P[9:8]

PLL3_Q[7:0]

PLL3_P[7:0]

PLL3_LF[2:0]

Osc_Cap[5:0]

PLL3_P[9:8]

Osc_Drv[1:0]

Addr S2 (1, 0)

b7

b6

b5

b4

PLL1_Q[7:0]

PLL1_P[7:0]

PLL1_LF[2:0]

b3

b2

b1

b0

40H

41H

42H

43H

44H

45H

46H

47H

48H

49H

4AH

4BH

4CH

4DH

4EH

4FH

50H

51H

52H

53H

54H

55H

56H

57H

000

001

010

011

100

101

110

111

DivSel

PLL1_En

PLL1_PO

PLL1_P[9:8]

PLL1_Q[7:0]

PLL1_P[7:0]

PLL1_LF[2:0]

PLL1_P[9:8]

PLL1_Q[7:0]

PLL1_P[7:0]

PLL1_LF[2:0]

PLL1_Q[7:0]

PLL1_P[7:0]

PLL1_LF[2:0]

PLL1_Q[7:0]

PLL1_P[7:0]

PLL1_LF[2:0]

PLL1_Q[7:0]

PLL1_P[7:0]

PLL1_LF[2:0]

PLL1_Q[7:0]

PLL1_P[7:0]

PLL1_LF[2:0]

PLL1_Q[7:0]

PLL1_P[7:0]

PLL1_LF[2:0]

Document Number: 38-07186 Rev. *N

Page 10 of 26

CY22393/CY223931

CY22394

CY22395

Start Bit; 7-bit Device Address (DA); R/W Bit; Slave Clock

Acknowledge (ACK); 8-bit Memory Address (MA); ACK; 8-bit

Data; ACK; 8-bit Data in MA+1 if desired; ACK; 8-bit Data in

MA+2; ACK; etc. until STOP Bit. The basic serial format is

illustrated in Figure 2.

SerialBusProgrammingProtocolandTiming

The CY22393, CY22394 and CY22395 have a 2-wire serial

interface for in-system programming. They use the SDAT and

SCLK pins, and operate up to 400 kbit/s in Read or Write mode.

Except for the data hold time, it is compliant with the I²C bus

standard. The basic Write serial format is as follows:

Figure 2. Data Frame Architecture

1 Bit

Slave

ACK

1 Bit

Slave

ACK

1 Bit

Slave

ACK

1 Bit

Slave

ACK

1 Bit

Slave

ACK

1 Bit

Slave

ACK

1 Bit

Slave

ACK

1 Bit

Slave

ACK

1 Bit

R/W = 0

SDAT Write

Multiple

Contiguous

Registers

7-bit

8-bit

Register

Data

8-bit

Register

Data

8-bit

Register

Data

Device

Address

Register Register Register

Address Data

Data

(XXH+1)

(XXH)

(XXH+2)

(FFH)

(00H)

Stop Signal

Start Signal

1 Bit

Slave

ACK

1 Bit

Slave

ACK

1 Bit

Master

NACK

1 Bit

R/W = 1

SDAT Read

7-bit

Device

Address

Current

Address

Read

8-bit

Register

Data

Stop Signal

Start Signal

1 Bit

Slave

ACK

1 Bit

Master

ACK

1 Bit

Master

ACK

1 Bit

Master

ACK

1 Bit

Master

ACK

1 Bit

Master

ACK

1 Bit

Slave

ACK

1 Bit

Master

NACK

1 Bit

R/W = 0

SDAT Read

Multiple

Contiguous

Registers

7-bit

Device

Address

8-bit

7-bit

8-bit

Register

Data

8-bit

Register

Data

8-bit

Register

Data

8-bit

Register

Data

Register Device

Address

(XXH)

Address

+R/W=1

(XXH)

(XXH+1)

(FFH)

(00H)

Stop Signal

Start Signal

Repeated

Start bit

Default Startup Condition for the CY22393/931/94/95

Device Address

The default (programmed) condition of each device is generally

set by the distributor, who programs the device using a customer

specified JEDEC file produced by CyClocksRT, Cypress’s propri-

etary development software. Parts shipped by the factory are

blank and unprogrammed. In this condition, all bits are set to 0,

all outputs are tristated, and the crystal oscillator circuit is active.

The device address is a 7-bit value that is configured during Field

Programming. By programming different device addresses, two

or more parts are connected to the serial interface and can be

independently controlled. The device address is combined with

a read/write bit as the LSB and is sent after each start bit.

The default serial interface address is 69H, but must there be a

conflict with any other devices in your system, this can also be

changed using CyClocksRT.

While users can develop their own subroutine to program any or

all of the individual registers as described in the following pages,

it may be easier to simply use CyClocksRT to produce the

required register setting file.

Document Number: 38-07186 Rev. *N

Page 11 of 26

CY22393/CY223931

CY22394

CY22395

Data Valid

Data is valid when the clock is HIGH, and can only be

transitioned when the clock is LOW as illustrated in Figure 3.

Figure 3. Data Valid and Data Transition Periods

Transition

to next Bit

Data Valid

SDAT

SCLK

t_SU:DAT

t_HD:DAT

t_HIGH

VIH

VIL

t_LOW

followed by register address (eight bits) and register data (eight

bits).

Data Frame

Every new data frame is indicated by a start and stop sequence,

as illustrated in Figure 4.

Stop Sequence - Stop Frame is indicated by SDAT going HIGH

when SCLK is HIGH. A Stop Frame frees the bus for writing to

another part on the same bus or writing to another random

register address.

Start Sequence - Start Frame is indicated by SDAT going LOW

when SCLK is HIGH. Every time a start signal is given, the next

8-bit data must be the device address (seven bits) and a R/W bit,

Figure 4. Start and Stop Frame

SDAT

SCLK

Transition

to next Bit

START

STOP

as illustrated in Figure 5. (N = the number of bytes transmitted).

During Read Mode, the master generates the acknowledge

pulse after the data packet is read.

Acknowledge Pulse

During Write Mode the CY22393, CY22394, and CY22395

respond with an Acknowledge pulse after every eight bits. To do

this, they pull the SDAT line LOW during the N × 9^thclock cycle,

Figure 5. Frame Format (Device Address, R/W, Register Address, Register Data)

SDAT

+

START

D7

D6

D1

D0

DA6

DA5 DA0

R/W

ACK

RA7

RA6 RA1

RA0

ACK

STOP

+

SCLK

Document Number: 38-07186 Rev. *N

Page 12 of 26

CY22393/CY223931

CY22394

CY22395

does not acknowledge the transfer, but generates a STOP

condition, which causes the CY22393, CY22394 and CY22395

to stop transmission.

Write Operations

Writing Individual Bytes

A valid write operation must have a full 8-bit register address

after the device address word from the master, which is followed

by an acknowledge bit from the slave (ack = 0/LOW). The next

eight bits must contain the data word intended for storage. After

the data word is received, the slave responds with another

acknowledge bit (ack = 0/LOW), and the master must end the

write sequence with a STOP condition.

Random Read

Through random read operations, the master may access any

memory location. To perform this type of read operation, first set

the word address. Do this by sending the address to the

CY22393, CY22394 and CY22395 as part of a write operation.

After the word address is sent, the master generates a START

condition following the acknowledge. This terminates the write

operation before any data is stored in the address, but not before

setting the internal address pointer. Next, the master reissues

the control byte with the R/W byte set to ‘1’. The CY22393,

CY22394 and CY22395 then issue an acknowledge and transmit

the 8-bit word. The master device does not acknowledge the

transfer, but generates a STOP condition which causes the

CY22393, CY22394 and CY22395 to stop transmission.

Writing Multiple Bytes

To write multiple bytes at a time, the master must not end the

write sequence with a STOP condition. Instead, the master

sends multiple contiguous bytes of data to be stored. After each

byte, the slave responds with an acknowledge bit, the same as

after the first byte, and accepts data until the STOP condition

responds to the acknowledge bit. When receiving multiple bytes,

the CY22393, CY223931, CY22394, and CY22395 internally

increment the register address.

Sequential Read

Sequential read operations follow the same process as random

reads except that the master issues an acknowledge instead of

a STOP condition after transmitting the first 8-bit data word. This

action increments the internal address pointer, and subsequently

outputs the next 8-bit data word. By continuing to issue

acknowledges instead of STOP conditions, the master serially

reads the entire contents of the slave device memory. Note that

register addresses outside of 08H to 1BH and 40H to 57H can

be read from but are not real registers and do not contain

configuration information. When the internal address pointer

points to the FFH register, after the next increment, the pointer

points to the 00H register.

Read Operations

Read operations are initiated the same way as Write operations

except that the R/W bit of the slave address is set to ‘1’ (HIGH).

There are three basic read operations: current address read,

random read, and sequential read.

Current Address Read

The CY22393, CY22394 and CY22395 have an onboard

address counter that retains “1” more than the address of the last

word access. If the last word written or read was word ‘n’, then a

current address read operation returns the value stored in

location ‘n+1’. When the CY22393, CY22394 and CY22395

receive the slave address with the R/W bit set to a ‘1’, they issue

an acknowledge and transmit the 8-bit word. The master device

Document Number: 38-07186 Rev. *N

Page 13 of 26

CY22393/CY223931

CY22394

CY22395

Serial Programming Interface Timing

Figure 6. Definition for Timing on the Serial BUS

SDAT

SCLK

t_f

t_LOW

t_r

t_SU;DAT

t_f

t_HD;STA

t_r

t_BUF

t_HD;STA

t_SU;STA

t_SU;STO

t_HD;DAT

t_HIGH

P

S

Sr

Serial Programming Interface Timing Specifications

Parameter

Description

Min

–

Max

400

–

Unit

kHz

s

f

t

Frequency of SCLK

SCLK

Hold time START condition

0.6

HD:STA

t

Low period of the SCLK clock

High period of the SCLK clock

1.3

0.6

100

–

s

ns

s

LOW

HIGH

SU:STA

HD:DAT

SU:DAT

R

Setup time for a repeated START condition

Data hold time

–

Data setup time

–

Rise time

300

–

Fall time

–

F

Setup time for STOP condition

Bus-free time between STOP and START conditions

0.6

1.3

SU:STO

BUF

–

Document Number: 38-07186 Rev. *N

Page 14 of 26

CY22393/CY223931

CY22394

CY22395

Package power dissipation ...................................... 350 mW

Absolute Maximum Conditions

Static discharge voltage

(per MIL-STD-883, Method 3015) ......................... > 2000 V

Supply voltage .............................................–0.5 V to +7.0 V

DC input voltage ......................... –0.5 V to + (AV + 0.5 V)

DD

Latch up (per JEDEC 17) ................................... > ±200 mA

Storage temperature ................................ –65 °C to +125 °C

Junction temperature ................................................. 125 °C

Data retention at Tj = 125 °C ................................> 10 years

Maximum programming cycles ....................................... 100

Stresses exceeding absolute maximum conditions may cause

permanent damage to the device. These conditions are stress

ratings only. Functional operation of the device at these or any

other conditions beyond those indicated in the operation

sections of this data sheet is not implied. Extended exposure to

Absolute Maximum Conditions may affect reliability.

Operating Conditions

Parameter

/AV /LV

DD

Description

Supply voltage

Part Numbers

Min

Typ

3.3

2.5

Max

3.465

2.625

Unit

V

All

3.135

2.375

DD

LV

2.5 V output supply voltage

CY22395

All

V

DD

T

Commercial operating

temperature, Ambient

A

0

–

+70

+85

C

Industrial operating temperature, All

Ambient

–40

C

Maximum load capacitance

External reference crystal

All

–

8

–

15

30

pF

LOAD_OUT

f

MHz

REF

[2]

External reference clock,

1

–

166

150

MHz

Commercial

[2]

External reference clock,

All

Industrial

Recommended Crystal Specifications

Parameter

Description

Conditions

Min

Typ

Max

Unit

F

Nominal crystal frequency

Parallel resonance, fundamental

mode

8

–

30

MHz

NOM

C

R

Nominal load capacitance

–

8

–

20

50

pF

LNOM

Equivalent series resistance

(ESR)

Fundamental mode



1

DL

Crystal drive level

No external series resistor assumed

–

0.5

2

mW

Note

2. External input reference clock must have a duty cycle between 40% and 60%, measured at V /2.

DD

Document Number: 38-07186 Rev. *N

Page 15 of 26

CY22393/CY223931

CY22394

CY22395

3.3 V Electrical Characteristics

[3]

Parameter

Description

Conditions

= (L)V – 0.5, (L)V = 3.3 V

Min

12

–

Typ

24

6

Max

–

Unit

mA

pF

[4]

I

Output high current

V

OH

OL

OH

DD

[4]

Output low current

= 0.5, (L)V = 3.3 V

–

OL

DD

[4]

[5]

C

Crystal load capacitance

Capload at minimum setting

Capload at maximum setting

Except crystal pins

–

XTAL_MIN

–

30

7

–

pF

XTAL_MAX

[4]

Input pin capacitance

–

pF

IN

IH

IL

V

I

High-level input voltage

Low-level input voltage

Input high current

CMOS levels,% of AV

70%

–

AV

DD

–

30%

10

–

V

= AV – 0.3 V

–

<1

A

IH

IN

DD

I

Input low current

= +0.3 V

–

A

IL

Output leakage current

Three-state outputs

–

OZ

DD

Total power supply current

3.3-V power supply;

2 outputs at 20 MHz;

4 outputs at 40 MHz

–

50

100

5

mA

3.3-V power supply;

2 outputs at 166 MHz;

4 outputs at 83 MHz

–

mA

I

Total power supply current in

shutdown mode

Shutdown active

20

A

DDS

2.5 V Electrical Characteristics

[6]

(CY22395 only)

Parameter

Description

Conditions

= LV – 0.5, LV = 2.5 V

Min

8

Typ

16

Max

Unit

mA

[4]

I

Output high current

V

–

OH_2.5

OL_2.5

OH

DD

[4]

Output low current

= 0.5, LV = 2.5 V

8

16

mA

OL

DD

Thermal Resistance

[7]

Parameter

Description

Test Conditions

16-pin TSSOP Unit

θ

Thermal resistance

(junction to ambient)

Test conditions follow standard test methods and

procedures for measuring thermal impedance, in

accordance with EIA/JESD51.

90

°C/W

JA

θ

Thermal resistance

(junction to case)

14

°C/W

JC

Notes

3. Unless otherwise noted, Electrical and Switching Characteristics are guaranteed across these operating conditions.

4. Guaranteed by design, not 100% tested.

5. External input reference clock must have a duty cycle between 40% and 60%, measured at V /2.

DD

6.

V

is only specified and characterized at 3.3 V ± 5% and 2.5 V ± 5%. V

may be powered at any value between 3.465 and 2.375.

DDL

7. These parameters are guaranteed by design and are not tested.

Document Number: 38-07186 Rev. *N

Page 16 of 26

CY22393/CY223931

CY22394

CY22395

3.3 V Switching Characteristics

Parameter

1/t

Description

Conditions

Min

Typ

Max

Unit

[8, 9]

Output frequency

Clock output limit, CMOS,

Commercial

–

200

MHz

1

Clock output limit, CMOS, Industrial

–

166

400

MHz

Clock output limit, PECL,

100

Commercial (CY22394 only)

Clock output limit, PECL,

Industrial (CY22394 only)

125

–

375

MHz

[8, 10]

t

Output duty cycle

Duty cycle for outputs,

45%

50%

55%

2

defined as t  t ,

2

1

Fout < 100 MHz, divider >= 2,

measured at V /2

DD

Duty cycle for outputs,

40%

50%

60%

defined as t  t ,

2

1

Fout > 100 MHz or divider = 1,

measured at V /2

DD

[8]

t

Rising edge slew rate

Output clock rise time, 20% to 80%

0.75

–

1.4

150

–

V/ns

ns

3

4

5

of V

DD

[8]

Falling edge slew rate

Output clock fall time, 20% to 80%

of V

DD

[8]

Output three-state timing

Time for output to enter or leave

three-state mode after

300

SHUTDOWN/OE switches

[8, 11]

t

Clock jitter

Peak-to-peak period jitter, CLK

–

400

0

–

ps

V

6

outputs measured at V /2

DD

[8]

v

P+/P– crossing point

Crossing point referenced to Vdd/2,

balanced resistor network

(CY22394 only)

–0.2

0.2

7

[8, 11]

t

P+/P– jitter

Peak-to-peak period jitter, P+/P–

outputs measured at crossing point

(CY22394 only)

–

200

1.0

–

3

ps

8

[8]

t

Lock time

PLL Lock Time from Power up

ms

9

2.5 V Switching Characteristics

[12]

(CY22395 only)

Parameter

1/t

Description

Conditions

Min

–

Typ

–

Max

133

Unit

[8, 9]

Output frequency

Clock output limit, LVCMOS

MHz

1_2.5

[8, 10]

t

Output duty cycle

Duty cycle for outputs,

40%

50%

60%

2_2.5

defined as t  t

2

1

measured at LV /2

DD

[8]

t

Rising edge slew rate

Output clock rise time, 20% to 80%

0.5

1.0

–

V/ns

3_2.5

of LV

DD

[8]

Falling edge slew rate

Output clock fall time, 20% to 80%

of LV

4_2.5

DD

Notes

8. Guaranteed by design, not 100% tested.

9. Guaranteed to meet 20%–80% output thresholds, duty cycle, and crossing point specifications.

10. Reference Output duty cycle depends on XTALIN duty cycle.

11. Jitter varies significantly with configuration. Reference Output jitter depends on XTALIN jitter and edge rate.

12. V

is only specified and characterized at 3.3 V ± 5% and 2.5 V ± 5%. V

may be powered at any value between 3.465 and 2.375.

DDL

Document Number: 38-07186 Rev. *N

Page 17 of 26

CY22393/CY223931

CY22394

CY22395

Switching Waveforms

Figure 7. All Outputs, Duty Cycle and Rise and Fall Time

t

1

t

2

OUTPUT

t

3

t

4

Figure 8. Output Tristate Timing

OE

t

5

t

5

ALL

TRISTATE

OUTPUTS

Figure 9. CLK Output Jitter

t₆

CLK

OUTPUT

Figure 10. P+/P– Crossing Point and Jitter

t₈

P–

v₇

V

/2

DD

P+

Figure 11. CPU Frequency Change

SELECT

CPU

OLD SELECT

NEW SELECT STABLE

t

9

F

new

F

old

Document Number: 38-07186 Rev. *N

Page 18 of 26

CY22393/CY223931

CY22394

CY22395

Test Circuit

Figure 12. Test Circuit

AV _DD

0.1 F

CLK out

C_LOAD

V_DD

P+/P- out

(L)V

DD

0.1 F

GND

Document Number: 38-07186 Rev. *N

Page 19 of 26

CY22393/CY223931

CY22394

CY22395

Ordering Information

Ordering Code

Pb-free

Package Type

Product Flow

CY22393FXC

CY22393FXCT

CY22393FXI

16-pin TSSOP

Commercial, 0 °C to 70 °C

16-pin TSSOP - Tape and Reel

16-pin TSSOP

Commercial, 0 °C to 70 °C

Industrial, –40 °C to 85 °C

Commercial, 0 °C to 70 °C

Industrial, –40 °C to 85 °C

Commercial, 0 °C to 70 °C

Industrial, –40 °C to 85 °C

CY22393FXIT

CY223931FXI

CY22394FXC

CY22394FXCT

CY22394FXI

16-pin TSSOP - Tape and Reel

16-pin TSSOP with NiPdAu lead finish

16-pin TSSOP

16-pin TSSOP - Tape and Reel

16-pin TSSOP

CY22394FXIT

CY22395FXC

CY22395FXCT

CY22395FXI

16-pin TSSOP - Tape and Reel

16-pin TSSOP

16-pin TSSOP - Tape and Reel

16-pin TSSOP

CY22395FXIT

16-pin TSSOP - Tape and Reel

Possible Configurations

Some product offerings are factory programmed customer specific devices with customized part numbers. The Possible

Configurations table shows the available device types, but not complete part numbers. Contact your local Cypress FAE or sales

representative for more information.

Ordering Code

Package Type

Product Flow

Pb-free

CY22393ZXC-xxx

CY22393ZXC-xxxT

CY22393ZXI-xxx

CY22393ZXI-xxxT

CY22394ZXC-xxx

CY22394ZXC-xxxT

CY22394ZXI-xxx

CY22394ZXI-xxxT

CY22395ZXC-xxx

CY22395ZXC-xxxT

CY22395ZXI-xxx

CY22395ZXI-xxxT

16-pin TSSOP

Commercial, 0 °C to 70 °C

16-pin TSSOP - Tape and Reel

16-pin TSSOP

Commercial, 0 °C to 70 °C

Industrial, –40 °C to 85 °C

Commercial, 0 °C to 70 °C

Industrial, –40 °C to 85 °C

Commercial, 0 °C to 70 °C

Industrial, –40 °C to 85 °C

16-pin TSSOP - Tape and Reel

16-pin TSSOP

16-pin TSSOP - Tape and Reel

16-pin TSSOP

16-pin TSSOP - Tape and Reel

16-pin TSSOP

16-pin TSSOP - Tape and Reel

16-pin TSSOP

16-pin TSSOP - Tape and Reel

Document Number: 38-07186 Rev. *N

Page 20 of 26

CY22393/CY223931

CY22394

CY22395

Ordering Code Definitions

(1)

(T)

(F) ZX C (-xxx)

CY 22393

T = tape and reel, blank = tube

Configuration specific identifier (factory programmed)

Temperature Range: C = Commercial, I = Industrial

Package:

ZX = TSSOP, Pb-free (factory programmed)

X = TSSOP, Pb-free (field programmable)

F = field programmable, blank = factory programmed

Lead finish:1 = NiPdAu, blank = unspecified

Part Identifier:

CY22393: 3.3 V CMOS clock generator

CY22394: CMOS and LVPECL clock generator

CY22395: 3.3 V/2.5 V CMOS clock generator

Company Code: CY = Cypress Semiconductor

Document Number: 38-07186 Rev. *N

Page 21 of 26

CY22393/CY223931

CY22394

CY22395

Package Diagram

Figure 13. 16-Pin TSSOP (4.40 mm Body) Package Outline, 51-85091

51-85091 *E

Document Number: 38-07186 Rev. *N

Page 22 of 26

CY22393/CY223931

CY22394

CY22395

Acronyms

Document Conventions

Units of Measure

Symbol

Acronym

Description

CMOS

ESR

FAE

complementary metal oxide semiconductor

equivalent series resistance

field application engineer

Unit of Measure

°C

degree Celsius

MHz

A

megahertz

microampere

microfarad

milliampere

millimeter

millisecond

milliwatt

FET

field effect transistor

F

LVCMOS low voltage complementary metal oxide semicon-

ductor

mA

mm

ms

mW

ns

LVPECL

LVTTL

MPEG

OE

low voltage positive emitter coupled logic

low voltage transistor-transistor logic

motion picture experts group

output enable

nanosecond

parts per million

picofarad

ppm

pF

PECL

PLL

positive emitter coupled logic

phase-locked loop

ps

picosecond

volt

TSSOP

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Document Number: 38-07186 Rev. *N

Page 23 of 26

CY22393/CY223931

CY22394

CY22395

Document History Page

Document Title: CY22393/CY223931/CY22394/CY22395, Three-PLL, Serial-Programmable, Flash-Programmable Clock

Generator

Document Number: 38-07186

Orig. of

Change

Submission

Date

Rev.

ECN

Description of Change

**

111984

129388

DSG

RGL

12/09/2001 Change from spec number 38-01144 to 38-07186.

*A

10/13/2003 Added “Serial Programming Interface (SPI) Protocol and Timing”.

Added Write Operations.

Added Read Operations.

Added Serial Programming Interface Timing.

Added Serial Programming Interface Timing Specifications.

*B

*C

237755

848580

RGL

06/25/2004 Updated Ordering Information:

Updated part numbers.

Updated Package Diagram:

spec 51-85091 – Changed revision from ** to *A.

03/15/2007 Updated Advanced Features:

Updated description.

Updated “Benefits”:

Updated description.

Updated Pin Definitions:

Updated details in “Description” column corresponding to SDAT (S0) and

SCLK (S1) pins.

Updated Serial Programming Interface (SPI) Protocol and Timing:

2

Updated heading to read as “I C Serial Programming Protocol and Timing”.

Updated description.

Updated to new template.

2

*D

*E

*F

2584052 AESA / KVM 10/10/2008 Replaced “I C” with “2-wire” in all instances across the document.

Updated “Serial Bus Programming Protocol and Timing”:

Updated heading to read as “Serial Bus Programming Protocol and Timing”.

Updated description.

Updated Serial Programming Interface Timing Specifications:

Changed minimum value of t parameter corresponding to “Data hold

(SCLK LOW to data transition)” from 0 ns to 100 ns.

Updated Ordering Information:

Updated part numbers.

Replaced “Lead-Free” with “Pb-Free”.

Added Note “Not recommended for new designs.” andreferred the samenote

in CY22393ZC-xxx, CY22393ZC-xxxT, CY22393FC, CY22393FCT,

CY22394FC, CY22394FCT and CY22395FC.

Updated to new template.

DH

2634202 KVM / AESA 01/09/2009 Updated Document Title to read as

“CY22393/CY223931/CY22394/CY22395, Three-PLLSerial-Programmable

Flash-Programmable Clock Generator”.

Added CY223931 part related information in all instances across the

document.

Updated Selection Guide:

Added CY22393_I, CY223931_I part numbers and their corresponding

details.

Updated details in “Part Number” column (Changed the format).

Updated Pin Definitions:

Replaced SUSPEND with SUSPEND in “Name” column.

Updated Ordering Information:

Updated part numbers.

Completing Sunset Review.

2748211

TSAI

08/10/2009 Updated to new template.

Post to external web.

Document Number: 38-07186 Rev. *N

Page 24 of 26

CY22393/CY223931

CY22394

CY22395

Document History Page (continued)

Document Title: CY22393/CY223931/CY22394/CY22395, Three-PLL, Serial-Programmable, Flash-Programmable Clock

Generator

Document Number: 38-07186

Orig. of

Change

Submission

Date

Rev.

ECN

Description of Change

*G

2897775

KVM

03/23/2010 Updated Ordering Information:

Updated part numbers.

Added Possible Configurations and moved xxx part numbers here.

*H

3048452

BASH

10/05/2010 Removed “Benefits”.

Updated Pinouts:

Updated Figure 1.

Updated Functional Overview:

Added Crystal Drive Level and Power.

Added Recommended Crystal Specifications.

Updated Ordering Information:

No change in part numbers.

Replaced “FTG Programmer” with “Programmer” in “Package Type” column

corresponding to “CY3672-USB”.

Added Ordering Code Definitions.

Updated Package Diagram:

spec 51-85091 – Changed revision from *B to *C.

Added Acronyms and Units of Measure.

Updated to new template.

*I

3562729

4576237

PURU

03/27/2012 Updated Package Diagram:

spec 51-85091 – Changed revision from *C to *D.

Completing Sunset Review.

*J

11/21/2014 Updated Functional Description:

Added “For a complete list of related documentation, click here.” at the end.

Updated Serial Bus Programming Protocol and Timing:

Updated Figure 2 (Updated last ACK in SDAT Read-Current Address Read

and SDAT Read-Multiple Contiguous Registers to “NACK”).

Updated Package Diagram:

spec 51-85091 – Changed revision from *D to *E.

*K

*L

4669878

5274688

XHT

PSR

02/25/2015 Updated Serial Bus Programming Protocol and Timing:

Removed Figure 2 “Data Transfer Sequence on the Serial Bus”.

Updated Serial Programming Interface Timing:

Added Figure 6.

Updated Serial Programming Interface Timing Specifications:

Updated details in “Parameter” and “Description” columns.

Completing Sunset Review.

05/17/2016 Updated Functional Overview:

Updated General Purpose Inputs:

Updated description.

Added Thermal Resistance.

Updated to new template.

*M

*N

5734090 AESATMP7 05/11/2017 Updated Cypress Logo and Copyright.

6523585

XHT

03/27/2019 Updated Ordering Information:

Updated part numbers.

Updated to new template.

Document Number: 38-07186 Rev. *N

Page 25 of 26

CY22393/CY223931

CY22394

CY22395

Sales, Solutions, and Legal Information

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®

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firmware included or referenced in this document (“Software”), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries worldwide. Cypress

reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other intellectual property

rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress hereby grants

you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to modify and reproduce

the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users (either directly or

indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress’s patents that are infringed by the Software (as provided by

Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation of the

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TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE

OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. No computing

device can be absolutely secure. Therefore, despite security measures implemented in Cypress hardware or software products, Cypress shall have no liability arising out of any security breach, such

as unauthorized access to or use of a Cypress product. CYPRESS DOES NOT REPRESENT, WARRANT, OR GUARANTEE THAT CYPRESS PRODUCTS, OR SYSTEMS CREATED USING

CYPRESS PRODUCTS, WILL BE FREE FROM CORRUPTION, ATTACK, VIRUSES, INTERFERENCE, HACKING, DATA LOSS OR THEFT, OR OTHER SECURITYINTRUSION (collectively, “Security

Breach”). Cypress disclaims any liability relating to any Security Breach, and you shall and hereby do release Cypress from any claim, damage, or other liability arising from any Security Breach. In

addition, the products described in these materials may contain design defects or errors known as errata which may cause the product to deviate from published specifications. To the extent permitted

by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any product or

circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is the

responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. “High-Risk Device”

means any device or system whose failure could cause personal injury, death, or property damage. Examples of High-Risk Devices are weapons, nuclear installations, surgical implants, and other

medical devices. “Critical Component” means any component of a High-Risk Device whose failure to perform can be reasonably expected to cause, directly or indirectly, the failure of the High-Risk

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and against all claims, costs, damages, and expenses, arising out of any claim, including claims for product liability, personal injury or death, or property damage arising from any use of a Cypress

product as a Critical Component in a High-Risk Device. Cypress products are not intended or authorized for use as a Critical Component in any High-Risk Device except to the limited extent that (i)

Cypress’s published data sheet for the product explicitly states Cypress has qualified the product for use in a specific High-Risk Device, or (ii) Cypress has given you advance written authorization to

use the product as a Critical Component in the specific High-Risk Device and you have signed a separate indemnification agreement.

Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in

the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.

Document Number: 38-07186 Rev. *N

Revised March 27, 2019

Page 26 of 26


型号：	CY223931FXI
厂家：	Infineon
描述：	6-Output Flash-Programmable Clock Generator 时钟光电二极管外围集成电路晶体
文件：	总27页 (文件大小：598K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

CY223931FXI [INFINEON]

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