CY2305SXC-1 [INFINEON]
3.3V Zero Delay Buffer;
| 型号： | CY2305SXC-1 |
| 厂家： | 
Infineon |
| 描述： | 3.3V Zero Delay Buffer 驱动 光电二极管 逻辑集成电路 |
| 文件： | 总26页 (文件大小：655K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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CY2305
CY2309
Low Cost 3.3 V Zero Delay Buffer
CY2305/CY2309, Low Cost 3.3
V Zero Delay Buffer
Features
Functional Description
■ 10 MHz to 100/133 MHz operating range, compatible with CPU
and PCI bus frequencies
The CY2309 is a low-cost 3.3 V zero delay buffer designed to
distribute high speed clocks and is available in a 16-pin SOIC or
TSSOP package. The CY2305 is an 8-pin version of the
CY2309. It accepts one reference input, and drives out five low
skew clocks. The -1H versions of each device operate at up to
100-/133 MHz frequencies, and have higher drive than the -1
devices. All parts have on-chip PLLs which lock to an input clock
on the REF pin. The PLL feedback is on-chip and is obtained
from the CLKOUT pad.
■ Zero input-output propagation delay
■ 60-ps typical cycle-to-cycle jitter (high drive)
■ Multiple low skew outputs
❐ 85 ps typical output-to-output skew
❐ One input drives five outputs (CY2305)
❐ One input drives nine outputs, grouped as 4 + 4 + 1 (CY2309)
The CY2309 has two banks of four outputs each, which can be
controlled by the select inputs as shown in Select Input Decoding
on page 5. If all output clocks are not required, BankB can be
three-stated. The select inputs also allow the input clock to be
directly applied to the outputs for chip and system testing
purposes.
■ Compatible with Pentium-based systems
■ Test Mode to bypass phase-locked loop (PLL) (CY2309)
■ Packages:
❐ 8-pin, 150-mil SOIC package (CY2305)
❐ 16-pin 150-mil SOIC or 4.4-mm TSSOP (CY2309)
The CY2305 and CY2309 PLLs enter a power-down mode when
there are no rising edges on the REF input. In this state, the
outputs are three-stated and the PLL is turned off, resulting in
less than 25.0 μA current draw for these parts. The CY2309 PLL
shuts down in one additional case as shown in Select Input
Decoding on page 5.
■ 3.3 V operation
■ Commercial and industrial temperature ranges
Multiple CY2305 and CY2309 devices can accept the same input
clock and distribute it. In this case, the skew between the outputs
of two devices is guaranteed to be less than 700 ps.
The CY2305/CY2309 is available in two or three different
configurations, as shown in Ordering Information on page 16.
The CY2305-1/CY2309-1 is the base part. The CY2305-1H/
CY2309-1H is the high-drive version of the -1, and its rise and
fall times are much faster than the -1.
For a complete list of related documentation, click here.
Logic Block Diagram
CLKOUT
MUX
PLL
REF
CLKA1
CLKA2
CLKA3
CLKA4
CLKB1
S2
Select Input
Decoding
CLKB2
CLKB3
CLKB4
S1
Cypress Semiconductor Corporation
Document Number: 38-07140 Rev. *Y
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised June 12, 2020
CY2305
CY2309
Contents
Pin Diagram .......................................................................3
Pin Description .................................................................3
Pin Diagram .......................................................................4
Pin Description .................................................................4
Select Input Decoding ......................................................5
Zero Delay and Skew Control ..........................................5
Absolute Maximum Conditions .......................................6
Operating Conditions .......................................................6
Electrical Characteristics .................................................6
Operating Conditions .......................................................7
Electrical Characteristics .................................................7
Test Circuits ......................................................................8
Thermal Resistance ..........................................................8
Typical Duty Cycle and IDD Trends .................................9
Typical Duty Cycle and IDD Trends ...............................10
Switching Characteristics ..............................................11
Switching Characteristics ..............................................12
Switching Characteristics ..............................................13
Switching Characteristics ..............................................14
Switching Waveforms ....................................................15
Ordering Information ......................................................16
Ordering Information ......................................................16
Ordering Code Definitions .........................................17
Package Drawing and Dimensions ...............................18
Acronyms ........................................................................20
Document Conventions .................................................20
Units of Measure .......................................................20
Errata ...............................................................................21
Part Numbers Affected ..............................................21
CY2305/CY2309 Qualification Status .......................22
CY2305/CY2309 Errata Summary ............................22
Document History Page .................................................23
Sales, Solutions, and Legal Information ......................25
Worldwide Sales and Design Support .......................25
Products ....................................................................25
PSoC® Solutions .......................................................25
Cypress Developer Community .................................25
Technical Support .....................................................25
Document Number: 38-07140 Rev. *Y
Page 2 of 25
CY2305
CY2309
Pin Diagram
Figure 1. 8-pin SOIC pinout
CY2305
1
8
CLKOUT
CLK4
V
DD
REF
CLK2
CLK1
GND
2
3
4
7
6
5
CLK3
Pin Description
For CY2305
Pin
Signal
REF[1]
Description
1
Input reference frequency, 5-V tolerant input
Buffered clock output
CLK2[2]
2
3
CLK1[2]
GND
Buffered clock output
4
5
Ground
CLK3[2]
VDD
CLK4[2]
Buffered clock output
6
7
3.3-V supply
Buffered clock output
CLKOUT[2]
8
Buffered clock output, internal feedback on this pin
Notes
1. Weak pull down.
2. Weak pull down on all outputs.
Document Number: 38-07140 Rev. *Y
Page 3 of 25
CY2305
CY2309
Pin Diagram
Figure 2. 16-pin SOIC / TSSOP pinout
CY2309
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
REF
CLKOUT
CLKA1
CLKA4
CLKA3
VDD
CLKA2
VDD
GND
GND
CLKB4
CLKB3
S1
CLKB1
CLKB2
S2
Pin Description
For CY2309
Pin
1
Signal
REF[3]
CLKA1[4]
CLKA2[4]
VDD
Description
Input reference frequency, 5-V tolerant input
Buffered clock output, Bank A
Buffered clock output, Bank A
3.3-V supply
2
3
4
5
GND
Ground
CLKB1[4]
CLKB2[4]
S2[5]
6
Buffered clock output, Bank B
Buffered clock output, Bank B
Select input, bit 2
7
8
S1[5]
9
Select input, bit 1
CLKB3[4]
CLKB4[4]
GND
10
11
12
13
14
15
16
Buffered clock output, Bank B
Buffered clock output, Bank B
Ground
VDD
3.3-V supply
CLKA3[4]
CLKA4[4]
CLKOUT[4]
Buffered clock output, Bank A
Buffered clock output, Bank A
Buffered output, internal feedback on this pin
Notes
3. Weak pull down.
4. Weak pull down on all outputs.
5. Weak pull ups on these inputs.
Document Number: 38-07140 Rev. *Y
Page 4 of 25
CY2305
CY2309
Select Input Decoding
For CY2309
S2
0
S1
0
CLOCK A1–A4
Three-state
Driven
CLOCK B1–B4
Three-state
Three-state
Driven
CLKOUT [6]
Driven
Output Source
PLL
PLL Shutdown
N
N
Y
N
0
1
Driven
PLL
1
0
Driven
Driven
Reference
PLL
1
1
Driven
Driven
Driven
Figure 3. REF. Input to CLKA/CLKB Delay vs. Loading Difference between CLKOUT and CLKA/CLKB Pins
Zero Delay and Skew Control
All outputs must be uniformly loaded to achieve zero delay between the input and output. Because the CLKOUT pin is the internal
feedback to the PLL, its relative loading can adjust the input-output delay. This is shown in the above graph.
For applications requiring zero input-output delay, all outputs, including CLKOUT, must be equally loaded. Even if CLKOUT is not
used, it must have a capacitive load, equal to that on other outputs, for obtaining zero input-output delay. If input to output delay
adjustments are required, use Figure 3 to calculate loading differences between the CLKOUT pin and other outputs.
Note
6. This output is driven and has an internal feedback for the PLL. The load on this output can be adjusted to change the skew between the reference and output.
Document Number: 38-07140 Rev. *Y
Page 5 of 25
CY2305
CY2309
Storage temperature .................................. –65°C to +150°C
Junction temperature ................................................. 150°C
Absolute Maximum Conditions
Supply voltage to ground potential ..............–0.5 V to +7.0 V
DC input voltage (Except REF) ..........–0.5 V to VDD + 0.5 V
DC input voltage REF .......................................–0.5 V to 7 V
Static discharge voltage
(per MIL-STD-883, Method 3015) .........................> 2,000 V
Operating Conditions
For CY2305SC-XX and CY2309SC-XX Commercial Temperature Devices
Parameter Description
VDD
Min
3.0
0
Max
3.6
70
30
10
7
Unit
V
Supply voltage
TA
Operating temperature (ambient temperature)
Load capacitance, below 100 MHz
Load capacitance, from 100 MHz to 133 MHz
Input capacitance
°C
pF
pF
pF
ms
CL
CL
CIN
tPU
–
–
–
Power-up time for all VDDs to reach minimum specified voltage (power ramps must
be monotonic)
0.05
50
Electrical Characteristics
For CY2305SC-XX and CY2309SC-XX Commercial Temperature Devices
Parameter
VIL
Description
Input LOW voltage [7]
Input HIGH voltage [7]
Input LOW current
Test Conditions
Min
–
Max
0.8
Unit
V
VIH
IIL
2.0
–
–
V
VIN = 0 V
50.0
100.0
0.4
μA
μA
V
IIH
Input HIGH current
Output LOW voltage [8]
VIN = VDD
–
VOL
IOL = 8 mA (–1)
–
I
OL = 12 mA (–1H)
IOH = –8 mA (–1)
OH = –12 mA (–1H)
Output HIGH voltage [8]
VOH
2.4
–
V
I
I
DD (PD mode) Power-down supply current
REF = 0 MHz
–
–
12.0
32.0
μA
IDD
Supply current
Unloaded outputs at 66.67 MHz,
SEL inputs at VSS
mA
Notes
7. REF input has a threshold voltage of V /2.
DD
8. Parameter is guaranteed by design and characterization. Not 100% tested in production.
Document Number: 38-07140 Rev. *Y
Page 6 of 25
CY2305
CY2309
Operating Conditions
For CY2305SI-XX and CY2309SI-XX Industrial Temperature Devices
Parameter
VDD
Description
Min
3.0
–40
–
Max
Unit
V
Supply voltage
3.6
85
30
10
7
TA
Operating temperature (ambient temperature)
Load capacitance, below 100 MHz
Load capacitance, from 100 MHz to 133 MHz
Input capacitance
°C
pF
pF
pF
ms
CL
CL
CIN
tPU
–
–
Power-up time for all VDDs to reach minimum specified voltage (power ramps must
be monotonic)
0.05
50
Electrical Characteristics
For CY2305SI-XX and CY2309SI-XX Industrial Temperature Devices
Parameter
VIL
Description
Input LOW voltage [9]
Input HIGH voltage [9]
Input LOW current
Test Conditions
Min
–
Max
0.8
Unit
V
VIH
IIL
2.0
–
–
V
VIN = 0 V
50.0
100.0
0.4
μA
μA
V
IIH
Input HIGH current
VIN = VDD
–
Output LOW voltage [10]
VOL
IOL = 8 mA (–1)
–
IOL =12 mA (–1H)
IOH = –8 mA (–1)
IOH = –12 mA (–1H)
REF = 0 MHz
Output HIGH voltage [10]
VOH
2.4
–
V
IDD (PD mode) Power-down supply current
–
–
25.0
35.0
μA
IDD
Supply current
Unloaded outputs at 66.67 MHz, SEL inputs at
VSS
mA
Notes
9. REF input has a threshold voltage of V /2.
DD
10. Parameter is guaranteed by design and characterization. Not 100% tested in production.
Document Number: 38-07140 Rev. *Y
Page 7 of 25
CY2305
CY2309
Test Circuits
Figure 4. Test Circuits
Test Circuit # 1
Test Circuit # 2
V
V
DD
DD
1 kΩ
1 kΩ
CLK out
0.1 μ F
0.1 μ F
OUTPUTS
OUTPUTS
10 pF
C
LOAD
V
V
DD
DD
0.1 μ F
GND
GND
0.1 μ F
GND
GND
For parameter t8 (output slew rate) on -1H devices
Thermal Resistance
Parameter [11]
Description
Test Conditions
8-pin SOIC
16-pin SOIC 16-pin TSSOP Unit
θJA
Thermal resistance
(junction to ambient)
Test conditions follow
standard test methods
and procedures for
measuring thermal
impedance, in
140
111
117
°C/W
θJC
Thermal resistance
(junction to case)
54
60
22
°C/W
accordance with
EIA/JESD51.
Note
11. These parameters are guaranteed by design and are not tested.
Document Number: 38-07140 Rev. *Y
Page 8 of 25
CY2305
CY2309
Typical Duty Cycle and I Trends
DD
For CY2305-1 and CY2309-1 [12, 13]
Duty Cycle Vs VDD
Duty Cycle Vs VDD
(for 30 pF Loads over Frequency - 3.3V, 25C)
(for 15 pF Loads over Frequency - 3.3V, 25C)
60
60
58
56
54
52
50
48
46
44
42
40
58
56
54
52
50
48
46
44
42
40
33 MHz
66 MHz
100 MHz
133 MHz
33 MHz
66 MHz
100 MHz
3
3.1
3.2
3.3
3.4
3.5
3.6
3
3.1
3.2
3.3
3.4
3.5
3.6
VDD (V)
VDD (V)
Duty Cycle Vs Frequency
(for 15 pF Loads over Temperature - 3.3V)
Duty Cycle Vs Frequency
(for 30 pF Loads over Temperature - 3.3V)
60
60
58
56
54
52
50
48
46
44
42
40
58
56
54
52
50
48
46
44
42
40
-40C
0C
-40C
0C
25C
70C
85C
25C
70C
85C
20
40
60
80
100
120
140
20
40
60
80
100
120
140
Frequency (MHz)
Frequency (MHz)
IDD vs Number of Loaded Outputs
(for 30 pF Loads over Frequency - 3.3V, 25C)
IDD vs Number of Loaded Outputs
(for 15 pF Loads over Frequency - 3.3V, 25C)
140
140
120
100
80
120
100
80
60
40
20
0
33 MHz
66 MHz
100 MHz
33 MHz
66 MHz
100 MHz
60
40
20
0
0
1
2
3
4
5
6
7
8
9
0
1
2
3
4
5
6
7
8
9
# of Loaded Outputs
# of Loaded Outputs
Notes
12. Duty cycle is taken from typical chip measured at 1.4 V.
13. I data is calculated from I = I
+ nCVf, where I is the unloaded current. (n = # of outputs; C = Capacitance load per output (F); V = Supply Voltage (V);
DD
DD
CORE
CORE
f = frequency (Hz)).
Document Number: 38-07140 Rev. *Y
Page 9 of 25
CY2305
CY2309
Typical Duty Cycle and I Trends
DD
For CY2305-1H and CY2309-1H [14, 15]
Duty Cycle Vs VDD
Duty Cycle Vs VDD
(for 15 pF Loads over Frequency - 3.3V, 25C)
(for 30 pF Loads over Frequency - 3.3V, 25C)
60
60
58
56
58
56
54
52
50
48
46
44
42
40
54
52
50
48
46
44
42
40
33 MHz
66 MHz
100 MHz
133 MHz
33 MHz
66 MHz
100 MHz
3
3.1
3.2
3.3
3.4
3.5
3.6
3
3.1
3.2
3.3
3.4
3.5
3.6
VDD (V)
VDD (V)
Duty Cycle Vs Frequency
(for 30 pF Loads over Temperature - 3.3V)
Duty Cycle Vs Frequency
(for 15 pF Loads over Temperature - 3.3V)
60
58
56
54
52
50
48
46
44
42
40
60
58
56
54
52
50
48
46
44
42
40
-40C
0C
-40C
0C
25C
70C
85C
25C
70C
85C
20
40
60
80
100
120
140
20
40
60
80
100
120
140
Frequency (MHz)
Frequency (MHz)
IDD vs Number of Loaded Outputs
(for 30 pF Loads over Frequency - 3.3V, 25C)
IDD vs Number of Loaded Outputs
(for 15 pF Loads over Frequency - 3.3V, 25C)
160
140
120
100
80
160
140
120
100
80
33 MHz
33 MHz
66 MHz
100 MHz
66 MHz
100 MHz
60
60
40
40
20
20
0
0
0
1
2
3
4
5
6
7
8
9
0
1
2
3
4
5
6
7
8
9
# of Loaded Outputs
# of Loaded Outputs
Notes
14. Duty cycle is taken from typical chip measured at 1.4 V.
15. I data is calculated from I = I
+ nCVf, where I
is the unloaded current. (n = # of outputs; C = Capacitance load per output (F); V = Supply Voltage (V);
DD
DD
CORE
CORE
f = frequency (Hz)).
Document Number: 38-07140 Rev. *Y
Page 10 of 25
CY2305
CY2309
Switching Characteristics
For CY2305SC-1 and CY2309SC-1 Commercial Temperature Devices
Parameter [16]
Description
Output frequency
Test Conditions
30-pF load
Min
10
Typ
–
Max
Unit
MHz
MHz
%
t1
100
133.33
60.0
10-pF load
10
–
Duty cycle [17] = t2 ÷ t1
tDC
Measured at 1.4 V,
Fout = 66.67 MHz
40.0
50.0
Rise time [17]
t3
t4
Measured between 0.8 V and 2.0 V
Measured between 0.8 V and 2.0 V
All outputs equally loaded
–
–
–
–
–
–
2.50
2.50
250
ns
ns
ps
ps
Fall time [17]
Output-to-output skew [17]
t5
85
0
t6A
Delay, REF rising edge to
CLKOUT rising edge [17]
Measured at VDD/2
±350
t6B
Delay, REF rising edge to
CLKOUT rising edge [17]
Measured at VDD/2.
Measured in PLL Bypass Mode,
CY2309 device only.
1
5
8.7
ns
Device-to-device skew [17]
Cycle-to-cycle jitter [17]
PLL lock time [17, 18, 19]
t7
Measured at VDD/2 on the CLKOUT
pins of devices
–
–
–
–
70
–
700
200
1.0
ps
ps
tJ
Measured at 66.67 MHz,
loaded outputs
tLOCK
Stable power supply, valid clock
presented on REF pin
ms
Notes
16. All parameters specified with loaded outputs.
17. Parameter is guaranteed by design and characterization. Not 100% tested in production.
18. The clock outputs are undefined until PLL is locked.
19. For on the fly change in reference input frequency, PLL lock time is only guaranteed when stop time between change in input reference frequency is > 10 µs, Figure 10.
Document Number: 38-07140 Rev. *Y
Page 11 of 25
CY2305
CY2309
Switching Characteristics
For CY2305SC-1H and CY2309SC-1H Commercial Temperature Devices
Parameter [20]
Description
Output frequency
Condition
Min
10
10
40.0
45.0
–
Typ
–
Max
Unit
MHz
MHz
%
t1
30 pF load
10 pF load
100
133.33
60.0
55.0
1.50
1.50
250
–
Duty cycle [21] = t2 ÷ t1
Duty cycle [21] = t2 ÷ t1
Rise time [21]
tDC
tDC
t3
Measured at 1.4 V, Fout = 66.67 MHz
Measured at 1.4 V, Fout < 50 MHz
Measured between 0.8 V and 2.0 V
Measured between 0.8 V and 2.0 V
All outputs equally loaded
50.0
50.0
–
%
ns
Fall time [21]
t4
–
–
ns
Output-to-output skew [21]
t5
–
85
–
ps
t6A
Delay, REF rising edge to
CLKOUT rising edge [21]
Measured at VDD/2
–
±350
ps
t6B
Delay, REF rising edge to
CLKOUT rising edge [21]
Measured at VDD/2.
Measured in PLL Bypass Mode,
CY2309 device only.
1
5
8.7
ns
Device-to-device skew [21]
Output slew rate [21]
t7
Measured at VDD/2 on the CLKOUT
pins of devices
–
1
–
–
–
–
700
ps
V/ns
ps
t8
Measured between 0.8 V and 2.0 V
using Test Circuit #2
Cycle-to-cycle jitter [21]
PLL lock time [21, 22, 23]
tJ
Measured at 66.67 MHz,
loaded outputs
60
–
200
1.0
tLOCK
Stable power supply, valid clock
presented on REF pin
ms
Notes
20. All parameters specified with loaded outputs.
21. Parameter is guaranteed by design and characterization. Not 100% tested in production.
22. The clock outputs are undefined until PLL is locked.
23. For on the fly change in reference input frequency, PLL lock time is only guaranteed when stop time between change in input reference frequency is > 10 µs, Figure 10.
Document Number: 38-07140 Rev. *Y
Page 12 of 25
CY2305
CY2309
Switching Characteristics
For CY2305SI-1 and CY2309SI-1 Industrial Temperature Devices
Parameter [24]
Description
Output frequency
Test Conditions
30 pF load
Min
10
10
40.0
–
Typ
–
Max
Unit
MHz
MHz
%
t1
100
133.33
60.0
10 pF load
–
Duty cycle [25] = t2 ÷ t1
Rise time [25]
tDC
t3
Measured at 1.4 V, Fout = 66.67 MHz
Measured between 0.8 V and 2.0 V
Measured between 0.8 V and 2.0 V
All outputs equally loaded
Measured at VDD/2
50.0
–
2.50
ns
Fall time [25]
t4
–
–
2.50
ns
Output-to-output skew [25]
t5
–
85
–
250
ps
t6A
Delay, REF rising edge to
CLKOUT rising edge [25]
–
±350
ps
t6B
Delay, REF rising edge to
CLKOUT rising edge [25]
Measured at VDD/2. Measured in
PLL Bypass Mode, CY2309 device
only.
1
5
8.7
ns
Device-to-device skew [25]
Cycle-to-cycle jitter [25]
PLL lock time [25, 26, 27]
t7
Measured at VDD/2 on the CLKOUT
pins of devices
–
–
–
–
70
–
700
200
1.0
ps
ps
tJ
Measured at 66.67 MHz, loaded
outputs
tLOCK
Stable power supply, valid clock
presented on REF pin
ms
Notes
24. All parameters specified with loaded outputs.
25. Parameter is guaranteed by design and characterization. Not 100% tested in production.
26. The clock outputs are undefined until PLL is locked.
27. For on the fly change in reference input frequency, PLL lock time is only guaranteed when stop time between change in input reference frequency is > 10 µs, Figure 10.
Document Number: 38-07140 Rev. *Y
Page 13 of 25
CY2305
CY2309
Switching Characteristics
For CY2305SI-1H and CY2309SI-1H Industrial Temperature Devices
Parameter [28]
Description
Output frequency
Conditions
Min
10
10
40.0
45.0
–
Typ
–
Max
Unit
MHz
MHz
%
t1
30 pF load
10 pF load
100
133.33
60.0
55.0
1.50
1.50
250
–
Duty cycle [29] = t2 ÷ t1
Duty cycle [29] = t2 ÷ t1
Rise time [29]
tDC
tDC
t3
Measured at 1.4 V, Fout = 66.67 MHz
Measured at 1.4 V, Fout < 50 MHz
Measured between 0.8 V and 2.0 V
Measured between 0.8 V and 2.0 V
All outputs equally loaded
50.0
50.0
–
%
ns
Fall time [29]
t4
–
–
ns
Output-to output skew [29]
t5
–
85
–
ps
t6A
Delay, REF rising edge to
CLKOUT rising edge [29]
Measured at VDD/2
–
±350
ps
t6B
Delay, REF rising edge to
CLKOUT rising edge [29]
Measured at VDD/2. Measured in
PLL Bypass Mode, CY2309 device
only.
1
5
8.7
ns
Device-to-device skew [29]
Output slew rate [29]
t7
Measured at VDD/2 on the CLKOUT
pins of devices
–
1
–
–
–
–
700
–
ps
V/ns
ps
t8
Measured between 0.8 V and 2.0 V
using Test Circuit #2
Cycle-to-cycle jitter [29]
PLL lock time [29, 30, 31]
tJ
Measured at 66.67 MHz, loaded
outputs
60
–
200
1.0
tLOCK
Stable power supply, valid clock
presented on REF pin
ms
Notes
28. All parameters specified with loaded outputs.
29. Parameter is guaranteed by design and characterization. Not 100% tested in production.
30. The clock outputs are undefined until PLL is locked.
31. For on the fly change in reference input frequency, PLL lock time is only guaranteed when stop time between change in input reference frequency is > 10 µs, Figure 10.
Document Number: 38-07140 Rev. *Y
Page 14 of 25
CY2305
CY2309
Switching Waveforms
Figure 5. Duty Cycle Timing
t
1
t
2
1.4 V
1.4 V
1.4 V
Figure 6. All Outputs Rise/Fall Time
3.3 V
0 V
2.0 V
0.8 V
2.0 V
0.8 V
OUTPUT
t
3
t
4
Figure 7. Output-Output Skew
1.4 V
OUTPUT
1.4 V
OUTPUT
t
5
Figure 8. Input-Output Propagation Delay
V
DD/2
INPUT
VDD/2
OUTPUT
t
6
Figure 9. Device-Device Skew
VDD/2
CLKOUT, Device 1
CLKOUT, Device 2
VDD/2
t7
Figure 10. Stop Time between Change in Input Reference Frequency
Stop Time
Document Number: 38-07140 Rev. *Y
Page 15 of 25
CY2305
CY2309
Ordering Information
For CY2305
Ordering Code
CY2305SC-1
Package Type
Operating Range
8-pin SOIC (150 Mils)
Commercial
Commercial
8-pin SOIC (150 Mils) – Tape and Reel
CY2305SC-1T
Pb-free
8-pin SOIC (150 Mils)
Commercial
Commercial
Industrial
CY2305SXC-1
CY2305SXC-1T
CY2305SXI-1
8-pin SOIC (150 Mils) – Tape and Reel
8-pin SOIC (150 Mils)
8-pin SOIC (150 Mils) – Tape and Reel
8-pin SOIC (150 Mils)
Industrial
CY2305SXI-1T
CY2305SXC-1H
CY2305SXC-1HT
CY2305SXI-1H
CY2305SXI-1HT
Commercial
Commercial
Industrial
8-pin SOIC (150 Mils) – Tape and Reel
8-pin SOIC (150 Mils)
8-pin SOIC (150 Mils) – Tape and Reel
Industrial
Ordering Information
For CY2309
Ordering Code
Pb-free
Package Type
Operating Range
16-pin SOIC (150 Mils)
Commercial
Commercial
Industrial
CY2309SXC-1
CY2309SXC-1T
CY2309SXI-1
16-pin SOIC (150 Mils) – Tape and Reel
16-pin SOIC (150 Mils)
16-pin SOIC (150 Mils) – Tape and Reel
16-pin SOIC (150 Mils)
Industrial
CY2309SXI-1T
CY2309SXC-1H
CY2309SXC-1HT
CY2309SXI-1H
CY2309SXI-1HT
CY2309ZXC-1H
CY2309ZXC-1HT
CY2309ZXI-1H
CY2309ZXI-1HT
Commercial
Commercial
Industrial
16-pin SOIC (150 Mils) – Tape and Reel
16-pin SOIC (150 Mils)
16-pin SOIC (150 Mils) – Tape and Reel
16-pin TSSOP (4.4 mm)
Industrial
Commercial
Commercial
Industrial
16-pin TSSOP (4.4 mm) – Tape and Reel
16-pin TSSOP (4.4 mm)
16-pin TSSOP (4.4 mm) – Tape and Reel
Industrial
Document Number: 38-07140 Rev. *Y
Page 16 of 25
CY2305
CY2309
Ordering Code Definitions
CY 2305 S (X) C – 1 (H) (T)
Tape and reel
Output Drive:
1 = standard drive
1H = high drive
Temperature Range:
C = Commercial
I = Industrial
Package:
S = SOIC, leaded
Z = TSSOP, leaded
SX = SOIC, Pb-free
ZX = TSSOP, Pb-free
Base device part number
2305 = 5-output zero delay buffer
2309 = 9-output zero delay buffer
Company ID: CY = Cypress
Document Number: 38-07140 Rev. *Y
Page 17 of 25
CY2305
CY2309
Package Drawing and Dimensions
Figure 11. 8-pin SOIC (150 Mils) S0815/SZ815/SW815 Package Outline, 51-85066
51-85066 *I
Document Number: 38-07140 Rev. *Y
Page 18 of 25
CY2305
CY2309
Package Drawing and Dimensions (continued)
Figure 12. 16-pin SOIC (150 Mils) S16.15/SZ16.15 Package Outline, 51-85068
51-85068 *F
Figure 13. 16-pin TSSOP (4.40 mm Body) Z16.173/ZZ16.173 Package Outline, 51-85091
51-85091 *E
Document Number: 38-07140 Rev. *Y
Page 19 of 25
CY2305
CY2309
Acronyms
Document Conventions
Units of Measure
Acronym
Description
PCI
Personal Computer Interconnect
Phase Locked Loop
Symbol
°C
Unit of Measure
PLL
degree Celsius
microampere
milliampere
millisecond
megahertz
nanosecond
picofarad
µA
mA
ms
MHz
ns
SDRAM
SOIC
TSSOP
ZDB
Synchronous Dynamic Random Access Memory
Small Outline Integrated Circuit
Thin Small Outline Package
Zero Delay Buffer
pF
ps
picosecond
volt
V
Document Number: 38-07140 Rev. *Y
Page 20 of 25
CY2305
CY2309
Errata
This section describes the errata for Cypress Zero Delay Clock Buffers of the family CY2305/CY2309. Details include errata trigger
conditions, scope of impact, available workaround, and silicon revision applicability. Contact your local Cypress Sales Representative
if you have questions.
Part Numbers Affected
Part Number
CY2305SC-1
Device Characteristics
All Variants
All Variants
All Variants
All Variants
All Variants
All Variants
All Variants
All Variants
All Variants
All Variants
All Variants
All Variants
All Variants
All Variants
All Variants
All Variants
All Variants
All Variants
All Variants
All Variants
All Variants
All Variants
All Variants
All Variants
All Variants
All Variants
All Variants
All Variants
All Variants
All Variants
All Variants
All Variants
All Variants
All Variants
All Variants
All Variants
All Variants
All Variants
CY2305SC-1T
CY2305SC-1H
CY2305SC-1HT
CY2305SI-1H
CY2305SI-1HT
CY2305SXC-1
CY2305SXC-1T
CY2305SXI-1
CY2305SXI-1H
CY2305SXC-1HT
CY2305SXI-1H
CY2305SXI-1HT
CY2309NZSXC-1H
CY2309NZSXC-1HT
CY2309NZSXI-1H
CY2309NZSXI-1HT
CY2309SC-1HT
CY2309SXC-1H
CY2309SXC-1HT
CY2309SXI-1H
CY2309SXI-1HT
CY2309ZC-1H
CY2309ZC-1HT
CY2309ZXC-1H
CY2309ZXC-1HT
CY2309ZXI-1H
CY2309ZXI-1HT
CY2309SXC-1
CY2309SXC-1T
CY2309SXI-1
CY2309SXI-1T
CY2309SC-1
CY2309SC-1T
CY2309SXC-1
CY2309SXC-1T
CY2309SXI-1
CY2309SXI-1T
Document Number: 38-07140 Rev. *Y
Page 21 of 25
CY2305
CY2309
CY2305/CY2309 Qualification Status
Product Status: In production
Qualification report last updated on 11/27/2012 (http://www.cypress.com/?rID=72595)
CY2305/CY2309 Errata Summary
Items
Part Number
Silicon Revision
Fix Status
[1.] Start up lock time issue.
CY2305
B
Silicon fixed. New silicon available
from WW 25 of 2011
CY2309
Silicon fixed. New silicon available
from WW 10 of 2013
1. Start up lock time issue.
Problem Definition
Parameters Affected
Trigger Condition(s)
Scope of Impact
Output of CY2305/CY2309 fails to locks within 1 ms (as per data sheet spec).
PLL lock time.
Start up.
It can impact the performance of system and its throughput.
Workaround
Apply reference input (RefClk) before power up (VDD) Input noise propagates to output due to absence
of reference input signal during power up. If reference input is present during power up, the noise will
not propagate to output and device will start normally without problems.
Fix Status
This issue is due to design marginality. Two minor design modifications have been made to address this
problem.
❐ Addition of VCO bias detector block as shown in the following figure which keeps comparator power
down till VCO bias is present and thereby eliminating the propagation of noise to feedback.
❐ Bias generator enhancement for successful initialization.
Document Number: 38-07140 Rev. *Y
Page 22 of 25
CY2305
CY2309
Document History Page
Document Title: CY2305/CY2309, Low Cost 3.3 V Zero Delay Buffer
Document Number: 38-07140
Submission
Revision
ECN
Description of Change
Date
**
110249
111117
10/19/01
03/01/02
Change from Spec number: 38-00530 to 38-07140
*A
Added t6B row to the Switching Characteristics Table; also added the letter “A” to the t6Arow
Corrected the table title from CY2305SC-IH and CY2309SC-IH to CY2305SI-IH and
CY2309SI-IH
*B
117625
10/21/02
Added eight-pin TSSOP packages (CY2305ZC-1 and CY2305ZC-1T) to the ordering infor-
mation table.
Added the Tape and Reel option to all the existing packages:
CY2305SC-1T, CY2305SI-1T, CY2305SC-1HT, CY2305SI-1HT, CY2305ZC-1T,
CY2309SC-1T, CY2309SI-1T, CY2309SC-1HT, CY2309SI-1HT, CY2309ZC-1HT,
CY2309ZI-1HT
*C
*D
*E
*F
*G
*H
121828
131503
214083
291099
390582
2542461
12/14/02
12/12/03
Power up requirements added to Operating Conditions information
Added Lead-free for all the devices in the ordering information table
See ECN Added a Lead-free with the new coding for all SOIC devices in the ordering information table
See ECN Added TSSOP Lead-free devices
See ECN Added typical values for jitter
07/23/08
Updated template. Added Note “Not recommended for new designs.”
Added part number CY2305ESXC-1, CY2305ESXC-1T, CY2305ESXI-1, CY2305ESXI-1T,
CY2305ESXC-1H, CY2305ESXC-1HT, CY2305ESXI-1H, CY2305ESXI-1HT,
CY2309ESXC-1, CY2309ESXC-1T, CY2309ESXI-1, CY2309ESXI-1T, CY2309ESXC-1H,
CY2309ESXC-1HT, CY2309ESXI-1H, CY2309ESXI-1HT, CY2309EZXC-1H,
CY2309EZXC-1HT, CY2309EZXI-1H, and CY2309EZXI-1HT in ordering information table.
Removed part number CY2305SZC-1, CY2305SZC-1T, CY2305SZI-1, CY2305SZI-1T,
CY2305SZC-1H, CY2305SZC-1HT, CY2305SZI-1H, CY2305SZI-1HT, CY2309SZC-1,
CY2309SZC-1T, CY2309SZI-1, CY2309SZI-1T, CY2309SZC-1H, CY2309SZC-1HT,
CY2309SZI-1H, CY2309SZI-1HT, CY2309ZZC-1H, CY2309ZZC-1HT, CY2309ZI-1H,
CY2309ZI-1HT, CY2309ZZI-1H, and CY2309ZZI-1HT in Ordering Information table.
Changed Lead-Free to Pb-Free.
*I
2565153
09/18/08
Removed part number CY2305ESXC-1, CY2305ESXC-1T, CY2305ESXI-1,
CY2305ESXI-1T, CY2305ESXC-1H, CY2305ESXC-1HT, CY2305ESXI-1H,
CY2305ESXI-1HT, CY2309ESXC-1, CY2309ESXC-1T, CY2309ESXI-1, CY2309ESXI-1T,
CY2309ESXC-1H, CY2309ESXC-1HT, CY2309ESXI-1H, CY2309ESXI-1HT,
CY2309EZXC-1H, CY2309EZXC-1HT, CY2309EZXI-1H, and CY2309EZXI-1HT in
ordering information table.
Removed note references to note 10 in Pb-Free sections of ordering information table.
Changed IDD (PD mode) from 12.0 to 25.0 μA for commercial temperature devices
Deleted Duty Cycle parameters for Fout < 50 MHz commercial and industrial devices.
*J
2673353
2904641
03/13/09
04/05/10
Reverted IDD (PD mode) and Duty Cycle parameters back to the values in revision *H:
Changed IDD (PD mode) from 25 to 12 μA for commercial devices.
Added Duty Cycle parameters for Fout < 50 MHz for commercial and industrial devices.
*K
Updated Ordering Information:
Removed parts CY2305SI-1, CY2305SI-1T, CY2309SI-1, CY2309SI-1H, CY2309SI-1HT,
CY2309SI-1T.
Updated Package Drawing and Dimensions.
*L
3047136
3146330
10/04/2010 Added Ordering Code Definitions under Ordering Information.
Updated Package Drawing and Dimensions.
Added Acronyms and Units of Measure.
*M
01/18/2011 Added “Not recommended for new designs” statement to Features on page 1. Added ‘not
recommended for new designs’ footnote to all parts in the ordering information table.
Document Number: 38-07140 Rev. *Y
Page 23 of 25
CY2305
CY2309
Document History Page (continued)
Document Title: CY2305/CY2309, Low Cost 3.3 V Zero Delay Buffer
Document Number: 38-07140
Submission
Revision
ECN
Description of Change
Date
*N
3241160
05/09/2011 Added Footnote 9 on page 6 (CDT 97105).
Removed first bullet point “Not recommended for new designs. The CY2305C and CY2309C
are form, fit, function compatible devices with improved specifications.” from Features
section. (CDT 99798).
Removed Footnote 20 and all its references from document. (CDT 99798).
*O
*P
3400613
3859773
10/10/2011 Added Footnote 19 and its reference to all PLL lock time parameters throughout the
document.
Added Figure 10 for Stop Time Illustration.
01/07/2013 Updated Ordering Information (Updated part numbers).
Updated Ordering Information (Updated part numbers).
Updated Package Drawing and Dimensions:
spec 51-85068 – Changed revision from *D to *E.
*Q
*R
3997602
4124780
05/11/2013 Updated Package Drawing and Dimensions:
spec 51-85066 – Changed revision from *E to *F.
Added Errata.
10/24/2013 Updated to new template.
Completing Sunset Review.
*S
*T
4307827
4578443
03/13/2014 Updated Errata.
11/25/2014 Updated Functional Description:
Added “For a complete list of related documentation, click here.” at the end.
Updated Ordering Information (Updated part numbers).
Updated Ordering Information (Updated part numbers).
*U
*V
5206812
5242499
04/05/2016 Updated Zero Delay and Skew Control:
Updated description.
Updated Package Drawing and Dimensions:
spec 51-85066 – Changed revision from *F to *H.
Updated to new template.
04/26/2016 Updated Electrical Characteristics:
Updated details in “Test Conditions” column corresponding to VOL and VOH parameters.
Updated Operating Conditions:
Added tPU parameter and its details.
Updated Electrical Characteristics:
Updated details in “Test Conditions” column corresponding to VOL and VOH parameters.
Added Thermal Resistance.
*W
5516682
11/10/2016 Updated to new template.
Completing Sunset Review.
*X
*Y
5708778
6897833
04/27/2017 Updated Cypress Logo and Copyright.
06/12/2020 Updated Package Drawing and Dimensions:
spec 51-85066 – Changed revision from *H to *I.
spec 51-85068 – Changed revision from *E to *F.
Updated to template.
Document Number: 38-07140 Rev. *Y
Page 24 of 25
CY2305
CY2309
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
®
Products
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Arm® Cortex® Microcontrollers
cypress.com/arm
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cypress.com/interface
cypress.com/iot
PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP | PSoC 6 MCU
Automotive
Cypress Developer Community
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Interface
Community | Code Examples | Projects | Video | Blogs |
Training | Components
Internet of Things
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Technical Support
cypress.com/memory
cypress.com/mcu
cypress.com/support
Microcontrollers
PSoC
cypress.com/psoc
cypress.com/pmic
cypress.com/touch
cypress.com/usb
Power Management ICs
Touch Sensing
USB Controllers
Wireless Connectivity
cypress.com/wireless
© Cypress Semiconductor Corporation, 2001-2020. This document is the property of Cypress Semiconductor Corporation and its subsidiaries (“Cypress”). This document, including any software or
firmware included or referenced in this document (“Software”), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries worldwide. Cypress reserves
all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other intellectual property rights. If
the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress hereby grants you a personal,
non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to modify and reproduce the Software
solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users (either directly or indirectly through
resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as provided by Cypress, unmodified)
to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation of the Software is prohibited.
TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE
OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. No computing
device can be absolutely secure. Therefore, despite security measures implemented in Cypress hardware or software products, Cypress shall have no liability arising out of any security breach, such
as unauthorized access to or use of a Cypress product. CYPRESS DOES NOT REPRESENT, WARRANT, OR GUARANTEE THAT CYPRESS PRODUCTS, OR SYSTEMS CREATED USING
CYPRESS PRODUCTS, WILLBE FREE FROM CORRUPTION,ATTACK, VIRUSES, INTERFERENCE, HACKING, DATALOSS OR THEFT, OR OTHER SECURITY INTRUSION (collectively, “Security
Breach”). Cypress disclaims any liability relating to any Security Breach, and you shall and hereby do release Cypress from any claim, damage, or other liability arising from any Security Breach. In
addition, the products described in these materials may contain design defects or errors known as errata which may cause the product to deviate from published specifications. To the extent permitted
by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any product or
circuit described in this document.Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is the responsibility
of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. “High-Risk Device” means any
device or system whose failure could cause personal injury, death, or property damage. Examples of High-Risk Devices are weapons, nuclear installations, surgical implants, and other medical devices.
“Critical Component” means any component of a High-Risk Device whose failure to perform can be reasonably expected to cause, directly or indirectly, the failure of the High-Risk Device, or to affect
its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim, damage, or other liability arising from any use of a Cypress product
as a Critical Component in a High-Risk Device. You shall indemnify and hold Cypress, its directors, officers, employees, agents, affiliates, distributors, and assigns harmless from and against all claims,
costs, damages, and expenses, arising out of any claim, including claims for product liability, personal injury or death, or property damage arising from any use of a Cypress product as a Critical
Component in a High-Risk Device. Cypress products are not intended or authorized for use as a Critical Component in any High-Risk Device except to the limited extent that (i) Cypress's published
data sheet for the product explicitly states Cypress has qualified the product for use in a specific High-Risk Device, or (ii) Cypress has given you advance written authorization to use the product as a
Critical Component in the specific High-Risk Device and you have signed a separate indemnification agreement.
Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in
the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
Document Number: 38-07140 Rev. *Y
Revised June 12, 2020
Page 25 of 25
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