CY2548QIT [INFINEON]
9-Output Low-Voltage Programmable Spread Spectrum Clock Generator;
| 型号： | CY2548QIT |
| 厂家： | 
Infineon |
| 描述： | 9-Output Low-Voltage Programmable Spread Spectrum Clock Generator |
| 文件： | 总17页 (文件大小：487K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY2544/CY2546/CY2548
Quad-PLL Programmable Clock Generator
with Spread Spectrum
Quad-PLL Programmable Clock Generator with Spread Spectrum
■ Glitch free outputs while frequency switching
■ 24-pin QFN package
Features
■ Four fully-integrated phase-locked loops (PLLs)
■ Commercial and Industrial temperature ranges
■ Input frequency range
■ One-time programmability
For programming support, contact Cypress technical support
or send an e-mail to clocks@cypress.com
❐ External crystal: 8 to 48 MHz for CY2544 and CY2546
❐ External reference: 8 to 166 MHz clock
■ Reference clock input voltage range
❐ 2.5 V, 3.0 V, and 3.3 V for CY2548
❐ 1.8 V for CY2544 and CY2546
Benefits
■ Multiple high-performance PLLs allow synthesis of unrelated
frequencies
■ Wide operating output frequency range
❐ 3 to 166 MHz
■ Nonvolatile programming for personalization of PLL
frequencies, spread spectrum characteristics, drive strength,
crystal load capacitance, and output frequencies
■ Programmable spread spectrum with center and down spread
option and Lexmark and Linear modulation profiles
■ VDD supply voltage options:
❐ 2.5 V, 3.0 V, and 3.3 V for CY2544 and CY2548
❐ 1.8 V for CY2546
■ Application specific programmable EMI reduction using spread
spectrum for clocks
■ Programmable PLLs for system frequency margin tests
■ Selectable output clock voltages:
❐ 1.8 V, 2.5 V, 3.0 V, and 3.3 V for CY2544 and CY2548
❐ 1.8 V for CY2546
■ Meets critical timing requirements in complex system designs
■ Suitability for PC, consumer, portable, and networking
applications
■ Frequency select feature with option to select eight different
frequencies over nine clock outputs
■ Capable of Zero PPM frequency synthesis error
■ Power down, output enable, and SS ON/OFF controls
■ Low jitter, high accuracy outputs
■ Uninterrupted system operation during clock frequency switch
■ Application compatibility in standard and low-power systems
■ Ability tosynthesizenonstandard frequencies with Fractional-N
capability
Functional Description
For a complete list of related documentation, click here.
■ Up to nine clock outputs with programmable drive strength
Logic Block Diagram
CLKIN
CLK1
Crossbar
XIN/
EXCLKIN
Bank
1
CLK2
Switch
OSC
Output
PLL1
PLL2
CLK3
CLK4
CLK5
CLK6
CLK7
CLK8
CLK9
XOUT
Dividers
and
Bank
2
MUX
and
Drive
FS 0
FS 1
FS 2
Strength
Control
Bank
3
Control
Logic
PLL3
(SS)
PLL4
(SS)
PD#/OE
SSON
Cypress Semiconductor Corporation
Document Number: 001-12563 Rev. *M
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised October 31, 2017
CY2544/CY2546/CY2548
Contents
Device Selection Guide ....................................................3
Pinout ................................................................................3
Pin Definitions ..................................................................3
Pinout ................................................................................4
Pin Definitions ..................................................................5
Functional Overview ........................................................5
Four Configurable PLLs ..............................................5
Input Reference Clocks ...............................................5
Multiple Power Supplies ..............................................6
Output Bank Settings ..................................................6
Output Source Selection .............................................6
Spread Spectrum Control ............................................6
Frequency Select ........................................................6
Glitch-Free Frequency Switch .....................................6
PD#/OE Mode .............................................................6
Output Drive Strength ..................................................6
Generic Configuration and Custom Frequency ...........6
Output Driver Supply
DC Electrical Specifications ............................................7
AC Electrical Specifications ............................................9
Configuration Example for C-C Jitter ............................. 9
Recommended Crystal Specification .............................9
Recommended Crystal Specification ...........................10
Test and Measurement Setup ........................................10
Voltage and Timing Definitions .....................................10
Ordering Information ......................................................11
Possible Configurations .............................................11
Ordering Code Definitions .........................................12
Package Drawing and Dimensions ...............................13
Acronyms ........................................................................14
Document Conventions .................................................14
Units of Measure .......................................................14
Document History Page .................................................15
Sales, Solutions, and Legal Information ......................17
Worldwide Sales and Design Support .......................17
Products ....................................................................17
PSoC® Solutions ......................................................17
Cypress Developer Community .................................17
Technical Support .....................................................17
and Multi-Function Input Restriction ...................................6
Absolute Maximum Conditions .......................................7
Recommended Operating Conditions ............................7
Document Number: 001-12563 Rev. *M
Page 2 of 17
CY2544/CY2546/CY2548
Device Selection Guide
Device
CY2544
CY2546
CY2548
Crystal Input
EXCKLKIN Input
1.8 V LVCMOS
1.8 V LVCMOS
CLKIN Input
2.5 V, 3.0 V, 3.3 V LVCMOS 2.5 V, 3.0 V, 3.3 V 1.8 V, 2.5 V, 3.0 V, 3.3 V
1.8 V LVCMOS 1.8 V 1.8 V
VDD
VDD_CLK_BX
Yes
Yes
No
2.5 V, 3.0 V, 3.3 V LVCMOS 2.5 V, 3.0 V, 3.3 V LVCMOS 2.5 V, 3.0 V, 3.3 V 1.8 V, 2.5 V, 3.0 V, 3.3 V
Pinout
Figure 1. 24-pin QFN pinout
CY2544 / CY2548
24
23
22
21
20
19
24
23
22
21
20
19
1
2
3
4
5
6
18
17
16
15
1
2
3
4
5
6
18
17
16
15
14
13
GND
GND
GND
GND
CLK1
CLK8
CLK1
CLK8
CY2544
CY2548
VDD_CLK_B3
VDD_CLK_B1
PD#OE
VDD_CLK_B3
VDD_CLK_B1
PD#OE
24LD QFN
24LD QFN
CLK7/SSON
CLK7/SSON
14 VDD_CLK_B2
NC
VDD_CLK_B2
NC
13
CLK2
CLK6
CLK2
CLK6
7
8
9
10
11
12
7
8
9
10
11
12
Pin Definitions
CY2544/CY2548 (VDD = 2.5 V, 3.0 V or 3.3 V Supply)
Pin Number
Name
GND
I/O
Description
1
2
Power
Output
Power supply ground
CLK1
Programmable clock output with spread spectrum. Output voltage depends on
VDD_CLK_B1 voltage
3
4
5
6
VDD_CLK_B1
PD#/OE
NC
Power
Input
NC
Power supply for Bank1, (CLK1, CLK2, CLK3) Outputs: 1.8 V/2.5 V/3.0 V/3.3 V
Multifunction programmable pin. Output enable or power-down mode
No Connect
CLK2
Output
Programmable clock output with spread spectrum. Output voltage depends on
VDD_CLK_B1 voltage
7
8
GND
Power
Power supply ground
CLK3/FS0
Output/input Multifunction programmable pin. Programmable clock output with no spread spectrum
or frequency select pin. Output voltage of CLK3 depends on VDD_CLK_B1 voltage
9
OE/FS1
Input
Multifunction programmable pin. Output enable or frequency select pin
10
CLK4/FS2
Output/input Multifunction programmable pin. Programmable clock output with no spread spectrum
or frequency select input pin. Output voltage of CLK4 depends on VDD_CLK_B2 voltage
Document Number: 001-12563 Rev. *M
Page 3 of 17
CY2544/CY2546/CY2548
Pin Definitions (continued)
CY2544/CY2548 (VDD = 2.5 V, 3.0 V or 3.3 V Supply)
Pin Number
Name
I/O
Description
Programmable clock output with no spread spectrum. Output voltage depends on
DD_CLK_B2 voltage
11
CLK5
Output
V
12
13
GND
Power
Output
Power supply ground
CLK6
Programmable clock output with spread spectrum. Output voltage depends on
VDD_CLK_B2 voltage
14
15
VDD_CLK_B2
Power
Power supply for Bank2, (CLK4, CLK5, CLK6) Outputs: 1.8 V/2.5 V/3.0 V/3.3 V
CLK7/SSON Output/input Multifunction programmable pin. Programmable clock output with spread spectrum or
spread spectrum ON/OFF control input pin. Output voltage of CLK7 depends on Bank3
voltage
16
17
VDD_CLK_B3
CLK8
Power
Output
Power supply for Bank3, (CLK7, CLK8, CLK9) Outputs: 1.8 V/2.5 V/3.0 V/3.3 V
Programmable output clock with spread spectrum. Output voltage depends on
Bank3 voltage
18
19
20
GND
GND
CLK9
Power
Power
Output
Power supply ground
Power supply ground
Programmable clock output with spread spectrum. Output voltage depends on
VDD_CLK_B3 voltage
21
CLKIN
Input
2.5 V/3.0 V/3.3 V reference clock input. The signal level of CLKIN input must track VDD
power supply on pin 22.
22
23
VDD
XOUT
Power
Output
Output
Input
Power supply. 2.5 V/3.0 V/3.3 V
Crystal output for CY2544
DNU
Do not use this pin for CY2548
24
XIN/EXCLKIN
EXCLKIN
Crystal input or 1.8 V external clock input for CY2544
2.5 V/3.0 V/3.3 V external clock input for CY2548
Input
Pinout
Figure 2. 24-pin QFN pinout
CY2546
24
23
22
21
20
19
1
2
3
4
5
6
18
17
16
15
GND
GND
CLK1
CLK8
VDD_CLK_B3
VDD_CLK_B1
PD#OE
CY2546
24LD QFN
CLK7/SSON
14 VDD_CLK_B2
VDD
13
CLK2
CLK6
7
8
9
10
11
12
Document Number: 001-12563 Rev. *M
Page 4 of 17
CY2544/CY2546/CY2548
Pin Definitions
CY2546 (VDD = 1.8 V Supply)
Pin Number
Name
GND
I/O
Description
1
2
Power
Output
Power supply ground
CLK1
Programmable clock output with spread spectrum. Output voltage depends on
VDD_CLK_B1 voltage
3
4
5
6
VDD_CLK_B1
PD#/OE
VDD
Power
Input
Power supply for Bank1, (CLK1, CLK2, CLK3) Outputs. 1.8 V
Multifunction programmable pin. Output enable or power down mode
Power supply. 1.8 V
Power
Output
CLK2
Programmable clock output with spread spectrum. Output voltage depends on
VDD_CLK_B1 voltage
7
8
GND
Power
Power supply ground
CLK3/FS0 Output/Input Multifunction programmable pin. Programmable clock output with no spread spectrum
or frequency select input pin. Output voltage of CLK3 depends on VDD_CLK_B1 voltage
9
OE/FS1
Input
Multifunction programmable pin. Output enable or frequency select pin
10
CLK4/FS2 Output/Input Multifunction programmable pin. Programmable clock output with no spread spectrum
or frequency select input pin. Output voltage of CLK4 depends on VDD_CLK_B2 voltage
11
CLK5
Output
Programmable clock output with no spread spectrum. Output voltage depends on
VDD_CLK_B2 voltage
12
13
GND
Power
Output
Power supply ground
CLK6
Programmable clock output with spread spectrum. Output voltage depends on
VDD_CLK_B2 voltage
14
15
VDD_CLK_B2
Power
Power supply for Bank2, (CLK4, CLK5, CLK6) Outputs. 1.8 V
CLK7/SSON Output/input Multifunction programmable pin. Programmable clock output with spread spectrum or
spread spectrum ON/OFF control input pin. Output voltage of CLK7 depends on
VDD_CLK_B3 voltage
16
17
VDD_CLK_B3
CLK8
Power
Output
Power supply for Bank3, (CLK7, CLK8, CLK9) Outputs. 1.8 V
Programmable clock output with spread spectrum. Output voltage depends on
VDD_CLK_B3 voltage
18
19
20
GND
GND
CLK9
Power
Power
Output
Power supply ground
Power supply ground
Programmable clock output with spread spectrum. Output voltage depends on
VDD_CLK_B3 voltage
21
22
23
24
CLKIN
VDD
Input
Power
Output
Input
External 1.8 V low voltage reference clock input
Power supply. 1.8 V
XOUT
Crystal output
XIN/EXCLKIN
Crystal input or 1.8 V external clock input
Input Reference Clocks
Functional Overview
The input to the CY2544, CY2548 and CY2546 can be either a
crystal or a clock signal. The input frequency range for crystal
Four Configurable PLLs
(XIN) is 8 MHz to 48 MHz and that for external reference clock
(EXCLKIN) is 8 MHz to 166 MHz. The voltage range for the
reference clock input of CY2548 is 2.5 V/3.0 V/3.3 V while that
for CY2544 and CY2546 is 1.8 V. This gives user an option for
this device to be compatible for different input clock voltage
levels in the system.
The CY2544, CY2548, and CY2546 have four programmable
PLLs that can be used to generate output frequencies ranging
from 3 to 166 MHz. The advantage of having four PLLs is that a
single device generates up to four independent frequencies from
a single crystal.
Document Number: 001-12563 Rev. *M
Page 5 of 17
CY2544/CY2546/CY2548
There is provision for a secondary reference clock input, CLKIN
with applied frequency range of 8 MHz to 166 MHz. When CLKIN
signal at pin 21 is used as a reference input to the PLL, a valid
signal at EXCLKIN (as specified in the AC and DC Electrical
Specification table) must be present for the devices to operate
properly.
PD#/OE Mode
PD#/OE (Pin 4) can be programmed to operate as either power
down (PD#) or output enable (OE) mode. PD# is a low-true input.
If activated it shuts off the entire chip, resulting in minimum power
consumption for the device. Setting this signal high brings the
device in the operational mode with default register settings.
Multiple Power Supplies
When this pin is programmed as Output Enable (OE), clock
outputs can be enabled or disabled using OE (pin 4). Individual
clock outputs can be programmed to be sensitive to this OE pin.
These devices are designed to operate at internal supply voltage
of 1.8 V. In the case of the high voltage part (CY2544/CY2548),
an internal regulator is used to generate 1.8 V from the
2.5 V/3.0 V/3.3 V VDD supply voltage at pin 22. For the low
voltage part (CY2546), this internal regulator is bypassed and
1.8 V at VDD pin 22 is directly used.
Output Drive Strength
The DC drive strength of the individual clock output can be
programmed for different values. Table 1 shows the typical rise
and fall times for different drive strength settings.
Output Bank Settings
Table 1. Output Drive Strength
There are nine clock outputs grouped in three output driver
banks. The Bank 1, Bank 2, and Bank 3 correspond to (CLK1,
CLK2, CLK3), (CLK4, CLK5, CLK6), and (CLK7, CLK8, CLK9)
respectively. Separate power supplies are used for each of these
banks and they can be any of 1.8 V, 2.5 V, 3.0 V, or 3.3 V for
CY2544/CY2548 and 1.8 V for CY2546 giving user multiple
choice of output clock voltage levels.
Rise/Fall Time (ns)
Output Drive Strength
(Typical Value)
Low
Mid Low
Mid High
High
6.8
3.4
2.0
1.0
Output Source Selection
These devices have programmable input sources for each of its
nine clock outputs (CLK1–9). There are six available clock
sources for these outputs. These clock sources are:
XIN/EXCLKIN, CLKIN, PLL1, PLL2, PLL3, or PLL4. Output clock
source selection is done using four out of six crossbar switch.
Thus, any one of these six available clock sources can be
arbitrarily selected for the clock outputs. This gives user a
flexibility to have up to four independent clock outputs.
Generic Configuration and Custom Frequency
There is a generic set of output frequencies available from the
factory that can be used for the device evaluation purposes. The
devices, CY2544, CY2548 and CY2546 can be custom
programmed to any desired frequencies and listed features. For
customer specific programming, contact your local Cypress Field
application engineer (FAE) or sales representative.
Spread Spectrum Control
Output Driver Supply and Multi-Function Input
Restriction
Two of the four PLLs (PLL3 and PLL4) have spread spectrum
capability for EMI reduction in the system. The device uses a
Cypress proprietary PLL and spread spectrum clock (SSC)
technology to synthesize and modulate the frequency of the PLL.
The spread spectrum feature can be turned on or off using a
multifunction control pin (CLK7/SSON). It can be programmed to
either center spread range from ±0.125% to ±2.50% or down
spread range from –0.25% to –5.0% with Lexmark or Linear
profile.
There are three programmable Output/Input function pins, for
CLK3/FS0, CLK4/FS2, and CLK7/SSON. These are configu-
rable as clock output or select input or spread spectrum ON/OFF
control input pin.
■ When configured as Output, the driver supply voltage is defined
by VDD_CLK_Bx and can be individually used with 1.8 V, 2.5 V,
3.0 V, or 3.3 V power supply apart from the VDD supply.
■ When configured as Input, the input threshold level is defined
by VDD supply while the protection diode is connected to the
respective VDD_CLK_Bx power supply. Therefore, if VDD_CLK_Bx
is less than VDD – 0.5 V, a large leakage current would flow
from the input pin to the VDD_CLK_Bx supply. The device does
not permit this condition; it is required that the power supply for
the bank (VDD_CLK_Bx) is more than VDD – 0.5 V.
Frequency Select
There are three multifunction frequency select pins (FS0, FS1
and FS2) that provide an option to select eight different sets of
frequencies among each of the four PLLs. Each output has
programmable output divider options.
Glitch-Free Frequency Switch
Example: In CY2544/CY2548, if VDD_CLK_B1 = 1.8 V, CLK3/FS0
is configured as FS0, and VDD = 3.3 V, there will be a leakage
current from FS0 high to VDD_CLK_B1. The multi-function pin
should only be used as clock output if the VDD_CLK_Bx is less than
When the frequency select pin (FS) is used to switch frequency,
the outputs are glitch-free provided frequency is switched using
output dividers. This feature enables uninterrupted system
operation while clock frequency is being switched.
VDD – 0.5 V. In other words, when these multi-function program-
mable pins are configured as input, the power supply for the bank
(VDD_CLK_Bx) should be more than VDD – 0.5 V.
Document Number: 001-12563 Rev. *M
Page 6 of 17
CY2544/CY2546/CY2548
Absolute Maximum Conditions
Parameter
VDD
Description
Conditions
Min
Max
Unit
Supply voltage for
CY2544/CY2548
–0.5
4.5
V
VDD
Supply voltage for CY2546
Output bank supply voltage
–0.5
–0.5
–0.5
2.6
4.5
V
V
V
VDD_CLK_BX
VIN
Input voltage for
CY2544/CY2548
Relative to VSS
VDD + 0.5
VIN
Input voltage for CY2546
Temperature, storage
Relative to VSS
Non functional
–0.5
–65
2.2
+150
–
V
°C
V
TS
ESDHBM
ESD protection (Human body
model)
JEDEC EIA/JESD22-A114-E
2000
UL-94
MSL
Flammability rating
V-0 at 1/8 in.
–
10
ppm
Moisture sensitivity level
3
Recommended Operating Conditions
Parameter
VDD
Description
Min
2.25
1.65
1.43
1.43
0
Typ
–
Max
3.60
1.95
3.60
1.98
+70
+85
15
Unit
V
VDD operating voltage for CY2544/CY2548
VDD operating voltage for CY2546
VDD
1.8
–
V
VDD_CLK_BX
Output driver voltage for Bank 1, 2 and 3 for CY2544/CY2548
Output driver voltage for Bank 1, 2 and 3 for CY2546
Commercial ambient temperature
V
–
V
TAC
TAI
–
°C
°C
pF
ms
–40
–
--
Industrial ambient temperature
CLOAD
tPU
Maximum load capacitance
–
Power up time for all VDD to reach minimum specified voltage (power
ramps must be monotonic)
0.05
–
500
DC Electrical Specifications
Parameter
Description
Output low voltage
Conditions
Min
Typ
Max
Unit
V
IOL = 2 mA, drive strength = [00]
IOL = 3 mA, drive strength = [01]
IOL = 7 mA, drive strength = [10]
IOL = 12 mA, drive strength = [11]
–
–
0.4
V
OL
V
Output high voltage
IOH = –2 mA, drive strength = [00] VDD_CLK_BX – 0.4
IOH = –3 mA, drive strength = [01]
–
–
V
OH
IOH = –7 mA, drive strength = [10]
I
OH = –12 mA, drive strength = [11]
V
V
Input low voltage of PD#/OE,
FS0, FS1, FS2 and SSON
–
–
–
–
–
0.2 × VDD
0.2 × VDD
V
V
IL1
Input low voltage of CLKIN for
CY2544/CY2548
–
IL2
Document Number: 001-12563 Rev. *M
Page 7 of 17
CY2544/CY2546/CY2548
DC Electrical Specifications (continued)
Parameter
Description
Conditions
Min
Typ
Max
Unit
V
V
V
V
V
V
V
V
Input low voltage of EXCLKIN for –
CY2544
–
–
0.3
V
IL3
Input low voltage of EXCLKIN for –
CY2548
–
–
–
0.2 × VDD
V
V
IL4
IL5
IH1
IH2
IH3
IH4
IH5
Input low voltage of CLKIN,
EXCLKIN for CY2546
–
–
–
–
0.2 × VDD
Input high voltage of PD#/OE,
FS0, FS1, FS2 and SSON
0.8 × VDD
–
–
–
V
Input high voltage of CLKIN for
CY2544/CY2548
0.8 × VDD
–
V
InputhighvoltageofEXCLKINfor –
CY2544
1.6
–
2.2
–
V
InputhighvoltageofEXCLKINfor –
CY2548
0.8 × VDD
–
V
Input high voltage of CLKIN,
EXCLKIN for CY2546
–
0.8 × VDD
–
–
V
IIL1
Input low current of PD#/OE and VIL = 0 V
FS1
–
–
–
10
10
10
36
250
µA
µA
µA
µA
k
IIH1
IIL2
IIH2
RDN
Input high current of PD#/OE and VIH = VDD
FS1
–
Input low current of SSON, FS0, VIL = 0 V
–
–
and FS2
(Internal pull dn = 160k typ)
Input high current of SSON, FS0, VIH = VDD
14
100
–
and FS2
(Internal pull dn = 160k typ)
Pull down resistor of SSON, FS0, Clock outputs in off-state by setting
FS2 and clocks (CLK1–CLK9) in PD# = Low
off-state
160
[1, 2]
I
Supply current for CY2546
PD# = High, No load
PD# = High, No load
–
–
20
22
–
–
mA
mA
DD
Supply current for
CY2544/CY2548
[1]
I
Standby current
PD# = Low
–
–
3
–
–
7
µA
pF
DDS
[1]
C
Input capacitance
SSON, CLKIN, PD#/OE, FS0, FS1,
and FS2 pins
IN
Notes
1. Guaranteed by design but not 100% tested.
2. Configuration dependent.
Document Number: 001-12563 Rev. *M
Page 8 of 17
CY2544/CY2546/CY2548
AC Electrical Specifications
Parameter
FIN (crystal)
FIN (clock)
Description
Conditions
Min
8
Typ
–
Max
48
Unit
MHz
MHz
Crystal frequency, XIN
–
Input clock frequency (CLKIN or –
EXCLKIN)
8
–
166
CY2544/CY2548 (VDD_CLK_Bx = 2.5 V, 3.0 V,
3.3 V) and CY2546
3
–
166
MHz
FCLK
Output clock frequency
CY2544/CY2548 (VDD_CLK_Bx = 1.8 V)
3
–
50
55
MHz
%
DC1
DC2
Output duty cycle, All clocks
except ref out
Duty cycle is defined in Figure 4; t1/t2,
measured at 50% of VDD_CLK_BX
45
50
Ref Out clock duty cycle
Output rise/fall Time
Ref In Min 45%, Max 55%
40
–
–
60
–
%
[3]
TRF1
Measured from 20% to 80% of VDD_CLK_BX
,
6.8
ns
as shown in Figure 5, CLOAD = 15 pF, Drive
strength [00]
[3]
TRF2
Output rise/fall time
Output rise/fall time
Output rise/fall time
Measured from 20% to 80% of VDD_CLK_BX
as shown in Figure 5, CLOAD = 15 pF, Drive
strength [01]
,
–
–
–
3.4
2.0
1.0
–
–
–
ns
ns
ns
[3]
TRF3
Measured from 20% to 80% of VDD_CLK_BX,
as shown in Figure 5, CLOAD = 15 pF, Drive
strength [10]
[3]
TRF4
Measured from 20% to 80% of VDD_CLK_BX,
as shown in Figure 5, CLOAD = 15 pF, Drive
strength [11]
[3,4]
TCCJ
Cycle-to-cycle Jitter (peak)
PLL lock time
Configurationdependent.SeeConfiguration
Example for C-C Jitter
–
–
150
1
–
3
ps
[3]
TLOCK
Measured from 90% of the applied power
supply level
ms
Configuration Example for C-C Jitter
CLK1 Output
CLK2 Output
CLK3 Output
CLK4 Output
Freq. C-CJitter
CLK5 Output
Ref. Freq.
(MHz)
Freq.
(MHz)
C-CJitter
Typ (ps)
Freq.
(MHz)
C-CJitter
Typ (ps)
Freq.
(MHz)
C-C Jitter
Typ (ps)
Freq.
(MHz)
C-CJitter
Typ (ps)
(MHz)
74.25
27
Typ (ps)
14.3181
19.2
27
8.0
134
99
166
166
27
103
94
48
92
91
81
Not Used
74.25
48
8
110
48
75
67
109
123
166
166
103
137
74.25
166
97
Not Used
48
48
93
27
138
8
103
Recommended Crystal Specification
For SMD Package
Parameter
Description
Range 1
8–14
135
Range 2
Range 3 Unit
F
Crystal frequency
14–28
50
28–48
30
MHz
IN
R1
Maximum motional resistance (ESR)
Parallel load capacitance (see Note 3 below)
Maximum crystal drive level
CL
8–18
300
8–14
300
8–12
300
pF
DL(max)
µW
Notes
3. Guaranteed by design but not 100% tested.
4. Configuration dependent.
Document Number: 001-12563 Rev. *M
Page 9 of 17
CY2544/CY2546/CY2548
Recommended Crystal Specification
For Thru-Hole Package
Parameter [5]
Description
Range 1
8–14
90
Range 2
14–24
50
Range 3 Unit
F
Crystal frequency
24–32
30
MHz
IN
R1
Maximum motional resistance (ESR)
Parallel load capacitance (see Note 6 below)
Maximum crystal drive level
CL
8–18
1000
8–12
1000
8–12
1000
pF
DL(max)
µW
Test and Measurement Setup
Figure 3. Test and Measurement Setup
VDD
Outputs
CLOAD
0.1 F
DUT
GND
Voltage and Timing Definitions
Figure 4. Duty Cycle Definition
t1
t2
VDD_CLK_BX
50% of V DD_CLK_BX
0V
Clock
Output
Figure 5. Rise Time = TRF, Fall Time = TRF
TRF
TRF
V DD_CLK_BX
80% of V
DD_CLK_BX
20% of V
0V
DD_CLK_BX
Clock
Output
Notes
5. CY2544, CY2548 and CY2546 have internal crystal load capacitance (CL) adjustment feature.
6. Guaranteed by design but not 100% tested.
Document Number: 001-12563 Rev. *M
Page 10 of 17
CY2544/CY2546/CY2548
Ordering Information
Part Number
Pb-free
Type [7]
Package
Supply Voltage
Operating Range
CY2544QFC
Field Programmable
24-pin QFN
2.5 V, 3.0 V or 3.3 V
2.5 V, 3.0 V or 3.3 V
2.5 V, 3.0 V or 3.3 V
2.5 V, 3.0 V or 3.3 V
2.5 V, 3.0 V or 3.3 V
2.5 V, 3.0 V or 3.3 V
Commercial, 0 °C to 70 °C
Commercial, 0 °C to 70 °C
Industrial, –40 °C to +85 °C
Industrial, –40 °C to +85 °C
Industrial, –40 °C to +85 °C
Industrial, –40 °C to +85 °C
CY2544QFCT Field Programmable
CY2544QFI Field Programmable
CY2544QFIT Field Programmable
24-pin QFN – Tape and Reel
24-pin QFN
24-pin QFN – Tape and Reel
24-pin QFN
CY2548QI
Field Programmable
Field Programmable
CY2548QIT
Programmer
24-pin QFN – Tape and Reel
CY3675-CLKMAKER1
CY3675-QFN24A
Programming kit
Socket adapter board, for programming CY2544 and CY2548[8]
Some product offerings are factory programmed customer specific devices with customized part numbers.
The Possible Configurations table shows the available device types, but not complete part numbers. Contact your local Cypress FAE
or sales representative for more information.
Possible Configurations
Part Number [9]
Type [7]
Package
Supply Voltage
Operating Range
Pb-free
CY2544QCxxx
Factory Programmed 24-pin QFN
2.5 V, 3.0 V or 3.3 V
Commercial, 0 °C to 70 °C
Commercial, 0 °C to 70 °C
Commercial, 0 °C to 70 °C
Commercial, 0 °C to 70 °C
Commercial, 0 °C to 70 °C
Commercial, 0 °C to 70 °C
Industrial, –40 °C to +85 °C
Industrial, –40 °C to +85 °C
Industrial, –40 °C to +85 °C
Industrial, –40 °C to +85 °C
Industrial, –40 °C to +85 °C
Industrial, –40 °C to +85 °C
CY2544QCxxxT Factory Programmed 24-pin QFN – Tape and Reel 2.5 V, 3.0 V or 3.3 V
CY2548QCxxx Factory Programmed 24-pin QFN 2.5 V, 3.0 V or 3.3 V
CY2548QCxxxT Factory Programmed 24-pin QFN – Tape and Reel 2.5 V, 3.0 V or 3.3 V
CY2546QCxxx Factory Programmed 24-pin QFN 1.8 V
CY2546QCxxxT Factory Programmed 24-pin QFN – Tape and Reel 1.8 V
CY2544QIxxx
CY2544QIxxxT
CY2548QIxxx
CY2548QIxxxT
CY2546QIxxx
CY2546QIxxxT
Factory Programmed 24-pin QFN
Factory Programmed 24-pin QFN – Tape and Reel 2.5 V, 3.0 V or 3.3 V
Factory Programmed 24-pin QFN 2.5 V, 3.0 V or 3.3 V
Factory Programmed 24-pin QFN – Tape and Reel 2.5 V, 3.0 V or 3.3 V
Factory Programmed 24-pin QFN 1.8 V
Factory Programmed 24-pin QFN – Tape and Reel 1.8 V
2.5 V, 3.0 V or 3.3 V
Notes
7. Field Programmable devices are shipped unprogrammed, and must be programmed before being installed on a board. Factory Programmed devices are shipped
fully configured and ready to install on a board.
8. The CY3675-QFN24A cannot be used to program the CY2546.
9. “xxx” is a variable that denotes a specific device configuration. For more details, contact your local Cypress FAE or sales representative.
Document Number: 001-12563 Rev. *M
Page 11 of 17
CY2544/CY2546/CY2548
Ordering Code Definitions
X
CY 254X
X
X
xxx
X = blank or T
blank = Tube; T = Tape and Reel
Customer Specific Configuration Code
Temperature Grade: X = C or I
C = Commercial; I = Industrial
Package Type: X = Q
Q = 24-pin QFN (Pb-free) 2.65 × 2.65 E-Pad (Sawn type)
Base Part Number: 254X = 2544 or 2546 or 2548
Company ID: CY = Cypress
Document Number: 001-12563 Rev. *M
Page 12 of 17
CY2544/CY2546/CY2548
Package Drawing and Dimensions
Figure 6. 24-pin QFN (4 × 4 × 0.55 mm) LQ24A 2.65 × 2.65 E-Pad (Sawn) Package Outline, 001-13937
001-13937 *F
Document Number: 001-12563 Rev. *M
Page 13 of 17
CY2544/CY2546/CY2548
Acronyms
Document Conventions
Units of Measure
Symbol
Acronym
Description
DL
Drive Level
Unit of Measure
DNU
DUT
EIA
Do Not Use
°C
fF
degree Celsius
femtofarad
megahertz
microsecond
microwatt
milliampere
millisecond
nanosecond
ohm
Device Under Test
MHz
s
Electronic Industries Alliance
Electromagnetic Interference
Electrostatic Discharge
EMI
ESD
FAE
FS
W
mA
ms
ns
Field Application Engineer
Frequency Select
JEDEC
Joint Electron Devices Engineering Council
LVCMOS Low Voltage Complimentary Metal Oxide
Semiconductor
ppm
pF
ps
parts per million
picofarad
picosecond
volt
OE
Output Enable
OSC
PD
Oscillator
V
Power Down
W
watt
PLL
PPM
SS
Phase-Locked Loop
Parts Per Million
Spread Spectrum
Spread Spectrum Clock
Spread Spectrum On
SSC
SSON
Document Number: 001-12563 Rev. *M
Page 14 of 17
CY2544/CY2546/CY2548
Document History Page
Document Title: CY2544/CY2546/CY2548, Quad-PLL Programmable Clock Generator with Spread Spectrum
Document Number: 001-12563
Orig. of
Change
Submission
Date
Revision
ECN
Description of Change
**
690257
790516
RGL
RGL
01/17/2007 New data sheet.
*A
02/20/2007 Separated the Pin Configuration drawing into two to show the difference
between CY2544 and CY2546 pinouts.
Updated DC Electrical Specifications:
Updated Test Conditions of IILPDOE parameter (Replaced “Internal pull up =
100k typical” with “No Internal pull up”).
Changed maximum value of IILPDOE parameter from 10 A to 1 A.
Updated Test Conditions of IIHPDOE parameter (Replaced “Internal pull up =
100k typical” with “No Internal pull up”).
Updated Test Conditions of IILSR parameter (Replaced “Internal pull down =
100k typical” with “Internal pull down = 160k typical”).
Updated Test Conditions of IIHSR parameter (Replaced “Internal pull down =
100k typical” with “Internal pull down = 160k typical”).
Changed the maximum value of IIHSR parameter from 10 A to 25 A.
Removed maximum value of IDD parameter (22 mA).
Added typical value of IDD parameter (15 mA).
*B
1508943
RGL /
AESA
10/03/2007 Changed status from Preliminary to Final.
Added Device Selection Guide.
Updated Absolute Maximum Conditions:
Changed condition of ESDHBM parameter from “MIL-STD-883, Method 3015”
to “JEDEC EIA/JESD22-A114-E”.
Updated DC Electrical Specifications:
Removed VIL, VIH, VILX, VIHX parameters and their details.
Added VIL1, VIH1, VIL2, VIH2, VIL3, VIH3, VIL4, VIH4, VIL5, VIH5 parameters and
their details.
Renamed IILPDOE parameter as IIL1, updated test conditions and changed
maximum value of the same parameter from 1 µA to 10 µA.
Renamed IIHPDOE parameter as IIH1, updated test conditions and changed
maximum value of the same parameter from 1 µA to 10 µA.
Renamed IILSR parameter as IIL2 and changed maximum value of the same
parameter from 1 µA to 10 µA.
Renamed IIHSR parameter as IIH2, changed maximum value of the same
parameter from 25 µA to 36 µA and also added minimum value of the same
parameter as 14 µA.
Added RDN parameter and its details.
Changed typical value of IDDS value from 50 µA to 3 µA.
Updated AC Electrical Specifications:
Added TRF1, TRF2, TRF3, TRF4 parameters and their details.
Renamed TCCJ1 parameter as TCCJ and added typical value.
Removed TLTJ parameter and its details.
Updated Configuration Example for C-C Jitter:
Removed details of “Long Term Jitter”.
Updated details corresponding to “Cycle-to-Cycle Jitter”.
Updated Recommended Crystal Specification:
Removed C0 parameter and its details.
Updated Recommended Crystal Specification:
Removed C0 parameter and its details.
Updated Ordering Information:
Deleted generic part numbers.
*C
*D
2748211
2764011
TSAI
CXQ
08/10/2009 Post to external web.
09/15/2009 Updated Ordering Information:
Fixed typo (Changed CY2548Cxxx and CY2548CxxxT to CY2548Ixxx and
CY2548IxxxT for industrial temp parts).
Document Number: 001-12563 Rev. *M
Page 15 of 17
CY2544/CY2546/CY2548
Document History Page (continued)
Document Title: CY2544/CY2546/CY2548, Quad-PLL Programmable Clock Generator with Spread Spectrum
Document Number: 001-12563
Orig. of
Change
Submission
Date
Revision
ECN
Description of Change
*E
2899758
KVM
03/26/2010 Updated Ordering Information:
Updated part numbers.
Updated Package Drawing and Dimensions.
Updated copyright section.
*F
2969587
KVM
07/09/2010 Minor change:
Added “with Spread Spectrum” in first page title to match spec title on the first
page with spec title on the document history page.
*G
*H
3115710
4239875
BASH
CINM
12/21/2010 Added Ordering Code Definitions under Ordering Information.
Added Acronyms and Units of Measure.
01/08/2014 Updated Package Drawing and Dimensions:
spec 51-85203 – Changed revision from *B to *D.
Updated to new template.
Completing Sunset Review.
*I
4586478
5208624
AJU
PSR
03/12/2014 Updated Functional Description:
Added “For a complete list of related documentation, click here.” at the end.
*J
04/06/2016 Updated Ordering Information:
Updated part numbers.
Updated Ordering Code Definitions.
Updated Package Drawing and Dimensions:
Added spec 001-13937 *F (Figure 6).
Updated to new template.
*K
5563470
PSR
12/22/2016 Updated Ordering Information:
Updated part numbers.
Updated Possible Configurations:
Updated part numbers.
Updated Ordering Code Definitions.
Updated Package Drawing and Dimensions:
Removed spec 51-85203 *D.
Updated to new template.
Completing Sunset Review.
*L
5778002
PSR
06/19/2017 Updated Features:
Added one-time programmability.
Updated Pin Definitions:
Updated details in “Description” column corresponding to pin numbers 2, 6, 11,
13, 17, and 20.
Updated Pin Definitions:
Updated details in “Description” column corresponding to pin numbers 2, 6, 11,
13, 17, and 20.
Updated Functional Overview:
Added Output Driver Supply and Multi-Function Input Restriction.
Updated to new template.
*M
5952620
XHT
10/31/2017 Updated DC Electrical Specifications:
Updated details in “Max” column corresponding to VIL2, VIL3, VIL4, and VIL5
parameters.
Updated details in “Min” column corresponding to VIH2, VIH4, and VIH5
parameters.
Updated to new template.
Document Number: 001-12563 Rev. *M
Page 16 of 17
CY2544/CY2546/CY2548
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturers’ representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
®
Products
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PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP | PSoC 6
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Forums | WICED IOT Forums | Projects | Video | Blogs |
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Internet of Things
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Technical Support
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© Cypress Semiconductor Corporation, 2007-2017. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document,
including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other
intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress
hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to
modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users
(either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as
provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation
of the Software is prohibited.
TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE
OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. To the extent
permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any
product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is
the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress products
are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or
systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the
device or system could cause personal injury, death, or property damage ("Unintended Uses"). A critical component is any component of a device or system whose failure to perform can be reasonably
expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim,
damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other
liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products.
Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in
the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
Document Number: 001-12563 Rev. *M
Revised October 31, 2017
Page 17 of 17
相关型号：
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