CY62128EV30LL-45ZAXI [INFINEON]
Asynchronous SRAM;
| 型号： | CY62128EV30LL-45ZAXI |
| 厂家： | 
Infineon |
| 描述： | Asynchronous SRAM 静态存储器 光电二极管 内存集成电路 |
| 文件： | 总19页 (文件大小：2169K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY62128EV30 MoBL®
1-Mbit (128K × 8) Static RAM
1-Mbit (128K
× 8) Static RAM
Features
Functional Description
■ Very high speed: 45 ns
The CY62128EV30 is a high performance CMOS static RAM
module organized as 128K words by 8-bits. This device features
advanced circuit design to provide ultra low active current. This
is ideal for providing More Battery Life™ (MoBL®) in portable
applications such as cellular telephones. The device also has an
automatic power-down feature that significantly reduces power
consumption when addresses are not toggling. Placing the
device in standby mode reduces power consumption by more
than 99 percent when deselected (CE1 HIGH or CE2 LOW). The
eight input and output pins (I/O0 through I/O7) are placed in a
high impedance state when the device is deselected (CE1 HIGH
or CE2 LOW), the outputs are disabled (OE HIGH), or a write
operation is in progress (CE1 LOW and CE2 HIGH and WE
LOW).
■ Temperature ranges:
❐ Industrial: –40 °C to +85 °C
■ Wide voltage range: 2.2 V to 3.6 V
■ Pin compatible with CY62128DV30
■ Ultra low standby power
❐ Typical standby current: 1 µA
❐ Maximum standby current: 4 µA
■ Ultra low active power
❐ Typical active current: 1.3 mA at f = 1 MHz
■ Easy memory expansion with CE1, CE2, and OE features
■ Automatic power-down when deselected
To write to the device, take chip enable (CE1 LOW and CE2
HIGH) and write enable (WE) inputs LOW. Data on the eight I/O
pins is then written into the location specified on the address pin
(A0 through A16).
■ Complementary metal oxide semiconductor (CMOS) for
optimum speed and power
To read from the device, take chip enable (CE1 LOW and CE2
HIGH) and output enable (OE) LOW while forcing write enable
(WE) HIGH. Under these conditions, the contents of the memory
location specified by the address pins appear on the I/O pins.
■ OfferedinPb-free32-pinsmalloutlineintegratedcircuit(SOIC),
32-pin thin small outline package (TSOP) Type I, and 32-pin
shrunk thin small outline package (STSOP) packages
For a complete list of related resources, click here.
Logic Block Diagram
I/O
0
INPUT BUFFER
A
A
A
A
A
A
A
A
A
0
1
2
3
4
5
6
7
8
I/O
1
I/O
2
128K x 8
ARRAY
I/O
3
I/O
I/O
I/O
I/O
4
5
6
7
A
A
A
9
10
11
CE
CE
1
2
POWER
DOWN
COLUMN DECODER
WE
OE
Cypress Semiconductor Corporation
Document Number: 38-05579 Rev. *N
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised September 22, 2016
CY62128EV30 MoBL®
Contents
Pin Configuration .............................................................3
Product Portfolio ..............................................................3
Maximum Ratings .............................................................4
Operating Range ...............................................................4
Electrical Characteristics .................................................4
Capacitance ......................................................................5
Thermal Resistance ..........................................................5
AC Test Loads and Waveforms .......................................5
Data Retention Characteristics .......................................6
Data Retention Waveform ................................................6
Switching Characteristics ................................................7
Switching Waveforms ......................................................8
Truth Table ......................................................................11
Ordering Information ......................................................12
Ordering Code Definitions .........................................12
Package Diagrams ..........................................................13
Acronyms ........................................................................16
Document Conventions .................................................16
Units of Measure .......................................................16
Document History Page .................................................17
Sales, Solutions, and Legal Information ......................19
Worldwide Sales and Design Support .......................19
Products ....................................................................19
PSoC®Solutions .......................................................19
Cypress Developer Community .................................19
Technical Support .....................................................19
Document Number: 38-05579 Rev. *N
Page 2 of 19
CY62128EV30 MoBL®
Pin Configuration
Figure 1. 32-pin STSOP pinout [1]
Figure 2. 32-pin TSOP I pinout [1]
A
A
A
1
2
32
31
A
A
A
OE
11
24
23
OE
A
25
26
11
A
9
8
10
9
8
10
3
4
5
6
7
8
30
29
28
27
26
25
24
23
22
21
20
19
18
17
CE
22
21
20
19
18
17
16
15
14
13
12
11
10
9
CE
I/O
I/O
I/O
I/O
I/O
26
7
1
1
A
28
29
30
31
32
1
2
3
4
5
6
7
8
A
WE
CE
I/O
I/O
I/O
I/O
I/O
13
7
6
5
13
7
6
5
4
3
WE
CE
2
2
A
A
15
4
3
15
Top View
(not to scale)
Top View
(not to scale)
V
V
NC
A
A
A
CC
CC
NC
9
GND
GND
A
I/O
I/O
10
11
12
13
14
15
16
16
2
16
2
I/O
1
I/O
1
A
A
14
12
14
I/O
I/O
0
0
12
A
A
6
A
A
4
A
0
A
7
A
A
A
2
7
0
A
A
6
1
1
A
2
A
5
5
A
3
A
A
4
3
Figure 3. 32-pin SOIC pinout [1]
Top View
V
NC
32
31
30
1
CC
A
16
A
15
2
3
A
14
CE
2
A
4
12
29
28
WE
5
A
A
A
A
13
A
8
A
7
27
26
6
6
5
7
9
25
24
23
22
21
A
A
3
8
9
10
11
12
13
A
4
11
OE
A
A
10
2
A
1
CE
I/O
I/O
1
7
6
A
0
I/O
0
I/O
1
I/O
2
20
19
I/O
5
4
3
14
15
16
I/O
I/O
18
17
GND
Product Portfolio
Power Dissipation
Operating ICC (mA)
f = 1 MHz f = fmax
Speed
(ns)
Product
Range
VCC Range (V)
Standby ISB2 (µA)
Min
Typ [2]
Max
Typ [2]
Max
Typ [2]
Max
Typ [2]
Max
CY62128EV30LL Industrial
2.2
3.0
3.6
45
1.3
2.0
11
16
1
4
Notes
1. NC pins are not connected on the die.
2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V = V
, T = 25 °C.
A
CC
CC(typ)
Document Number: 38-05579 Rev. *N
Page 3 of 19
CY62128EV30 MoBL®
DC input voltage [3, 4] ...................–0.3 V to VCC(max) + 0.3 V
Output current into outputs (LOW) ............................. 20 mA
Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the
device. User guidelines are not tested.
Static discharge voltage
(MIL-STD-883, method 3015) .................................> 2001 V
Storage temperature ................................ –65 °C to +150 °C
Latch-up current ....................................................> 200 mA
Ambient temperature
with power applied ................................... –55 °C to +125 °C
Operating Range
Supply voltage
to ground potential [3, 4] ...............–0.3 V to VCC(max) + 0.3 V
Ambient
[5]
Device
Range
VCC
Temperature
DC voltage applied to outputs
in high Z State [3, 4] ......................–0.3 V to VCC(max) + 0.3 V
CY62128EV30LL Industrial –40 °C to +85 °C 2.2 V to 3.6 V
Electrical Characteristics
Over the Operating Range
45 ns (Industrial)
Parameter
VOH
Description
Test Conditions
Unit
Min
2.0
2.4
–
Typ [6]
Max
Output HIGH voltage
IOH = –0.1 mA
–
–
–
V
V
IOH = –1.0 mA, VCC > 2.70 V
IOL = 0.1 mA
–
VOL
VIH
VIL
Output LOW voltage
Input HIGH voltage
Input LOW voltage
–
0.4
V
IOL = 2.1 mA, VCC > 2.70 V
VCC = 2.2 V to 2.7 V
VCC= 2.7 V to 3.6 V
VCC = 2.2 V to 2.7 V
VCC= 2.7 V to 3.6 V
GND < VI < VCC
–
–
0.4
V
1.8
2.2
–0.3
–0.3
–1
–1
–
–
VCC + 0.3 V
V
–
VCC + 0.3 V
V
–
0.6
0.8
+1
V
–
V
IIX
Input leakage current
–
µA
µA
mA
mA
IOZ
ICC
Output leakage current
VCC operating supply current
GND < VO < VCC, output disabled
–
+1
f = fmax = 1/tRC
f = 1 MHz
VCC = VCCmax
OUT = 0 mA
CMOS levels
11
1.3
16
I
–
2.0
[7]
ISB1
Automatic CE power-down
current – CMOS inputs
CE1 > VCC0.2 V, CE2 < 0.2 V
VIN > VCC – 0.2 V, VIN < 0.2 V
f = fmax (address and data only),
–
1
1
4
µA
f = 0 (OE and WE), VCC = 3.60 V
CE1 > VCC – 0.2 V, CE2 < 0.2 V
[7]
ISB2
Automatic CE power-down
current – CMOS inputs
–
4
µA
VIN > VCC – 0.2 V or VIN < 0.2 V,
f = 0, VCC = 3.60 V
Notes
3.
4.
V
V
= –2.0 V for pulse durations less than 20 ns.
IL(min)
= V + 0.75 V for pulse durations less than 20 ns.
IH(max)
CC
5. Full device AC operation assumes a 100 µs ramp time from 0 to V
and 200 µs wait time after V stabilization.
CC
CC(min)
6. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V = V
, T = 25 °C.
A
CC
CC(typ)
7. Chip enables (CE and CE ) must be at CMOS level to meet the I
/ I
/ I
spec. Other inputs can be left floating.
1
2
SB1 SB2 CCDR
Document Number: 38-05579 Rev. *N
Page 4 of 19
CY62128EV30 MoBL®
Capacitance
Parameter [8]
Description
Input capacitance
Output capacitance
Test Conditions
Max
10
Unit
pF
CIN
TA = 25 °C, f = 1 MHz, VCC = VCC(typ)
COUT
10
pF
Thermal Resistance
Parameter [8]
Description
Test Conditions
32-pin TSOP I 32-pin SOIC 32-pin STSOP Unit
JA
Thermal resistance
(junction to ambient)
Still air, soldered on a 3 × 4.5 inch,
four-layer printed circuit board
56.90
79.34
69.47
°C/W
JC
Thermal resistance
(junction to case)
14.81
18.49
13.39
°C/W
AC Test Loads and Waveforms
Figure 4. AC Test Loads and Waveforms
R1
ALL INPUT PULSES
VCC
VCC
OUTPUT
90%
10%
90%
10%
R2
GND
Rise Time = 1 V/ns
30 pF
Fall Time = 1 V/ns
INCLUDING
JIG AND
Equivalent to:
THEVENIN EQUIVALENT
SCOPE
RTH
OUTPUT
VTH
Parameters
2.50 V
16667
15385
8000
3.0 V
1103
1554
645
Unit
R1
R2
V
RTH
VTH
1.20
1.75
Note
8. Tested initially and after any design or process changes that may affect these parameters.
Document Number: 38-05579 Rev. *N
Page 5 of 19
CY62128EV30 MoBL®
Data Retention Characteristics
Over the Operating Range
Parameter
Description
VCC for data retention
Data retention current
Conditions
Min
1.5
–
Typ [9]
Max
–
Unit
V
VDR
–
–
[10]
ICCDR
VCC = 1.5 V,
CE1 > VCC 0.2 V or CE2 < 0.2 V,
IN > VCC 0.2 V or VIN < 0.2 V
Industrial
3
µA
V
[11]
tCDR
Chip deselect to data retention
time
0
–
–
–
–
ns
ns
[12]
tR
Operation recovery time
45
Data Retention Waveform
Figure 5. Data Retention Waveform [13]
DATA RETENTION MODE
VCC(min)
VCC(min)
V
DR
> 1.5 V
VCC
CE
t
t
R
CDR
Notes
9. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V = V
, T = 25 °C.
A
CC
CC(typ)
10. Chip enables (CE and CE ) must be at CMOS level to meet the I
/ I
/ I
spec. Other inputs can be left floating.
1
2
SB1 SB2 CCDR
11. Tested initially and after any design or process changes that may affect these parameters.
12. Full device AC operation requires linear V ramp from V to V > 100 µs or stable at V 100 µs.
CC(min)
CC
DR
CC(min)
13. CE is the logical combination of CE and CE . When CE is LOW and CE is HIGH, CE is LOW; when CE is HIGH or CE is LOW, CE is HIGH.
1
2
1
2
1
2
Document Number: 38-05579 Rev. *N
Page 6 of 19
CY62128EV30 MoBL®
Switching Characteristics
Over the Operating Range
45 ns (Industrial)
Unit
Parameter [14, 15]
Description
Min
Max
Read Cycle
tRC
Read cycle time
45
–
–
45
–
ns
ns
ns
ns
ns
ns
ns
tAA
Address to data valid
Data hold from address change
CE LOW to data valid
OE LOW to data valid
OE LOW to low Z [16]
OE HIGH to high Z [16, 17]
CE LOW to low Z [16]
CE HIGH to high Z [16, 17]
CE LOW to power-up
CE HIGH to power-down
tOHA
tACE
tDOE
tLZOE
tHZOE
10
–
45
22
–
–
5
–
18
–
tLZCE
tHZCE
10
–
ns
ns
18
–
tPU
0
–
ns
ns
tPD
45
Write Cycle [18, 19]
tWC
tSCE
tAW
tHA
Write cycle time
45
35
35
0
–
–
ns
ns
ns
ns
ns
CE LOW to write end
Address setup to write end
Address hold from write end
Address setup to write start
WE pulse width
–
–
tSA
0
–
–
tPWE
tSD
35
25
0
ns
ns
ns
ns
ns
Data setup to write end
Data hold from write end
WE LOW to high Z [16, 17]
WE HIGH to low Z [16]
–
tHD
–
tHZWE
tLZWE
–
18
–
10
Notes
14. CE is the logical combination of CE and CE . When CE is LOW and CE is HIGH, CE is LOW; when CE is HIGH or CE is LOW, CE is HIGH.
1
2
1
2
1
2
15. Test Conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns or less (1 V/ns), timing reference levels of V
/2, input
CC(typ)
pulse levels of 0 to V
, and output loading of the specified I /I as shown in the Figure 4 on page 5.
CC(typ)
OL OH
16. At any given temperature and voltage condition, t
is less than t
, t
is less than t
, and t
is less than t
for any given device.
HZCE
LZCE HZOE
LZOE
HZWE
LZWE
17. t
, t
, and t
transitions are measured when the output enter a high impedance state.
HZOE HZCE
HZWE
18. The internal write time of the memory is defined by the overlap of WE, CE = V . All signals must be ACTIVE to initiate a write and any of these signals can terminate
IL
a write by going INACTIVE. The data input setup and hold timing should be referenced to the edge of the signal that terminates the write.
19. The minimum write pulse width for WRITE Cycle No.3 (WE Controlled, OE LOW) should be sum of t
and t
.
HZWE
SD
Document Number: 38-05579 Rev. *N
Page 7 of 19
CY62128EV30 MoBL®
Switching Waveforms
Figure 6. Read Cycle 1 (Address Transition Controlled) [21, 22]
tRC
ADDRESS
t
AA
t
OHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
Figure 7. Read Cycle No. 2 (OE Controlled) [22, 23, 24]
ADDRESS
CE
t
RC
t
ACE
OE
t
HZOE
t
DOE
t
HZCE
t
LZOE
HIGH
IMPEDANCE
HIGH IMPEDANCE
DATA VALID
DATA OUT
t
LZCE
t
PD
ICC
ISB
t
V
PU
CC
50%
SUPPLY
CURRENT
50%
Notes
20. The internal write time of the memory is defined by the overlap of WE, CE = V . All signals must be ACTIVE to initiate a write and any of these signals can
IL
terminate a write by going INACTIVE. The data input setup and hold timing should be referenced to the edge of the signal that terminates the write.
21. The device is continuously selected. OE, CE = V , CE = V .
1
IL
2
IH
22. WE is HIGH for read cycle.
23. CE is the logical combination of CE and CE . When CE is LOW and CE is HIGH, CE is LOW; when CE is HIGH or CE is LOW, CE is HIGH.
1
2
1
2
1
2
24. Address valid before or similar to CE transition LOW and CE transition HIGH.
1
2
Document Number: 38-05579 Rev. *N
Page 8 of 19
CY62128EV30 MoBL®
Switching Waveforms (continued)
Figure 8. Write Cycle No. 1 (WE Controlled) [25, 26, 27, 28]
t
WC
ADDRESS
CE
t
SCE
t
t
HA
AW
t
SA
t
PWE
WE
OE
t
t
SD
HD
29
DATA I/O
NOTE
DATA VALID
t
HZOE
Figure 9. Write Cycle No. 2 (CE1 or CE2 Controlled) [25, 26, 27, 28]
t
WC
ADDRESS
CE
t
SCE
t
SA
t
t
HA
AW
t
PWE
WE
t
t
HD
SD
DATA I/O
DATA VALID
Notes
25. The internal write time of the memory is defined by the overlap of WE, CE = V . All signals must be ACTIVE to initiate a write and any of these signals can
IL
terminate a write by going INACTIVE. The data input setup and hold timing should be referenced to the edge of the signal that terminates the write.
26. CE is the logical combination of CE and CE . When CE is LOW and CE is HIGH, CE is LOW; when CE is HIGH or CE is LOW, CE is HIGH.
1
2
1
2
1
2
27. Data I/O is high impedance if OE = V
.
IH
28. If CE goes HIGH or CE goes LOW simultaneously with WE HIGH, the output remains in high impedance state.
1
2
29. During this period, the I/Os are in output state. Do not apply input signals.
Document Number: 38-05579 Rev. *N
Page 9 of 19
CY62128EV30 MoBL®
Switching Waveforms (continued)
Figure 10. Write Cycle No. 3 (WE Controlled, OE LOW) [30, 31, 33]
t
WC
ADDRESS
CE
t
SCE
t
t
HA
AW
t
SA
t
PWE
WE
t
t
HD
SD
32
NOTE
DATA VALID
DATA I/O
t
t
LZWE
HZWE
Notes
30. CE is the logical combination of CE and CE . When CE is LOW and CE is HIGH, CE is LOW; when CE is HIGH or CE is LOW, CE is HIGH.
1
2
1
2
1
2
31. If CE goes HIGH or CE goes LOW simultaneously with WE HIGH, the output remains in high impedance state.
1
2
32. During this period, the I/Os are in output state. Do not apply input signals.
33. The minimum write pulse width for WRITE Cycle No.3 (WE Controlled, OE LOW) should be sum of t
and t
.
SD
HZWE
Document Number: 38-05579 Rev. *N
Page 10 of 19
CY62128EV30 MoBL®
Truth Table
CE1
CE2
X [34]
L
WE
X
OE
X
Inputs/Outputs
High Z
Mode
Deselect/power-down
Deselect/power-down
Read
Power
H
X [34]
L
Standby (ISB
)
)
X
X
High Z
Standby (ISB
H
H
L
Data out
Data in
Active (ICC
Active (ICC
Active (ICC
)
)
)
L
H
L
X
Write
L
H
H
H
High Z
Selected, outputs disabled
Note
34. The ‘X’ (Don’t care) state for the Chip enables in the truth table refer to the logic state (either HIGH or LOW). Intermediate voltage levels on these pins is not permitted.
Document Number: 38-05579 Rev. *N
Page 11 of 19
CY62128EV30 MoBL®
Ordering Information
Speed
(ns)
Package
Diagram
Operating
Range
Ordering Code
Package Type
45
CY62128EV30LL-45SXI
CY62128EV30LL-45ZXI
CY62128EV30LL-45ZAXI
51-85081 32-pin 450-Mil SOIC (Pb-free)
51-85056 32-pin TSOP Type I (Pb-free)
51-85094 32-pin STSOP (Pb-free)
Industrial
Contact your local Cypress sales representative for availability of these parts.
Ordering Code Definitions
X
- 45 XX
I
2
621
E V30
LL
CY
8
Temperature Grade:
I = Industrial
Pb-free
Package Type: XX = S or Z or ZA
S = 32-pin SOIC
Z = 32-pin TSOP Type I
ZA = 32-pin STSOP
Speed Grade: 45 = 45 ns
LL = Low Power
Voltage Range: V30 = 3 V typical
Process Technology: E = 90 nm Technology
Bus Width: 8 = × 8
Density: 2 = 1-Mbit
Family Code: 621 = MoBL SRAM family
Company ID: CY = Cypress
Document Number: 38-05579 Rev. *N
Page 12 of 19
CY62128EV30 MoBL®
Package Diagrams
Figure 11. 32-pin Molded SOIC (450 Mil) S32.45/SZ32.45, 51-85081
51-85081 *E
Document Number: 38-05579 Rev. *N
Page 13 of 19
CY62128EV30 MoBL®
Package Diagrams (continued)
Figure 12. 32-pin TSOP I (8 × 20 × 1.0 mm) Z32, 51-85056
51-85056 *G
Document Number: 38-05579 Rev. *N
Page 14 of 19
CY62128EV30 MoBL®
Package Diagrams (continued)
Figure 13. 32-pin Small TSOP (8 × 13.4 × 1.2 mm) ZA32, 51-85094
51-85094 *G
Document Number: 38-05579 Rev. *N
Page 15 of 19
CY62128EV30 MoBL®
Acronyms
Document Conventions
Units of Measure
Symbol
Acronym
Description
BHE
BLE
Byte High Enable
Unit of Measure
Byte Low Enable
Chip Enable
°C
MHz
A
s
mA
mm
ns
degree Celsius
megahertz
microampere
microsecond
milliampere
millimeter
nanosecond
ohm
CE
CMOS
I/O
Complementary Metal Oxide Semiconductor
Input/Output
OE
Output Enable
SOIC
SRAM
STSOP
TSOP
WE
Small Outline Integrated Circuit
Static Random Access Memory
Shrunk Thin Small Outline Package
Thin Small Outline Package
Write Enable
%
percent
pF
V
picofarad
volt
W
watt
Document Number: 38-05579 Rev. *N
Page 16 of 19
CY62128EV30 MoBL®
Document History Page
Document Title: CY62128EV30 MoBL®, 1-Mbit (128K × 8) Static RAM
Document Number: 38-05579
Submission
Date
Orig. of
Change
Rev.
ECN No.
Description of Change
**
285473
461631
See ECN
See ECN
PCI
New data sheet.
Changed status from Preliminary to Final.
*A
NXR
Removed 35 ns speed bin related information in all instances across the
document.
Removed “L” version of CY62128EV30 related information in all instances
across the document.
Removed Reverse TSOP I package related information in all instances across
the document.
Updated Electrical Characteristics:
Changed typical value of ICC parameter from 8 mA to 11 mA corresponding to
Test Condition “f = fmax”.
Changed maximum value of ICC parameter from 12 mA to 16 mA
corresponding to Test Condition “f = fmax”.
Changed maximum value of ICC parameter from 1.5 mA to 2.0 mA
corresponding to Test Condition “f = 1 MHz”.
Changed typical value of ISB2 parameter from 0.5 μA to 1 μA.
Changed maximum value of ISB2 parameter from 1 μA to 4 μA.
Updated AC Test Loads and Waveforms:
Updated Figure 4:
Changed value of AC Test load Capacitance from 50 pF to 30 pF.
Updated Data Retention Characteristics:
Changed maximum value of ICCDR parameter from 1 µA to 3 µA corresponding
to Test Condition “LL”.
Updated Switching Characteristics:
Changed minimum value of tLZOE parameter from 3 ns to 5 ns for 45 ns speed
bin.
Changed minimum value of tLZCE parameter from 6 ns to 10 ns for 45 ns speed
bin.
Changed maximum value of tHZCE parameter from 22 ns to 18 ns for 45 ns
speed bin.
Changed minimum value of tPWE parameter from 30 ns to 35 ns for 45 ns speed
bin.
Changed minimum value of tSD parameter from 22 ns to 25 ns for 45 ns speed
bin.
Changed minimum value of tLZWE parameter from 6 ns to 10 ns for 45 ns speed
bin.
Updated Ordering Information.
*B
*C
464721
See ECN
See ECN
NXR
VKN
Updated Logic Block Diagram.
1024520
Added final Automotive-A and Automotive-E information in all instances across
the document.
Updated Electrical Characteristics:
Added Note 7 and referred the same note in ISB2 parameter.
Updated Data Retention Characteristics:
Added Note 10 and referred the same note in ICCDR parameter.
Updated Ordering Information.
*D
*E
*F
2257446
2702841
2781490
See ECN
05/06/2009
10/08/2009
NXR
Updated Maximum Ratings:
Changed the Maximum rating of “Ambient Temperature with Power Applied”
from 55 °C to +125 °C to –55 °C to +125 °C.
VKN /
PYRS
Updated Switching Characteristics:
Updated description of tPD parameter.
Updated Ordering Information (Added -45SXA part).
VKN
Updated Ordering Information (Included “CY62128EV30LL-45ZAXA” part).
Document Number: 38-05579 Rev. *N
Page 17 of 19
CY62128EV30 MoBL®
Document History Page (continued)
Document Title: CY62128EV30 MoBL®, 1-Mbit (128K × 8) Static RAM
Document Number: 38-05579
Submission
Date
Orig. of
Change
Rev.
ECN No.
Description of Change
*G
2934428
06/03/10
VKN
Updated Truth Table:
Added Note 34 and referred the same note in ‘X’ in “CE1” and “CE2” columns.
Updated Package Diagrams.
Updated to new template.
*H
3026548
09/12/2010
AJU
Updated Pin Configuration.
Added Ordering Code Definitions.
Added Acronyms and Units of Measure.
Minor edits.
*I
3115909
3292906
01/06/2011
06/25/2011
RAME
AJU
Separated Automotive and Industrial parts from this data sheet.
Removed Automotive related information in all instances across the document.
*J
Updated Functional Description:
Removed the Note “For best practice recommendations, refer to the Cypress
application note “System Design Guidelines” at http://www.cypress.com
website.” and its reference.
Updated Package Diagrams.
Updated to new template.
*K
4499499
09/11/2014
MEMJ
Updated Switching Characteristics:
Added Note 19 and referred the same note in “Write Cycle”.
Updated Switching Waveforms:
Added Note 33 and referred the same note in Figure 10.
Updated Package Diagrams:
spec 51-85081 – Changed revision from *C to *E.
spec 51-85056 – Changed revision from *F to *G.
spec 51-85094 – Changed revision from *F to *G.
Updated to new template.
Completing Sunset Review.
*L
4581542
11/27/2014
VINI
Updated Functional Description:
Added “For a complete list of related resources, click here.” at the end.
Updated Maximum Ratings:
Referred Notes 3, 4 in “Supply voltage to ground potential”.
*M
*N
4920942
5445076
09/15/2015
09/22/2016
VINI
VINI
Updated to new template.
Completing Sunset Review.
Updated Thermal Resistance:
Replaced “two-layer” with “four-layer” in “Test Conditions” column.
Updated all values of JA and JC parameters.
Updated to new template.
Completing Sunset Review.
Document Number: 38-05579 Rev. *N
Page 18 of 19
CY62128EV30 MoBL®
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
®
Products
PSoC Solutions
ARM® Cortex® Microcontrollers
cypress.com/arm
cypress.com/automotive
cypress.com/clocks
cypress.com/interface
cypress.com/iot
PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP
Automotive
Cypress Developer Community
Clocks & Buffers
Interface
Forums | Projects | Video | Blogs | Training | Components
Technical Support
Internet of Things
Lighting & Power Control
Memory
cypress.com/support
cypress.com/powerpsoc
cypress.com/memory
cypress.com/psoc
PSoC
Touch Sensing
USB Controllers
Wireless/RF
cypress.com/touch
cypress.com/usb
cypress.com/wireless
© Cypress Semiconductor Corporation, 2004-2016. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document,
including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other
intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress
hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to
modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users
(either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as
provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation
of the Software is prohibited.
TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE
OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. To the extent
permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any
product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is
the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress products
are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or
systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the
device or system could cause personal injury, death, or property damage ("Unintended Uses"). A critical component is any component of a device or system whose failure to perform can be reasonably
expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim,
damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other
liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products.
Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in
the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
Document Number: 38-05579 Rev. *N
Revised September 22, 2016
Page 19 of 19
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